JPH0795659A - Integral control unit for automobile - Google Patents

Abstract

PURPOSE:To allow the control unit to easily and flexibly cope with a control system by providing an arithmetic unit and an input output processing unit to the control unit and interfacing them with an interface device. CONSTITUTION:An arithmetic unit 1 is provided with an arithmetic means 4 and calculates its output through the use of an input value from an input/ output unit 3 based on the content of control. The unit 3 is provided with an arithmetic means 5 to process an input/output signal and a means fetching an input signal from a sensor 6 and outputting it to the unit 1 and drives an actuator 7 based on a control variable from the unit 1. The units 1, 3 are interfaced with each other by using an interface means 2, through which signals transmitted/received with each other. Since the input output and the arithmetic means 1 are provided independently in this way, the input output signal processing and arithmetic processing for a versatile system are realized efficiently by using one or plural processing means and arithmetic means. Furthermore, since the interface means is provided independently, the interface means suitable for configuration system is employed and the versatile system is efficiently realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vehicle integrated control unit, and more particularly to a vehicle integrated control unit suitable for configuring or reconfiguring a plurality of systems in a plurality of forms.

[0002]

2. Description of the Related Art Since the use of microcomputers for vehicle control, many systems such as engine control, A / T control, suspension control, etc. have been computerized, and each system has made great progress. In recent years, in order to obtain cars with higher added value, more sophisticated control and enhancement of self-diagnosis function have been demanded,
As one of the means, a system that allows free data communication between different systems has appeared.

Conventionally, this type of system is constructed, for example, as described in Japanese Patent Application Laid-Open No. 61-195453 by combining each system that previously worked independently by using a communication means such as a LAN. It enabled data communication between systems. Further, as disclosed in, for example, Japanese Unexamined Patent Publication No. 3-283843, a communication node for a controller and a communication node for a sensor and an actuator are independently provided in a multiplex transmission line, and the data is configured to be connected to each other. It was possible to send and receive freely.

[0004]

Of the above-mentioned conventional techniques,
When the existing independent systems are connected by communication means as in the former case, input / output to / from each unit is performed from sensors and actuators required for the system. Therefore, when the installation positions of the sensor and the actuator are distributed in various places in the vehicle, there is a problem that the wire harness unavoidably becomes large due to the wiring between the unit and the sensor and the actuator.

Further, in such a method, one system basically needs to be composed of one unit. Therefore, in order to easily configure and reconfigure multiple systems, it is necessary to design with sufficient margins so that all systems can build units that can be used in common in multiple systems, resulting in a large waste in a small system. There was also the problem that things were unavoidable.

On the other hand, in the latter case, in the case where the sensor and the actuator and the arithmetic unit, each of which is provided with the communication means, are connected by the communication means, the unit, the sensor, the actuator and the like are used to provide flexibility. It is possible to configure the system to. However, since it is necessary to send all the raw data through the communication means, the burden on the communication means is large, and in addition, in the event that the communication means fails in addition to the need for ultra-high speed communication means. There was a problem that there was a high possibility that the system would completely go down. Not only that, since the signals of each sensor and actuator are all transmitted through the communication means, it is necessary to provide each sensor and actuator with a transmission means and a signal processing means, which significantly increases the number of components of the system. It had a drawback that it would end up.

The object of the present invention is to flexibly and easily cope with diversified automobile control systems, and further, to suppress the increase in the number of parts of the control device and to construct the whole at low cost. At the same time, it is to provide a comprehensive control unit for automobiles in which each part can be arranged reasonably.

[0008]

[Means for Solving the Problems] To achieve the above object,
An integrated control unit for an automobile according to the present invention basically uses an input / output processing unit capable of processing a plurality of input / output signals in an automobile control system, and a signal processed by the input / output processing unit. It is characterized by comprising an arithmetic unit for performing various vehicle control arithmetic operations and an interface means for connecting these two units.

As a more specific example, the input / output processing means is divided into an input unit for executing processing of a plurality of input signals and an output unit for executing processing of a plurality of output signals, The interface means may be one using a multiplex communication means.

[0010]

According to the present invention having such a configuration, since the input / output processing means and the arithmetic means are provided independently, one or a plurality of input / output signal processing and arithmetic processing in various systems are performed. It can be efficiently realized by using the input / output processing means and the arithmetic means. Further, since the interface means is provided independently of the input / output processing means and the arithmetic means, it is possible to use the interface means suitable for the system to be configured, and from this, various systems can be constructed by using a common unit. Can be realized efficiently.

Furthermore, a standardized input / output processing means is provided.
Because of the structure that can handle multiple I / O processes, when configuring a system that requires a large number of I / O processes, input signals that are close to each other in terms of physical layout without increasing the number of parts excessively. Or, it is possible to output, and it is possible to efficiently reduce the wire harness.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a first embodiment according to the present invention. 1, an overall control unit for an automobile according to the present invention uses an input / output unit 3 which is an input / output processing means capable of processing a plurality of input / output signals and a signal processed by the input / output unit 3. It is composed of a computing unit 1 which is a computing unit for carrying out a vehicle control computation, and an interface unit 2 which couples these two units 1 and 3. The arithmetic unit 1 includes an arithmetic means 4 and
The output value is calculated using the input value from the input / output unit 3 based on the control content. The input / output unit 3 includes an arithmetic unit 5 for processing an input / output signal, a unit (not shown) for receiving an input signal from the sensor 6 and outputting the input signal to the arithmetic unit, and outputs the arithmetic unit 1. A means (not shown) for driving the actuator 7 based on the control value is provided. The two units are connected by the interface means 2 and have a structure capable of exchanging signals with each other.

FIG. 2 shows a second embodiment according to the present invention.
An example of a system configuration diagram when multiplex communication such as LAN is used for the interface is shown in FIG.
01 and the input / output unit 202 are connected via the communication means 203. FIG. 3 shows an example of the configuration of a system with an inter-unit interface using the arithmetic unit, the input / output unit, and the communication means of FIG. In FIG. 3, an arithmetic unit 301 is a CPU 306 for performing unit management and various arithmetic operations, and an input / output unit 302 is a C for performing unit management and data processing.
Each of them has a PU 307, and when transmitting and receiving data between the units, these CPUs 306 and 307 output to the communication connectors 308 and 308 via the address bus and the data buses 310 and 310. The communication connectors 308 and 308 are communication circuits 30.
The communication circuits 309 and 309 have processing related to communication and a diagnostic function of the unit, and transmit data from the CPUs 306 and 307 and a diagnostic result of the units 301 and 302 are displayed on the communication line 303. In addition to being sent to the other unit through the, it also serves to send various information flowing on the communication line 303 to the CPU of the unit. Thus, in the illustrated example, the unit 30
The communication circuits 309 and 309 are provided on the communication connectors 308 and 308 outside the CPUs 1 and 302, and the CPU 30
6, an address bus and a data bus 310
By connecting with, it is possible to increase the degree of freedom before the communication connectors 308, 308.

In order to make a structural comparison between the present invention and the prior art, FIG. 4 shows an example of the actual configuration of a conventional vehicle control system. FIG. 4 shows control systems for engine control, A / T control, active suspension control, traction control (TCS), some control systems such as sensors and actuators, and the wiring of each control system. It is shown that this is done for each system. In FIG. 4, the input signal line 405 from each sensor to each control unit is shown by a chain line, and the output signal 406 from each control unit to each actuator is shown by a dotted line. In particular, a plurality of signal lines are bundled and wired. The parts that were marked are shown in bold lines.

FIG. 5 is a block diagram of the second embodiment of the present invention including the arithmetic unit, the input / output unit, and the interface using communication shown in FIG. 3 applied to the control system shown in FIG. , Was specifically realized. In FIG. 5, the communication and power line 50
0 is a solid line, the input signal line 514 from the sensor to the control unit is a dashed line, and the output signal line 515 from the control unit to the actuator is a dotted line.

In FIG. 5, a communication and power supply line 500 is provided in the entire vehicle, and it is connected to arithmetic units 501, 502, 503, 504 for each control, and sensors and actuators located close to each other in physical arrangement. Input / output units (indicated as IO / U in the figure) 507, 508, 50 arranged at various places to enable connection.
9, 510, 511 and 512 are connected. As can be seen from FIG. 5, an appropriate number of sensors and actuators are connected to the input / output units 507 to 512 in the vicinity of the positions where they are arranged. Therefore, wiring from the sensors and actuators to the units is performed. Is Figure 4
It has a short and well-ordered rational arrangement compared to the wiring in the prior art configuration. Regarding the arithmetic units 501 to 504 shown in FIG. 5, it is not necessary to provide a unit for each control system in the configuration of this illustrated example, and in consideration of the amount of computation, the computing capacity of the unit, the environmental conditions, etc. It is possible to freely decide the number and the arrangement position. Furthermore, the input / output unit 5
It is needless to say that the numbers 07 and 512 are not limited to the illustrated shapes, and the number and arrangement position may be freely determined according to the number and types of input signals or output signals.

Further, in the embodiment shown in FIG. 5, an interface utilizing multiplex communication is used as an interface between the units, and a power line 500 is provided as a communication line. From this power supply line 500, each arithmetic unit 501
˜504, input / output units 507 to 512, and electric components and the like provided in the vehicle can be supplied with electric power.
00 is a power supply control unit 5 provided in the engine room
05 or fail safe unit (FS / U) 506
It is connected to the battery 513 via. The power supply control unit 505 has a function of controlling the supply of power to the power supply line, such as stopping the power supply to each unit during long-time parking to prevent the battery from running down. In addition, the fail safe unit 506 is the power control unit 50.
5 has an alternative function of the power supply control unit 505 for the purpose of preventing the power supply to various places from being stopped in the event of a failure, and also grasps the failure status of the units in the vehicle through communication lines, etc. Is provided and a function for recording necessary information is provided.

FIG. 6 shows a third embodiment of the present invention. The function of the input / output unit shown in FIG. 2 is controlled by an input unit 602 capable of inputting / processing a plurality of sensor signals 604 and control. The system is configured by dividing the output unit 603 into two units capable of driving the plurality of actuators 605 based on the values.
The input unit 602 and the output unit 603 are connected with the arithmetic unit 601 through the multiplex communication means 606. According to the configuration of the illustrated example, it is not necessary to provide a circuit for driving the actuator 605 and a circuit for processing an input signal in the same unit, so that noise countermeasures are easy.

The third embodiment of the present invention is combined with the input / output unit shown in FIG. 2 as a constituent element. For example, there are three types of units: an arithmetic unit, an input / output unit and an input unit, an arithmetic unit, an input / output unit and an output unit. In addition to the method of configuring a control system using units, the method of configuring a system using four types of units including an arithmetic unit, an input / output unit, an input unit, and an output unit, in addition to the various system configurations described above, The technology is a smart sensor (a sensor that has a calculation function and a function that outputs data after converting it to a form suitable for use in subsequent calculations) and a smart actuator (a calculation function that has a given control value. There are many possible implementation methods, such as a method of combining actuators that can operate based on.

FIG. 7 specifically shows a third embodiment of the present invention which is an example of the configuration of a system using an inter-unit interface using the arithmetic unit, the input unit, the output unit and the communication means shown in FIG. It is a thing. In FIG. 7, an arithmetic unit 703 includes a CPU 707 for performing unit management and various arithmetic operations, and an input unit 7
Reference numeral 04 is a CPU 7 for unit management and data processing
08, the output unit 705 is provided with a CPU 709 for performing unit management and data output processing, respectively, and these CPUs 707, 708, and 709 have an address bus and a data bus 710 when transmitting / receiving data between the units. The data is output to the communication connectors 702, 702, 702 via 710, 710. Each communication connector 702, 702, 702 includes a communication circuit 706, 706, 706.
Reference numerals 06, 706 and 706 are provided with processing relating to communication and a diagnostic function of the unit, and each CPU 707, 70
8, 709, the transmission data from the unit and the diagnosis result of the unit are sent to another unit via the communication line 701, and various information flowing on the communication line 701 is transmitted to the C of the unit.
It works to send to PU.

In addition to the above, although not particularly shown, the unit interface means shown in FIGS.
As described above, it is possible to configure the system by freely combining the arithmetic unit, the input / output unit, the input unit, the output unit, and the like. Further, as shown in FIG. 3 and FIG. 7, when a communication circuit is provided outside the unit and input / output between the units is performed via a bus, C
Different from the one using the communication, such as the data transmission / reception between PUs, for example, FIGS. 9 and 10 described later.
The system can be configured by connecting the units using the inter-unit interface as shown in FIG.
As a result, it is possible to efficiently realize a control system configuration that is diversified in scale and form and greatly differs depending on the vehicle by using several common units, and reduce the number of vehicle control parts. Leads to.

FIG. 8 is an example of a layout diagram of a vehicle control system specifically realized by applying the second embodiment of the present invention to the control system shown in FIG. Figure 8
In the above, a communication line and a power line 800 are provided in the entire vehicle, and arithmetic units 801 and 80 for control are provided on the communication line and the power line 800.
2, 803, 804, input units (indicated as S / U in the drawing) 809, 810, 811, output units arranged at various locations to enable connection with sensors and actuators located close to each other in physical arrangement (Indicated as D / U in the figure) 807 and 808 are connected. As described above, the input units 809 to 811, and the output units 807 and 808 are connected with appropriate numbers of sensors and actuators that are close to each other in position. for that reason,
The wiring from the sensor and actuator to each unit is shorter than the wiring in the configuration of the prior art shown in FIG. 4, and has a well-ordered and rational arrangement. Regarding the arithmetic units 801 to 804 shown in FIG. 8, the number and arrangement position of the arithmetic units 801 to 804 in the present system are taken into consideration without considering the configuration of the control system in consideration of the amount of arithmetic operation, the arithmetic capacity of the units, environmental conditions, and the like. You can freely decide. Further, it is needless to say that the input units and the output units may be freely determined in number and arrangement position according to the number and types of input signals and output signals without being stuck to the shapes shown.

Further, in FIG. 8, multiple communication is used for the inter-unit interface, as in the case of FIG. 5, and a power supply line is provided side by side with the communication line 800. Each arithmetic unit 801-804, input unit 80
9 to 811, the output units 807, 808, and electric components provided in the vehicle can be supplied with electric power from the power supply line 800, but in the illustrated example, the power supply line 800 is connected to the engine mullet. Power supply control unit 805 or fail-safe unit (FS / U) 8 provided
It is connected to the battery 813 via 06. Further, the power supply control unit 805 and the fail-safe unit 806 have the same operation as the power supply control unit 505 and the fail-safe unit 506 described in the description of FIG. .

Although the vehicle control system was often considered in the embodiments shown in FIGS. 5 and 8, the signals handled in the present invention are all signals used in the vehicle. In addition to the control signal, various signals such as a signal from a switch operated by a passenger, a signal taken from outside the vehicle, and a signal from an environment that changes due to external factors are included.

FIG. 9 shows a fourth embodiment in which the same units as the arithmetic unit and the input / output unit in the system configuration of the second embodiment of the present invention shown in FIG. 2 are used and different types of interfaces are used. 2 shows an example of the system configuration of FIG. In FIG. 9, the arithmetic unit 901 and the input / output unit 902 are connected by an interface 903 different from the one used in FIG. 2, and a dual port RAM (DPRAM and (Notation) 905
An address bus and a data bus 907, 908 inside each unit are connected to. In the configuration of the illustrated example, data transmission / reception between the units 901 and 902 is performed through the DPRAM 905. With such a configuration, it is possible to provide a function equivalent to that of a unit having a conventional input / output and to configure the whole at a low cost, and to obtain a system capable of high-speed operation with a small chip.

FIG. 10 is a block diagram of the third embodiment of the present invention shown in FIG. 6, in which the same units as the arithmetic unit, the input unit, and the output unit are used, and different types of interfaces are used. It is an example of a system configuration of the fifth embodiment. In FIG. 10, an arithmetic unit 1001 and an input unit 100
2 and the output unit 1003 are coupled by an interface 1004 similar to that shown in FIG. 9, and a dual port RAM (denoted as DPRAM in the figure) 100 provided in the interface 1004.
5 is an address bus and a data bus 1 inside each unit
008 and 1009 are connected. In this configuration,
Data transmission / reception between units is performed through this DPRAM.

In the embodiment shown in FIG. 10, the input unit 1002, the output unit 1003 and the DPRAM 1005.
Are connected by a common bus 1009, but in this case, the address area of the DPRAM 1005 is allocated to each unit and used. Alternatively, although not shown in the drawing, the interface 1005 is provided with two DPRAMs connected to the buses of the input unit 1002 and the output unit 1003, respectively, and the arithmetic unit 100 is provided.
It is also possible to connect one bus to the two DPRAMs and exchange data.

Next, a specific example of the common unit that can be widely applied to various control systems will be described. The common unit can be connected to each other by a plurality of different interfaces,
For example, the arithmetic unit, the input / output unit, the input unit, and the output unit will be described in detail with reference to FIGS.

FIG. 11 is an example of a configuration diagram of the arithmetic unit. In FIG. 11, a ROM 1103 for storing control contents, a data table indicating each state of the system, and the like.
And a flash memory 1105, a RAM 110 used for storing signals input to the unit, assisting computation, etc.
4. C that actually performs the calculation based on the stored control contents
A watchdog timer 1107 for monitoring the abnormality of the PU 1106 and the CPU 1106 is provided, and these are connected by a data bus and an address bus 1109. Here, the ROM 1103 and the flash memory 1
As for 105, even if only at least one of them is provided, a sufficient function can be achieved. When both are provided, for example, the contents that can be commonly used in all systems can be written in the ROM 1103, and the contents that change depending on the system such as the data table of the connected device can be written in the flash memory 1105. is there. Further, the watchdog timer 1107 for monitoring the abnormal operation of the CPU 1106 is the CPU 11
When an abnormality of 06 is detected, a signal is output to the communication circuit 1102.
Through this, other units are notified of the abnormality of the arithmetic unit.

Further, the CPU 110 is provided in the arithmetic unit.
6, a DC-DC converter 110 that supplies power for erasing and rewriting the flash memory 1105.
8 is provided, and its power is supplied to the unit together with the power supply to the unit through the communication connector 1101 from the power line attached to the communication line 1110. However, if the flash memory 1105 is not provided, the DC-DC converter 1108 becomes unnecessary.

FIG. 12 is an example of a block diagram of an input / output unit capable of processing an arbitrary input / output signal. The input / output unit according to this illustrated example is basically shown in FIGS.
Of the input and output units shown at 4,
It is configured by using components having the same configuration or the same function. In FIG. 12, the input / output unit includes a ROM 1203, a RAM 1204, a flash memory 1205, a CPU 1206, a watchdog timer 1207, an A / D converter 1215, and a D / A converter 121.
6, a free-run timer 1217, a serial communication interface 1218, and I / O interfaces 1219, 1219, 1219, 1219 are provided, which are connected to each other via a data bus and an address bus 1220.

ROM 1203 and flash memory 12
05 includes a sensor 122 connected to the input / output unit.
1 and the information about the actuator 1222, the data regarding the processing of each input / output signal, the input / output allocation port, the procedure for actually processing them, etc. are stored, but if necessary, the ROM 1203 and the flash memory 1205 are stored. Both or at least one of them may be used. Also, the flash memory 1205
DC-DC converter for erasing and rewriting data
The method of supplying power to 223 and the unit, and the watchdog timer 1207 that monitors the abnormality of the CPU are the same as those of the above-described arithmetic unit. RAM120
4 can be used for various purposes such as auxiliary use during data processing, but it is not necessary if it is unnecessary.

The CPU 1206 responds to input / output signals by
The input unit and the output unit, which will be described later, have a function capable of being processed by both CPUs, and perform necessary processing. The A / D converter 1215 is shown in FIG.
14 has the same function as the A / D converter used in the input unit, and the D / A converter 1216 has the same function as the D / A converter used in the output unit shown in FIG.

A free-run timer 1217 and a serial communication interface 1218 are also provided.
Is used in the example shown in FIGS. 13 and 14 described later,
It has both functions of input processing and output processing by a free-run timer and a serial communication interface, and also has an address bus and a data bus 122.
I / O interfaces 1219, 121
9 ...

Further, the I / O interface 121
9, 1219, ... are input and output ports,
It has both the functions of an I / O interface used in the input unit and the output unit of FIGS. 13 and 14, which will be described later, and the input line, power circuits 1226, 1226, 1226, and the failure detection circuit 122 are provided in the subsequent stage.
7, 1227 and 1227 are connected in the same manner as in the illustrated examples of FIGS. 13 and 14 described later.

FIG. 13 is an example of a block diagram of the input unit. In FIG. 13, the input unit includes a ROM 130.
3, RAM 1304, flash memory 1305, CP
U1306, watchdog timer 1307, A / D
Converter 1315, free-run timer 1317, silicon communication interface 1318, I /
O interfaces 1319, 1319, 1319 are provided, which are data bus and address bus 1325.
Are connected to each other via.

ROM 1303 and flash memory 13
05 includes a sensor 132 connected to the input unit.
Information about 1, 1321, 1321 and data regarding processing of each input signal, a procedure for actually processing them, and the like are stored. The CPU 1306 performs necessary processing based on these, and calculates them via an interface. You can send data to the unit. However, either one of the ROM 1303 and the flash memory 1305 may be used, or both may be provided and used properly. In addition, the DC-DC converter 13 for use in erasing and rewriting the flash memory 1305
23, the power supply system to the unit, and the watchdog timer 1307 for monitoring the abnormality of the CPU 1306 are the same as those in the above-described arithmetic unit.

The RAM 1323 can be used for various purposes such as auxiliary use during data processing, but it is not necessary if it is unnecessary. The A / D converter 1315 converts the analog input signal, the free-run timer 1317 converts the PWM input signal, and the serial communication interface 1318 converts the serial input signal into a digital signal, which are sent to the CPU 1306 via the bus 1325.
In the figure, a 16-bit free-run timer 1317, which is generally considered to have necessary and sufficient accuracy for automobiles.
However, a necessary one such as a 10-bit one or a 20-bit one can be used in consideration of the contents of the system.

Further, the I / O interface 1319,
An A / D converter 1315, a free-run timer 1317, a serial communication interface 1318, and a bus 1325 are connected to 1319 and 1319, respectively, and signals of various sensors 1321 are transmitted by an internal switching circuit (not shown). The configuration is such that it can be selectively used as an input port or a bus input port. Therefore, according to the input unit of this illustrated example, it is possible to input a sensor signal arbitrarily selected and connected in various systems and send it to the arithmetic unit.

FIG. 14 is an example of a block diagram of the output unit. The output unit of the illustrated example includes a ROM 1403, R
AM1404, flash memory 1405, CPU14
06, watchdog timer 1407, D / A converter 1416, free-run timer 1417, serial communication interface 1418, I / O interfaces 1419, 1419, 1419, which are connected to each other via a data bus and an address bus 1425. Has been done. Here, the ROM 1403 and the flash memory 1405 store information regarding the actuators 1422, 1422, 1422 connected to this unit, data regarding the processing of each output signal, output allocation ports, and a procedure for actually processing them. However, like the case of the input unit described above,
ROM 1403 and flash memory 1 as required
It is also possible to adopt a configuration in which both or either of 405. The DC-DC converter 1423 used for erasing and rewriting the flash memory 1405, the power supply system to the unit, and the watchdog timer 1407 for monitoring the abnormality of the CPU 1406 are the same as those of the arithmetic unit.

The RAM 1404 can be used for various purposes such as auxiliary use during data processing, but it is not necessary if it is unnecessary. The CPU 1406 uses the ROM 1403 and the flash memory 14 for the data sent from the arithmetic unit 1 of FIG. 1 via the interface.
Processing is performed based on the procedure stored in 05, and the result is D / A converter 1416 and free-run timer 141.
7 or output to the serial communication interface 1418.

The D / A converter 1416, the free-run timer 1417, and the serial communication interface 1418 convert the data from the CPU 1406 into an analog signal, a PWM signal, and a serial signal, respectively, and output them to the I / O interface 1419.
However, in the figure, a 16-bit free-run timer, which generally has sufficient and sufficient accuracy for automobiles, is shown, but 10-bit or 20-bit ones that are necessary considering the contents of the system are necessary. Can be used.

The I / O interface 1419, ... Has a D / A converter 1416 and a free-run timer 141.
7. Serial communication interface 14
18 and the bus 1425 are connected to each other, and an internal switching circuit (multiplexer or the like) can be used as an output port of a signal to various actuators 1422, ... Or an output port of a bus. Therefore, according to this unit, the structure is such that signals can be output to and driven by the actuators 1422, ... Which are arbitrarily selected and connected in various systems.

The output ports of the I / O interfaces 1419, ...
Since 2, ... Are connected, some actuators require a large amount of electric power to drive. Therefore, power circuits 1426, 1426, 1426 for amplification can be provided at the output terminals of the I / O interfaces 1422, .... Further, as a countermeasure against the failure of the actuators 1422, ..., Actuator failure detection circuits 1427, 1427,
It is configured so that ... can be provided. The output terminal of the failure detection circuit 1427, ... Is the CPU of the unit.
It is connected to 1406, and when a failure of the actuator or the like is detected, necessary processing can be performed.

FIG. 15 shows an I / O having an input / output switching means.
It is an example of a block diagram of an O interface. In FIG. 15, the output terminals of the A / D converter 1501, the D / A converter 1502, and the free-run timer 15
03, serial communication interface 1
Of the input / output terminals of 504, the address bus and the data bus 1505, two each are shown as an example. Further, two terminals each of the terminals of the four input / output ports 1506, 1506 ... Are shown as an example. As can be seen from FIG. 15, these terminals are configured so that they can be arbitrarily connected to each other through the switches 1507, ... And the switching means connects the terminals in accordance with an instruction from the CPU. For this switching means, a circuit such as a macyplexer may be used.

Further, as shown in the figure, each switching means has a data bus and an address bus 1505 in the unit.
Is connected, and the command for switching is on this bus 1
505 from the CPU of the unit. According to this method, it is also possible to switch the input and output to and from the devices connected to the same input / output port by software.

FIG. 16 is an example of a block diagram of the actuator failure detection circuit in FIGS. 12 and 14 described above. In FIG. 16, the drive current of the load 1600 flows from the power supply line 1610 taken into the unit, through the resistor R ₀ 1601 of the drive circuit and the switching element 1602, through the load 1600, and to the ground side. The switching element 1602 is turned on / off by a control signal 1604 issued from the CPU 1603 in the unit.

Here, an actual detection method will be described.
On the current path of the drive current, the switching element 1
A current measuring resistor R is connected between 602 and the load 1600.₁16
When 05 is provided, R is proportional to the load current value.₁16
A potential difference occurs at both ends of 05. In this detector,
Using the operational amplifier 1607, the potential difference is set to the value V of the potential of 0. ₃
Amplified as, generated from the comparison potential generator 1608
Upper limit voltage V_Five, Lower limit reference voltage V₆With comparator 1
Input to 609. V in the comparator 1609₆≤V₃And
V₃≤V_FiveCPU 1 determines whether the normal condition of
To the CPU 603, and the CPU 1603 outputs the control signal 1604.
If it is ON and the normal condition is not established, it is judged as abnormal
And process.

Next, the operational amplifier 1607 and comparison potential generation
Details of the unit 1608 will be described. In FIG.
Current measuring resistance R₁Load side voltage of 1605 is V₁,Power supply
Side voltage is V₂Input resistance, output resistance of operational amplifier
R as shown₁, R₂Then, operational amplifier 1
Output voltage V from 607_FiveIs the potential from the ground endIt can be expressed as. In addition, the comparison potential generator 1 of FIG.
At 608, the resistance R _Five, R₆Is a variable resistor,
Fixed resistance R₃, R_FourIs directly connected to. Potential V
_FiveIs the potential of the power supply with respect to the ground_Five/ (R₃+ R_Five)
Double the potential V₆Is the potential of the power supply with respect to ground
R₆/ R_Four+ R₆) It is doubled.

By having this type of detection circuit in the unit, it is possible to detect an actuator abnormality such as disconnection or short circuit, and use it as part of the self-diagnosis function added to the system for maintenance and repair. In addition to helping the driver, the driver can be notified of the failure of the actuator as soon as possible to further enhance safety.

Next, the multiplex communication means used in the embodiment of the present invention will be described. When a wide variety of information is collectively transmitted using a multiplex communication means such as a LAN, the time delay of the transmission becomes a problem in some high-speed signals, so that the real-time property is high and the fail-safe property is high. It can be said that advanced communication technology is indispensable for improving its effectiveness.

FIG. 17 is an example of a block diagram showing an outline of multiplex communication. In the illustrated example, a distributed control LAN with priority (communication line A1702) and a distributed control LAN provided with a communication control line A'1701 for realizing a priority interrupt.
It is a dual communication system of (communication line B1703). The distributed control LAN 1702 with priority has a mechanism that allows data to be preferentially transmitted according to a priority level described later, and high-speed data is transmitted with a small waiting time. Further, since it is possible to transmit other data from the communication line B1703 even when the communication line A1702 is being used, data communication with extremely little waiting can be expected. Furthermore, since it is a dual LAN, even if one of the LANs becomes incapable of communication due to a disconnection, etc., the other LAN can be used to ensure the minimum required communication. The system is a very fail-safe communication system.

In FIG. 17, the communication interface 1
704 includes a communication control line A'1701 and a communication line A17.
02 connected communication circuit A1705 and communication line B17
Two communication circuits of the communication circuit B1706 of No. 03 are provided, and these are mainly connected to the address bus and the data bus 1707 in the unit 1706. When a data transmission request is generated in the unit 1706, the CPU 1708 in the unit 1706 performs transmission using the communication line A or B. The procedure is as shown in FIGS. 18 and 19 described below.

FIG. 18 is a flow chart showing a data transmission priority processing procedure, and FIG. 19 is a flow chart of the communication system.
It is explanatory drawing which showed one Example of the flow of the signal in a communication line. In FIG. 18, it is assumed that a transmission request for L of arbitrary data is generated in a certain unit X (1801).
Here, the data L is given a priority of use of the communication line A called a priority level, and these are stored in, for example, a flash memory in the unit. This priority level is low for data that has a relatively long time, such as an operation switch of a power window, and for high-speed data that requires real-time information such as an engine speed signal, for example. It is set to have a high priority level, and several levels are set. When transmitting data, sieving is performed based on this priority level, and the transmission route is determined according to the usage status of the communication line and the priority level at that time.
Both the variable length and the fixed length can be considered for the data length of the priority level. However, when the fixed length is used, the end of data transmission can be easily detected. The priority level is fixed with the line forced release signal.

First, data having a low priority level of data, that is, low-speed data is screened out in advance to avoid congestion of the communication line A (1802) and transmitted from the communication line B (1809). However, if the communication line B is in use at this time, it waits until B becomes empty (1812). Next, if the communication line A is vacant, the data of higher priority levels will be transmitted from the communication line A (1803). As for the procedure at this time, as shown in FIG. 19, first, the unit X transmits the processing start signal 1901 from the communication control line A ′. This means that another unit is prohibited from transmitting to the communication control line A ', and the other unit decodes the priority level signal 1902 transmitted subsequently, and the data L by the unit X is transmitted. The value is stored until the end of the transmission of. When the transmission of the priority level is completed, the prohibition of transmission to the communication control line A'is released. Subsequently, the unit X transmits the actual data L via the communication line A, and a transmission end signal is added to the end of the data L (1807, 1903, 1906).
When the other units decode this transmission end signal, they know that the communication line A is free, clear the priority level, and prepare for the next communication.

If the communication line A is used for other data communication in the vacancy determination 1803 of the communication line A in FIG. 18 and it is not vacant, the vacancy determination 1808 of the communication line B is entered. If the communication line B is empty, the data L is transmitted through the communication line B (1809). Communication line B availability determination 180
If the communication line B is in use at 8, the communication line A is examined again. That is, data L currently waiting to be transmitted with respect to the priority level of the data currently transmitted using the communication line A, which is assumed to be M.
Is determined to be low, the same level, or high (1805), and if the priority level of the data L is low or the same level, communication of the data L is completed until the transmission of the data M is completed. Transmission from line A is not performed, communication line A
Of the communication line B and the vacancy of the communication line B are repeatedly checked, and one of the communication lines waits until the vacancy appears, and then the transmission is performed from the vacant communication line. On the other hand, when the priority level of the data L is high, the unit X transmits the compulsory release signal 1904 of the communication line A shown in FIG. 19 from the communication control line A ′ (181).
1), followed by priority level signal 190 shown in FIG.
5 is transmitted (1805). The subsequent processing is the same as the normal transmission method when the communication line A is used. Here, it is assumed that the data M whose transmission has been interrupted newly starts from the initial processing 1801 as transmission waiting data. However,
If the communication processing capacity of the unit is sufficiently large, a specific processing for communication waiting data may be performed.

There are various methods of determining the priority interrupt, for example, a method based on the fact that the value of the priority level of the data L is larger than the value of the priority level of the data M, and the value is 1 or more. There are various ways to decide the criteria, such as a method based on the larger one, and the way to decide the priority level.
The unit may actually perform these communication processes by the communication circuit A or the communication circuit B, a part of the process may be performed by the CPU in the unit, or an external unit. In addition, a circuit for performing the processing may be provided.

As is apparent from the above description, according to the present invention, since the unit for arithmetic operation and the unit for performing a plurality of input / output processing are separately provided and are connected by the interface, Since the input / output processing of can be performed by any unit, it becomes possible to take in the signal to the unit close to the physical location, and even if the system becomes complicated, the wire for input / output of the signal The harness is not enlarged, and it is possible to flexibly and easily respond to system changes.

Further, since the input / output unit is provided with the function of processing a plurality of input / output signals, it is possible to increase the utilization rate of the signal processing means and the interface, and even if the input / output signals increase, the configuration of the entire system can be improved. The system can be configured without extremely increasing the number of parts. further,
Since the input / output unit is configured to handle any input / output signal, multiple systems can be configured using a common unit, and various vehicle control systems can be configured using common parts. Easy to configure.

In addition, since an interface between units such as multiplex communication is provided independently of the units, it is possible to connect common units with various interfaces, and use systems having different scales by using common units. Easy to implement.

[0061]

As can be understood from the above description, according to the present invention, it is possible to flexibly and easily cope with diversified automobile control systems, and increase the number of parts of the control device. It is possible to suppress the cost and configure the entire structure at a low cost, and the respective parts can be rationally arranged.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a system configuration using a calculation / input / output separation type unit according to the present invention.

FIG. 2 is a configuration diagram showing an embodiment of a system configuration by an interface using arithmetic, input / output separation type unit and multiplex communication according to the present invention.

FIG. 3 is a configuration diagram showing an embodiment of a system configuration including an operation / input / output separation type unit and an interface according to the present invention.

FIG. 4 is a wiring diagram showing an example of signal lines in a conventional system.

FIG. 5 is a signal line when the system according to the present invention is used,
And a wiring diagram showing an example of a power supply line.

FIG. 6 is a configuration diagram showing an embodiment of a system configuration with an interface using arithmetic, input, output separation type unit, and multiplex communication according to the present invention.

FIG. 7 is a configuration diagram showing an embodiment of a system configuration including a calculation, input / output separation type unit, and interface according to the present invention.

FIG. 8 is a signal line when the system according to the present invention is used,
And a wiring diagram showing an example of a power supply line.

FIG. 9: Arithmetic / I / O separated unit, D according to the present invention
The block diagram which shows one Example of the system configuration by the interface which used PRAM.

FIG. 10 is a configuration diagram showing an embodiment of a system configuration by an interface using a calculation, input / output separation type unit, and DPRAM according to the present invention.

FIG. 11 is a configuration diagram showing an embodiment of an arithmetic unit that can be connected by a plurality of types of interfaces according to the present invention to form a system.

FIG. 12 is a configuration diagram showing an embodiment of an input / output unit that is connected by a plurality of types of interfaces according to the present invention and that can form a system.

FIG. 13 is a configuration diagram showing an embodiment of an input unit that can be connected by a plurality of types of interfaces according to the present invention to configure a system.

FIG. 14 is a configuration diagram showing an embodiment of an output unit which is connected by a plurality of types of interfaces according to the present invention and which can form a system.

FIG. 15 is a configuration diagram showing an embodiment of an I / O interface section having input / output switching means in a unit capable of output processing according to the present invention.

FIG. 16 is a circuit diagram showing an embodiment of a failure detection circuit.

FIG. 17 is a configuration diagram showing an embodiment of an inter-unit interface using duplex communication having a data priority processing function according to the present invention.

18 is a flowchart showing a transmission priority processing procedure of the data of FIG.

19 is an explanatory diagram showing an example of a signal flow in a communication line of the communication system of FIG.

[Explanation of symbols]

 1 computing unit 2 interface means 3 input / output unit 4 computing means 5 computing means 6 sensor 7 actuator

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication H04L 12/40 (72) Inventor Shigeki Morinaga 7-1 Omika-cho, Hitachi-shi, Ibaraki Stock ceremony Hitachi, Ltd. Hitachi Research Laboratory

Claims (9)

[Claims] 1. An arithmetic unit for performing an arithmetic operation based on control contents, an input / output processing unit for executing processing of a plurality of input / output signals, and an interface unit for connecting the arithmetic unit and the input / output processing unit. Comprehensive control unit for automobiles characterized by being configured. 2. The input / output processing means is divided into an input unit for processing a plurality of input signals and an output unit for processing a plurality of output signals. Integrated control unit for automobiles. 3. An integrated control unit for an automobile according to claim 1, wherein a multiplex communication means is used as the interface means. 4. The interface means comprises a dual port RAM, and at least one of a data bus and an address bus is used as a connecting means between the interface means and the computing means and between the interface means and the input / output unit. The integrated control unit for an automobile according to claim 1, which is used. 5. The computing means and the input / output processing means each include a communication circuit and a CPU, and the communication circuit and the CPU in each of the means are provided separately from each other. Communication circuit and C
The vehicle integrated control unit according to claim 1, wherein the PUs are connected to each other using at least one of a data bus and an address bus. 6. The calculating means, the input unit, and the output unit each include a communication circuit and a CPU, and the communication circuit and the CPU in each means and unit are separated from each other. 3. The vehicle integrated control unit according to claim 2, wherein the communication circuit and the CPU are connected to each other using at least one of a data bus and an address bus. 7. A plurality of in-vehicle electrical equipments are physically arranged close to one of the input / output processing means or one of the input unit and the output unit, and a communication means is provided between the respective means or units. The integrated control unit for an automobile according to claim 1, wherein the integrated control unit is provided. 8. A control unit in which a power supply line capable of supplying power to the computing means is provided side by side with a communication line used for the multiplex communication means, and the electrical equipment in the vehicle is physically located near this power supply equipment. 4. The integrated control unit for an automobile according to claim 3, wherein the integrated control unit is arranged so as to be driven by. 9. A means is provided, wherein priority is provided to data to be transmitted between a plurality of control units, and means for transmitting data based on the priority when transmission requests for a plurality of data occur simultaneously. A comprehensive control unit for automobiles.