JP5220266B2 - Method and apparatus for generating filter tap weights and biases for signal dependent branch metric computation - Google Patents

Description

  The present invention relates generally to channel equalization and decoding techniques, and in particular to sequence prediction techniques with noise correction.

  The magnetic recording read channel converts the analog read channel into an estimate of user data recorded on the magnetic medium. Read heads and magnetic media introduce noise and other distortions into the read signal that correlate with the written user data. In order to improve the performance of the read channel, several techniques have been proposed or presented that take into account the statistical correlation between written user data and distortion.

  Traditional techniques that use data-dependent statistics to improve detector error rates have been cumbersome because they required off-board processing to calculate detector parameters from the statistics offloaded from the instrument . This offload calculation and onload cycle takes a significant amount of time if the number of different data conditions used and the number of correlation lags used are large enough to provide significant gains in error rate performance. It will be complicated.

Therefore, there is a need for a method and apparatus for meeting these data correlations without relying on external calculations or circuitry. Can adapt to these data correlations during normal read operations and provide parameter values to the sequence detector (or to a post-processor that operates based on the AN initial NRZ estimate generated by the sequence detector) There is a further need for methods and apparatus that can be used.
US Pat. No. 6,594,094 A. Kavic, “Decision Feedback Evaluation in Channels with Signal Dependent Media Noise”, IEEE Transactions on Magnetics, Vol 37, 1909-11 (2001).

  In general, a method and apparatus is provided for determining a plurality of filter tap weights and / or biases for a noise prediction filter used to generate one or more signal dependent branch metrics. Filter tap weights and / or filter biases are adaptively accumulated for each possible data condition so that a data dependent branch metric can be calculated. The data conditions can include, for example, each possible data pattern for a given data dependency length. Accumulation can be performed by selecting an appropriate accumulated filter tap weight or bias and updating based on the data conditions associated with the current received data.

Once determined, the accumulated filter tap weights and / or biases are based on, for example, a Viterbi detector that calculates one or more branch metrics, or an initial data estimate generated by the Viterbi detector. Can be provided to a post-processor operating in According to another aspect of the present invention, the filter tap weights associated with a zero delay tap may be different from each other except in the case of a single normalization condition where the corresponding zero delay tap remains fixed. Adapted to filter conditions.

  The invention and many more features and advantages of the invention will be better understood with reference to the following detailed description and drawings.

The present invention provides an adaptive circuit 100 described below with reference to FIG. This circuit generates tap weights and biases for the noise prediction filter. Tap weights and bias are used to calculate the branch metric. In one embodiment of the self-adaptive circuit 100, the generated tap weights and bias provide a bias corrected branch metric for signal dependent noise prediction. First, the calculation of the branch metric will be described in the “Maximum Likelihood Branch Metric” section before describing the details of the self-adaptive circuit 100.
Maximum likelihood branch metric

The Viterbi detector and the event-based post processor calculate the log likelihood of the received sequence given the corresponding NRZ sequence as the sum of the log cycle increments of bit cycles, called branch metrics, according to the sequence. The basic assumption behind calculating the log likelihood of a sequence as a sum of increments is that the statistical events whose log likelihood correspond to the increments are statistically independent. Statistical independence is achieved by using conventional linear predictive filtering. Where noise and data are correlated, statistical independence is achieved even more strictly by conditioning noise prediction filtering of a given NRZ sequence.

  The basic assumption behind calculating each log likelihood increment (branch metric) as a square difference is that the difference as a random variable takes a Gaussian probability distribution with a mean of zero. Therefore, the bias in the filtered noise sample needs to be subtracted before the square operation.

These considerations lead to the definition of data-dependent filtered, bias-corrected noise statistics as follows. First, the notation of NRZ conditions for noise prediction filtering and bias correction is introduced. Next, the data condition length d is fixed. The partitioning of the set of all 2 ^d length d blocks of bits is fixed to the disjoint set β.
{0,1} ^d = ∪β

Each set β is a bias condition. Another coarser partition of {0,1} ^d is fixed to a relatively prime set α such that each set β is included in a partial set α. Each set α is a filtering condition.
The most important example of the two divisions of {0, 1} ^d into bias and filter conditions is the single set β = {b _{−d + 1} . . . b ₀ },
And each filtering condition includes two exact opposite bit sequences.

Although empirical secondary conditional noise statistics are almost unchanged under polarity reversal, these splits are important in practice because primary conditional bias changes sign under polarity reversal.
Finally, the number of elements in the set α is shown as m (α).

Correlation length c corresponding to the maximum tap delay of the noise prediction filter is also fixed. The equalization target length e is fixed. Here, the ideal equalization samples y _i are respectively NRZ bits b _{i−e + 1} . . . It depends on b _i . To simplify the notation, assume that the data dependency length d ≦ c + e (this is true in practice).

の以下の定式において、ビット・シーケンスｂ_ｉ−d+1．．．ｂ_ｉは

として示される。

ここで

および

は

を満たし、条件共分散行列Ｒ^［α］は以下の式によって定義される。

統計

は、信号依存ノイズ予測フィルタリングおよびバイアス補正後の残差ノイズである。
Ｒ^［α］は、以下の定式で表すことができるので、対称行列であることに留意されたい。

これは、

から得られる。
条件共分散行列Ｒ^［α］が正の定数であると仮定すると、これを反転することができ、続いてノイズ予測フィルタ・タップのベクトル

が（

がスケールを固定するので）一意的に判別される。
データ従属フィルタ処理されたバイアス補正済みノイズのサンプル

が以下の式を満たすことを検証することができる。

各フィルタ条件αごとに、ノイズ予測フィルタ・タップおよび補正バイアスの選択は、次のように、

のすべてのフィルタ・タップ重みの集合に対して、平均値の分散を最小化する。

各バイアス条件βが単一のＮＲＺシーケンスで構成される場合、各フィルタ条件αはＮＲＺシーケンスの正反対のペアから成り、二次ノイズ統計は極性反転のもとで不変である。

従って分散は以下のようになる。

独立条件は、

ノイズ統計（ノイズが多変量ガウス形であることを含む）に関する一定の仮定のもとで統計

が真のＮＲＺ格子状パスに沿ってほぼ独立していることを示す。 Correlation length c, data dependency length d, the equalization target length e, division of {0, 1} ^d to bias condition sets beta, when fixing the coarser division of {0, 1} ^d to the filter conditions set alpha, The branch metric underlying the data dependent filtered biased noise statistics corresponding to the NRZ sequence is:
a _{-c-e + 1} ... a _-1 a ₀
It can be defined as follows:
Let β be a bias condition of a _{−d + 1} ... a ₋₁ a ₀ ∈β,
α is a filter condition of β⊂α.
Data dependent filtered bias correction noise

In the following formulation, the bit sequence b _{i-d + 1} . . . b _i is

As shown.

here

and

Is

And the conditional covariance matrix R ^[α] is defined by the following equation.

statistics

Is the residual noise after signal-dependent noise prediction filtering and bias correction.
Note that R ^[α] is a symmetric matrix because it can be expressed by the following formula:

this is,

Obtained from.
Assuming that the conditional covariance matrix R ^[α] is a positive constant, it can be inverted, followed by a vector of noise prediction filter taps

But(

Is uniquely determined).
Data dependent filtered sample of bias corrected noise

Can be verified to satisfy the following equation.

For each filter condition α, the noise prediction filter tap and correction bias selection is as follows:

The variance of the mean value is minimized for the set of all filter tap weights.

If each bias condition β is composed of a single NRZ sequence, each filter condition α consists of the exact opposite pair of NRZ sequences and the secondary noise statistics are unchanged under polarity reversal.

Therefore, the dispersion is as follows.

Independence condition is

Statistics under certain assumptions about noise statistics (including noise being multivariate Gaussian)

Are almost independent along the true NRZ lattice path.

対数項が無視され、上記の式が

を乗じることにより（α_０は固定の正規化フィルタ条件）正規化される場合、分岐メトリックは以下のように表される。

If these three points are combined, a _{i-d + 1} . . . NRZ sequence a _{i−c−e + 1 with} a _i−1 a _i ∈β⊂α. . . It discusses that the log likelihood increments corresponding to the branches with a _i-1 a _i are represented using the following (negative) log probabilities:

The log term is ignored, and the above formula becomes

When normalized by multiplying (α ₀ is a fixed normalization filter condition), the branch metric is expressed as:

正規化バイアス

をフィルタ出力から差し引いて、最後に二乗演算を行う。要約すると、ｂ_ｉ−d+1．．．ｂ_ｉ−１ｂ_ｉ∈β⊂αであるＮＲＺシーケンス

に対応する分岐メトリック

は、以下の式によって求められる。

本発明は、分岐メトリック

のこの計算に使用される正規化ノイズ予測タップ重み

および正規化バイアスμ^［β］を判別する自己適応回路１００を提供する。
分岐メトリック計算のためのタップ重みおよびバイアスの生成 In practice, the normalization condition α ₀ is selected to minimize δ ^[α] .
This branch metric can be calculated in hardware by setting the tap weights to normalized noise prediction filter coefficients (such as tap weights) and first filtering the noise estimate using FIR: ,

Normalization bias

Is subtracted from the filter output and finally the square operation is performed. In summary, b _{i−d + 1} . . . NRZ sequence with b _i-1 b _i εβ⊂α

Branch metric corresponding to

Is obtained by the following equation.

The present invention provides a branch metric

Normalized noise prediction tap weight used for this calculation of

And a self-adaptive circuit 100 for discriminating the normalized bias μ ^[β] .
Generation of tap weights and biases for branch metric computation

にそれぞれ集束する累算レジスタ３００、５００を含んでおり、これらが前述の分岐メトリック

を計算するために使用される。 FIG. 1 is a block circuit diagram illustrating an adaptive circuit 100 for determining a branch metric filter and bias according to the present invention. In general, the adaptive circuit 100 includes a normalized bias μ ^[β] and a normalized noise prediction tap weight.

Includes accumulating registers 300 and 500, respectively, which focus on the branch metric described above.

Used to calculate

は、（従来の線形ノイズ予測の場合のように固定されるのではなく）対応する遅延０のタップが

に固定されたままの単一の正規化条件α_０の場合を除いて各フィルタ条件αに適合する。 As shown in FIG. 1, an exemplary implementation of adaptive circuit 100 includes three positive delay filter taps 400-1 through 400-3, which are described below with reference to FIG. Further explanation will be given. In other words, the correlation length c is equal to 3. The adaptation circuit 100 is implemented as a noise prediction FIR modified herein to provide several new features and functions. In accordance with the data dependency feature of the present invention, the filter tap weights of filter taps 400-1 through 400-3 and the correction bias of bias correction block 200 used in any update cycle (see FIG. 2 below). Will be further explained) is controlled (multiplexed) by estimating NRZ data in accordance with noise prediction. In accordance with the bias correction function of the present invention, the output of the filter is corrected by a bias cancellation circuit in a filter tap weight matching loop. According to the conditional distributed normalization function of the present invention, the tap weight with zero delay

Is the corresponding delay zero tap (rather than being fixed as in the case of conventional linear noise prediction)

Each filter condition α is met except in the case of a single normalization condition α ₀ that remains fixed at.

  The adaptive noise prediction block 100 includes a plurality of delay elements 150, a multiplier 160, and an adder 170 that operate in a conventional manner to properly align the various data elements and integrate the values from each cycle. Yes.

Once the tap weights and biases generated by the adaptive noise prediction block 100 of FIG. 1 have converged (reached equilibrium), these are the circuits (not shown) that actually calculate the signal dependent noise predicted bias corrected branch metric. ). For an exemplary circuit for calculating such a signal dependent noise predicted bias corrected branch metric, see, for example, A.S. Kavic, “Decision Feedback Equalization in Channels with Signal Dependent Media Noise”, IEEE Transactions on Magnetics, Vol. 37, 1909-11 (2001), 94, 1909-11 (2001).
Data dependency and bias correction

との間の差分として計算される。

As shown in FIG. 1, the adaptive noise prediction block 100 includes a noise prediction n _i and four consecutive NRZ predictions b _i−3 b _{i− 2} . . . b _i is received. The noise predictions n _i and NRZ predictions are matched as usual, where n _i is equalized sample y _i and target [t ₀ t ₁ . . . . . . the opposite NRZ convolved in t _e-1 ]

Is calculated as the difference between

The NRZ stream functions as a control signal for the tap update blocks 400-1 to 400-3 and the bias correction block 200.
As mentioned above, the correction bias of the bias correction block 200 used in any update cycle is controlled (multiplexed) according to the present invention by estimation of NRZ data correlated with the data and matched to noise prediction. ). FIG. 2 is a circuit block diagram showing the bias correction block 200 of FIG. 1 in more detail.
The bias correction block 200 implements data dependent offset control. Bias correction block 200 to zero respectively the conditional mean value of the error signal e _i. Therefore, in the equilibrium state:
E (e _i | b _{i−d + 1} ... B _i ∈β) = 0, (β).

  The bias correction block 200 can be implemented as a separate accumulator (read and exchange function) for each bias condition β. In an exemplary embodiment where the data dependency d is 4 bits each with two potential values, there are 16 distinct bias conditions β and there are 16 accumulation registers 300, for which FIG. Is described further below. Since only one bias condition β lasts any bit cycle, the accumulators can share a single adder 210 for accumulation, and the multiplier 220 can be shared for gain control. .

を読み取り、加算器２１０および乗算器２２０を使用してレジスタ内の値を更新済みバージョン

に置き換える。 FIG. 3 is a circuit block diagram illustrating the 16 register read and exchange accumulator 300 of FIG. 2 in further detail. The appropriate register to update, ie b _{i = d + 1} . . . The selection of the register corresponding to the bias condition β of b _i εβ is such that when d = 4, the NRZ bits b _{i−d + 1} . . . It is controlled by a block of b _i. The “read and exchange” circuit 300 is from an appropriate register 320 (indexed by a block of NRZ bits b _{i−d + 1} ... B _i ).

, And use adder 210 and multiplier 220 to update the value in the register

Replace with

  As mentioned above, the exemplary implementation of adaptation circuit 100 includes three positive delay filter taps 400-1 through 400-3. FIG. 4 is a circuit block diagram illustrating an exemplary positive delay filter tap 400. In general, the positive delay filter tap 400 implements a separate accumulator for each filter condition α. As described above, if each bias condition β is composed of a single NRZ sequence, each filter condition α is composed of the opposite pair of NRZ sequences. Due to the symmetry property, the filter condition α associated with the 16 distinct bias conditions β in the exemplary embodiment can be folded twice into 8 distinct filter conditions α (see FIG. 7). (See also description below). For example, bit patterns 0110 and 1001 share the same noise condition, and the corresponding filter condition α can be folded into a single condition. Since only one filter condition α lasts an arbitrary bit cycle, the eight accumulators share a single adder 410 for accumulation and the multipliers 420, 430 share noise prediction, An accumulated increment can be calculated based on the error and gain factors.

は、加算器４１０および乗算器４２０、４３０を使用して以下のように更新される。

続いて、平衡状態において以下のようになる。
Ｅ（ｎ_ｉ−ｊｅ_ｉ｜ｂ_{ｉ−ｄ＋１}．．．ｂ_ｉ∈α）＝０，（１≦ｊ≦ｃ） FIG. 5 is a circuit block diagram illustrating the 8-register dual read single write accumulator 500 of FIG. 4 in further detail. The choice of which accumulator to update is via multiplexor 510 and demultiplexer 530, NRZ blocks b _{i-d + 1} . . . controlled by b _i . Multiplexer 510 and demultiplexer 530 have bi _{-d + 1} . . . Select a filter condition α where b _i εα. Register value of delay j tap

Is updated using adder 410 and multipliers 420, 430 as follows.

Subsequently, in the equilibrium state:
E (n _i−j e _i | b _{i−d + 1} ... B _i εα) = 0, (1 ≦ j ≦ c)

を使用して計算されるように調整されていることに留意されたい。さらに、「ａｄａｐｔ ｓｅｌ」信号の遅延は、タップ重み

が更新される条件αが、更新に使用されたフィルタ出力サンプルの計算でタップ重みを選択するために以前のｊサイクルで使用されたものと同じ条件であるように調整されることにも留意されたい。
前述のように、遅延０のフィルタ・タップ６００の遅延０のタップ重み

は、図６に示すように、（従来の線形ノイズ予測の場合のように固定されるのではなく）対応する遅延０のタップが

に固定されたままの単一の正規化条件α_０の場合を除いて各フィルタ条件αに適合する。図６は、典型的な遅延０のフィルタ・タップ６００を示す回路ブロック図である。図６に示すように、ブロック６００によって実装される適合ループは、各条件α≠α_０に対する遅延０のタップ重み

を以下の安定した値にする。

再び、正規化条件ａ_０の遅延０のタップ重み

は、値１で固定される。他の各々の条件に対する遅延０のタップ重み

は、負とならないように制約される（飽和される）のみである。この制約は、望ましい安定点の負となるαに対する第２の望ましくない安定点を禁止する。 As shown in FIG. 5, the choice of which accumulated value to use as the tap weight for noise filtering is the various delayed versions of the four NRZ bit blocks labeled “tap wt sel” in FIG. Controlled by. The relative delay between “tap wt sel” and “adapt sel” is shown in FIG. In particular, the “adapt sel” signal controlling the tap block with delay j (and noise prediction) (1 ≦ j ≦ c) is compared to the “tap wt sel” signal controlling the same tap block. Delayed by j bit cycles (using delay element 145). The delay of the “tap wt sel” signal is the tap weight where all the addends contributing to a single filter output sample correspond to a single condition α.

Note that it has been adjusted to be calculated using In addition, the delay of the “adapt sel” signal is the tap weight.

Note also that the condition α at which is updated is adjusted to be the same condition used in the previous j cycle to select the tap weights in the calculation of the filter output samples used for the update. I want.
As described above, the delay 0 tap weight of the delay 0 filter tap 600

As shown in FIG. 6, the corresponding delay zero tap (rather than being fixed as in the case of conventional linear noise prediction)

Each filter condition α is met except in the case of a single normalization condition α ₀ that remains fixed at. FIG. 6 is a circuit block diagram illustrating a typical zero delay filter tap 600. As shown in FIG. 6, the adaptation loop implemented by block 600 is a _zero- delay tap weight for each condition α ≠ α0.

Is set to the following stable value.

Again, tap weight of delay 0 of normalization condition a ₀

Is fixed at the value 1. Tap weight with zero delay for each of the other conditions

Is only constrained to be negative (saturated). This constraint prohibits a second undesired stable point for α, which is the negative of the desired stable point.

さらに、μ_ｉ＋１は負とならないように飽和される。
μ_ｉ＋１≧０
したがって、μ_ｉは、

の場合にサイクルｉに制約された｜ｅ_ｉ｜のローパス・バージョンである。正規化条件α_０に対する｜ｅ_ｉ｜のこのフィルタリングにより、その平均値からのμ_ｉの変動が｜ｅ_ｉ｜と弱く相関するだけになっている。さらに、これは平衡状態においてμ_ｉの更新計算式から得られる。

読み取りおよび交換レジスタ６７０は、加算器６２０、乗算器６３０およびマルチプレクサ６４０と共に、条件α≠α_０の遅延０タップに対応するレジスタ値

に対する以下の更新計算式を実装する。

読み取りおよび交換レジスタ６７０は、図３を参照して前述されているレジスタ３００に対しても同様の方法で実装できることに留意されたい。これは平衡状態において以下の更新計算式から導かれる。

これは、

および、ノイズが多変量ガウス形であるという前提と共に、フィルタ条件αおよびα_０に対するフィルタ処理されたバイアス補正ノイズｅ_ｉの等しい条件付き分散をもたらす。

適応回路の変形 The circuit 600 implements the following update formula: In FIG. 6, μ _i is the register value held in the register 610 labeled “abs accum”. The update calculation formula of μ _i implemented using the register 610, the adders 615 and 650, the multiplexer 640, and the multiplexer 625 is as follows.

Furthermore, μ _{i + 1} is saturated so as not to be negative.
μ _{i + 1} ≧ 0
Therefore, μ _i is

Is a low-pass version of | e _i | constrained to cycle i. This filtering of | e _i | relative to the normalization condition α ₀ ensures that the variation of μ _i from its average value is only weakly correlated with | e _i |. Furthermore, this is obtained from the update formula of μ _{i in} the equilibrium state.

Reading and exchange register 670, adder 620, multiplier 630, and with a multiplexer 640, a register value corresponding to the delay 0 tap condition alpha ≠ alpha ₀

Implement the following update formula for.

Note that read and exchange register 670 can be implemented in a similar manner to register 300 described above with reference to FIG. This is derived from the following update formula in the equilibrium state.

this is,

And, with the assumption that the noise is multivariate Gaussian, results in equal conditional variance of the filtered bias correction noise e _i for filter conditions α and α ₀ .

Adaptation circuit deformation

  In this section, a minor modification of the adaptive circuit 100 that allows the dependent length d to be programmable from d = 0 to a maximum value is described. In practice, the dependency length needs to be programmed to be a minimum that saturates the performance gain provided by data dependency with increasing detail. There are two advantages to doing this. The first is that each time d is decremented by 1, the adaptation time is shortened to almost half. Second, if d exceeds the true data dependency window of noise and distortion, the difference between the fits for the two conditions with the same statistics is due to the fit noise. Such a difference only reduces performance.

  FIG. 7 shows that eight typical filter conditions α (each consisting of diametrically opposite pairs of length 4 NRZ sequence) are reduced in pairs as d is decremented by 1 starting at d = 4 It is the table | surface 700 which shows a process.

Note that the control lines that control the multiplexer and demultiplexer in FIGS. 3, 5 and 6 include a bus of four consecutive delays of binary NRZ estimation. FIG. 8 is a control circuit 800 showing a programmable number of conditions (d = 4 to d = 0). FIG. 8 shows the changes to these four delays located upstream from the multiplexer and demultiplexer. The programmable number of the oldest bits is forced to zero, so that the corresponding subset of the accumulation registers in the adaptation circuit is used during adaptation.
In one typical application, the adaptation circuit serves to adjust the parameters used in the Viterbi detector. In another application, the adaptation circuit serves to adjust parameters used in a post processor that operates based on the initial NRZ prediction generated by the Viterbi detector.

  It will be understood that the embodiments and variations described herein are merely illustrative of the spirit of the invention and that various changes may be made by those skilled in the art without departing from the scope and spirit of the invention. I want. For example, the present invention can be implemented in applications such as a magnetic recording system, a general Ethernet (registered trademark), particularly a next-generation 10 gigabit Ethernet (registered trademark) using a copper wire system, and wireless communication.

FIG. 6 is a block circuit diagram illustrating an adaptation circuit that determines the prediction filter tap weights and biases required to calculate a branch metric according to the present invention. FIG. 2 is a circuit block diagram showing the bias correction block of FIG. 1 in more detail. FIG. 3 is a circuit block diagram illustrating the exemplary 16 register read and exchange accumulator of FIG. 2 in further detail. FIG. 2 is a circuit block diagram illustrating the exemplary positive delay filter tap of FIG. FIG. 5 is a circuit block diagram illustrating the exemplary 8-register dual read single write accumulator of FIG. FIG. 2 is a circuit block diagram illustrating the exemplary delay zero filter tap of FIG. 1. 8 is a table showing a process in which eight typical filter conditions α are reduced in pairs every time the data dependent parameter is decremented. FIG. 5 is a control circuit showing a programmable number of data dependents. FIG.

Claims (8)

A method for determining a plurality of filter tap weights used to generate one or more branch metrics, comprising:
Accumulating a plurality of sets of adaptive filter tap weights, each set of adaptive filter tap weights corresponding to a data pattern , wherein at least one of the set of adaptive filter tap weights comprises: response to Ru is updated, methods in occurrence of the defined data pattern before the occurrence of the step of the accumulation. The method of claim 1, wherein the accumulating step further comprises selecting one of the accumulated filter tap weights to update based on the occurrence of the data pattern .   The method of claim 1, further comprising providing the accumulated matched filter tap weights to a Viterbi detector for calculating the one or more branch metrics.   The method of claim 1, further comprising providing the accumulated matched filter tap weights to a post processor that operates based on an initial NRZ data prediction generated by a Viterbi detector. An adaptive noise prediction circuit that determines filter tap weights used to generate one or more branch metrics;
A register for accumulating a plurality of sets of adaptive filter tap weights, each of the sets of adaptive filter tap weights corresponding to a data pattern , wherein at least one of the set of adaptive filter tap weights is: wherein in response to generation of a data pattern that is defined before the occurrence of cumulative to process and Ru are updated, conform noise prediction circuit. 6. The adaptive noise prediction circuit of claim 5 , further comprising a multiplexer that selects one of the accumulated filter tap weights to update based on the occurrence of the data pattern . 6. The adaptive noise prediction circuit of claim 5 , further comprising a shared adder that adds a previous value of the filter tap weight to a current value of the filter tap weight for each of the data patterns . 6. The adaptive noise prediction circuit of claim 5 , further comprising a register that accumulates an adaptive filter bias for each data pattern .

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