JP5216130B2 - A device to accelerate the processing of the extended primitive vertex cache - Google Patents

Description

  The present invention relates to the field of three-dimensional computer graphics. More particularly, the present invention relates to a method and system for processing information at high speed in hardware for geometric primitives with many complex vertices, referred to herein as extended primitives.

  Traditionally, interactive computer graphics approximate simple complex geometric shapes and use simple geometric primitives such as points, lines, and triangles. Existing computer graphics hardware is optimized to speed up the processing of such simple primitives, especially triangular meshes. Primitive simple triangles are the simplest polygons that can be used for linear approximation of 3D surface fragments. Various triangles, lines, and points can be approximated to fairly complex shapes. Currently existing hardware designs can greatly benefit from the possibility of independently processing the vertices of primitives in their series from each other.

  The need for complex multi-vertex primitive processing occurs in various areas of 3D computer graphics. In effect, many complex shapes are modeled with higher order plane primitives such as NURBS patches and subdivision surfaces. In either case, the coarse control mesh and rule set is used to generate a shape that is smooth, fine, and easily deformed by affecting the control mesh. Usually, the patch itself is formed by a variable size set of vertices of the control mesh, as well as additional information that controls the tessellation process. Enabling NURBS or subdivision surface patch tessellation in hardware greatly reduces shape manipulation storage, bandwidth requirements, and simplicity, as a result of which interactive 3D graphics can greatly benefit . Another set of algorithms requires access to a more complex part of the processing form than just a single triangle in the approximation at a time. Usually, access to some limited neighboring vertices of a triangle is necessary to detect silhouette edges, such as curvature at mesh vertices.

  Support for processing complex primitives is difficult among existing 3D graphics accelerator structures for several reasons. When access is limited to three vertices only for simple triangles, the processing of complex primitives immediately requires fast access to multiple vertices for processing algorithms. If the attribute data for the vertices of a complex of primitives such as those used for subdivision surfaces and NURBS patches are scattered across the memory, the processing algorithm can be used because access results in significant latency in data transfer. May be low performance. Optimize the programmable processing elements of the current programmable architecture's geometric pipeline to process a single vertex at a time. It then assembles primitives from a sequence of vertices with fixed logic (which can't be manipulated on any other primitive type, but simple).

  The kernel structure of 3D graphics hardware accelerators available for personal computers and workstations also adapts in some cases with fast processing and representation of simple primitive lists such as triangles, lines, and points. FIG. 1 shows a portion of a typical 3D graphics hardware accelerator pipeline. The list of primitives is described by an index buffer 1100 and a vertex buffer 1200. Typically stored in the host machine memory 1000, the index and contents of the vertex buffer are illustrated in FIGS. 2A and 2B. In the case of FIG. 2A, possibly a set of triangles 101 sharing a vertex is represented by a set of vertex data continuously packed in the vertex buffer 1200 and the index buffer 1100. In the case where the latter content references vertices by the vertex buffer and the index buffer triangle set 101, position 3, 1100 defines a triangle. If the next three positions define the next triangle, etc. in set 101, and most of the vertices in vertex buffer 1200 are reused, at which point the reused vertex in vertex buffer 1200 Triangle set surrogates can be fairly compact when vertex data marked with a dotted padding pattern usually requires much more accumulated space than the index buffer. Referring to FIG. 2B, the representation is more concise in the case of the triangle piece 102. In this case, the vertices taken with the previous two vertices referenced in the index buffer form a triangle. As a result, only one index is needed to define further triangles after the first is processed. The contents of the index buffer describe the triangle set more effectively in this case with respect to the number of index lists per triangle. Using the index and vertex buffer, a similar method can be described in which a set of line segments is defined with two vertices and a set of tips defined by one vertex per point.

  A vertex cache device is used to accelerate the processing of a set of defined primitives by using an index and a vertex buffer. According to FIG. 1, the contents of the index buffer 1100 are not only used to extract the vertex buffer 1200, but are also used to detect if a vertex with the same index has recently been processed, in the cache. It may still be available. The vertex cache controller 2000 acquires the contents of the index buffer 1100 and analyzes it. Initially, since the cache is empty, the vertex cache controller initializes delivery of vertex buffer contents including vertex data for the index list obtained from the index buffer 1100 to the first vertex cache 3000. Typically, memory access potential penalties are obtained from the vertex buffer in a manner that minimizes a relatively large contiguous memory block that can contain vertex data correspondences that are not currently processed by the vertex cache controller only into the index list. Nevertheless, it is retained in the first vertex cache 3000 because it may be used later by the indexed index list. If the vertex data caches 3000 because the index is already at the first vertex, no host memory access is performed.

Usually, the vertex data sent to the first vertex cache 3000 needs to be converted.
For example, vertex positions may need to be converted from one coordinate system to another. Vertex color is calculated based on standard, position, etc. The vertex cache controller 2000 controls the delivery of vertex data from the first vertex cache to the vertex processor 4000. The converted vertex data is delivered to the secondary vertex cache 5000. From the secondary vertex cache 5000, the transformed vertex data is used to form a fixed set of primitives, such as triangles, lines, and points, from the vertex sequence, and the processing pipeline with the triangle setup 7000 and rasterizer 8000 fixed. The remaining primitives are assembled and the fixed primitive assembly 6000 is reached. Since the index presents it in the secondary vertex cache 5000, it delivers the vertex data transformed to any other to the primitive assembly 6000 without overhead.

  Design hardware capable of processing such primitives on the chip for the benefit that accelerated processing of hardware for extended primitives can be introduced in particular in complex shaped models and image fields However, a great effort was intensified. Introducing completely different hardware, including subdivision surface on chip and NURBS surface tessellation, but nevertheless dedicated to the task of processing complex primitives in question or existing structures Attempted to use programmable elements in Simple primitive-only constants and traditional architectures are still limited by support for the absence of primitive generation facilities.

  WO 03/081528 describes a complex structure with the possibility of reusing its hardware for any other purpose or sharing devices for simple primitive processing. Dedicated hardware unit to process special description of control mesh on subdivision surface with a lack of need to prepare for, describing connectivity information for control mesh in a form suitable for hardware processing Has been. A similar approach is also disclosed in US Patent Application No. 2005/0012750 (Patent Document 2), which realizes accelerated processing with the hardware of the NURBS patch.

  With the introduction of programmable 3D acceleration hardware, some attempts were made to perform complex primitive processing with it. Nevertheless, an effective implementation has not been realized with commercially available hardware when the primitive is not limited to the generation of any primitive, even though it is still simple to process.

  One problem with processing extended primitives in the case of random access, vertex data, especially in the case of subdivision surface tessellation, is providing the necessary information to the processing algorithm. Random memory access is currently expensive with existing hardware and is possible only in limited places in the processing pipeline. The most versatile capability currently in existing hardware is related to mesh sampling that can be controlled by vertices or fragment programs with programmable hardware. For the usefulness of random memory access on a per-mesh basis, the implementation obtains mesh connectivity information packed into the mesh. In the case of dedicated tessellation hardware, special mesh representations that allow the acquisition of the information necessary to implement the tessellation algorithm are used with high preparation drawbacks to maintain cost. Another current device in traditional architectures that allows random memory access is the vertex cache.

WO03 / 081528 brochure US Patent Application Specification 2005/0012750

  The present invention addresses on-chip processing related to extended geometric primitives such as subdivision surface patches, NURBS patches and adjacent triangles used as input information in algorithms used in 3D computer graphics. The purpose is to solve. Such algorithms include Catmull-Clark loop, which is a 4-3 subdivision scheme, NURBS surface segmentation, silhouette discovery, and triplet vertices to construct triangles, which are the simplest planar geometric primitives. Various schemes implemented in known computer graphics, such as algorithms that require

  Information processing on geometric primitives fully extended on chip leads to the rapid rendering of complex geometric shapes. Furthermore, it leads to obtaining more realistic images using computer graphics, and also to obtaining primitives that are directly extended using simple primitives such as triangles.

  The size of primitives in current 3D computer graphics is fixed. For example, there are three vertices in the case of a triangle, two vertices in the case of a straight line, and one vertex in the case of a point. On the other hand, in the extended primitive used especially in the case of subdivision of the surface patch, the size of the primitive can be arbitrary. When using extended primitives in a reasonable range and at the maximum range, primitives with various numbers of vertices are required to be realized on the chip.

  The next problem is the difficulty of achieving random memory access, particularly used when processing information using extended primitives. The vertex data constituting the primitive can be distributed and stored in the storage unit as in the simple primitive. The problem here is the number of vertices in the extended primitive, which is several times larger than usual, and it may be necessary to access memory randomly to fetch only the corresponding vertex data. It is. Random access in graphics devices is limited to creating serious defects if not properly cached, and is typically used only for devices related to vertex caches and texture sampling.

  If only simple geometric primitives such as triangles are used effectively using hardware, the number of gates cannot be reduced, resulting in a problem of complicating the chip configuration. Even if the logic circuit for drawing the extended primitive is provided separately from the processing circuit for the simple primitive, the configuration of the chip is complicated. Therefore, if simple primitives and extended primitives can be processed by a single processing system instead of separate processing circuits, the problem that the chip becomes complicated can be solved.

  In addition, there are problems in expressing extended primitives. In order to unify the processing and APIs, ie application programming interfaces, for simple primitives and extended primitives as widely used for various types of extended primitives, the storage capacity is reduced as in simple primitives. It is desirable to reduce the data transfer rate. Hereinafter, how the present invention has solved the above-described problems will be described.

  In the present invention, basically, an index is assigned to each vertex, the index is stored in the index buffer, the vertex in the primitive is expressed using the stored index, and the vertex information associated with the index is then displayed in the vertex buffer. Is used for primitive processing. Further, regular primitives such as triangles and quadrilaterals are used as normal primitives, but the present invention also uses primitives with more than four vertices, although these regular ones are used. Such primitives with a variable number of vertices and more than usual are called extended primitives of variable size. In the present invention, when vertex information related to a certain primitive is input, it is determined whether the primitive is a normal primitive or an extended primitive of variable size. This determination can be easily made based on the number of vertices in one primitive. In the case of a normal primitive, the arithmetic processing may be performed in the same manner as usual by using a device similar to the normal one. On the other hand, in the case of an extended primitive of variable size, the index of the polygon that becomes the center is read, and then the index of the polygon that is adjacent to the triangle or the rectangle that becomes the center is read. After that, the vertex data related to these indexes is acquired, and the arithmetic processing for assembling the primitive is performed. The system of the present invention includes a vertex engine that receives various types of information from a computer and converts information about vertices, and a primitive engine that receives vertex information converted from the vertex engine and assembles primitives. The primitive assembled by the primitive engine is rasterized by a rasterizer, stored as a three-dimensional computer graphics in a frame buffer or the like, and rendered on a monitor or the like. Vertex conversion means arithmetic processing such as viewpoint conversion for vertices. Regardless of whether the primitive is a point, a line, a triangle, or a polygon greater than a quadrangle, an arithmetic process necessary for vertex information is performed. Primitive assembly means that converted individual vertices are assembled into a primitive. After the primitive assembly, individual processing is performed for each primitive. In the present invention, the primitive may include a variable size. When the primitive size is 3, as in the case where the primitive is a triangle, the index table may be accessed every multiple of 3. Therefore, the device only needs to remember the number 3 and does not need to be described. However, in the present invention, since the primitive size can be changed for each primitive, it is difficult to understand how far the next primitive is. Therefore, in the present invention, it is preferable to always describe so that the following elements constitute the primitive. In the present invention, the primitive size is described in the index table. When there are a plurality of index tables that are a preferred aspect of the present invention, it is preferable to describe the primitive size in the index table including the position attribute.

In order to draw more objects, it is preferable to reduce the number of vertices. For example, consider drawing a vertex adjacent to each triangle primitive and drawing two adjacent triangles. The first triangle is composed of (v ₁ , v ₂ , v ₃ : where v _m is (x _m , y _m , z _m )), where the vertex is v _m , and the color of each vertex is red , White and yellow. Since the second triangle adjacent to the first triangle shares p ₂ and p ₃ , it can be described as (v ₂ , v ₃ , v ₄ : where p ₄ is blue). Then, although there are actually only four vertices, a description about six vertices is required. That is, although this method is simple, a description of 3 × n vertices is required to draw n triangles. That is, since a large number of vertices have to be described, a large amount of memory is consumed. Next, a case where a triangle strip is used will be described. In this drawing method, after describing the vertex of the first primitive, the description about the shared vertex is used when the next primitive is described. For example, if the primitive is a triangle, the next triangle is drawn with the condition that two vertices of the previous triangle are used. That is, of the vertices of the triangle described above, the vertices excluding the top vertex are the two vertices of the next triangle, and the next triangle is expressed using another vertex. This method can greatly reduce the memory cost. However, it is still necessary to describe 2 × n or more vertices to draw n triangles.

In the present invention, an index table is used to express (v ₁ , v ₂ , v ₃ : where v _m is (x _m , y _m , z _m )). Instead, information such as (v ₁ , v ₂ , v ₃ ) is simply stored, and by using this information, each vertex information (for example, v ₁ is (x ₁ , y ₁ , z ₁ ) and is called red Information). That is, the index is stored in the index table so that one triangle is formed by v ₁ , v ₂ , v ₃ and the next triangle is formed by v ₂ , v ₃ , v ₄ . Since an index table that can read out vertex data from the vertex buffer or the like of the vertex engine is used in this way, one vertex only needs to be described once, and as a result, the amount of vertex description can be reduced. On the other hand, in this method, it is necessary to describe an index. The width of the index table differs depending on the primitive, and is 3 if the primitive is a triangle. In this method, since one vertex is shared by multiple triangles, it is necessary to repeatedly deliver information about one vertex. It is normal to have one index table, which is sufficient under most circumstances. In fact, the OpenGL / ES interface has only one index table. However, some interfaces have independent index tables for vertex attributes, such as XYZ coordinates (position attributes), colors (vertex color attributes), and texture coordinates (texture attributes). A famous example of such an interface is Direct3D.

  The subject matter of the present invention relates to the use of vertex cache facilities in a suitable graphics accelerator to allow processing of extended geometric primitives. This is a device added in comparison with the prior art, and represents the primitive engine (primitive engine) used for assembling and processing the extended primitive proposed in the present invention and the extended primitive. This is accomplished by using a combination of an extended index / vertex buffer to represent the polygon mesh used for the purpose.

  In the present invention, the extended primitive is represented based on an extended index / vertex buffer for representing a polygon mesh. There are currently three-dimensional graphic libraries such as Direct3D and openGL, and a method for rapidly processing a polygon mesh using such a representation using hardware is provided. In the representation process, the vertex buffer stores vertex attributes at each vertex of the polygon mesh being processed, while the contents of the index buffer contain mesh connection information. The index buffer includes a description related to a polygon string of the same size associated with a vertex number constituting an index string indicating the contents of the vertex buffer. For example, an index string belonging to a polygon describes a vertex string of the polygon by referring to vertex data in the vertex buffer, and a polygon edge string formed by continuous connection of the vertices in the polygon. In the present invention, an index buffer can be used in the same way as an extended primitive sequence having a certain size. An index buffer that stores index values that have been previously fixed to other indices that reference the vertices that form the extended primitives of various sizes along with the primitive size to represent the extended primitives of various sizes Used.

  The problem described above can be solved by improving the index buffer and the vertex buffer in order to perform the arithmetic processing related to the extended primitive. Extended primitives of different sizes and fixed sizes that must specify the number of vertices, which is the number of additional vertices, in the vertex list via an index stored only in the extended primitive or index buffer Or enough to represent variable size extended primitives of different sizes. The creation of size, vertex list, and certain special types of primitives is done by the primitive creation algorithm itself, so the representation is independent of the primitive size. This is similar to the representation of simple primitives. From the point of view of the graphic library, the representation is the same as that for simple primitives, and even if the primitive sequence is expanded compared to the case of processing simple primitive sequences, a large change is required in the API. This reduces the required memory.

  This representation can reduce memory costs when vertices are shared between primitives whose vertices are stored only once in the vertex buffer. As with simple primitives, referencing an index requires much less memory space.

  The present invention uses a combination of a vertex cache and a primitive engine in order to quickly compute a hardware extended primitive. The vertex cache enables access with a short waiting time to the vertex that has just been processed. In the case of the expression by the index buffer and the vertex buffer, the vertex index can be used as the cache tag. Therefore, if the vertex index is the same as that in the cache, the one stored in the latter is used for further computation. The present invention preferably also uses the vertex cache for arithmetic processing of extended primitives.

  Since simple primitives and extended primitives have similar expressions, vertex caches can be used for extended primitives with low latency access to vertices that have been processed immediately before, as in simple primitives. This eliminates performance degradation due to many random accesses required when fetching the extended primitive vertex data. Also, since the same vertex cache hardware is used in the arithmetic processing of simple primitives and extended primitives, the hardware size can be reduced. In addition, since the vertex cache is used, there is no upper limit on the maximum size of the extended primitive. In addition, the vertex cache is used for vertices in fixed size extended primitives as well as vertices in variable size extended primitives. However, effective arithmetic processing can be performed by performing arithmetic processing on primitives having vertex data in the vertex cache in which a reasonable upper limit is set on the maximum size of the extended primitive that performs arithmetic processing. As a result, it is possible to solve a problem in processing a fixed-size or variable-size extended primitive larger than a simple primitive.

  In the present invention, the assembly and operation processing of the extended primitive are processed by a primitive engine which is a module added to conventional hardware. This module receives input information in the form of transformed vertex data for each vertex of the extended primitive from the vertex cache, and additionally receives size information about variable size extended primitives from the cache controller .

  The primitive engine executes an extended primitive arithmetic processing algorithm. The algorithm interprets the extended primitive vertex sequence and outputs the computed result as a simple primitive sequence. This can solve the following problems. The first is versatility when processing extended primitives. In the case of being controlled and programmable by the primitive engine, any extended primitive can be realized by using the expression by the extended index buffer and the vertex buffer proposed by the present invention. Provides quick access to data. Since it connects directly to the vertex cache, the latency problem of assembling extended primitives and obtaining vertex data for processing is greatly reduced. Reusing the pipeline for arithmetic processing and performing arithmetic processing on the extended primitive chip also contribute to this. Since the operation result for the extended primitive is a simple primitive sequence and is directly supported by the result of the operation pipeline, the extended primitive sequence is directly used for the simple primitive sequence without using the operation result to the host computer. Therefore, the problem of performing arithmetic processing only on the chip can be solved.

  By using a combination of extended index / vertex buffer representation, minor modifications to the vertex cache logic that computes simple primitives, and the primitive engine, fixed size extended primitives and variable size extended It is possible to perform arithmetic processing on a chip for subdivision surface rendering that does not exist in current three-dimensional graphics hardware such as NURBS tessellation.

FIG. 1 shows a conventional hardware architecture of a vertex cache device. FIG. 2A shows an index / vertex buffer layout for sampling a triangle row. FIG. 2B shows the index / vertex buffer layout for sampling a triangle strip sequence. FIG. 3 shows the vertex cache of the architecture in the present invention. FIG. 4A shows a triangle and its neighboring fixed size extended primitives. FIG. 4B shows a triangle and its neighboring fixed-size extended primitive strip sequence. FIG. 4C shows a fixed size extended primitive index / vertex buffer layout of the triangle and its neighbors. FIG. 4D shows the index / vertex buffer layout of the triangle and its neighboring fixed-size extended primitive strip sequence. FIG. 5A shows a fixed-size extended primitive fan sequence around a triangle and its neighbors. FIG. 5B shows the silhouette structure of the edge-based flap. FIG. 5C shows the index / vertex buffer layout of a fixed-size extended primitive fan array of triangles and their neighbors. FIG. 6A shows a variable-size extended primitive. FIG. 6B shows a Catmull-Clark subdivision patch with variable size extended primitives. FIG. 6C shows the index / vertex buffer layout of the Catmull-Clark subdivision patch with variable size extended primitives. FIG. 7 shows the communication path between the vertex cache controller, the primitive engine and the fixed size primitive integrated circuit introduced by the present invention. FIG. 8A shows a rendering result when silhouette detection and visualization are not performed. FIG. 8B shows a rendering result when silhouette detection and visualization are performed. FIG. 9A shows a rendering result of the wire frame shape when the re-division is not performed. FIG. 9B shows a rendering result of the wire frame shape when the re-division is performed. FIG. 10A shows the rendering result of the wire frame when the subdivision is not performed, and the inside of the box shows the coarse elements of the mesh. FIG. 10B shows the rendering result of the wire frame when the subdivision is performed, and the inside of the box shows the coarse element of the mesh that is smoothed during the subdivision. FIG. 11A shows a rendered image when no re-division is performed. FIG. 11B shows a rendered image when re-division is performed.

101 simple triangle row
102 simple triangle strip row
103 Simple triangle with adjacent primitives
104 Simple triangle strip sequence with adjacent primitives
105 Simple triangle with adjacent primitive fan train
106 Catmull-Clark subdivision surface patch group
107 Catmull-Clark Mosaic of subdivided surface patches
110-115
Mesh fragment triangle
210 Cache Destination Multiplexer
220 Fixed Size Primitive Integrated Circuit Unit Source Multiplexer
1000 host memory
1100 Index buffer
1200 vertex buffer
2000 Vertex cache controller
2100 vertex counter
2300 Information transfer path for exchanging vertex delivery completion signals between the vertex cache controller and the primitive engine
3000 vertex cache storage
4000 vertex processing units
5000 Second vertex cache storage
6000 fixed size primitive integrated circuit unit
7000 fixed size primitive setup unit
8000 Primitive Rasterizer
9000 primitive engine
9100 Primitive size register

  Hereinafter, embodiments of the present invention will be described. The present invention basically relates to on-chip processing of complex geometric primitives (also called extended primitives) formed by a fixed or variable number of vertices.

  A first aspect of the present invention is a three-dimensional computer graphic that describes a simple primitive and describes a variable-size extended primitive sequence using four or more vertex data for each variable-size extended primitive. Can store a group of vertices containing multiple attributes, and indicates the position of the attribute in the buffer memory by multiplying the index that is the vertex number in the vertex sequence by an integer, and the type of the attribute Using a vertex buffer that can be determined by biasing with a number, using the index and a number indicating the type of attribute, identifying the position of the vertex attribute of a vertex in the vertex buffer in memory, Stores the vertex buffer attribute value sequence in the vertex buffer in relation to the specific process of the vertex buffer and the vertex sequence, variable size The size of the extended primitive is stored as an index, the fixed-size primitive sequence can be reconstructed using the vertex sequence, and the variable-size extended primitive sequence is used together with the primitive size. Primitives, even variable size extended primitives, for index buffer identification process, index buffer identification process, and remaining vertex attributes not found in the process The present invention relates to a method having a plurality of index buffer specifying steps for obtaining all remaining vertex attributes by a method similar to that for obtaining vertex position attributes except that no size-related index is used. In this specification, the extended primitive may include four or more vertices, and the number of vertices is, for example, 4, 5, 6, 7, 8, 9, or 10.

  The method is such that the fixed size primitive sequence can be reconstructed using the vertex sequence, and in the case of variable size extended primitive sequences, it can be reconstructed using the primitive size. Since the index sequence corresponding to the vertex sequence of the vertex position attribute is stored, and the size of the variable-sized extended primitive is stored as the index value of the index buffer, the index buffer is specified. A geometric primitive sequence can be reconstructed from the vertex sequence that composes it. In addition, since the primitive size can be included before the index sequence that refers to the vertex position attribute of the variable size extended primitive, the method can be reconstructed by the size and the vertex sequence that forms the size. A size-extended primitive can be described. The method may further include identifying multiple index buffers for all remaining vertex attributes, so that each attribute is addressed by its own index, thus requiring a separate index buffer. If required, all required vertex attributes can be specified for extended primitive vertices, such as neighboring points.

  The method steps for identifying extended primitive sequences introduced by the present invention have the following advantages. Various types of extended primitives can be identified, for example, types that can be reconstructed from fixed-size or variable-size vertex sequences. It becomes compact by being expressed as vertices shared by primitive sequences referenced by a compact index. Since this method is extended to the representation by the index buffer / vertex buffer used in the 3D graphic library for specifying the triangle mesh / rectangular mesh, simple primitives such as extended primitive sequences and triangles, rectangles, lines, points, etc. The library APIs need only be modified slightly for applications to prepare and duplicate extended primitive sequences. Each step will be described in detail below.

  The method extends the index / vertex buffer to represent simple primitive sequences to describe fixed size or variable size extended primitive sequences. In this specification, the simple primitive means a basic shape used in computer graphics such as a triangle, a quadrangle, a line, and a point. Such arithmetic processing of a primitive sequence is usually the biggest problem in a three-dimensional graphic library such as openGL and Direct3D. In this specification, the extended primitive means a geometric primitive formed by a fixed number or a variable number of vertex rows having four or more vertex numbers.

  The index buffer / vertex buffer for representing a simple primitive means that the simple primitive is represented as a simple primitive sequence represented as a vertex sequence constituting the primitive. The vertex buffer means a storage device for vertex attributes used in computer graphics. In this specification, the vertex attribute means an attribute related to a point in a four-dimensional homogeneous space used as a vertex of a primitive. Preferred examples of vertex attributes include points in space, colors, texture coordinates, normal vectors, tangent vectors, and the like. An attribute can have various dimensions such as a scalar, two component vectors, three component vectors, and can take various types of values such as a 1-byte integer, a 2-byte integer, a 4-byte integer, and a 4-byte floating point. Each attribute example requires a storage of a fixed memory size determined by its dimension and value type. A method for identifying a vertex buffer includes placing attribute strings in memory in such a way that attribute values of the same attribute type are similarly placed in memory. Therefore, the position of an attribute in the vertex buffer can be easily recovered by its position and placement in the column associated with the attribute type. Thus, an attribute value can be represented by an integer position or index in the column. If all the attribute columns have the same size, the index value of the vertex derived from the attribute value vertex sequence is increased in relation to the number of vertices in the column. In such a case, a vertex sequence can be specified, and therefore a simple primitive sequence can be specified without using an index buffer.

  In this specification, such a situation is referred to as a “vertex buffer-only representation”. The term “index buffer” means an array in memory that contains a sequence of integer values to identify a vertex attribute index. If a vertex sequence contains only one of all types of index sequences of its associated vertex attributes, it is sufficient to specify one index buffer to fully describe the vertex sequence for all vertex attributes It is. Conversely, there are cases where each vertex attribute type is unique to the vertex attribute of the vertex index in relation to the vertex sequence. In such cases, the number of index buffers to identify is only the same as the number of attribute types. Combining a vertex buffer with an index buffer with all the required index arrays in it forms an index / vertex buffer that is represented by a sequence of simple primitives.

  As described above, the step of specifying the vertex buffer is a step for specifying the vertex attributes associated with each vertex, such as the index buffer and / or the vertex buffer in a simple primitive sequence.

  The step of specifying the index buffer is a step for specifying an index related to the attribute of the vertex position in order to form a primitive in which the vertex is extended. For the various extended size attributes in the extended primitive, this step includes specifying the primitive size by the index value in the index buffer for vertex position specification. If a variable-size primitive is used to implement a vertex sequence that constitutes a primitive, this step may include identifying an extended primitive sequence by specifying a primitive size for each primitive. The present invention can be used for an extended primitive in which all necessary information can be provided by the size of the primitive, the vertex sequence that can form the primitive, and the specific value of the vertex sequence.

  In the present invention, an example of a fixed-size extended primitive is a triangle “Triangle with Neighborhood” (TWN) primitive that includes a neighbor. Such a primitive is a mesh that forms a space closed by triangles in a three-dimensional space (the triangles share multiple sides). It can be formed by studying in a continuous mesh).

The above will be described with reference to FIG. FIG. 4A is a conceptual diagram of a triangular mesh. As shown in FIG. 4A, the fragment 103 is drawn on the triangular mesh.
For a triangle formed by vertices {v ₁ , v ₂ , v ₃ }, the TWN primitive is the triangle and each side {v ₂ , v ₁ } of the triangle {v ₁ , v ₂ , v ₃ }. }, {v ₁ , v ₃ }, {v ₃ , v ₂ }, {v ₀ , v ₁ , v ₂ }, {v ₁ , v ₅ , v ₃ }, {v ₂ , v ₃ , v ₄ }. In this specification, the triangles {v ₁ , v ₂ , v ₃ } are also referred to as “center” triangles. In order to express the TWN primitive in this way, a total of 6 vertex sequences are required. Preferred examples of the vertex determination in the TWN primitive, that is, the mapping method between the vertex positions and the connection relation between each vertex in the primitive and other vertices are as follows. For triangles adjacent to the triangle formed by the vertex sequence {v ₀ , v ₁ , v ₂ }, correspond to edges {v ₀ , v ₁ }, {v ₁ , v ₂ }, {v ₂ , v ₀ } The vertices are v ₀₁ , v ₁₂ , v ₂₀ (where v ₀₁ , v ₁₂ , v ₂₀ are triangles adjacent to the central triangle, respectively, and {v ₀ , v ₁ , v _{2 of the} triangle sharing the above-mentioned side] Vertices for expressing the TWN primitive are {v ₀ , v ₁ , v ₀₁ , v ₂ , v ₂₀ , v ₁₂ }. For the triangle {v ₂ , v ₁ , v ₃ } shown in FIG. 4A, the vertices for expressing the TWN primitive are {v ₂ , v ₁ , v ₀ , v ₃ , v ₄ , v ₅ }. It becomes. That is, if vj is the vertex position having the attribute index j, the vertex position sequence of the specific index of the TWN primitive of the center triangle {v ₂ , v ₁ , v ₃ } is {2,1,0,3,4, 5}. If the edges of the original mesh are open, then at least one triangle adjacent to them can be adjacent, and if all edges in the mesh have no more than two adjacent triangles, Further TWN primitives can be generated for all such triangles. Furthermore, for a side having only one adjacent triangle, an artificially missing triangle can be supplemented. One way is to create a degenerate triangle by using the artificially created open edge vertices twice. Another method is to use the vertex of the central triangle located at the opposite position from the open edge, in which case the triangle is not degenerated and coincide with the central triangle.

A fixed-size extended primitive sequence can be formed by concatenating the vertex sequences of each primitive in the primitive sequence. The index buffer for vertex position attributes can be expressed as an intex sequence of vertex position attributes of vertices in the concatenated sequence. For TWN primitives, there are three preferred primitive string representation methods. That is, what is expressed as a separate TWN primitive sequence, what is expressed as a TWN strip, and what is expressed as a TWN fan. They are based on separate central triangle rows, based on central triangle strips, and based on central triangle fans.

Separated TWN primitive sequences can be designed by concatenating the vertices for each generated TWN primitive with the TWN primitive for each triangle as the central triangle. FIG. 4A illustrates a TWN primitive fragment formed by a sequence of central triangles {v ₂ , v ₁ , v ₃ } and {v ₃ , v ₁ , v ₅ }. The corresponding vertices are {v ₂ , v ₁ , v ₀ , v ₃ , v ₄ , v ₅ , v ₃ , v ₁ , v ₂ , v ₅ , v ₆ , v ₇ }, and the corresponding vertex position attributes The index string corresponding to is {2,1,0,3,4,5,3,1,2,5,6,7}. As shown in FIG.

A TWN strip can be composed of a triangular strip. In the triangle strip, the fact that two consecutive triangles share two vertices allows the second or next TWN primitive in the strip to be defined by only two vertices for each primitive. In the present invention, triangular strips formed by vertex rows {v ₀ , v ₁ , v ₂ , v ₃ , v ₄ , v ₅ ,...}, {V ₀ v ₁ , v ₀ v ₂ , v ₁ v ₃ , v ₂ v ₄ , v ₃ v 5,...} along the side of the triangle adjacent to the triangle strip on the opposite side of the side, the vertex row {v ₀₁ , v ₀₂ , v ₁₃ , v ₂₄ , For the triangle strip formed by v ₃₅ ,...}, the vertex sequence defined by the TWB strip is: That is, {v ₀ , v ₁ , v ₀₁ , v ₂ , v ₀₂ , v ₃ , v ₁₃ , v ₄ , v ₂₄ , v ₅ , v ₃₅ , ...}, and the first six vertex rows are , Define the first TWN primitive, and the next two vertices represent the following TWN primitive. In FIG. 4B, a mesh fragment is represented by a triangle strip 104 composed of two triangles {v ₂ , v ₁ , v ₃ } and {v ₃ , v ₁ , v ₅ }. This strip can be formed by four length vertex sequences {v ₂ , v ₁ , v ₃ , v ₅ }. In the example of FIG. 4B, two TWN primitives that define a TWN strip are {v ₂ , v ₁ , v ₀ , v ₃ , v ₄ , v ₅ , v ₇ , v ₆ }, and correspond to them. The index string for specifying the vertex position is {2,1,0,3,4,5,7,6} as shown in FIG.

Similar to the TWN strip, the TWN fan can also be formed from a triangular fan. Also with the TWN fan, it is possible to reduce the number of index buffers required for expressing the TWN primitive string of the triangle fan string corresponding to the center. In the present invention, the triangular fan has a vertex sequence {v ₀ , v ₁ , v ₂ , v ₃ , v ₄ , v ₅ ,...} And {v ₀ v ₁ , v ₁ v ₂ , v ₂ v ₃ , v ₃ v ₄ , v ₄ v ₅ ,...} Along the edge, the vertex of the triangle adjacent to the triangle {v ₀₁ , v ₁₂ , v ₂₃ , v ₃₄ , v ₄₅ , v ₄₅ , v ...}. The vertex sequence that defines the TWN fan is represented by {v ₀ , v ₁ , v ₀₁ , v ₂ , v ₁₂ , v ₃ , v ₂₃ , v ₄ , v ₃₄ , v ₅ , v ₄₅ ,. The six vertices in the mean the first TWN primitive, and every two vertices that follow define a continuous TWN primitive. Note that the first six vertex rows are different from the TWN strip. FIG. 5A shows a mesh fragment by two triangles {v ₂ , v ₁ , v ₃ } and {v ₂ , v ₃ , v ₄ } constituting the triangle fan 105. This fan can be expressed by a vertex sequence {v ₁ , v ₂ , v ₃ , v ₄ } having a length of 4. In the present invention shown in FIG. 5A, the vertex sequence of the TWN fan by the two TWN primitives is {v ₂ , v ₁ , v ₀ , v ₃ , v ₅ , v ₄ , v ₆ , v ₇ }. , The index string corresponding to the attribute of the vertex position corresponding thereto is {2,1,0,3,5,4,6,7} as shown in FIG.

A preferred example of a variable size extended primitive includes the Catmul-Clark subdivision patch primitive (CCSP). In the present invention, the CCSP is composed of polygons each represented by a quadrilateral mesh having four or more adjacent edges and one or more vertices having different numbers. From the point of view of a quadrilateral mesh by Catmull-Clark subdivision, a vertex with a number of adjacent edges that differ from four and a number of vertices
Adjacent edges being different from four) are called irregular vertices. The number of edges adjacent to a vertex is called a valence of vertex. That is, when the vertex value is other than 4, it is regarded as an irregular vertex from the viewpoint of Catmull-Clark subdivision. A CCSP primitive is formed by vertices in a rectangle and all adjacent vertices in a polygon sharing each vertex of the rectangle. In the CCSP primitive, a rectangle located at the center is called a center rectangle. If vertex values of irregular vertices exist, the center rectangle is different from other rectangles in the mesh, and the number of vertices around the center rectangle and the CCSP primitive also change. In the CCSP primitive, the number of vertices related to the irregular vertex value is expressed as N = 2 * V + 8, where V is the number of vertices in the CCSP primitive and V is the vertex value of the irregular vertex. be able to. In this case, multiplying V by a predetermined number is called scaling, 2 is called scale, and adding a predetermined number such as 8 is called bias.

Since the size is known, a CCSP primitive can be represented by a vertex sequence that is mapped between vertices in successive vertex sequences, thereby determining the position of the CCSP primitive. In a preferred embodiment of the present invention, the vertex sequence and mapping are formed as follows. For square meshes, the CCSP primitive has vertices {v ₀ , v ₁ , v ₂ , v ₃ }, which are square edges (v ₀ v ₁ , v ₁ v ₂ , v ₂ v ₃ , v ₃ v ₀ ), respectively. If there is an irregular vertex, it is v ₀ . Vertex sequences describing CCSP primitives are formed as follows. First, the quadrangular vertices are arranged in the order of numbers {v ₀ , v ₁ , v ₂ , v ₃ }. Thereafter, for example, the vertices of adjacent sides that share v ₀ and belong to the quadrangle constituting the mesh of v ₀ and v ₁ are selected. The sixth is on the same side as v ₁ and the same vertex as v ₀ . The remaining adjacent vertices are selected according to the following rules: After an adjacent vertex is selected, the next vertex is selected to share the previously selected edge. As shown in FIG. 6 (A), fragments of the control mesh (106), two adjacent CCSP primitive _{{v 9, v 5, v} 6, v 10} and _{{v 9, v 10, v} 16, v ₁₅ } is described as the center rectangle. The vertex v ₉ is an irregular vertex having a vertex value of 5. Vertex sequences describing the first and second primitives are {v ₉ , v ₅ , v ₆ , v ₁₀ , v ₈ , v ₄ , v ₀ , v ₁ , v ₂ , v ₃ , v ₇ , respectively. v ₁₁ , v ₁₇ , v ₁₆ , v ₁₅ , v ₁₄ , v ₁₃ , v ₁₂ } and {v ₉ , v ₁₀ , v ₁₆ , v ₁₅ , v ₅ , v ₆ , v ₇ , v ₁₁ , v ₁₇ , v ₁₇ , v _21, v is _{20, v 19, v 18,} v 14, v 13, v 12, v 8, v 4}. In the present invention, the index indicating the attribute of the vertex position of the CCSP primitive is determined together with the CCSP primitive in the index buffer including the index indicating the attribute of the vertex position. That is, as the contents of the vertex groups in the two CCSP primitives shown in FIG. 6A, the index buffer 1200 (or vertex buffer 1100) is {18, 9, 5, 6 as shown in FIG. 6C. , 10,8,4,0,1,2,3,7,11,17,16,15,14,13,12,18,9,10,16,15,5,6,7,11,17 , 21, 20, 19, 18, 14, 13, 12, 8, 4}.

The process of identifying the index buffer sequence for the remaining vertex attributes is the process of identifying the vertex attributes such that another index is required so that the same index is not used to refer to all attributes of the vertex. is there. In this case, the vertices are formed by a set of attribute indices, which are indices associated with the different attributes of the vertices. If the above is not true, all vertex attributes can be identified by one index corresponding to the vertex position attribute. Otherwise, a set of index buffers must be specified to specify all vertex attributes. Since the index buffer related to the vertex position attribute includes the primitive size, as described above, special handling is performed when handling an extended primitive of a variable size. Other index buffers do not have information about the primitive size, and can have a smaller length than that of the vertex position attribute when expressing variable-size primitives. In the present invention, the index of the vertex attribute for a certain vertex is determined as follows. For extended attributes of fixed size, the index buffer value at the i th position is all derived from the index column of the i th vertex in the index buffer where N is the length of the vertex column and i is greater than or equal to 0 and less than N The value of the attribute. For extended primitives of variable size, the situation is more complicated. For vertex sequences formed by concatenating vertex sequences to represent variable-size extended primitive sequences, the index sequence of the i-th vertex is (i + N _i − in the index buffer indicating the vertex position attribute). 1) It is formed based on the i th value and the i th value of another index buffer, where N _i is the number of primitives included in the i th vertex, where the initial value of the number of primitives is 1.

A second aspect of the present invention is a method for processing fixed-size or variable-size extended primitives at high speed using a vertex cache (vertex buffer). Fetching the primitive size of a primitive of size and delivering the primitive size to a primitive engine, a computing device programmable to process a particular circuit or extended primitive assembly; and vertex data from a vertex cache Otherwise, the vertex data for the extended primitive vertices in the vertex cache is fetched, converted, stored, and the converted vertices for assembly and operation of the extended primitive To the primitive engine And a process for assembling and processing the extended primitive in the primitive engine, and a simple primitive of a fixed size obtained by the operation processing of the extended primitive in the primitive engine via the pipeline for primitive rasterization. And delivering to a fixed-size primitive integrated circuit.

The method is based on extending a vertex cache device in high speed hardware of extended 3D computer graphics to implement fixed size or variable size extended primitive processing. In this specification, a vertex cache facility refers to a system for achieving high-speed processing of a sequence of simple primitives specified using an index or a value from a vertex buffer. In this specification, the function of the vertex cache device traverses (sweeps) the specified vertex sequence using the value from the index / vertex buffer, and determines the attribute sequence of the corresponding vertex in the vertex sequence to be processed. It is determined whether the vertex is the same column as the attribute available in the storage unit in the vertex cache device as the vertex cache storage unit (store). Sample vertex attribute values from the vertex buffer according to the vertex attribute index sampled from the index buffer, or if the vertex is not in the vertex cache and is stored in the vertex cache store, the vertex buffer may be generated sequentially . The assembled vertex is sent based on the attribute value for the vertex transformation, and additionally, the transformation result is stored in the storage part of the vertex cache. The transformed vertices are delivered to a fixed size primitive integrated circuit device to represent a simple primitive sequence represented by an index / vertex buffer. In order to accelerate vertex transformations or if vertex data is present in the vertex cache, the transformed vertices are fixed-size primitive integrated circuits to eliminate the need to sample the vertex buffer and eliminate the need to transform the vertices again. You may deliver to an apparatus. Additional devices may be provided as appropriate depending on the mounted mode. The term fixed primitive assembler (fixed primitive assembler) refers to a system that implements collecting and reconstructing simple primitives from a sequence of vertices. In this document, assembling of primitives means collecting all the information necessary to reconstruct the primitive, eg, storing information about all vertices in the primitive for further processing. It means to do. For example, in the case of separate triangle rows, three vertex rows existing in each triangle correspond to necessary information. Similarly, for separate lines, two consecutive vertices constituting the line correspond to it. In the case of a triangle strip, the three vertices of the first triangle and the vertex sequence of adjacent triangles correspond to this. The fixed primitive assembly unit is processed and returns the vertex sequence corresponding to the type of delivered primitive to the state of the simple primitive so that it can be sent to a rasterization pipeline that only processes simple primitives.

The method according to the second aspect of the present invention extends the vertex cache device in various aspects. First, according to the second aspect of the present invention, a new logic circuit is required to fetch variable-size extended primitives. It then provides information exchange with the primitive engine (separate device for assembling and processing information about extended primitives) that functions between the vertex cache device and the fixed primitive assembly device.

Since the method includes fetching the size of the primitive from the index buffer for the vertex position attribute, the variable size extended primitive vertex sequence expressed using the method according to the first aspect of the present invention is processed. Can be used for The process of fetching, transporting, and accumulating extended primitive vertex data in the vertex cache can assemble vertices from vertex attribute values, transport vertices, and later transfer the same vertices When referencing, the retrieval is performed quickly and the vertex can be stored in the vertex cache store. This process is the same regardless of whether the extended primitive sequence or simple primitive sequence is processed. The method includes delivering the transferred vertices to a primitive engine, processing the extended primitives in the primitive engine, and delivering the processed results in the form of simple primitives to the rest of the processing pipeline. Is also included. Examining the first step provides the necessary information to assemble the primitive extended by that step, the processing algorithm that drives the primitive engine, and as if there was no primitive interference The output result is delivered for processing. There are the following merits by combining. The process of fetching, delivering and storing vertex data in the vertex cache is substantially the same whether processing simple primitives or extended primitive sequences, so this The method can achieve random access to the vertex buffer to assemble vertices of primitives extended from attributes associated with the attribute index fetched from the index buffer without using any special method. For the same reason as explained above, most logic circuits used in the process of fetching, distributing and storing vertex data can be shared between simple primitive processing and extended primitive processing. In addition, the hardware cost of the logic circuit implemented to realize the extended primitive processing can be reduced. Using a vertex cache reduces the latency when delivering primitive engine vertex data to extended primitive assembly and processing algorithms. As a result, the performance related to the operation processing of the extended primitive is improved. Fetching the primitive size of a variable-size primitive from the index buffer, delivering it to the primitive engine, assembling the extended primitive, and delivering the transformed vertices to the primitive engine for processing On the primitive engine, it is possible to deliver all the information necessary to compute the extended primitive using the method introduced by the first aspect of the present invention. Output of extended primitives processed by the primitive engine is achieved in a manner similar to that of simple primitives, and the pipeline for primitive operations needs to be particularly modified to perform the processing of extended primitives. There is no. Further, in the processing of the simple primitive sequence, the vertex converted by the arithmetic processing of the simple primitive sequence is directly delivered from the vertex cache to the remaining arithmetic processing pipeline bypassed by the primitive engine. This method does not require any additional additions compared to processing simple primitive sequences.

Fetch primitive size of variable-size primitive from index buffer of vertex position attribute, and deliver the primitive size to primitive engine, which is a programmable arithmetic unit that can process a specific circuit or extended primitive assembly The process to be performed is as follows. That is, it is a step of retrieving the primitive size from the index buffer of the vertex position attribute. In order to represent the extended primitive determined in connection with the first aspect of the present invention, a variable-size extended primitive is located therein. The primitive size is delivered to the primitive engine as it may be needed in the processing of the extended primitive.

In the present invention, the information regarding the primitive size precedes the information regarding the vertex of the primitive in the index buffer of the vertex position attribute. As a result of the primitive size fetching, the latter is delivered to the primitive engine ahead of any other information about the primitive. Knowing the primitive size can determine the offset of the index array of vertex position attributes with respect to the beginning of the next variable size primitive, so that the index contains the size information of the next primitive. The primitive size is also needed to be able to begin operations on variable-size primitives. The latter ends after the primitive engine has obtained the vertices of all primitives controlled by the primitive size. This step is required only when realizing a variable-size extended primitive. This step can be omitted when performing arithmetic processing of other primitives.

If the vertex data cannot be obtained from the vertex cache, the process of fetching, converting, and storing the vertex data of the extended primitive vertex in the vertex cache is as follows. As described above, this is a process of fetching, converting, and accumulating in the vertex cache by the vertex cache device. Since the vertex cache device does not perform processing of the extended primitive, the processing of this step is processing of an extended primitive sequence having a fixed size even if it is a simple primitive with respect to the vertex cache device. Will not change. Therefore, it is possible to share in terms of devices such as a circuit for performing simple primitive calculation processing and extended primitive calculation processing. This step can be omitted if necessary vertex information is already stored in the vertex cache. This process is performed even when the index buffer / vertex buffer represents an extended primitive sequence. In such a case, the vertex attribute index is sampled from the index buffer. Also, when the vertex buffer represents only fixed size extended primitives, vertex attribute indexes are generated in order.

When computing variable size extended primitives, fetching primitive size may require modification of fetching primitive vertex data if separate index buffers with different vertex attributes are used . The reason is that the index buffer length difference of the vertex position attribute and the index buffer describing all other attribute columns contain information about the primitive size, and the length is the number of other index columns. This is because it is larger than the buffer. The process of fetching vertex data for a vertex needs to form an index string for each vertex attribute corresponding to the vertex in question. When processing separate index arrays for different vertex attributes, fixed-size primitives, or simple primitive sequences, this formation will sample all index buffer positions corresponding to vertex positions. Done. When computing variable-size extended primitive sequences, this formation is modified as follows: In other words, the index values for all attributes other than the vertex position attribute are obtained by sampling the index buffer position determined by the vertex position. Obtained by the index buffer of the vertex position attribute of the position obtained by adding the number of previous primitives being performed. This step uses the index buffer and the vertex buffer for the variable-size extended primitive sequence, and is introduced according to the first aspect of the present invention.

The process of delivering the converted vertices to the primitive engine for extended primitive assembly and computation is to convert the input vertex information to an algorithm by the primitive engine for assembling and computing the extended primitive. It is a process for delivering. In the present invention, this step is accomplished by selecting a primitive engine to which the transformed vertices from the vertex cache are delivered instead of a fixed primitive assembler. In this specification, the term “primitive engine” means a fixed circuit or a programmable system for realizing the operation processing of an extended primitive by the following. In the case of a variable-size extended primitive, information on the primitive size is received and stored on the primitive vertex stored therein. Reconstruct primitives based on information about the accumulated primitives. Arithmetic processing for reconstructing primitives is performed according to an algorithm that results in a simple primitive sequence that can be accessed by a fixed primitive assembling device as a result of arithmetic processing of extended primitives of variable size.

  The process of delivering a fixed-size simple primitive obtained by the operation processing of the extended primitive in the primitive engine to the fixed-size primitive integrated circuit via the pipeline for primitive rasterization includes the following steps. Delivering extended primitives that are formatted to be processed by a fixed primitive assembling device. In the present invention, this delivery is delivered in exactly the same way that the transformed vertices are delivered directly from the vertex cache to the fixed primitive assembler when a simple primitive sequence is processed by the vertex cache device. . Therefore, there is no need to modify the fixed primitive assembly device, and there is no need to modify the rasterization pipeline in order to be able to perform extended primitive operations.

  In the primitive engine, the process of assembling and calculating the extended primitive is a process for implementing a predetermined algorithm using the primitive engine and performing an arithmetic process on the extended primitive. Preferred examples of algorithms for processing fixed-size extended primitives implemented by the primitive engine include, but are not limited to, the following. In other words, the TWN primitive sequence is processed in order to realize detection and visualization of the mesh silhouette. In this specification, a mesh silhouette means a set of triangle sides shared by a set of triangles, one facing the viewpoint direction and the other facing the other direction. Visualizing a mesh silhouette means a method of visually enhancing silhouette edges when rendering a mesh. The outline of the algorithm for detecting and visualizing silhouettes is as follows. Accumulate vertex data for TWN primitives. Determine the direction of the triangle adjacent to the central triangle. This process may be performed partially in parallel. A silhouette edge is detected by comparing the directions of the triangles from each of the three sides of the central triangle. Generate a rectangular flap of the detected silhouette edge and deliver it for rasterization. The same processing is performed for the next primitive. Since the primitive size is fixed, it is not necessary to perform the process of fetching the primitive size.

In the case of a TWN strip or TWN fan, the first and subsequent primitives in the strip / fan are stored differently. The first primitive requires six vertices before the operation on the primitive begins. The second and subsequent primitives require only two additional vertices since they can make use of already stored vertices. In the case of the separated TWN primitive sequence, vertex data is accumulated in the same way as the first primitive even for the second and subsequent primitives.

As shown in FIG. 4B, each of the vertex sequences {v ₂ ,
TWN primitive strips corresponding to the two central triangles 111 and 113 constituted by v ₁ , v ₃ } and {v ₃ , v ₁ , v ₅ } are {2,1 as shown in FIG. , 0,3,4,5,7,6} is represented as the contents of the index buffer corresponding to the vertex position attribute sequence indicated by. The vertex cache device reads out the vertex corresponding to the index from the index buffer and transmits it to the primitive engine. For example, the sixth vertex transmitted from the vertex cache device to the primitive engine corresponds to an index value of 5. If the primitive engine obtains information about all vertices for the triangle 101, 112, and 113 adjacent to the center triangle 111, the primitive engine will begin to detect the direction of the first triangle, silhouette edge, etc. in the TWN strip sequence. Can do. The calculation of the direction of the triangle is evaluated by a scalar by three inner products composed of three component vectors constituted by x, y, and w of the vertex position of the triangle in the system coordinates, and is evaluated by the following matrix.

Here, the subscripts 0, 1, and 2 mean the first, second, and third vertices in the triangle, respectively. If this sign is different from two triangles sharing an edge, the edge is a silhouette. Therefore, four evaluations of the central triangle of the TWN primitive and three adjacent triangles are required to determine the silhouette side.

In order to detect the silhouette edges, an extra geometric figure is designed that forms a rectangular flap in the direction perpendicular to the observer's field of view, i.e. in the direction of the Z axis in the view coordinates, which is outside the object. To grow. The direction outside the object is the normal represented by the attributes of the other vertices that can be obtained after the vertices are transported from the vertex cache unit to the primitive engine and the normal vector at each vertex of the mesh. Converted to direction. For example, the first and second vertices of the silhouette edges, v ₀ and at _{x 0, y 0, z 0} , w 0 viewpoint coordinate system and x _1, y _1, z _1, w ₁ viewpoint coordinate system v _1, with normal vectors n ₀ and n ₁ associated with each. The generated flap is a rectangle represented by vertices having the following coordinate values in the viewpoint coordinate system {x ₀ , y ₀ , z ₀ , w ₀ },
{x ₁ , y ₁ , z ₁ , w ₁ }, {x ₁ + offset _X * n _1x * w ₁ , y ₁ + offset _Y * n _1y , z ₁ , w ₁ }, and {x ₀ + offset _X * n _0x , y ₀ + offset _Y * n _0y , z ₀ , w ₀ }. The flaps thus obtained are generated so as to have a certain width in the screen space regardless of the distance to the observer. FIG. 5 (B) is the same value as the coefficient offset _X and the coefficient offset _Y, in the case where the n _0z and n _1z is 0, is a diagram showing a configuration of such flaps.

For the next primitive, two vertices with index values 7 and 6 are delivered from the vertex cache unit, thereby further defining two triangles 115 and 114. With this information, the silhouette calculation of the second triangle in the strip can be performed. However, it should be noted that the previously obtained four vertices are used again. Furthermore, by calculating the direction of the triangle, two triangles will be used again. One is the triangle in question and the other is the adjacent triangle. In the case shown in FIG. 4B, the two triangles are 113 and 111, respectively. According to this method, the calculation cost for implementing an algorithm for detecting silhouettes can be greatly reduced. In order to prevent the occurrence of overlapping geometric flaps at the silhouette sides, the flaps must be generated to be TWN primitives in a certain triangle direction, for example, the direction facing the viewer. Other primitives can be ignored.

Finally, for each processed TWN primitive, the primitive engine can also output a simple fixed size primitive. In the special case of silhouette detection and visualization algorithms, the output includes an invariant central triangle and two triangles that form the geometric flap that forms the silhouette edge. For flaps, some attributes can be changed in implementing the algorithm. For example, the color is replaced with a black one if it forms a black appearance. The output triangles are delivered to the fixed primitive assembler and processed as if delivered directly from the vertex cache unit.

An example of an algorithm for realizing that the primitive engine processes variable-size extended primitives includes, but is not limited to, an implementation of the Catmull-Clark subdivision method. Similarly, other subdivision schemes, such as a loop subdivision scheme or a 4-3 subdivision scheme, can be realized. Catmull-Clark, CC, subdivision method consists of multiple steps, generates a smooth and fine grid-like mesh from a rough mesh, and each step subdivides the mesh obtained in the previous step It is a process. In other words, the rules in the basic mesh are applied in a recursive manner and refined. The rule generates a new vertex for each face of the mesh obtained in the previous step, a new vertex for each side of the mesh obtained in the previous step, and Rearrange mesh vertex positions with respect to position. In any of the above three cases, the vertex position of the mesh in the next process is limited to the linear combination of the vertices of the adjacent side or face to which the mesh belongs. More specifically, the face points are located at the average of the positions of the original vertex faces. The position of the edge point is calculated as the average of the center position of the original side and the average of two newly adjacent face points. The vertices from the previous process are positioned as shown in the following equation. S ′ = (Q + 2R + S (n−3)) / n. Where S ′ is the latest position of the vertex, Q is the average value of the new face points located around the vertex, and R is the average value of the midpoints of the edges sharing the vertex. Yes, S is the vertex position in the previous step, and n is the number of edges sharing the vertex, ie the vertex value.

The number of vertices required to calculate the vertex position in the next subdivision step is fixed to 6 for the side vertices and 4 for the face. On the other hand, in order to determine the positions of the vertices from the previous process, information on all the vertices belonging to one adjacent object to be rearranged is required. A neighbor with vertices is formed by all vertices that share a mesh face with it. FIG. 6 (A), the in case of shown in FIG. 6 (B) and FIG. 6 (C) is adjacent ones of the vertex _{v 9} in base mesh 106, vertex _{v 13, v 12, v 8} , v 4, v ₅ , v ₆ , v ₁₀ , v ₁₆ , v ₁₅ and v ₁₄ , the value of which is 5. Vertex values can take any value, so when executing a subdivision rule, information about the number of vertices in the neighborhood is needed. However, in practice, the maximum vertex value can be limited, and a subdivision rule can be implemented with no particular limit to subdivide a certain account.

The CC scheme can be used for all meshes, but different rules can be used for each patch. The subdivision surface patch can be formed so as to deviate from the face of the basic mesh as a row of vertices belonging to one neighbor of the face. That is, since the subdivision rule is limited to one adjacent one, the collection of adjacent ones with surface vertices includes the vertices of the surface itself. It is known that after performing CC subdivision two steps, all the faces in the subdivided mesh are rectangular and there is no abnormal irregular vertex on the face. The basic surface can be designed in that way, but only one CC subdivision process needs to be performed to achieve the same result. In any case, subdivision of patches formed to be not irregular rectangles with one or more irregular vertices per face without losing the general CC scheme can be considered. The CCSP primitive described in the first aspect of the present invention satisfies the above-described requirements, and CC subdivision can be realized by the CCSP primitive group corresponding to the square group of the basic mesh.

With reference to FIG. 6, a method for forming a CCSP primitive from an index / vertex buffer and an algorithm for performing CC subdivision in the primitive engine will be described. FIG. 6A shows an irregular vertex v ₉ having a vertex value of 5 formed by the center squares {v ₉ , v ₅ , v ₆ , v ₁₀ } and {v ₉ , v ₁₀ , v ₁₆ , v ₁₅ }. FIG. 3 is a diagram illustrating a basic control mesh 106 having two adjacent CCSP primitive sequences to share. The index buffer including the index column of the vertex position attribute is as follows. {18,9,5,6,10,8,4,0,1,2,3,7,11,17,16,15,14,13,12,18,9,10,16,15,5 , 6,7,11,17,21,20,19,18,14,13,12,8,4}. The processing of the CCSP sequence is as follows. The step of fetching the primitive size is performed by a vertex cache device that retrieves the primitive size value 18 from the first position in the vertex position attribute index group and delivers it to the primitive engine. The vertex cache device delivers 18 vertices to the primitive engine according to the vertex position attribute index. When the last vertex of the primitive corresponding to the vertex v ₁₂ is delivered to the primitive engine, processing the CCSP primitive begins. Since the primitive size and the vertex sequence can be obtained, the CCSP primitive can be reconstructed by the description method introduced by the first aspect of the present invention by the algorithm implemented by the primitive engine. After reconstructing the primitive, all the information for performing the re-segmentation is obtained, so the reconstructed CCSP primitive is the Catmull-Clark re-segmentation surface (Jeffrey Bloz and Peter Schroder, in Proceedings of the Web). 3D 2002 Symposium (WEB3D-02), pages 11-18, New York, February 24-28, 2002, ACM Press), and the like. The subdivision scheme used is a set of rectangles corresponding to a fine tessellation of the center rectangle of the CCSP primitive that has been processed to be rendered as a fragment of the mosaic mesh (107). Each of the obtained rectangles is further processed and divided into two triangles for rasterization and delivered to a fixed primitive assembler. These steps are repeated for the processing of the next CCSP primitive.

The third aspect of the present invention realizes the processing method according to the first aspect of the present invention for processing a fixed-size primitive or a variable-size primitive sequence by using the method according to the second aspect of the present invention. For the system.

As shown in FIG. 3, the system according to the third aspect of the present invention is adapted to change the process related to the prior art vertex processing in order to process the extended primitives. According to the index stored in the index buffer 1100 and generated, the vertex data from the vertex buffer 1200 is fetched, and the vertex data is converted to the vertex processing unit 4000. The converted vertex data is delivered to the primitive engine 9000, where the extended primitive is assembled and processed. Simple primitives generated by the assembly process of primitives extended by the primitive engine 9000 are delivered to the remaining processing pipelines such as the integrated circuit 6000 that processes fixed primitives. Such a process is particularly useful only when processing extended primitives. When processing a simple primitive, there is no second step as described above, and the transferred vertex may be directly delivered to the integrated circuit 6000 that processes the fixed primitive. As the integrated circuit 6000 for processing fixed primitives, for example, a known circuit as shown in FIG.

As shown in FIG. 3, a specific example of the system of the present invention is a system including the following modules. That is, the system of the present invention includes a vertex cache control unit, VCC, 2000, first vertex cache storage unit, PVC, 3000, second vertex cache storage unit, SVC, 5000, one or more vertex processing units, VPU 4000, Primitive Engine, PE, 9000, and Fixed Size Primitive Integrated Circuit, FPA, 6000. The remaining pipeline relates to a system comprising a fixed size primitive setup unit 7000 and a rasterizer 8000 that implements processing of a fixed sequence of simple primitives such as triangles.

FIG. 3 does not show other units that exchange information and process information with the above system. This is for the sake of brevity and assembling what is characteristic of the present invention. Specifically omitted are a host CPU, a host memory, a triangular rasterization pipeline, and the like. The mutual exchange of information will be described to the extent necessary in relation to the present invention. In the above-described module, the logic circuit of the vertex cache control unit related to processing of the primitive engine and the variable-size extended primitive can be modified as appropriate, and the others can be used as appropriate. In other words, modules other than those described above should appropriately adopt modules similar to those used in current three-dimensional computer graphics in order to implement simple fixed-size primitives such as points, lines, and triangles. Can do.

The vertex cache control unit, VCC, 2000 performs the following processing. Analyzes the contents of the index buffer. The contents of the vertex buffer of the PVC 3000 are fetched according to the vertex index fetched from the index buffer 1100 according to the state of the PVC 3000 and the SVC 5000. In order to execute processing for each vertex of the vertex data, the vertex data transmitted from the PVC 3000 to the VPU (s) 4000 is controlled. Controls the accumulation of transferred vertex data that can be communicated from the VPU (s) 4000 to the SVC 5000. The contents of the SVC 5000 are delivered to the PE 9000 or the FPA 6000 depending on the type of primitive (whether it is an extended primitive of variable size) (specifically, the type of primitive is determined, and the size of the primitive is variable) If it is a primitive, the contents of the SVC 5000 are delivered to the PE 9000). When processing an extended primitive with a variable size, information on the size of the primitive is delivered to PE 9000. The PE 9000 is informed that there is a possibility that processing regarding the extended primitive of variable size may be started after the information regarding the size of the primitive and the vertex data regarding the vertices of all the primitives are delivered. As described above, in the preferred embodiment of the present invention, the primitive size is delivered only to PE9000. In addition, the contents of the SVC are delivered to the PE, and after the information about the size of the primitive and the vertex data about the vertices of all the primitives are delivered to the PE 9000, it is possible to start processing on the extended primitive of variable size I can tell you that there is. The process of analyzing the index buffer is also a process unique to the present invention, and is related to the extraction of primitive sizes and the processing of extended primitives of variable sizes. As other processing steps, known processing steps performed on simple primitives can be appropriately employed.

The first vertex cache storage unit PVC is a place where information from a large number of vertex buffers is continuously transmitted from the host memory and cached. The PVC also functions to store vertex data that has not been delivered to VPU (s) in per-vertex processing. By filling the PVC with non-delivered vertex data for a relatively large continuous memory block, the latency problem with respect to memory transfer can be reduced. Also, PVC and VPU (s) are physically or electrically located close together to reduce the waiting time for transport when there is vertex data that is not delivered in the PVC and must be processed. it can.

The vertex processing unit VPU (s) may be a module that achieves a certain fixed function, or may be a programmable module that can execute vertex processing based on, for example, OpenGL and / or Direct3D 3D graphics APIs. . VPU (s) receives as input various vertex attributes that have not been transferred such as position, color, and text coordinates, and generates various attributes of the transferred vertex such as position, color, text coordinates, and viewpoint vector. The number and dimensions of the input and output, that is, the format of the vertex information of the input and output may be different. VPU (s) receives information from the PVC and communicates its output to the SVC.

  The primitive engine PE is a module that realizes a certain fixed function for performing information processing on the extended primitive, or a programmable module. Mounting a PE as a module that realizes a fixed function is effective for a purpose of realizing a limited function with high performance. Realizing PE as a programmable module is preferable because it gives the algorithm for processing extended primitives a degree of freedom of selection. In the extended primitive processing mode, the PE receives the output for the vertices transferred from the SVC, assembles the primitive, performs the processing for the primitive, and outputs it as a sequence of simple primitives understood by the FPA. PE is a module unique to the present invention. On the other hand, when implemented as a programmable module, a programmable VPU (s) is added except that a function for controlling the operation result of the extended primitive obtained in the form of a simple primitive sequence is transferred to the FPA. It is only necessary to have the same function as the programmable VPU (s), such as sharing many functional logics. The PE receives input information from the SVC and the VCC as in the case of the FPA. The main differences between PE and other devices are the extended primitive size information and the vertex data for delivering all the vertices of the extended primitive when processing variable size extended primitives. This is because it is necessary to send and receive a notification signal about delivery. The VCC uses the same data channel to convey information about the primitive size to the PE for vertex data as described below.

  Finally, the fixed-size primitive integrated circuit from the vertex sequence delivered from the SVC is a module having a fixed function for assembling simple primitives such as points, lines, and triangles. SVC implements a collection of primitives that can be used in modern 3D graphics APIs such as openGL and Direct3D, such as points, lines, line loops, triangles, triangle strips, and triangle fans. When processing extended primitives, the FPA receives input information from the PE, but the PE or SVC can transfer vertex data to the FPA as a protocol for transferring information about the transferred vertices. The source may be completely transparent to this module in order to use the same thing.

  The vertex cache control unit controls all primitive processing on the chip. The vertex cache control unit uses the information stored in the PVC and the SVC to indirectly reference the vertex data for the primitive through the information stored in the index buffer. Processing can be accelerated. Further, when the vertex data for the primitive is formed by the vertex data string in the vertex buffer using PVC, the vertex cache control unit can accelerate the processing by referring only to the vertex buffer. The VCC performs arithmetic processing of two modes, a mode for processing primitives having a fixed size and a mode for processing primitives having an extended size, in accordance with the primitives. The VCC calculation process is the same as the calculation process for a simple primitive or a fixed-size extended primitive.

  First, in order to perform the calculation processing of the vertex attribute index set corresponding to the currently processed vertex, the vertex data relating to the vertex that has not been transferred is loaded and sent to the VPU (s). If there are no transferred vertices corresponding to the vertex attribute index string from the currently sampled SVC and there is no transferred vertex data in the PVC, the VCC is stored in the vertex buffer from the host memory to the PVC. Upload a chunk of content. The chunk contains, or overwrites, unused data previously stored in the PVC containing the vertex data for the index sequence that is queried using the vacant space of the PVC. The chunk may contain other index vertex data, and therefore the chunk may be further utilized if present in the PVC. When vertex data becomes available in the PVC, the VCC begins delivery to the VPU (s), either by a round-robin scheme or other methods. If the converted vertex data does not exist in the SVC and there is something that is not transferred to the PVC, the VCC starts transferring the vertex data from the VPU (s) to the PVC without accessing the host memory. For this reason, the access time to the host memory can be reduced. In this way, PVC leads to an improvement in processing speed for performing arithmetic processing on vertex data that is not transferred.

  The storage locations of different vertex attributes in the host memory are preferably distributed for different spacing and attribute sizes. The VCC assembles input data to the VPU from such distributed vertex attributes. In a specific implementation, the input to the VPU is a four component floating vector, and the input data for each vertex can span several such vectors. The VCC assembles input data from distributed vertex attributes by performing a necessary type of conversion process. For example, a 2-byte integer value is converted into a floating-point number, and the packing attribute is converted into four vectors according to the configuration. For example, two sets of two component texture coordinate attributes are converted into four component input vectors. Then, it is transferred as a lot of input data during the time when the VPU can operate.

When processing on the vertex data is completed and one or several VPS (s) is available, the input for the next vertex to be transferred is input to the VPU as a four-component floating point vector. (4 component floating point
vectors). After receiving a certain number of vectors, the VPU starts processing on the vertices. The number depends on the number of attributes for each vertex and their packing, and is determined through VPU. When the VPU finishes the transfer, the VPU outputs the four component floating point vectors to the SVC. When several VPUs operate in parallel, the VCC manages that the VPU for representing the vertex sequence accesses the SVC. The format of the transferred vertices, ie the number of attributes and the packing into the output vector, may be different from the one entered.

The SVC storage entity is also a four component floating point vector. Therefore, each transferred vector is occupied by an input string to the SVC.
In an actual embodiment, the SVC simply performs a FIFO queue and rushes out the oldest data if the FIFO overflows when transferring the transferred data to the recently processed vertex. Of course, this does not prevent the SVC from storing other methods such as LRU (least recently used). The essence of the present invention is not related to such a trivial matter.

  In the operation processing of the simple primitive sequence, the transferred vertex data is delivered from the SVC to the FPA according to the order of the vertex sequence. The FPA starts vertex calculation when a predetermined number of four-component vectors are received from the SVC. The predetermined number is equal to the number of vectors output by the VPU for the transferred vertices. The FPA assembles triangles from the transferred vertex sequence and delivers them to the rasterization pipeline for rasterization processing.

  Since the operation processing of the extended primitive is performed in the PE, the converted vertex data is first sent to the PE. The PE also has two main operation modes: a fixed size primitive calculation process and a variable size extended primitive calculation process. In the fixed-size primitive calculation mode, when the PE receives a predetermined number of four component vectors from the SVC, similarly to the FPA, the PE starts the vertex calculation process. The operation result of the extended primitive is delivered from the PE to the FPA in the form of a simple sequence of primitives. A simple primitive sequence output from the PE is realized in a format reproducible as a vertex sequence of simple primitives, and the primitive sequence is represented by four component vectors. This is because most hardware used for arithmetic processing of simple primitives such as VCC, PVC, VPUs, SVC, and FPA only adds an arithmetic processing mechanism for primitive processing extended to PE, This means that it can be reused when processing. Furthermore, with respect to vertex attributes stored in the host memory, the vertex cache is used only to the same extent as the computation processing of simple primitives, so that the computation processing of extended primitives can be performed quickly, and as a result, it has been expanded. It is possible to realize quick calculation processing on the chip regarding the primitive.

  In the mode of processing fixed-size extended primitives, the PE executes an arithmetic processing algorithm after receiving each vertex data, that is, after receiving a specific number of four vectors from the SVC. The arithmetic processing algorithm manages the accumulation of received vertex data and detects the moment when a fixed-size extended primitive is reconstructed from a vertex sequence and the moment when the arithmetic processing is simplified.

  One preferred operating system for processing fixed size extended primitives is the mode of processing TWN primitive sequences, which is performed according to the fixed size extended primitive processing described above. The TWN primitive sequence has the same spatial consistency as one of the central triangle sequences. However, since the size of the primitive is twice that of a simple triangle, the size of the secondary cache must be increased in order for the cache size to be printed in the same way as that of the arithmetic processing with the cache hit rate being the central triangle row. .

  The TWN primitive column is subjected to the same arithmetic processing as the simple primitive column with respect to fetching, transporting, and caching of vertex data. The difference is that the destination of the converted vertex data is PE, not FPA. The converted vertex data is delivered one by one from the SVC to the PE in the order of the input vertices.

  In order to perform operations on extended primitives of variable size, the VCC logic circuit is modified in the present invention to provide the following means. That is, means for accurately analyzing the contents of the index buffer, separating the primitive size from the vertex attribute index of the vertex position attribute of the vertex forming the primitive, means for delivering information about the primitive size to the PE, and processing from now on The number of vertices of extended primitives of variable size that have not yet been delivered is counted and communicated to the PE, and the delivery of vertex data is completed to the PE to start the processing related to the primitive. It is a means to inform. This modification is unique to the present invention. The remaining functions of VCC can be used as they are for arithmetic processing of fixed-size primitives, and therefore functions for arithmetic processing of fixed-size primitives can be used as they are.

  In a specific implementation, the initial index of the primitive in the index buffer for the vertex position attribute determines its size in the VCC logic circuit's variable size extended primitive operation mode. Referring to FIG. 7, the VCC 2000 initializes the vertex counter 2100 therein, and decreases the counter value for each index processed next in order to detect the start of the next primitive. Since PE is available in the primitive calculation process, the size is the same as the primitive size register in the PE using the same path as the vertex attribute of the vertex sequence for forming the extended primitive is delivered from the SVC. Delivered to 9100. The primitive size register 9100 is mounted so that it can be accessed by a primitive arithmetic processing algorithm in the PE, and a primitive can be reconstructed using a vertex sequence.

  Since the information regarding the primitive size is delivered from the PE to the VCC, the VCC can start sending the vertex data converted from the SVC to the PE. Arithmetic processing related to the fetching, transfer and delivery of vertex data to the SVC is the same as that of the fixed primitive. The vertex delivery command is determined by an index string stored in the index buffer following the first index including size information. The algorithm for computing primitives in the PE is implemented so that vertex information is accumulated and the attribute sequence of each vertex is delivered to the PE in order to reduce the value of the VCC vertex counter 2100. The When the counter reaches 0, this means that all vertex data has been delivered to the PE, and a notification signal to that effect is delivered from the VCC to the PE via the connection 2300. When a signal is received via connection 2300, the PE begins internal primitive processing. One preferred example of system operation is to perform processing on a CCSP primitive sequence to generate a subdivision surface from a control mesh described as a basic CCSP primitive sequence. The arithmetic processing is performed according to the arithmetic processing of the variable-size extended primitive. Spatial coherency with the CCSP primitive sequence is extremely high. In fact, in the computation of adjacent patches other than irregular vertices, the CCSP primitive can share as many as 12 vertices out of 16 vertices, and therefore 4 to compute the next CCSP primitive. It is sufficient to perform an arithmetic process for adding only the vertex and deliver it to the SVC. In this way, the use of a vertex cache to compute extended primitives significantly reduces data access costs and allows computation on the chip of subdivision patches in the vicinity of the patch. . In the example shown in FIG. 6, there are two consecutive patches that share 14 of the 22 vertices, and the SVC hit rate is about 64%, which is higher for longer sequences. Conceivable. If a vertex cache or index buffer / vertex buffer is not used to perform processing related to such a large primitive, it is considered that extremely large memory costs are required for vertex processing.

In the case of a CCSP primitive subdivision patch that receives and processes a signal from the connection 2300 as described above, since all information necessary for the arithmetic processing is delivered to the PE, the PE is a Catmull-Clark subdivision surface. Algorithm (Jeffrey Bolz and Peter Schroder, in Proceedings
of the Web3D 2002
Symposium (WEB3D-02)), the Web3D 2002 Symposium (WEB3D-02), pages 11-18, New York,
February 24 28
The subdivision mesh included in the center rectangle of the CCSP primitive can be started in accordance with the arithmetic processing disclosed in 2002, ACM Press, and other subdivision algorithms for each patch. The result of the calculation processing of the subdivided patch is a triangle, a triangle strip in the FPA, or the like according to the input information, like other extended primitives. Another aspect of the present invention realizes the above-described system in an integrated circuit, and can process fixed or variable-sized extended primitives on-chip. A graphic card including such an integrated circuit and a video game device including such an integrated circuit are also provided.

  The present invention relates to a system using an integrated circuit as described above to realize high-speed processing of a subdivision surface generated by the Catmull-Clark subdivision scheme. The apparatus for computing extended primitives of the present invention can be used for interactive 3D computer graphics for real-time rendering. As 3D computer graphics, an algorithm for accessing multiple vertices of a polygon mesh at the same time is implemented, and a complex geometric shape expressed by a grid of NURBS patches and a subdivided surface. For real-time rendering.

  For example, such a device can be used for a hardware accelerator card, a personal digital assistance, a video game device, a car navigation system, etc. in 3D computer graphics for visualizing a 3D image.

  These images were obtained by mounting the apparatus of the present invention on an emulator known as PICA of Digital Media Professional Inc. to obtain various three-dimensional computer graphics images. 8A, 8B, 9A, 9B, 10A, 10B, 11A and 11B show the image results obtained using the apparatus of the present invention. FIG. 8A and FIG. 8B compare the silhouette directions and examine the possibility of visualization. FIG. 8A cannot be visualized, and FIG. 8B can be visualized. For example, a silhouette visualization as shown in FIG. 8B can be used for an application where it is necessary to emphasize the outline of a shape such as animating a manga character.

  FIG. 9A and FIG. 9B show a rendered version of a simple disc-like shape before and after re-division in the present invention. FIG. 9A shows the one using the original rough mesh, and FIG. 9B shows the one using the mesh that is subdivided by adding polysilver in the subdivision process. FIG. 10A and FIG. 10B are diagrams showing re-division into a more complicated shape as compared with FIG. 9A and FIG. 9B. 11A and 11B relate to the shading in FIGS. 10A and 10B, respectively, excluding the wire frame. The present invention is accelerated by the vertex cache and can implement the subdivision algorithm on-chip. Therefore, according to the present invention, it is possible to generate and visualize in real time a complex shape obtained by performing subdivision based on a simple mesh that is an important feature in video games.

The apparatus for processing the extended primitive of the present invention can be used in the field of real-time three-dimensional computer graphics.

Claims (9)

By using a vertex cache in a 3D computer graphics computer system with a vertex cache control unit, it is possible to perform arithmetic processing of fixed-size simple primitive sequences and fixed-size extended or variable-size extended primitive sequences. A way to do,
The vertex cache control unit analyzes the contents of an index buffer that stores the simple primitive sequence and the extended primitive sequence, and determines whether the primitive is the variable size extended primitive according to the type of the primitive. An analysis process for determining whether or not,
When the vertex cache controller determines in the analyzing step that the primitive is the extended primitive of the variable size, the primitive size of the extended primitive of the variable size is fetched from the index buffer of the vertex position attribute. And delivering the primitive size of the variable-size extended primitive to a primitive engine that is a unit for assembling and calculating the variable-size extended primitive;
When there is no vertex data from the vertex cache, the vertex cache control unit fetches vertex data related to the vertices of the extended primitive into the vertex cache, converts the vertex data, and stores the vertex data;
To perform assembling and processing of the extended primitives, wherein the vertex cache control unit, a step of delivering the transformed vertex data to the primitive engine,
The primitive engine, comprising the steps of assembling and processing of the extended primitives,
The primitive engine, a simple primitives fixed size caused by the processing of the extended primitives, and outputting the rasterized pipeline primitives,
A method including the step of delivering the simple primitive to a pipeline for rasterizing the primitive when the vertex cache control unit determines that the primitive is the simple primitive in the analyzing step . Fetching the primitive size of the variable size extended primitive from the index buffer of the vertex position attribute,
Access the index buffer that describes the vertex position attribute sequence for a vertex of a variable-size extended primitive, and retrieve the first index value for that primitive, along with the next _Ni index that references the vertex forming the primitive Is done by
Here, N _i indicates the retrieved value of the i th primitive, and the size of the next primitive is stored in the N _{i + 1} th position following the size position of the previous primitive in the index buffer.
The method of claim 1. When there is no more vertex data from the vertex cache, the steps of fetching vertex data relating to the vertices of the extended primitive to the vertex cache, converting the vertex data, and storing are as follows:
In the case of fixed-size extended primitives, this is done from the vertex buffer indicated by aligning the fixed-size extended primitives or those stored in the vertex buffer;
When performing operations on variable-size extended primitives, fixed-size extensions with the first index associated with the primitive in the index buffer, including the index of the vertex position attribute that is not relevant by referring to the contents in the vertex buffer In the case of a selected primitive or a variable-size extended primitive, from the vertex buffer of the column selected from one or more index buffers,
The method of claim 1. In 3D computer graphics, a system that performs processing of a fixed-size simple primitive sequence and a fixed-size extended or variable-size extended primitive sequence using a vertex cache ,
An initial vertex buffer store (PVC) for accessing a portion of the recently used vertex buffer and obtaining vertex data from the vertex buffer;
One or more vertex processing units (VPUs) for transporting the vertex data obtained from the initial vertex buffer store (PVC);
A second vertex cache store (SVC) for accessing transformed vertex data recently processed by the vertex processing unit (VPU);
Primitives for storing and calculating simple and extended primitives assembled by the vertex data delivered from the second vertex cache store (SVC), and for the calculation result of the calculation processing to be a series of simple primitives An engine (PE),
A rasterizer for collecting a series of fixed-size simple primitives from the series of simple primitives, rasterizing the series of fixed-size simple primitives into fragments, and outputting the fragments to a processing pipeline;
A vertex cache control unit (VCC),
The vertex cache control unit (VCC)
By accessing the index buffer for storing the simple primitive sequence and the extended primitives column, analyzes the contents of the index buffer, depending on the type of primitive, or primitives are extended primitives of said variable size Determine whether or not
When processing an extended primitives of the variable size, conveys information about the extended primitive size of primitives of said variable size to the primitive engine (PE),
Controlling the initial vertex buffer store (PVC) to obtain vertex data from the vertex buffer;
Controls the collection of vertex data stored in the initial vertex buffer store (PVC) and if the transferred vertex data is lost from the initial vertex buffer store (PVC), the vertex processing unit ( Control to transfer the collected vertex data to the VPU), and
To perform these processes as well as collect information about the simple primitives and the extended primitive control that vertex data is delivered the second vertex cache store from (SVC) to the primitive engine (PE) Do,
system. When processing variable-sized extended primitives, the process of delivering the primitive size to the primitive engine also delivers the vertex data converted to the primitive engine to form the vertices forming the primitive. ,
The system according to claim 4. The vertex cache controller (VCC) simple primitives and fixed size, and is designed to handle the extended primitives that expanded or variable size of a fixed size,
The fixed-size simple primitive processing mode is used for fixed-size simple primitive arithmetic processing and fixed-size extended or variable- size extended primitive arithmetic processing.
On the other hand, the variable-size extended primitive calculation mode is used for variable-size extended primitive calculation processing.
The system according to claim 4.   5. An integrated circuit comprising the system of claim 4, wherein the series of fixed size extended primitives operates on a series of variable size extended primitives.   A graphics card comprising the integrated circuit according to claim 7.   A video game machine comprising the integrated circuit according to claim 7.

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