JP5214263B2 - ESD protection circuit - Google Patents

Description

  The present invention relates to an electrostatic discharge protection circuit for protecting a semiconductor integrated circuit from electrostatic discharge.

  When a charge due to electrostatic discharge (ESD) is applied to a semiconductor integrated circuit, an element in the semiconductor integrated circuit may be damaged. Therefore, for example, Patent Document 1 proposes a technique for protecting an element in the semiconductor integrated circuit by providing an electrostatic discharge protection circuit in the semiconductor integrated circuit and discharging the charge due to ESD by the electrostatic discharge protection circuit. Has been.

  FIG. 9 is a diagram showing a configuration of the electrostatic discharge protection circuit proposed in Patent Document 1. In FIG.

  The electrostatic discharge protection circuit 100 shown in FIG. 9 is provided in a semiconductor integrated circuit, and a DC power source (not shown) is connected to the electrostatic discharge protection circuit 100 so that the potential VDD becomes the power supply voltage potential VDD. One power supply line 100_1 and a second power supply line 100_2 having a potential VSS lower than the potential VDD are provided. The second power supply line 100_2 is connected to the frame ground GND.

  The electrostatic discharge protection circuit 100 includes a time constant circuit 101 including a resistor 101a and a capacitor 101b connected in series between the first power supply line 100_1 and the second power supply line 100_2. .

  Further, the electrostatic discharge protection circuit 100 includes a relatively large N-channel transistor 102 connected between the first power supply line 100_1 and the second power supply line 100_2.

  The electrostatic discharge protection circuit 100 includes three inverters 103, 104, and 105 connected in series between a connection node between the resistor 101 a and the capacitor 101 b and the gate of the N-channel transistor 102. The inverter 103 includes a P-channel transistor 103a and an N-channel transistor 103b connected in series between the first power supply line 100_1 and the second power supply line 100_2. The inverter 104 includes a P-channel transistor 104a and an N-channel transistor 104b connected in series between the first power supply line 100_1 and the second power supply line 100_2. Further, the inverter 105 includes a P-channel transistor 105a and an N-channel transistor 105b connected in series between the first power supply line 100_1 and the second power supply line 100_2.

  The electrostatic discharge protection circuit 100 includes a diode 106 having a cathode connected to the first power supply line 100_1 and an anode connected to the second power supply line 100_2. An internal circuit (not shown) constituting a semiconductor integrated circuit is connected to both ends of the diode 106.

  First, a normal operation in the electrostatic discharge protection circuit 100 will be described. During normal operation, a predetermined operating voltage is applied from the DC power source to the first power supply line 100_1, and the capacitor 101b is charged with a charge corresponding to the predetermined operating voltage via the resistor 101a. Therefore, the node on the input side of the inverter 103 is at the “H” level, the node on the input side of the inverter 104 in the next stage is at the “L” level, and the node on the input side of the inverter 105 in the next stage is “H”. 'At the level. Therefore, the node on the output side of the inverter 105 is at the “L” level. That is, the gate of the N-channel transistor 102 is at the “L” level. Therefore, the N channel transistor 102 is in an off state. As described above, the electrostatic discharge protection circuit 100 illustrated in FIG. 9 is configured such that no current flows between the first power supply line 100_1 and the second power supply line 100_2 during normal operation. Therefore, the electrostatic discharge protection circuit 100 does not operate during normal operation.

  Next, the operation of the electrostatic discharge protection circuit 100 when the semiconductor integrated circuit receives an ESD event will be described. An ESD event occurs when static electricity is charged on a human body or a transport device when the semiconductor integrated circuit is transported and flows into the semiconductor integrated circuit. At the first time, the first power supply line 100_1 is equipotential with the second power supply line 100_2. Here, it is assumed that a positive ESD surge is applied to the first power supply line 100_1 with respect to the second power supply line 100_2 as an ESD event. The charge due to the ESD surge is charged in the capacitor 101b via the resistor 101a. Here, the value of the time constant RC determined by the resistance value of the resistor 101a and the capacitance value of the capacitor 101b is sufficiently large. Therefore, the node on the input side of the inverter 103 is maintained at the 'L' level for a period corresponding to the time constant RC. Is done. In a state where the node on the input side of the inverter 103 is maintained at the “L” level, the gate of the N-channel transistor 102 is set to the “H” level via the inverters 104 and 105. Accordingly, the N-channel transistor 102 is turned on. In this manner, a surge current can be released by the N-channel transistor 102 and high voltage can be prevented from being applied between the first power supply line 100_1 and the second power supply line 100_2. Note that the gate potential of the N-channel transistor 102 decreases with the ESD surge.

On the other hand, when a positive ESD surge is applied to the second power supply line 100_2 with respect to the first power supply line 100_1 as an ESD event, the charge due to the ESD surge is transferred to the first power supply via the diode 106. Flows to line 100_1. In this manner, the surge current can be released by the diode 106, and a high voltage can be prevented from being applied between the second power supply line 100_2 and the first power supply line 100_1.
US Patent Application Publication No. 2006/0039093

  In a conventional electrostatic discharge protection circuit typified by the electrostatic discharge protection circuit proposed in Patent Document 1 described above, a time constant circuit for detecting an ESD event requires a large time constant on the order of 10 μS. For this reason, the circuit area occupied by the resistors and capacitors constituting the time constant circuit in the electrostatic discharge protection circuit is large. The electrostatic discharge protection circuit is usually formed in the I / O region of the semiconductor integrated circuit. In general, in the I / O region, the circuit area occupied by the capacitor is large, and the ratio of the circuit area occupied by the capacitor in the entire semiconductor integrated circuit increases as the circuit scale of the semiconductor integrated circuit increases.

  In recent years, the circuit scale of a semiconductor integrated circuit tends to increase more and more as the semiconductor integrated circuit becomes more multifunctional and highly integrated. Therefore, in the semiconductor integrated circuit, the ratio of the circuit area occupied by the capacitor for detecting the ESD event tends to increase more and more. However, in the conventional electrostatic discharge protection circuit, there is a problem that the capacitor does not contribute to improving some circuit performance of the semiconductor integrated circuit other than the detection of the ESD event.

  In view of the above circumstances, an object of the present invention is to provide an electrostatic discharge protection circuit that can sufficiently discharge electric charges due to electrostatic discharge and that can remove noise during normal operation.

The electrostatic discharge protection circuit of the present invention that achieves the above object is as follows.
By connecting the DC power supply, a first power supply line having a predetermined first potential and a second power supply line having a second potential lower than the first potential,
A capacitor on the first power supply line side connected in series between the first power supply line and the second power supply line and a first threshold voltage having a negative threshold voltage on the second power supply line side A time constant circuit composed of an N-channel transistor;
An inverter having an input side connected to a connection node between the capacitor and the first N-channel transistor, and an output side connected to a gate of the first N-channel transistor;
Connected between the first power supply line and the second power supply line, the gate is indirectly connected to the connection node between the capacitor and the first N-channel transistor, and the potential of the connection node is increased. And a second N-channel transistor that conducts in response to a rise in the potential of its gate.

  In the electrostatic discharge protection circuit according to the present invention, when an ESD event occurs, the potential of the connection node of the capacitor and the first N-channel transistor having a negative threshold rises rapidly, and the 'L' level is output from the inverter. The This 'L' level is input to the gate of the first N-channel transistor. For this reason, the value of the on-resistance of the first N-channel transistor is large, and therefore, the first N-channel transistor plays a role of a high resistance that constitutes a CR time constant circuit together with the capacitor. Further, this 'L' level is indirectly input to the gate of the second N-channel transistor, whereby the second N-channel transistor is turned on and the surge current due to the ESD event can be released. As described above, according to the present invention, the time constant CR determined by the product of the value of the capacitor and the value of the on-resistance of the N-channel transistor (for example, on the order of several MΩ by the input of the “L” level). The N-channel transistor is turned on for a time corresponding to the value. Therefore, the surge current due to the ESD event can be sufficiently discharged.

  Further, in the electrostatic discharge protection circuit of the present invention, during normal operation, the connection node between the capacitor and the first N-channel transistor is at the “L” level, so that the inverter outputs the “H” level. This 'H' level is input to the gate of the first N-channel transistor. That is, the gate of the first N-channel transistor receives the 'H' level feedback from the inverter and is held at a predetermined operating voltage (power supply voltage). For this reason, the first N-channel transistor has a small on-resistance value on the order of, for example, 100Ω, and therefore the connection node is maintained at the “L” level. Since this 'L' level is indirectly input to the gate of the second N-channel transistor, the second N-channel transistor remains in a non-conductive state.

  Thus, during normal operation, the first N-channel transistor constituting the time constant circuit has a small on-resistance value. Therefore, during normal operation, the capacitor connected in series with the first N-channel transistor can function as a decoupling capacitor, and the electrostatic discharge protection circuit of the present invention plays a role of removing power supply noise and ground noise. You can carry it.

  Therefore, the electrostatic discharge protection circuit of the present invention can sufficiently discharge electric charges due to electrostatic discharge, and can eliminate power supply noise and ground noise during normal operation.

  Here, it is also preferable that a second inverter having the output of the inverter as an input is provided, and the output of the second inverter and the gate of the second N-channel transistor are connected.

  In this way, with a simple circuit configuration, the second N-channel transistor can be turned on when an ESD event occurs, and can be turned off during normal operation.

  It is also preferable that a diode having a cathode connected to the first power supply line and an anode connected to the second power supply line is provided.

  In this case, when a positive ESD surge is applied to the second power supply line with respect to the first power supply line as an ESD event, the charge due to the ESD surge is transferred to the first via the diode. Can flow through the power line. Therefore, it is possible to prevent a high voltage from being applied between the second power supply line and the first power supply line.

  According to the electrostatic discharge protection circuit of the present invention, electric charges due to electrostatic discharge can be sufficiently discharged, and noise can be removed during normal operation.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of an electrostatic discharge protection circuit according to an embodiment of the present invention.

  The electrostatic discharge protection circuit 10 shown in FIG. 1 is provided in a semiconductor integrated circuit, and a DC power source (not shown) is connected to the electrostatic discharge protection circuit 10 so that a predetermined first potential VDD and The first power supply line 10_1 and the second power supply line 10_2 having the second potential VSS lower than the first potential VDD are provided.

  In addition, the electrostatic discharge protection circuit 10 includes a time constant circuit 11 connected between the first power supply line 10_1 and the second power supply line 10_2. The time constant circuit 11 includes a capacitor 11a on the first power supply line 10_1 side and an N channel transistor 11b on the second power supply line 10_2 side (corresponding to an example of the first N channel transistor in the present invention). Yes. Here, the value of the capacitor 11a is on the order of several pF. N channel transistor 11b has a negative threshold voltage.

  Further, the electrostatic discharge protection circuit 10 includes an inverter 12 whose input side is connected to the connection node A of the capacitor 11a and the first N-channel transistor 11b and whose output side is connected to the gate of the first N-channel transistor 11b. ing. The inverter 12 includes a P-channel transistor 12a on the first power supply line 10_1 side and an N-channel transistor 12b on the second power supply line 10_2 side.

  Further, the electrostatic discharge protection circuit 10 is provided with an inverter 13 (corresponding to an example of a second inverter in the present invention) that receives the output of the inverter 12 as an input. The inverter 13 includes a P-channel transistor 13a on the first power supply line 10_1 side and an N-channel transistor 13b on the second power supply line 10_2 side.

  Further, the electrostatic discharge protection circuit 10 includes an N-channel transistor 14 (corresponding to an example of the second N-channel transistor in the present invention) connected between the first power supply line 10_1 and the second power supply line 10_2. Is provided. The gate of the N-channel transistor 14 is connected to the output of the inverter 13.

  The electrostatic discharge protection circuit 10 includes a diode 15 having a cathode connected to the first power supply line 10_1 and an anode connected to the second power supply line 10_2.

  First, the operation of the electrostatic discharge protection circuit 10 when an ESD event is generated will be described. At the first time, the first power supply line 10_1 is equipotential with the second power supply line 10_2. Here, it is assumed that a positive ESD surge is applied to the first power supply line 10_1 with respect to the second power supply line 10_2 as an ESD event. Then, the potential of the connection node A between the capacitor 11a and the N-channel transistor 11b rises rapidly, and the gates of the P-channel transistor 12a and the N-channel transistor 12b are both set to the “H” level. Accordingly, the P-channel transistor 12a and the N-channel transistor 12b are turned off and on. Therefore, the ‘L’ level is output from the inverter 12. This 'L' level is input to the gate of the N-channel transistor 11b having a negative threshold. For this reason, the on-resistance value of the N-channel transistor 11b is large. Therefore, the N-channel transistor 11b plays a role of a high resistance that constitutes a CR time constant circuit together with the capacitor 11a.

  Further, since the 'L' level output from the inverter 12 is input to the gates of the P-channel transistor 13a and the N-channel transistor 13b, the P-channel transistor 13a and the N-channel transistor 13b are turned on and off, respectively. It becomes a state. Accordingly, the inverter 13 outputs the “H” level. This 'H' level is input to the gate of the N-channel transistor 14. Therefore, the N-channel transistor 14 is turned on, and thereby a surge current due to an ESD event can be released. As described above, in the present embodiment, the value of the capacitor 11a (a value on the order of several pF) and the value of the on-resistance of the N-channel transistor 11b (a value on the order of several MΩ due to the input of the 'L' level). An 'H' level trigger signal that holds a voltage level equal to the surge application node (VDD) for a time corresponding to the value of the time constant CR determined by the product appears at the connection node A, and this trigger signal is Via the two inverters 12 and 13 connected in series between the connection node A and the gate of the N-channel transistor 14, the N-channel transistor 14 is turned on to discharge a surge current due to an ESD event to the ground. At this time, the gate of the N-channel transistor 11b receives the feedback of the potential ('L' level) at the output node B of the inverter 12 and is held at the ground level, so that the N-channel transistor 11b has an on-resistance value on the order of several MΩ. Therefore, the time constant of the time constant circuit 11 is on the order of several microseconds, and therefore the ESD surge can be sufficiently discharged to the ground.

  Next, normal operation in the electrostatic discharge protection circuit 10 will be described. During normal operation, a predetermined operating voltage is applied from the DC power supply to the first power supply line 10_1. Here, the operating voltage, which is a DC voltage, is cut off by the capacitor 11a, and therefore the connection node A between the capacitor 11a and the N-channel transistor 11b is at the 'L' level. Therefore, the gates of the P-channel transistor 12a and the N-channel transistor 12b are both at the 'L' level, and the P-channel transistor 12a and the N-channel transistor 12b are in the on state and the off state, respectively. Accordingly, the inverter 12 outputs the “H” level. This 'H' level is input to the gate of the N-channel transistor 11b having a negative threshold voltage. In other words, the gate of the N-channel transistor 11b receives the feedback of the potential ('H' level) at the output node B of the inverter 12 and is held at a predetermined operating voltage (power supply voltage). Therefore, the N-channel transistor 11b has a small on-resistance value on the order of 100Ω, and therefore the connection node A is maintained at the “L” level.

  Further, since the “H” level output from the inverter 12 is input to the gates of the P-channel transistor 13a and the N-channel transistor 13b, the P-channel transistor 13a and the N-channel transistor 13b are turned off and on, respectively. Is in a state. Therefore, the ‘L’ level is output from the inverter 13. Since this ‘L’ level is input to the gate of the N-channel transistor 14, the N-channel transistor 14 is in an OFF state. Further, the diode 15 remains in a non-conductive state when a predetermined operating voltage is applied to the first power supply line 10_1. As described above, the electrostatic discharge protection circuit 10 shown in FIG. 1 is configured such that no current flows between the first power supply line 10_1 and the second power supply line 10_2 during normal operation.

  Here, as described above, during normal operation, the N-channel transistor 11b constituting the time constant circuit 11 has a small on-resistance value on the order of 100Ω. Therefore, during normal operation, the capacitor 11a connected in series with the N-channel transistor 11b can function as a decoupling capacitor, and the electrostatic discharge protection circuit 10 of the present embodiment has a role of removing power supply noise and ground noise. Can be carried. Therefore, the electrostatic discharge protection circuit 10 of the present embodiment can sufficiently discharge electric charges due to electrostatic discharge, and can remove power supply noise and ground noise during normal operation.

  Next, in order to confirm the noise removal effect during normal operation of the electrostatic discharge protection circuit 10 of the present embodiment, the electrostatic discharge protection circuit 10 of the present embodiment and the conventional electrostatic discharge protection circuit 100 (see FIG. 9) On the other hand, an analysis using a circuit simulator was performed.

  FIG. 2 is a diagram showing a state in which noise generated by the circuit simulator is applied to the electrostatic discharge protection circuit of the present embodiment and the conventional electrostatic discharge protection circuit.

  FIG. 2A shows a state in which power supply noise and ground noise generated by a circuit simulator are applied to the electrostatic discharge protection circuit 10 of the present embodiment. FIG. 2B shows a state in which power supply noise and ground noise generated by a circuit simulator are applied to the conventional electrostatic discharge protection circuit 100.

  In the electrostatic discharge protection circuit 10 shown in FIG. 2A, inverters 21_1, 21_2,..., 21_n constituting a circuit simulator are connected in series. An inductance 23 is provided between the power supply terminal 22 and the electrostatic discharge protection circuit 10, and an inductance 25 is provided between the ground terminal 24 and the electrostatic discharge protection circuit 10. Here, the inductances 23 and 25 are 10 nH inductances imitating inductance parasitic on the bonding wire. Further, 1.0 V is applied to the power supply terminal 22 as the power supply voltage VDD, and the ground terminal 24 is installed at the ground GND.

  In the semiconductor integrated circuit provided with the electrostatic discharge protection circuit 10 shown in FIG. 2A, the inverters 21_1 and 21_2 are supplied with clocks CLK having frequencies of 1 MHz, 10 MHz, and 100 MHz, respectively, as noise generated in the internal circuit during normal operation. ,..., 21_n are modeled by noise generated between the node N1 on the power supply voltage VDD side and the node N2 on the ground GND side by performing a switching operation.

  Further, the conventional electrostatic discharge protection circuit 100 shown in FIG. 2B is also the inverter 21_1 with the clock CLK having the frequencies of 1 MHz, 10 MHz, and 100 MHz, similarly to the electrostatic discharge protection circuit 10 shown in FIG. , 21_2,..., 21_n are modeled by noise generated between the node N1 and the node N2. Here, FIG. 3, FIG. 4 and FIG. 5 show the results of analysis using the circuit simulator for the electrostatic discharge protection circuit 10 of the present embodiment and the conventional electrostatic discharge protection circuit.

  FIG. 3 is a diagram showing response waveforms to noise generated by the clock CLK having a frequency of 1 MHz in both the electrostatic discharge protection circuit of the present embodiment and the conventional electrostatic discharge protection circuit.

  The vertical axis | shaft shown in FIG. 3 shows voltage (V). Specifically, a potential difference between the nodes N1 and N2 in the electrostatic discharge protection circuit 10 of the present embodiment and a potential difference between the nodes N1 and N2 in the conventional electrostatic discharge protection circuit 100 are shown. The horizontal axis indicates time.

  FIG. 3 shows a response waveform A with respect to noise generated by the clock CLK having a frequency of 1 MHz in the electrostatic discharge protection circuit 10 of the present embodiment. In addition, a response waveform B with respect to noise generated by the clock CLK having a frequency of 1 MHz in the conventional electrostatic discharge protection circuit 100 is also shown.

  In the waveform A, the peak voltage value of the noise represented by the waveform A is within a small range from 0.96V to 1.05V. On the other hand, in the waveform B, the peak voltage value of noise is in a large range from 0.93V to 1.07V. In the waveform A, the noise is rapidly attenuated at each time. On the other hand, in the waveform B, the noise is gradually attenuated.

  FIG. 4 is a diagram showing response waveforms to noise generated by the clock CLK having a frequency of 10 MHz in both the electrostatic discharge protection circuit of the present embodiment and the conventional electrostatic discharge protection circuit.

  FIG. 4 shows a response waveform A (a waveform in the vicinity of a voltage of 1 V) with respect to noise generated by the clock CLK having a frequency of 10 MHz in the electrostatic discharge protection circuit 10 of the present embodiment. In addition, a response waveform B with respect to noise generated by the clock CLK having a frequency of 10 MHz in the conventional electrostatic discharge protection circuit 100 is also shown.

  In the waveform A, the peak voltage value of noise is within a small range from 0.97V to 1.02V. On the other hand, in the waveform B, the peak voltage value of noise is in a large range from 0.94V to 1.06V. In the waveform A, the noise is rapidly attenuated at each time. On the other hand, in the waveform B, the attenuation of the noise is moderate, and the noise generated at the next time is superimposed before it sufficiently attenuates.

  FIG. 5 is a diagram showing response waveforms to noise generated by the clock CLK having a frequency of 100 MHz in both the electrostatic discharge protection circuit of the present embodiment and the conventional electrostatic discharge protection circuit.

  FIG. 5 shows a response waveform A to the noise generated by the clock CLK having a frequency of 100 MHz in the electrostatic discharge protection circuit 10 of the present embodiment. In addition, a response waveform B with respect to noise generated by the clock CLK having a frequency of 100 MHz in the conventional electrostatic discharge protection circuit 100 is also shown.

  In the waveform A, the noise peak voltage value is within a small range from 0.95V to 1.05V. On the other hand, in the waveform B, the peak voltage value of noise is in a large range from 0.8V to 1.2V.

  As apparent from FIGS. 3, 4, and 5, the electrostatic discharge protection circuit 10 according to the present embodiment is compared with the conventional electrostatic discharge protection circuit 100 during the normal operation. , Ground GND side), the peak voltage value of noise generated is suppressed small. Also, the noise itself is quickly attenuated.

  Furthermore, in order to confirm the effect of the electrostatic discharge protection circuit 10 of the present embodiment at the time of an ESD event, the electrostatic discharge protection circuit 10 of the present embodiment and the conventional electrostatic discharge protection circuit 100 (see FIG. 9) are compared. Then, analysis using SPICE (Simulation Program with Integrated Circuit Emphasis) simulation, which is one of circuit simulations, was performed.

  FIG. 6 is a diagram showing a SPICE simulation circuit for examining a difference in response to an ESD surge between the electrostatic discharge protection circuit of this embodiment and the conventional electrostatic discharge protection circuit.

  From the viewpoint of the reliability of semiconductor integrated circuits, the electrostatic discharge phenomenon is mainly charged with a machine model that models the static electricity discharged from a charged transfer device (machine such as a robot arm) to a semiconductor integrated circuit and a charged model. It is standardized to two types of human body models that model the static electricity discharged from the human body to the semiconductor integrated circuit.

  FIG. 6A shows a circuit for examining a difference in response in the machine model between the electrostatic discharge protection circuit 10 of the present embodiment and the conventional electrostatic discharge protection circuit 100. FIG. 6B shows a circuit for examining the difference in response in the human body model between the electrostatic discharge protection circuit 10 of the present embodiment and the conventional electrostatic discharge protection circuit 100.

  First, FIG. 6A will be described. FIG. 6A shows an ESD pulse generator 31 that generates static electricity and a DUT (Device Under Test) 40 in the machine model.

  The ESD pulse generator 31 is a pulse generator that models an electrostatic discharge that is actually discharged from a charged transport device. The ESD pulse generator 31 includes an AC power supply 31a that changes in voltage in 200V steps, and a 200 pF power supply. A capacitor 31b, a 600nH inductance 31c, and a 0Ω resistor 31d are provided.

  The DUT 40 is the electrostatic discharge protection circuit 10 of the present embodiment or the conventional electrostatic discharge protection circuit 100.

  First, the electrostatic discharge protection circuit 10 of this embodiment is mounted as the DUT 40, an ESD surge generated by the ESD pulse generator 31 is applied, and a voltage waveform A at a connection point P between the ESD pulse generator 31 and the electrostatic discharge protection circuit 10 is obtained. obtain. Next, a conventional electrostatic discharge protection circuit 100 is mounted in place of the electrostatic discharge protection circuit 10 of the present embodiment, and an ESD surge generated by the ESD pulse generator 31 is applied, whereby the ESD pulse generator 31 and the electrostatic discharge protection circuit 100 are applied. A voltage waveform B at the connection point P is obtained. These waveforms A and B will be described later.

  Next, FIG. 6B will be described. FIG. 6B shows an ESD pulse generator 32 that generates static electricity and a DUT 40 in the human body model.

  The ESD pulse generator 32 is a pulse generator that models an electrostatic discharge that is actually discharged from a charged human body. The ESD pulse generator 32 includes an AC power supply 32a whose voltage changes in 2 KV steps, and a 100 pF capacitor. 32b, an inductance 32c of 2.4 μH, and a resistor 32d of 1.5 KΩ are provided.

  First, the electrostatic discharge protection circuit 10 of this embodiment is mounted as the DUT 40, an ESD surge generated by the ESD pulse generator 32 is applied, and a voltage waveform A at a connection point Q between the ESD pulse generator 32 and the electrostatic discharge protection circuit 10 is obtained. obtain. Next, a conventional electrostatic discharge protection circuit 100 is mounted in place of the electrostatic discharge protection circuit 10 of the present embodiment, and an ESD surge generated by the ESD pulse generator 32 is applied, whereby the ESD pulse generator 32 and the electrostatic discharge protection circuit 100 are applied. A voltage waveform B is obtained at the connection point Q. These waveforms A and B will also be described later.

  FIG. 7 is a diagram showing voltage waveforms A and B at the connection point P between the ESD pulse generator and the DUT in the machine model shown in FIG.

  The vertical axis | shaft shown in FIG. 7 shows the voltage (V) of the voltage waveforms A and B in the connection point P shown to Fig.6 (a). Specifically, the voltage waveforms A and B at the connection point P of the electrostatic discharge protection circuit 10 of the present embodiment and the conventional electrostatic discharge protection circuit 100 are shown. The horizontal axis indicates the time of these voltage waveforms A and B.

  As is clear from FIG. 7, the difference between the voltage waveform A and the voltage waveform B is small. Therefore, the electrostatic discharge protection circuit 10 of this embodiment is different in response in the machine model compared to the conventional electrostatic discharge protection circuit 100. Is negligible.

  FIG. 8 is a diagram showing voltage waveforms A and B at the connection point Q between the ESD pulse generator and the DUT in the human body model shown in FIG. 6B.

  The vertical axis | shaft shown in FIG. 8 shows the voltage (V) of the voltage waveforms A and B in the connection point Q shown in FIG.6 (b). Specifically, the voltage waveforms A and B at the connection point Q of the electrostatic discharge protection circuit 10 of the present embodiment and the conventional electrostatic discharge protection circuit 100 are shown. The horizontal axis indicates the time of these voltage waveforms A and B.

  As can be seen from FIG. 8, there is no difference between the voltage waveform A and the voltage waveform B. Therefore, the electrostatic discharge protection circuit 10 of the present embodiment is compared with the conventional electrostatic discharge protection circuit 100 in the human body model. There is no difference in response.

  Thus, it can be seen that there is no difference in performance between the electrostatic discharge protection circuit 10 of the present embodiment and the conventional electrostatic discharge protection circuit 100 from the viewpoint of electrostatic protection.

It is a figure which shows the structure of the electrostatic discharge protection circuit of one Embodiment of this invention. It is the figure which showed a mode that the noise generated with the circuit simulator was applied to the electrostatic discharge protection circuit of this embodiment, and the conventional electrostatic discharge protection circuit. It is a figure which shows the response waveform with respect to the noise which generate | occur | produced with the clock CLK of the frequency of 1 MHz of both the electrostatic discharge protection circuit of this embodiment, and the conventional electrostatic discharge protection circuit. It is a figure which shows the response waveform with respect to the noise which generate | occur | produced with the clock CLK of the frequency of 10 MHz of both the electrostatic discharge protection circuit of this embodiment, and the conventional electrostatic discharge protection circuit. It is a figure which shows the response waveform with respect to the noise which generate | occur | produced with the clock CLK of the frequency of 100 MHz of both the electrostatic discharge protection circuit of this embodiment, and the conventional electrostatic discharge protection circuit. It is a figure which shows the circuit of SPICE simulation which investigates the difference in the response with respect to ESD surge of the electrostatic discharge protection circuit of this embodiment, and the conventional electrostatic discharge protection circuit. It is a figure which shows the voltage waveforms A and B in the connection point P of an ESD pulse generator and DUT in the machine model shown to Fig.6 (a). It is a figure which shows the voltage waveforms A and B in the connection point Q of an ESD pulse generator and DUT in the human body model shown in FIG.6 (b). It is a figure which shows the structure of the electrostatic discharge protection circuit proposed by patent document 1. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Electrostatic discharge protection circuit 10_1 1st power supply line 10_2 2nd power supply line 11 Time constant circuit 11a, 31b, 32b Capacitor 11b N channel transistor 12, 13, 21_1, 21_2, ..., 21_n Inverter 12a, 13a P channel transistor 12b , 13b, 14 N-channel transistor 15 Diode 22 Power supply terminal 23, 25, 31c, 32c Inductance 24 Ground terminal 31, 32 ESD pulse generator 31a, 32a AC power supply 31d, 32d Resistance 40 DUT

Claims (3)

By connecting the DC power supply, a first power supply line having a predetermined first potential and a second power supply line having a second potential lower than the first potential,
A capacitor on the first power supply line side connected in series between the first power supply line and the second power supply line, and a first threshold voltage having a negative threshold voltage on the second power supply line side A time constant circuit composed of an N-channel transistor;
An inverter having an input side connected to a connection node between the capacitor and the first N-channel transistor, and an output side connected to a gate of the first N-channel transistor;
Connected between the first power supply line and the second power supply line, and the gate is indirectly connected to a connection node between the capacitor and the first N-channel transistor, and the potential of the connection node is increased. An electrostatic discharge protection circuit comprising: a second N-channel transistor which conducts in response to a rise in the potential of the gate due to the above.   2. The electrostatic discharge according to claim 1, further comprising a second inverter having the output of the inverter as an input, wherein the output of the second inverter is connected to the gate of the second N-channel transistor. Protection circuit.   3. The electrostatic discharge protection circuit according to claim 1, further comprising a diode having a cathode connected to the first power supply line and an anode connected to the second power supply line.

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