JP5214220B2 - Pulse modulator and charge pump circuit, switching regulator and control circuit using the same - Google Patents

Description

  The present invention relates to a pulse modulator.

  Electronic devices such as cellular phones and PDAs (Personal Digital Assistants) in recent years are equipped with devices that require a driving voltage higher than the battery voltage, such as LEDs (Light Emitting Diodes) used for liquid crystal backlights. The For example, in these small information terminals, a Li-ion battery is often used, and its output voltage is normally about 3.5V, and even when fully charged, it is about 4.2V. Requires a higher voltage. Thus, when a voltage higher than the battery voltage is required, the battery voltage is boosted using a charge pump circuit or a switching regulator to obtain a voltage necessary for driving the LED.

  A power supply circuit such as a switching regulator is pulse-modulated and driven so that the output voltage Vout is constant. When the output current (load current) of the switching regulator decreases and the light load state occurs, it is necessary to stop the switching operation and reduce the current consumption of the circuit.

In order to reduce power consumption at light load, the pulse width of the pulse modulated pulse signal (pulse modulated signal) is monitored, and switching is stopped when the pulse width becomes smaller than the predetermined minimum pulse width. Drive systems have been proposed. In this driving method, when a light load state is reached, an intermittent operation (referred to as an intermittent mode or a PFM mode) in which a switching period and a switching stop period are alternately repeated is performed.
JP 2000-262043 A

  It is desirable to stop switching immediately when the pulse width of the pulse modulation signal is below the minimum pulse width. Even though the pulse width is smaller than the minimum pulse width, if switching is performed with the pulse, the output voltage rises and a ripple occurs.

  The present invention has been made in view of these problems, and an object thereof is to provide a pulse modulator capable of reducing ripples in a PFM mode (intermittent mode) at light load.

  An aspect of the invention receives a feedback voltage corresponding to an output voltage of a power supply circuit, generates a pulse modulation signal whose duty ratio is controlled so that the feedback voltage approaches a predetermined reference voltage, and a switching element of the power supply circuit The present invention relates to a pulse modulator that outputs the signal. The pulse modulator amplifies the error between the feedback voltage and the reference voltage to generate an error voltage, an oscillator that generates a sawtooth wave periodic voltage having a predetermined frequency, and slices the periodic voltage with the error voltage. A comparator that outputs a pulse signal whose level changes at the intersection, a pulse divider that divides the pulse signal by half and generates a first pulse signal and a second pulse signal that are opposite in phase, and a first pulse The pulse width of the signal is compared with a predetermined minimum pulse width to generate a first mask signal that has a predetermined level when the pulse width of the first pulse signal is shorter than the minimum pulse width, and the pulse width of the second pulse signal is predetermined A mask signal generating unit that generates a second mask signal that has a predetermined level when the pulse width of the second pulse signal is shorter than the minimum pulse width compared to the minimum pulse width of Either the pulse signal or the second pulse signal, comprising a first, a period masked second mask signal becomes a predetermined level, and a mask processing unit that outputs a pulse modulated signal.

  According to this aspect, in a light load state, when the pulse width becomes smaller than a predetermined minimum pulse width, switching can be stopped and an intermittent mode (PFM mode) can be realized. Furthermore, the pulse width is smaller than the minimum pulse width by dividing the pulse signal with the same frequency as the periodic voltage, reducing the frequency of the pulse modulation signal, and generating the mask signal at the original frequency before frequency division. Unnecessary pulses can be masked. As a result, the ripple of the output voltage of the power supply circuit can be reduced.

  The mask signal generation unit receives a first minimum duty ratio setting signal having a frequency that is ½ of the periodic voltage and transitioning to a high level after a predetermined time delay from the positive edge of the first pulse signal. The first mask signal may be generated based on a comparison result between the timing of the positive edge of the duty ratio setting signal and the timing of the negative edge of the first pulse signal. The mask signal generation unit receives a second minimum duty ratio setting signal having a frequency that is ½ of the periodic voltage and transitioning to a high level after a predetermined time delay from the positive edge of the second pulse signal. The second mask signal may be generated based on a comparison result between the positive edge timing of the 2 minimum duty ratio setting signal and the negative edge timing of the second pulse signal.

  The mask signal generator has a first flip-flop in which the first minimum duty ratio setting signal is input to the clock terminal, the first pulse signal is input to the input terminal, and the second minimum duty ratio setting signal is input to the clock terminal. And a second flip-flop in which the second pulse signal is input to the input terminal, and the outputs of the first and second flip-flops may be output as the first and second mask signals, respectively.

  The pulse divider may generate the first pulse signal by performing a logical operation of the first maximum duty ratio setting signal having a frequency that is 1/2 the periodic voltage and a predetermined maximum duty ratio, and the pulse signal. Further, the pulse divider has a frequency that is ½ of the periodic voltage and a predetermined maximum duty ratio, and is based on a logical operation of the first maximum duty ratio setting signal, the second maximum duty ratio setting signal having a phase opposite to the first maximum duty ratio setting signal, and the pulse signal. A second pulse signal may be generated.

  The pulse divider outputs a first AND gate that outputs a logical product of the first maximum duty ratio setting signal and the pulse signal as a first pulse signal, and a logical product of the second maximum duty ratio setting signal and the pulse signal as a second pulse signal. And a second AND gate that outputs as a second AND gate.

The pulse modulator may further include a mask signal delay unit that delays the first and second mask signals by a predetermined delay time.
By delaying the mask signal, generation of whiskers (notches) in the pulse modulation signal can be prevented.

  The pulse modulator may further include a mask signal delay unit that delays the first and second mask signals by a predetermined delay time. The mask signal delay unit includes a third flip-flop in which the first mask signal is input to the input terminal and the first minimum duty ratio setting signal inverted to the clock terminal is input, and the second mask signal is input to the clock terminal. And a fourth flip-flop to which the inverted second minimum duty ratio setting signal is input.

  The periodic voltage may alternately repeat a first period in which the level is low and a second period in which the periodic voltage rises with a certain slope. At this time, the pulse divider outputs a logical product of the first maximum duty ratio setting signal and the pulse signal, which is at a high level, as the first pulse signal while the periodic voltage is odd-numbered in the second period. A gate and a second AND gate that outputs a logical product of the second maximum duty ratio setting signal and the pulse signal that are at a high level while the periodic voltage is in the second period evenly, as a second pulse signal. Good. The mask signal generation unit latches the first pulse signal by the positive edge of the first minimum duty ratio setting signal that becomes high level at a timing after a predetermined time has elapsed since the periodic voltage becomes the second period odd number. The second pulse is generated by the first flip-flop that generates one mask signal and the positive edge of the second minimum duty ratio setting signal that becomes high level at a timing after a predetermined time has elapsed since the periodic voltage has become the second period evenly. A second flip-flop that latches the signal and generates a second mask signal. The mask processing unit may include an AND gate that outputs a logical product of either the first pulse signal or the second pulse signal and the first and second mask signals. The odd-numbered and even-numbered items here represent positions with respect to a virtual reference pulse.

  Another aspect of the present invention relates to a control circuit for a charge pump circuit having at least one flying capacitor and at least one output capacitor. The control circuit includes a first switch group including at least one switch provided in a path for charging the flying capacitor using the input voltage, and a path for charging the output capacitor using the charge stored in the flying capacitor. A second switch group including at least one switch provided in the circuit, a feedback voltage corresponding to an output voltage of the charge pump circuit, and any one of the above-described pulse modulators that generate a pulse modulation signal; A driver that receives the pulse modulation signal, turns on one of the first and second switch groups for a period corresponding to the high period of the pulse modulation signal, and turns on the other for the period corresponding to the low period.

  According to this aspect, the charge pump circuit can be driven by the PWM method, and can be operated in the intermittent mode in a light load state. In addition, the ripple of the output voltage in a light load state can be reduced.

  Yet another embodiment of the present invention is a charge pump circuit. The charge pump circuit includes a flying capacitor, an output capacitor, and the above-described control circuit that controls charging and discharging states of the flying capacitor and the output capacitor.

  Yet another embodiment of the present invention relates to a control circuit for a switching regulator having at least one switching element. The control circuit receives a feedback voltage corresponding to the output voltage of the switching regulator, generates a pulse modulation signal, receives the pulse modulation signal from the pulse modulator, and based on the pulse modulation signal. And a driver for driving the switching element.

  Yet another embodiment of the present invention is a switching regulator. This switching regulator includes the above-described control circuit.

  Still another embodiment of the present invention relates to a pulse modulation method for generating a pulse modulation signal in which a duty ratio is controlled so that a level of a feedback signal approaches a predetermined reference value. This method includes a step of amplifying an error between a feedback signal and a reference value to generate an error signal, a step of generating a sawtooth wave periodic signal having a predetermined frequency, slicing the periodic signal with an error signal, and A step of generating a pulse signal whose level changes, a step of dividing the pulse signal by 1/2 and generating a first pulse signal and a second pulse signal having opposite phases, and a pulse width of the first pulse signal. Generating a first mask signal having a predetermined level when the pulse width of the first pulse signal is shorter than the minimum pulse width compared to the predetermined minimum pulse width; and changing the pulse width of the second pulse signal to the predetermined minimum pulse width And generating a second mask signal having a predetermined level when the pulse width of the second pulse signal is shorter than the minimum pulse width, and the first pulse signal or the second pulse. One of signals, comprising the steps of first, second mask signal to produce a pulse modulated signal with a period masks a predetermined level, the.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  According to the pulse modulation technique of the present invention, output voltage ripple in a light load state can be reduced.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A and the member B are connected” means that the member A and the member B are physically directly connected, or the member A and the member B are in an electrically connected state. Including the case of being indirectly connected through other members that do not affect the above.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical connection. The case where it is indirectly connected through another member that does not affect the state is also included.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a charge pump circuit 120 according to the first embodiment of the present invention. The charge pump circuit 120 boosts the input voltage Vin input to the input terminal 122 and outputs the output voltage Vout from the output terminal 124. As the input voltage Vin, a battery voltage output from a battery (not shown) or a power supply voltage Vdd supplied from a power supply circuit is used. The present invention can be applied to a charge pump circuit having an arbitrary step-up ratio. However, in order to facilitate understanding, a double charge pump circuit will be described below.

  The charge pump circuit 120 includes a control circuit 100, a flying capacitor Cf1, an output capacitor Co1, and feedback resistors R1 and R2. The charge pump circuit of FIG. 1 has one flying capacitor Cf1 and one output capacitor Co1 because the boost rate is twice, but when the boost rate is different or when generating a plurality of output voltages, There may be a plurality of capacitors and output capacitors.

  The control circuit 100 includes a first switch group 10, a second switch group 12, a pulse modulator 20, and a driver 40, and is a functional circuit integrated on one semiconductor substrate. An input voltage Vin from the outside is applied to the input terminal 102. A flying capacitor Cf1 is connected between the capacitor terminal 104 and the capacitor terminal 106, and an output capacitor Co1 is connected between the output terminal 108 and the ground. The ground terminal 110 is grounded, and a feedback voltage Vfb corresponding to the output voltage Vout is input to the feedback terminal 112. The feedback voltage Vfb is a voltage obtained by dividing the output voltage Vout by the feedback resistor R1 and the feedback resistor R2.

  Generally, the charge pump circuit generates a boosted voltage by repeating a charging period φ1 for charging the flying capacitor and a discharging period φ2 for charging the output capacitor using the charge stored in the flying capacitor. .

  The first switch group 10 includes at least one switch provided in a path for charging the flying capacitor Cf1 using the input voltage Vin. The first switch group 10 and the flying capacitor Cf1 form a series path between the input terminal 122 and the ground. In the present embodiment, the first switch group 10 includes a first switch SW1 and a second switch SW2. Specifically, the first switch SW1 is provided between the input terminal 102 and the capacitor terminal 104, and the second switch SW2 is provided between the capacitor terminal 106 and the ground terminal 110. The first switch SW1 is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the second switch SW2 is an N-channel MOSFET.

  The second switch group 12 includes at least one switch provided in a path for charging the output capacitor Co1 using the charge stored in the flying capacitor Cf1 during the charging period φ1. In the present embodiment, the second switch group 12 includes a third switch SW3 and a fourth switch SW4. Specifically, the third switch SW3 is provided between the input terminal 102 and the capacitor terminal 106. The fourth switch SW4 is provided between the capacitor terminal 104 and the output terminal 108. Both the third switch SW3 and the fourth switch SW4 are P-channel MOSFETs.

  The driver 40 includes a level shift circuit, and controls on / off by switching gate voltages of the first switch SW1 to the fourth switch SW4.

  When both the first switch SW1 and the second switch SW2 are turned on during the charging period φ1, the input voltage Vin is applied to one end of the flying capacitor Cf1, and the other end is grounded. As a result, the flying capacitor Cf1 is charged with the input voltage Vin. Is done. A potential difference between both ends of the flying capacitor Cf1 is ΔV.

  When both the third switch SW3 and the fourth switch SW4 are turned on during the discharge period φ2, the potential of the capacitor terminal 106 becomes equal to the input voltage Vin, and the potential of the capacitor terminal 104 becomes Vin + ΔV. The potential of the capacitor terminal 104 is applied to the output capacitor Co1 via the fourth switch SW4, whereby the output capacitor Co1 is charged.

  The driver 40 alternately repeats the charging period φ1 and the discharging period φ2 to boost the input voltage Vin. In the conventional charge pump circuit, the charging period φ1 and the discharging period φ2 are assigned to the high level and the low level of the clock signal having a duty ratio of 50%, so that the charging period φ1 and the discharging period φ2 are fixed. On the other hand, the charge pump circuit 120 according to the present embodiment is characterized in that the charging period φ1 and the discharging period φ2 are adjusted by feedback.

  The pulse modulator 20 generates a pulse modulation signal Spwm3 and supplies it to the driver 40. The driver 40 assigns the high period TH of the pulse modulation signal Spwm3 to either the charging period φ1 or the discharging period φ2, assigns the low period TL to the other, and turns on the first switch group 10 and the second switch group 12 alternately. .

  A feedback voltage Vfb corresponding to the output voltage Vout of the charge pump circuit 120 is input to the pulse modulator 20. The pulse modulator 20 adjusts the duty ratio of the pulse modulation signal Spwm3 so that the feedback voltage Vfb matches the predetermined reference voltage Vref. The duty ratio is a ratio of the cycle time Tp (= TH + TL) to the high period TH. In the present embodiment, the pulse modulator 20 performs pulse width modulation.

  The driver 40 provides a dead time so that the first switch group 10 and the second switch group 12 are not turned on at the same time, and the first switch group 10 and the second switch group 10 in the vicinity of the positive edge and the negative edge of the pulse modulation signal Spwm3. It is preferable to set a dead time during which both the two switch groups 12 are turned off. A known technique may be used as a dead time setting method.

  The pulse modulator 20 adjusts the duty ratio of the pulse modulation signal Spwm3 by limiting it to a predetermined range. Hereinafter, the reason will be described.

  When the duty ratio of the pulse modulation signal Spwm3 is 0%, the first switch group 10 is not turned on, so that the flying capacitor Cf1 is not charged by the input voltage Vin. Therefore, charge transfer to the output capacitor Co1 is not performed, and the current supply capability (driving capability) to a load (not shown) connected to the output terminal 124 is low (substantially 0).

  As the duty ratio of the pulse modulation signal Spwm3 increases within a certain range, the charging period φ1 for the flying capacitor Cf1 becomes longer. Accordingly, the amount of charge stored in the flying capacitor Cf1 increases during the charging period φ1, and the potential difference ΔV of the flying capacitor Cf1 immediately after the charging period φ1 increases.

  As described above, the output capacitor Co1 is charged with a voltage of Vin + ΔV in the discharge period φ2. Therefore, when the potential difference ΔV of the flying capacitor Cf1 increases, the amount of charge supplied to the output capacitor Co1 during the discharge period φ2 increases. That is, as the duty ratio of the pulse modulation signal Spwm3 increases, the current supply capability to the load increases.

  As the duty ratio of the pulse modulation signal Spwm3 is increased, the charging period φ1 for the flying capacitor Cf1 becomes longer. However, the upper limit value of the potential difference ΔV immediately after the charging period φ1 is the input voltage Vin. Now, the duty ratio when the potential difference ΔV reaches the upper limit value is written as α%. As the duty ratio of the pulse modulation signal Spwm3 increases beyond α%, the discharge period φ2 becomes shorter while the amount of charge supplied to the flying capacitor Cf1 is constant during the charge period φ1. As a result, as the duty ratio increases, the amount of charge supplied to the output capacitor Co1 during the discharge period φ2 decreases. That is, as the duty ratio of the pulse modulation signal Spwm3 increases beyond α%, the current supply capability with respect to the load decreases.

  When the duty ratio of the pulse modulation signal Spwm3 becomes 100%, charge transfer from the flying capacitor Cf1 to the output capacitor Co1 is not performed, and the current supply capability to the load becomes substantially zero.

  That is, the current supply capability of the charge pump circuit 120 is minimum when the duty ratio is 0% and 100%, and is maximum when the duty ratio is a certain value α%. In other words, the duty ratio has a value that gives the maximum value to the current supply capability of the charge pump circuit.

  Therefore, the output voltage Vout is monitored, and when the output voltage Vout decreases, that is, when the load current increases, the current supply capability of the charge pump circuit 120 is increased, and conversely, when the output voltage Vout increases, That is, when the load current decreases, the output voltage Vout can be maintained at a constant value by performing feedback so as to decrease the current supply capability of the charge pump circuit 120.

  If the duty ratio of the pulse modulation signal Spwm3 changes across α%, the output voltage Vout becomes unstable because feedback is applied in a direction away from the target value. Therefore, the charge pump circuit 120 according to the present embodiment limits the duty ratio of the pulse modulation signal Spwm3 to a predetermined range.

  Thus, in the charge pump circuit 120 according to the present embodiment, the output voltage is controlled by controlling the first switch group 10 and the second switch group 12 based on the pulse modulation signal Spwm3 in which the range of the duty ratio is limited. Vout can be stabilized.

  The conventional charge pump circuit can output only the 4V output voltage Vout when the input voltage is 2V. Therefore, in order to obtain a desired voltage of 4 V or less, it is necessary to provide a linear regulator before or after the charge pump circuit, which increases the circuit area. On the other hand, according to the charge pump circuit 120 according to the present embodiment, since the output voltage Vout can be stabilized to a desired value without providing a regulator, the circuit area can be reduced.

  Further, when a regulator is provided as in the prior art, since the power transistor is inserted on the path from the input terminal to which the input voltage is supplied to the load, the efficiency is reduced due to the power loss of the power transistor. On the other hand, since the charge pump circuit 120 according to the present embodiment does not require a power transistor, the circuit efficiency can be improved.

  The value α depends on the capacitance values of the flying capacitor Cf1 and output capacitor Co1 and the frequency (period time Tp) of the pulse modulation signal Spwm3, but is typically 50%. Hereinafter, a case where α = 50% will be described.

The predetermined range is
(1) 0% to βmax%
(2) γ min% to 100%
Can be set to either. Hereinafter, feedback control in each range will be described.

(1) First Control Method The pulse modulator 20 modulates the pulse modulation signal Spwm3 so that the high period TH becomes longer as the feedback voltage Vfb is lower. At this time, the upper limit value βmax is set to the duty ratio of the pulse modulation signal Spwm3, and modulation is performed so that the duty ratio of the pulse modulation signal Spwm3 changes within the range of 0% to the upper limit value βmax%.

  It is desirable to set βmax ≦ α. In this case, since the change across the duty ratio α can be prevented, the output voltage Vout can be stabilized. However, βmax may be set to be larger than α when it is permissible to generate ripples in the output voltage Vout. In order to maximize the efficiency of the charge pump circuit, it is preferable to set βmax = α. When α = 50, βmax is set as large as possible between 0% and 50%.

  When βmax = 45%, the high period TH changes in a range of Tp × (0 to 0.45), and the low period TL changes in a range of Tp × (1 to 0.55). That is, the low period TL is limited to be longer than the high period TH. At this time, the driver 40 preferably turns on the first switch group 10 for a period corresponding to the high period TH of the pulse modulation signal Spwm3 and turns on the second switch group 12 for a period corresponding to the low period TL. That is, it is preferable that the time for which the second switch group 12 is turned on is lengthened. The reason for this will be explained.

Now, the capacity desired from the output terminal 124 to the control circuit 100 side will be considered. In the charging period φ1, the fourth switch SW4 is turned off, so that the capacitor connected to the output terminal 124 is only the output capacitor Co1. In the discharge period φ2, the flying capacitor Cf1 is connected in addition to the output capacitor Co1. When the load current is constant, the fluctuation of the output voltage Vout becomes smaller as the capacitance connected to the output terminal 124 is larger.
Therefore, by assigning the time corresponding to the high period TH of the pulse modulation signal Spwm3 to the charging period φ1, the discharging period φ2 becomes longer than the charging period φ1, and therefore the ripple of the output voltage Vout can be reduced.

  Although the longer discharge period φ2 has the advantage that the ripple of the output voltage Vout can be reduced, the high period TH may be assigned to the discharge period φ2 when the capacitance of the output capacitor Co1 is large or when the ripple is acceptable.

  The control circuit 100 in FIG. 1 shows a configuration for executing the first control method. The pulse modulator 20 includes an error amplifier 22, an oscillator 24, a PWM (Pulse Width Modulation) comparator 26, an AND gate 30, a minimum duty comparator 32, a PFM (Pulse Frequency Modulation) controller 34, and a maximum duty comparator 28.

  The error amplifier 22 receives the feedback voltage Vfb at the inverting input terminal and the reference voltage Vref at the non-inverting input terminal, and amplifies the error between the two voltages. The output of the error amplifier 22 is referred to as an error voltage Verr. The oscillator 24 outputs a triangular wave or a sawtooth wave periodic voltage Vosc. The PWM comparator 26 receives the error voltage Verr at the non-inverting input terminal and the periodic voltage Vosc at the inverting input terminal. The PWM comparator 26 slices the periodic voltage Vosc with the error voltage Verr and outputs a pulse signal Spwm1 whose level changes at the intersection. The pulse width of the pulse signal Spwm1 is modulated so that the output voltage Vout approaches the target value.

  Maximum duty comparator 28 receives periodic voltage Vosc and maximum voltage Vmax. The maximum duty comparator 28 slices the periodic voltage Vosc with the maximum voltage Vmax, and generates a maximum pulse modulation signal Smax having a predetermined duty ratio. The value of the maximum voltage Vmax is set so that the duty ratio of the maximum pulse modulation signal Smax matches the value of β described above.

  The AND gate 30 receives the pulse modulation signal Spwm2 output from the PFM controller 34 and the maximum pulse modulation signal Smax, and outputs a logical product of the two signals. The output of the AND gate 30, that is, the duty ratio of the pulse modulation signal Spwm3 coincides with the duty ratio of the pulse signal Spwm1 when the duty ratio of the pulse signal Spwm1 is equal to or less than βmax%, and the duty ratio of the pulse signal Spwm1 is equal to or greater than βmax%. Then βmax%. In order to limit the duty ratio of the pulse modulation signal Spwm3, another circuit configuration may be used, and the format is not limited.

  The pulse modulator 20 compares the duty ratio of the pulse signal Spwm1 with a predetermined lower limit value βmin. When the duty ratio of the pulse signal Spwm1 is smaller than the lower limit value βmin, the level of the pulse signal Spwm1 is fixed, and the first switch group 10. Stop the switching of the second switch group 12. That is, no pulse is output from the pulse modulator 20. For this purpose, a minimum duty comparator 32 and a PFM controller 34 are provided.

  The pulse modulator 20 desirably fixes the level of the pulse modulation signal Spwm3 so that the second switch group 12 is turned on when the duty ratio of the pulse modulation signal Spwm3 is smaller than the lower limit value βmin. The reason will be described later.

  The minimum duty comparator 32 receives the periodic voltage Vosc and the minimum voltage Vmin. The minimum duty comparator 32 slices the periodic voltage Vosc with the minimum voltage Vmin, and generates a minimum pulse modulation signal Smin having a predetermined duty ratio. The value of the minimum voltage Vmin is set so that the duty ratio of the minimum pulse modulation signal Smin is about 20%.

  The PFM controller 34 receives the pulse signal Spwm1 and the minimum pulse modulation signal Smin, and compares the duty ratios of the two signals. When the duty ratio of the pulse signal Spwm1 becomes smaller than the duty ratio of the minimum pulse modulation signal Smin, the duty ratio of the pulse modulation signal Spwm2 is fixed to a low level. When the duty ratio of the pulse signal Spwm1 is larger than the duty ratio of the minimum pulse modulation signal Smin, the pulse modulation signal Spwm2 is equal to the pulse signal Spwm1.

  Note that the order of the AND gate 30 and the PFM controller 34 may be reversed.

  The operation of the charge pump circuit 120 configured as described above will be described. FIG. 2 is a signal waveform diagram of the charge pump circuit 120 of FIG. In the waveform diagrams shown in this specification, the vertical axis and the horizontal axis are appropriately enlarged or reduced for the sake of brevity of explanation or easy understanding.

  As the load current increases, a large amount of charge is supplied from the output capacitor Co1 to the load, so that the output voltage Vout decreases and the error voltage Verr increases. The duty ratio of the pulse signal Spwm1 increases as the output voltage Vout decreases. However, the duty ratio of the pulse modulation signal Spwm3 is limited to be equal to or less than the duty ratio βmax of the maximum pulse modulation signal Smax. When the duty ratio of the pulse signal Spwm1 becomes smaller than the duty ratio βmin of the minimum pulse modulation signal Smin, the pulse modulation signal Spwm3 is fixed at a low level and the pulse is cut.

FIGS. 3A and 3B are operation waveform diagrams of the charge pump circuit 120 at normal load and light load, respectively.
As shown in FIG. 3A, when the load current is large and constant, the duty ratio of the pulse signal Spwm1 is adjusted by feedback. The first switch group 10 is turned on during the charging period φ1 when the pulse modulation signal Spwm3 is high level, and the second switch group 12 is turned on during the discharge period φ2 when the pulse signal Spwm1 is low level. In the charging period φ1, since the load current flows out from the output capacitor Co1, the output voltage Vout decreases. In the discharge period φ2, since the output capacitor Co1 is charged using the flying capacitor Cf1, the output voltage Vout rises. By repeating the charging period φ1 and the discharging period φ2, the output voltage Vout is stabilized near the target value while slightly changing.

  FIG. 3B shows the operation at light load. In a light load state, the duty ratio of the pulse signal Spwm1 is smaller than the minimum duty ratio βmin. As a result, the switching of the first switch group 10 and the second switch group 12 stops, and the charging operation of the output capacitor Co1 stops. During this time, since the output capacitor Co1 is discharged by a small load current, the output voltage Vout gradually decreases. As the output voltage Vout decreases, the error voltage Verr increases, and when the duty ratio of the pulse signal Spwm1 exceeds the minimum duty ratio βmin at time t1, the pulse modulation signal Spwm3 becomes high level and the charging period φ1 is reached. . In the discharge period φ2 immediately after that, the output capacitor Co1 is charged, and the output voltage Vout rises. When the output voltage Vout increases, the error voltage Verr decreases again, the duty ratio becomes smaller than the minimum duty ratio βmin, and switching stops.

  Thus, in the charge pump circuit 120 according to the present embodiment, the duty ratio of the pulse modulation signal Spwm3 is monitored, and a pulse smaller than the lower limit value βmin is cut to operate in the intermittent mode in a light load state. Can do. In order to switch the first switch group 10 and the second switch group 12 on and off, a drive current for charging and discharging the gate capacitance of each transistor is required. Therefore, current consumption of the charge pump circuit 120 can be reduced.

Further, when the pulse modulation signal Spwm3 is fixed at a low level at a light load, the circuit stops in a state where the second switch group 12 is turned on. Therefore, since the combined capacitance of the flying capacitor Cf1 and the output capacitor Co1 is connected to the output terminal 124, the ripple of the output voltage Vout can be reduced.
However, the present invention is not limited to this, and the pulse modulation signal Spwm3 may be fixed at a high level at light load.

  Note that the ripple of the output voltage Vout shown in FIG. 3B is larger than that of FIG. 3A, but is actually the same or smaller. This is because the amount of discharge from the output capacitor Co1 is small and the amount of decrease in the output voltage Vout is small when the load current is small and the load is light.

The above is the operation of the charge pump circuit 120 according to the present embodiment. It should be noted that the pulse modulation technique of the charge pump circuit 120 has a different idea from the pulse modulation technique of the switching regulator. That is, when performing pulse width modulation in a step-up switching regulator, the duty ratio Dsr of the generated pulse modulation signal is:
Dsr = 1−Vin / Vout
Given in. That is, the duty ratio of the pulse modulation signal is adjusted according to the input voltage Vin and the target value Vout of the output voltage.

  On the other hand, in the pulse modulation of the charge pump circuit 120 according to the present embodiment, the duty ratio of the pulse modulation signal Spwm3 is different from the pulse modulation of the switching regulator in that it is determined according to the load current.

  In the switching regulator, feedback is applied in the direction in which the output voltage Vout increases as the duty ratio is increased. In the charge pump circuit, however, the feedback direction is reversed when the duty ratio crosses a certain boundary value. For this reason, in the charge pump circuit 120 according to the present embodiment, a limit is provided in the range of the duty ratio of the pulse modulation signal Spwm3.

(2) Second Control Method In the first control method, the pulse modulation signal is modulated so that the high period TH becomes longer as the feedback voltage Vfb is lower. On the other hand, in the second control method, the pulse modulation signal Spwm3 is modulated so that the low period TL becomes longer as the feedback voltage Vfb is lower. Further, a lower limit value γmin is set for the duty ratio of the pulse modulation signal Spwm3, and modulation is performed so that the duty ratio of the pulse modulation signal Spwm3 changes in a range from the lower limit value γmin% to 100%.

  At this time, it is desirable to set γmin ≧ α. In this case, since the change across α can be prevented, the output voltage Vout can be stabilized. However, γmin may be made smaller than α when ripples are allowed to occur in the output voltage Vout.

  In order to maximize the efficiency of the charge pump circuit, it is preferable to set γmin = α. When α = 50, γmin is set as small as possible between 50% and 100%.

  When γmin = 55%, the high period TH changes in a range of Tp × (0.55 to 1), and the low period TL changes in a range of Tp × (0.45 to 0). That is, the high period TH is limited to be longer than the low period TL. At this time, the driver 40 preferably turns on the first switch group 10 for a period corresponding to the low period TL of the pulse modulation signal Spwm3 and turns on the second switch group 12 for a period corresponding to the high period TH. That is, it is preferable that the time for which the second switch group 12 is turned on is lengthened. Thereby, the ripple of the output voltage Vout can be reduced.

  In order to realize the second control method, the control circuit 100 of FIG. 1 may be modified. For example, the reference voltage Vref may be input to the inverting input terminal of the error amplifier 22 and the feedback voltage Vfb may be input to the non-inverting input terminal. In this case, the smaller the load current, that is, the larger the output voltage Vout, the larger the error voltage Verr, and the duty ratio of the pulse signal Spwm1 approaches 100%. As a result, the current supply capability to the load is reduced, and appropriate feedback can be applied. As the load current increases, the duty ratio approaches α and the current supply capability increases.

  In this case, the maximum duty comparator 28 generates a pulse modulation signal having a duty ratio of γmin, and the duty ratio of the pulse modulation signal Spwm3 may be limited to be γmin or more.

  In the second control method, in order to realize the intermittent mode at light load, the upper limit value γmax is set to the duty ratio of the pulse modulation signal Spwm3, and the pulse modulation is performed when the duty ratio of the pulse modulation signal Spwm3 is larger than the upper limit value γmax. The level of the signal Spwm3 is fixed. In this case, a pulse modulation signal having a duty ratio γmax may be generated by the minimum duty comparator 32.

  In the second control method, the same effect as that of the first control method can be obtained.

(Second Embodiment)
In the second embodiment, another configuration of a pulse modulator that can be suitably used for the charge pump circuit 120 according to the first embodiment will be described.
This pulse modulator is similar to that described in the first embodiment.
(1) Function for limiting the duty ratio of the pulse modulation signal Spwm3 to a predetermined range (2) Monitoring the duty ratio of the pulse modulation signal Spwm3 and cutting a pulse smaller than the lower limit value so that the intermittent mode can be used in a light load state. (Hereinafter also referred to as PFM mode).

  FIG. 4 is a circuit diagram showing a configuration of a pulse modulator 20a according to the second embodiment. The pulse modulator 20a includes an error amplifier 22, an oscillator 24, a PWM comparator 26, a pulse divider 50, and a PFM controller 60.

  The error amplifier 22 receives the feedback voltage Vfb at the inverting input terminal and the reference voltage Vref at the non-inverting input terminal, and amplifies the error between the two voltages. The oscillator 24 outputs a periodic voltage Vosc of a sawtooth wave (ramp waveform). The PWM comparator 26 receives the error voltage Verr at the non-inverting input terminal and the periodic voltage Vosc at the inverting input terminal. The PWM comparator 26 slices the periodic voltage Vosc with the error voltage Verr and outputs a pulse signal Spwm1 whose level changes at the intersection. The pulse width of the pulse signal Spwm1 is modulated so that the output voltage Vout approaches the target value.

  The pulse divider 50 divides the pulse signal Spwm1 having the same frequency as the periodic voltage Vosc by 1/2 to generate a first pulse signal S1 and a second pulse signal S2 that are in opposite phases to each other. The pulse divider 50 in FIG. 4 alternately distributes each pulse included in the pulse signal Spwm1 to the first pulse signal S1 and the second pulse signal S2. That is, the first pulse signal S1 includes an odd-numbered (or even-numbered) pulse of the pulse signal Spwm1, and the second pulse signal S2 includes an even-numbered (or odd-numbered) pulse. As a result, the frequencies of the first pulse signal S1 and the second pulse signal S2 are both ½ of the frequency of the pulse signal Spwm1.

  One of the first pulse signal S1 and the second pulse signal S2 is masked by the PFM controller 60 at the subsequent stage as necessary, and is output as the final pulse modulation signal Spwm3. In the circuit of FIG. 4, the first pulse signal S <b> 1 is masked by the PFM controller 60.

  For example, the pulse divider 50 includes two first AND gates 52 and a second AND gate 54. The first AND gate 52 generates a logical product of the pulse signal Spwm1 and a first maximum duty ratio setting signal (hereinafter referred to as a MAXDUTY1 signal) as the first pulse signal S1. Similarly, the second AND gate 54 generates a logical product of the pulse signal Spwm1 and a second maximum duty ratio setting signal (hereinafter referred to as a MAXDUTY2 signal) as the second pulse signal S2.

  The MAXDUTY1 signal and the MAXDUTY2 signal have a frequency that is ½ of the frequency of the periodic voltage Vosc, and have a predetermined duty ratio. For example, these signals are at a high level during the period when the periodic voltage Vosc rises with a constant slope. The MAXDUTY1 signal and the MAXDUTY2 signal alternately become high level in synchronization with the periodic voltage Vosc.

  The pulse frequency divider 50 generates a first pulse signal S1 and a second pulse signal S2 having a frequency half that of the pulse signal Spwm1 and having opposite phases.

  The PFM controller 60 receives the first pulse signal S1 and the second pulse signal S2. The PFM controller 60 uses the first pulse signal S1, the second pulse signal S2, the first minimum duty ratio setting signal (hereinafter referred to as MINDUTY1 signal), and the second minimum duty ratio setting signal (hereinafter referred to as MINDUTY2 signal). First mask signal Smsk1 and second mask signal Smsk2 for masking first pulse signal S1 at the time of light load are generated. Pulses having a duty ratio smaller than the lower limit value are cut by the first mask signal Smsk1 and the second mask signal Smsk2.

  The PFM controller 60 includes a mask signal generation unit 62, a mask signal delay unit 64, and a mask processing unit 66.

  The mask signal generator 62 monitors the pulse width (high level time) TH1 of the first pulse signal S1 and compares it with the minimum pulse width tmin. The mask signal generation unit 62 generates a first mask signal smsk1 that is at a high level when TH1 <tmin. Similarly, the mask signal generator 62 monitors the pulse width (high level time) TH2 of the second pulse signal S2, and compares it with the minimum pulse width tmin. The mask signal generation unit 62 generates a second mask signal smsk2 that is high when TH2 <tmin.

The mask signal generation unit 62 includes a first flip-flop FF1 and a second flip-flop FF2.
The first flip-flop FF1 latches the first pulse signal S1 using the positive edge of the MINDUTY1 signal. The second flip-flop FF2 latches the second pulse signal S2 using the positive edge of the MINDUTY2 signal.
The MINDUTY1 signal and the MINDUTY2 signal each have a frequency that is ½ of the frequency of the periodic voltage Vosc, and are opposite phase signals that alternately become a high level. The MINDUTY1 signal has a positive edge at a timing delayed by the minimum pulse width tmin from the positive edge of the MAXDUTY1 signal. Similarly, the MINDUTY2 signal has a positive edge at a timing delayed by the minimum pulse width tmin from the positive edge of the MAXDUTY2 signal.

  That is, the mask signal generation unit 62 generates the first mask signal Smsk1 based on the comparison result between the positive edge timing of the MINDUTY1 signal and the negative edge timing of the first pulse signal S1. Similarly, the mask signal generation unit 62 generates the second mask signal Smsk2 based on the comparison result between the positive edge timing of the MINDUTY2 signal and the negative edge timing of the second pulse signal S2.

  FIG. 5 is a time chart showing operation states of the pulse frequency divider 50 and the PFM controller 60.

  The periodic voltage Vosc shown in FIG. 5 alternately repeats a first period τ1 that is at a low level and a second period τ2 that rises at a constant slope. The MAXDUTY1 signal is at a high level while the periodic voltage Vosc is odd-numbered for the second period τ2. The MAXDUTY2 signal is at a high level while the periodic voltage Vosc is in the even-numbered second period τ2. The MINDUTY1 signal becomes a high level at a timing after the elapse of a predetermined period corresponding to the minimum pulse width tmin after the periodic voltage Vosc is odd-numbered in the second period τ2. The MINDUTY2 signal becomes a high level at a timing after the elapse of a predetermined time corresponding to the minimum pulse width tmin after the periodic voltage Vosc becomes the second period τ2 evenly.

  The first pulse signal S1 is generated when the pulse width (duty ratio) of the pulse signal Spwm1 is limited by the MAXDUTY1 signal. Since the first pulse signal S1 is a logical product of the pulse signal Spwm1 and MAXDUTY1, the positive edge of the first pulse signal S1 coincides with the positive edge of the MAXDUTY1 signal.

  As described above, the positive edge of the MINDUTY1 signal appears later than the positive edge of the MAXDUTY1 signal and the first pulse signal S1 by the minimum pulse width tmin. Therefore, by latching the value of the first pulse signal S1 with the positive edge of the MINDUTY1 signal, it is possible to determine whether the pulse width TH1 of the first pulse signal S1 is longer or shorter than the minimum pulse width tmin. The output signal of the first flip-flop FF1 is high level when TH> tmin, and low level when TH <tmin. The output signal of the first flip-flop FF1 is output as the first mask signal Smsk1. A similar process is performed on the second pulse signal S2 by the second flip-flop FF2, and a second mask signal Smsk2 is generated.

The mask signal delay unit 64 delays the first mask signal Smsk1 and the second mask signal Smsk2 generated by the mask signal generation unit 62 by a predetermined time (hereinafter referred to as a delay time) td.
The mask signal delay unit 64 includes a third flip-flop FF3, a fourth flip-flop FF4, a first NOT gate 68, and a second NOT gate 70.

  The MINDUTY1 signal is inverted by the first NOT gate 68. The third flip-flop FF3 latches the first mask signal Smsk1 at the positive edge of the output of the first NOT gate 68, that is, the negative edge of the MINDUTY1 signal.

  The output Smsk1 'of the third flip-flop FF3 transitions the first mask signal Smsk1 with a delay of the pulse width td of the MINDUTY1 signal. That is, the third flip-flop FF3 functions as a delay circuit. The fourth flip-flop FF4 and the second NOT gate 70 delay the second mask signal Sskk2 by the pulse width td of the MINDUTY1 signal.

  The mask processing unit 66 masks either the first pulse signal S1 or the second pulse signal S2 for a period during which the first mask signal Smsk1 ′ and the second mask signal Smsk2 ′ are at a predetermined level (low level). The modulated signal Spwm3 is output.

  The mask processing unit 66 is an AND gate, and outputs a logical product of the first pulse signal S1, the first mask signal Smsk1 ', and the second mask signal Smsk2'. That is, the first pulse signal S1 is masked using the first mask signal Smsk1 'and the second mask signal Sskk2'. The output of the mask processing unit 66 is output to the driver 40 as a pulse modulation signal Spwm3. The mask processing unit 66 may mask and output the second pulse signal S2 instead of the first pulse signal S1.

  The above is the configuration of the pulse modulator 20a. Next, the operation of the pulse modulator 20a will be described. FIG. 6 is a time chart showing an operation state of the pulse modulator 20a of FIG.

The time chart of FIG. 6 shows a waveform when transitioning from a heavy load state to a light load state. Before the time t0, it is a heavy load state, and then the load gradually decreases.
As the load becomes lighter, the error voltage Verr decreases and the duty ratio of the pulse signal Spwm1 decreases. The duty ratio of the first pulse signal S1 and the second pulse signal S2 obtained by dividing the pulse signal Spwm1 also follows the duty ratio of the pulse signal Spwm1.

  Since the pulse width TH1 of the first pulse signal S1 and the pulse width TH2 of the second pulse signal S2 are both longer than the minimum pulse width tmin, the first mask signal Ssk1 and the second mask signal Ssk2 are set to a high level. As a result, the first pulse signal S1 is output as it is as the pulse modulation signal Spwm3 (PWM mode).

  Since the first pulse signal S1 is generated by dividing the original pulse modulation signal Spwm3 by ½, its duty ratio is limited to 50% or less. Strictly speaking, since the frequency division of the first pulse signal S1 is performed by mask processing using the MAXDUTY1 signal whose duty ratio is slightly smaller than 50%, the duty ratio of the first pulse signal S1 (pulse modulation signal Spwm3) is , Limited to the duty ratio of the MAXDUTY1 signal. That is, the pulse modulator 20a has the above function (1).

  At time t1, the pulse width TH2 of the second pulse signal S2 becomes shorter than the minimum pulse width tmin, and the second mask signal Sskk2 transitions to a low level at the timing of the positive edge of the MINDUTY2 signal. At the timing of the negative edge of the subsequent MINDUTY2 signal, the second mask signal Sskk2 'transitions to a low level.

  At the subsequent time t2, the pulse width TH1 of the first pulse signal S1 becomes shorter than the minimum pulse width tmin, and the first mask signal Smsk1 transitions to the low level at the timing of the positive edge of the MINDUTY1 signal. At the timing of the negative edge of the subsequent MINDUTY1 signal, the first mask signal Smsk1 'transitions to a low level.

  When at least one of the first mask signal Sskk1 'and the second mask signal Smsk2' becomes low level, the pulse of the first pulse signal S1 is masked, and the pulse modulation signal Spwm3 is fixed at low level. When the pulse modulation signal Spwm3 is fixed at a low level, the switching operation of the charge pump circuit 120 is stopped, so that the charge supply to the output capacitor Co1 is stopped. As a result, the output voltage Vout gradually decreases with time.

  As the output voltage Vout decreases, the error voltage Verr starts to increase, and the duty ratio (pulse width) of the pulse signal Spwm1 starts to increase. That is, the pulse widths of the first pulse signal S1 and the second pulse signal S2 also start to increase.

  At time t3, the pulse width TH1 of the first pulse signal S1 becomes longer than the minimum pulse width tmin, and the first mask signal Smsk1 transitions to a high level at the timing of the positive edge of the MINDUTY1 signal. At the timing of the negative edge of the subsequent MINDUTY1 signal, the first mask signal Smsk1 'transitions to a high level.

  At subsequent time t4, the pulse width TH2 of the second pulse signal S2 becomes longer than the minimum pulse width tmin, and at the timing of the positive edge of the MINDUTY2 signal, the second mask signal Smsk2 transitions to a high level. At the timing of the negative edge of the subsequent MINDUTY2 signal, the second mask signal Sskk2 'transitions to a high level.

  When both the first mask signal Smsk1 'and the second mask signal Smsk2' are at the high level, the pulse of the first pulse signal S1 is not masked but directly output as the pulse modulation signal Spwm3. Thereafter, the mode shifts to the normal PWM mode. That is, it can be seen that the pulse modulator 20a has the above-described function (2).

  The pulse modulator 20a can realize the functions (1) and (2) described above and has the following effects.

  A characteristic of the pulse modulator 20a is that the pulse signal Spwm1 is divided, decomposed into odd-numbered pulses and even-numbered pulses, and both are monitored to generate mask signals Smsk1 and Sskk2. The effect of this feature is clarified by comparison with the operation in the case where only the first mask signal Smsk1 based on the first pulse signal S1 is generated and the first pulse signal S1 is masked only by the first mask signal Smsk1. Become.

  If the first pulse signal S1 is masked only by the first mask signal Smsk1, the hatched pulse P1 in FIG. 6 is output without being masked. Since the pulse width of the pulse P1 is shorter than the minimum pulse width tmin, it should not be output originally. That is, since the output capacitor Co1 is overcharged, the ripple of the output voltage Vout increases.

  On the other hand, in the pulse modulator 20a according to the embodiment, the pulse width of one cycle before is monitored using the second pulse signal S2, so that the pulse width of the second pulse signal S2 is the minimum pulse. As soon as the width becomes shorter than the width tmin, the mask signal becomes a low level, and the pulse P1 can be prevented from being output.

  Another feature of the pulse modulator 20a is that the mask signals Smsk1 and Smsk2 generated by the mask signal generator 62 are delayed to generate the final mask signals Smsk1 'and Smsk2'. The effect of this feature becomes clear by comparison with the operation when the first pulse signal S1 is masked only by the first mask signal Smsk1.

  If the first pulse signal S1 is masked only by the first mask signal Smsk1, the hatched portion of the pulse P2 in FIG. 6, that is, the first mask signal Sskk1 transitions to the high level, and then the first pulse signal S1. A very short pulse until transition to low level appears in the pulse modulation signal Spwm3 as a beard (notch).

  On the other hand, the pulse modulator 20a according to the embodiment uses the mask signals Smsk1 ′ and Smsk2 ′ obtained by delaying the mask signals Smsk1 and Smsk2, so that a whisker (notch) corresponding to the pulse P2 is output. Can be prevented.

  The charge pump circuit 120 according to the embodiment has been described above. Those skilled in the art will understand that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there. Hereinafter, such modifications will be described.

  The pulse modulator 20a according to the second embodiment can be used for pulse width modulation other than the charge pump circuit. For example, the pulse modulator 20a can be used for a step-up, step-down, or step-up / step-down switching regulator.

  FIGS. 7A and 7B are circuit diagrams showing configurations of switching regulators 200a and 200b using the pulse modulator 20a of FIG. FIG. 7A shows a step-up switching regulator. FIG. 7B shows a step-down switching regulator. The pulse modulator 20a can be used for a synchronous rectification type switching regulator instead of the diode rectification type. Since the configuration other than the pulse modulator 20a is known, the description thereof is omitted.

  By using the pulse modulator 20a as a switching regulator, it is possible to operate in the PFM mode at a light load as in the case of the charge pump circuit, and to reduce the ripple of the output voltage Vout at the light load. it can.

  The configuration of the charge pump circuit is not limited to the topology of FIG. For example, a diode may be used instead of the transistor switch. In the embodiment, the charge pump circuit having a boosting ratio of 2 has been described. However, an addition type charge pump circuit that adds two input voltages may be used. In this case, the commonly connected terminals of the first switch SW1 and the third switch SW3 may be separated, and the first input terminal and the second input terminal may be provided. Then, one end of the first switch SW1 is connected to the first input terminal, and one end of the third switch SW3 is connected to the second input terminal.

  Further, the charge pump circuit may have a boost rate of 1.5 times or 4 times, or may be a charge pump circuit in which a plurality of boost rates can be switched. Furthermore, the present invention can be applied to a voltage inversion type charge pump circuit for generating a negative voltage.

  In the embodiment, the case where the first switch SW1 to the fourth switch SW4 are built in the control circuit 100 has been described, but a discrete element may be used and provided outside the control circuit 100.

  The logic level of each signal is not limited to that in the embodiment, and can be reversed as appropriate.

  Although the present invention has been described using specific words and phrases based on the embodiments, the embodiments are merely illustrative of the principles and applications of the present invention, and the embodiments are defined in the claims. Many modifications and arrangements can be made without departing from the spirit of the present invention.

1 is a circuit diagram showing a configuration of a charge pump circuit according to a first embodiment of the present invention. FIG. 2 is a signal waveform diagram of the charge pump circuit of FIG. 1. 3A and 3B are operation waveform diagrams of the charge pump circuit of FIG. 1 at normal load and light load, respectively. It is a circuit diagram which shows the structure of the pulse modulator which concerns on 2nd Embodiment. It is a time chart which shows the operation state of a pulse divider and a PFM controller. It is a time chart which shows the operation state of the pulse modulator of FIG. FIGS. 7A and 7B are circuit diagrams showing the configuration of a switching regulator using the pulse modulator of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Control circuit, 102 ... Input terminal, 104 ... Capacitor terminal, 106 ... Capacitor terminal, 108 ... Output terminal, 110 ... Ground terminal, 112 ... Feedback terminal, 120 ... Charge pump circuit, 122 ... Input terminal, 124 ... Output terminal , Cf1 ... Flying capacitor, Co1 ... Output capacitor, R1 ... Feedback resistor, R2 ... Feedback resistor, 10 ... First switch group, 12 ... Second switch group, SW1 ... First switch, SW2 ... Second switch, SW3 ... First 3 switches, SW4 ... 4th switch, 20 ... pulse modulator, 22 ... error amplifier, 24 ... oscillator, 26 ... PWM comparator, 28 ... maximum duty comparator, 30 ... AND gate, 32 ... minimum duty comparator, 34 ... PFM controller 40 ... Driver, 50 ... Pulse divider, 52 ... AND 54 ... AND gate, 60 ... PFM controller, 62 ... mask signal generation unit, 64 ... mask signal delay unit, 66 ... AND gate, FF1 ... first flip-flop, FF2 ... second flip-flop, FF3 ... third flip-flop FF4 ... fourth flip-flop, 68 ... first NOT gate, 70 ... second NOT gate, Vin ... input voltage, Vout ... output voltage, S1 ... first pulse modulated signal, S2 ... second pulse modulated signal, SMSk1 ... first 1 mask signal, Smsk2... Second mask signal.

Claims (12)

A pulse that receives a feedback voltage corresponding to the output voltage of the power supply circuit, generates a pulse modulation signal whose duty ratio is controlled so that the feedback voltage approaches a predetermined reference voltage, and outputs the pulse modulation signal to the switching element of the power supply circuit A modulator,
An error amplifier that amplifies an error between the feedback voltage and the reference voltage to generate an error voltage;
An oscillator that generates a sawtooth-shaped periodic voltage having a predetermined frequency;
A comparator that slices the periodic voltage with the error voltage and outputs a pulse signal whose level changes at an intersection;
A pulse divider that divides the pulse signal by 1/2 to generate a first pulse signal and a second pulse signal that are in opposite phases to each other;
The pulse width of the first pulse signal is compared with a predetermined minimum pulse width to generate a first mask signal that has a predetermined level when the pulse width of the first pulse signal is shorter than the minimum pulse width, and the second pulse signal A mask signal generation unit that compares the pulse width of the second pulse signal with a predetermined minimum pulse width and generates a second mask signal having a predetermined level when the pulse width of the second pulse signal is shorter than the minimum pulse width;
A mask processing unit that masks either the first pulse signal or the second pulse signal while the first and second mask signals are at the predetermined level, and outputs the mask signal as the pulse modulation signal;
With
The mask signal generator is
Receiving a first minimum duty ratio setting signal having a frequency of ½ of the periodic voltage and transitioning to a high level after a predetermined time delay from the positive edge of the first pulse signal; Generating the first mask signal based on the comparison result between the timing of the positive edge of the signal and the timing of the negative edge of the first pulse signal;
The second minimum duty ratio setting signal is received by receiving a second minimum duty ratio setting signal having a frequency half that of the periodic voltage and transitioning to a high level with a predetermined time delay from the positive edge of the second pulse signal. and timing of the positive edge of the signal, based on the comparison result of the timing of the negative edge of the second pulse signal, wherein the to Rupa pulse modulator to generate a second mask signal. The mask signal generator is
A first flip-flop in which the first minimum duty ratio setting signal is input to a clock terminal and the first pulse signal is input to an input terminal;
A second flip-flop in which the second minimum duty ratio setting signal is input to a clock terminal and the second pulse signal is input to an input terminal;
Hints, pulse modulator as claimed in claim 1, wherein the first, the output of the second flip-flop, respectively, the first, and outputs the second mask signal. The pulse divider is
The first pulse signal is generated by a logical operation of a first maximum duty ratio setting signal having a frequency of ½ of the periodic voltage and a predetermined maximum duty ratio and the pulse signal,
The second maximum duty ratio setting signal having a frequency half that of the periodic voltage and the predetermined maximum duty ratio and having a phase opposite to that of the first maximum duty ratio setting signal and the pulse signal is used for the second operation. The pulse modulator according to claim 1 , wherein the pulse modulator generates a pulse signal.   A pulse that receives a feedback voltage corresponding to the output voltage of the power supply circuit, generates a pulse modulation signal whose duty ratio is controlled so that the feedback voltage approaches a predetermined reference voltage, and outputs the pulse modulation signal to the switching element of the power supply circuit A modulator,
  An error amplifier that amplifies an error between the feedback voltage and the reference voltage to generate an error voltage;
  An oscillator that generates a sawtooth-shaped periodic voltage having a predetermined frequency;
  A comparator that slices the periodic voltage with the error voltage and outputs a pulse signal whose level changes at an intersection;
  A pulse divider that divides the pulse signal by 1/2 to generate a first pulse signal and a second pulse signal that are in opposite phases to each other;
  The pulse width of the first pulse signal is compared with a predetermined minimum pulse width to generate a first mask signal that has a predetermined level when the pulse width of the first pulse signal is shorter than the minimum pulse width, and the second pulse signal A mask signal generation unit that compares the pulse width of the second pulse signal with a predetermined minimum pulse width and generates a second mask signal having a predetermined level when the pulse width of the second pulse signal is shorter than the minimum pulse width;
  A mask processing unit that masks either the first pulse signal or the second pulse signal while the first and second mask signals are at the predetermined level, and outputs the mask signal as the pulse modulation signal;
  With
  The pulse divider is
  The first pulse signal is generated by a logical operation of a first maximum duty ratio setting signal having a frequency of ½ of the periodic voltage and a predetermined maximum duty ratio and the pulse signal,
  The second maximum duty ratio setting signal having a frequency half that of the periodic voltage and the predetermined maximum duty ratio and having a phase opposite to that of the first maximum duty ratio setting signal and the pulse signal is used for the second operation. A pulse modulator for generating a pulse signal. The pulse divider is
A first AND gate that outputs a logical product of the first maximum duty ratio setting signal and the pulse signal as the first pulse signal;
A second AND gate that outputs a logical product of the second maximum duty ratio setting signal and the pulse signal as the second pulse signal;
5. The pulse modulator according to claim 3 , comprising: The first pulse modulator as claimed in claim 1 or 2, further comprising a mask signal delay unit for delaying the second mask signal by a predetermined delay time. A mask signal delay unit for delaying the first and second mask signals by a predetermined delay time;
The mask signal delay unit is
A third flip-flop in which the first mask signal is input to an input terminal and the first minimum duty ratio setting signal inverted to a clock terminal is input;
A fourth flip-flop in which the second mask signal is input to the input terminal and the second minimum duty ratio setting signal inverted to the clock terminal is input;
The pulse modulator according to claim 1 , comprising: A pulse that receives a feedback voltage corresponding to the output voltage of the power supply circuit, generates a pulse modulation signal whose duty ratio is controlled so that the feedback voltage approaches a predetermined reference voltage, and outputs the pulse modulation signal to the switching element of the power supply circuit A modulator,
An error amplifier that amplifies an error between the feedback voltage and the reference voltage to generate an error voltage;
An oscillator that generates a sawtooth-shaped periodic voltage having a predetermined frequency;
A comparator that slices the periodic voltage with the error voltage and outputs a pulse signal whose level changes at an intersection;
A pulse divider that divides the pulse signal by 1/2 to generate a first pulse signal and a second pulse signal that are in opposite phases to each other;
The pulse width of the first pulse signal is compared with a predetermined minimum pulse width to generate a first mask signal that has a predetermined level when the pulse width of the first pulse signal is shorter than the minimum pulse width, and the second pulse signal A mask signal generation unit that compares the pulse width of the second pulse signal with a predetermined minimum pulse width and generates a second mask signal having a predetermined level when the pulse width of the second pulse signal is shorter than the minimum pulse width;
A mask processing unit that masks either the first pulse signal or the second pulse signal while the first and second mask signals are at the predetermined level, and outputs the mask signal as the pulse modulation signal;
With
The periodic voltage alternately repeats a first period of low level and a second period of rising at a constant slope,
The pulse divider is
A first AND gate that outputs, as the first pulse signal, a logical product of the first maximum duty ratio setting signal that is at a high level and the pulse signal while the periodic voltage is odd-numbered in the second period;
A second AND gate that outputs a logical product of the second maximum duty ratio setting signal and the pulse signal, which is at a high level while the periodic voltage is in the even-numbered second period, as the second pulse signal;
Including
The mask signal generator is
The first mask is latched by a positive edge of a first minimum duty ratio setting signal that becomes a high level at a timing after a predetermined time has elapsed since the periodic voltage has oddly entered the second period, and the first mask A first flip-flop for generating a signal;
The second pulse signal is latched by a positive edge of a second minimum duty ratio setting signal that becomes a high level at a timing after the predetermined time has elapsed since the periodic voltage becomes the second period evenly. A second flip-flop for generating a mask signal;
Including
The mask processing unit, one and one of the first pulse signal or the second pulse signal, said first, features and to Rupa Luz modulation that includes an AND gate for outputting a logical product of the second mask signal vessel. A control circuit for a charge pump circuit having at least one flying capacitor and at least one output capacitor,
A first switch group including at least one switch provided in a path for charging the flying capacitor using an input voltage;
A second switch group including at least one switch provided in a path for charging the output capacitor using the charge stored in the flying capacitor;
The pulse modulator according to any one of claims 1 to 8 , which receives a feedback voltage according to an output voltage of the charge pump circuit and generates a pulse modulation signal;
The pulse modulation signal is received from the pulse modulator, one of the first and second switch groups is turned on for a period corresponding to the high period of the pulse modulation signal, and the other is set for the period corresponding to the low period. A driver to turn on,
A control circuit comprising: A flying capacitor,
An output capacitor;
The control circuit according to claim 9, which controls charge / discharge states of the flying capacitor and the output capacitor;
A charge pump circuit comprising: A switching regulator control circuit having at least one switching element,
The pulse modulator according to any one of claims 1 to 8 , which receives a feedback voltage corresponding to an output voltage of the switching regulator and generates a pulse modulation signal;
A driver for receiving the pulse modulation signal from the pulse modulator and driving the switching element based on the pulse modulation signal;
A control circuit comprising:   A switching regulator comprising the control circuit according to claim 11.

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