JP5211511B2 - Process execution device, process execution method, and program - Google Patents

Description

  The present invention relates to a process execution device, a process execution method, and a program for executing a predetermined process.

  In recent years, when predetermined processing is performed by a computer, a control device such as a processor using multithread processing that makes it appear that a plurality of processes are performed simultaneously (in parallel) has been put into practical use (for example, (Refer nonpatent literature 1.).

  In this multi-thread processing, if it is determined that there is no thread to be executed in the cycle next to the cycle in which the current thread is being executed at a certain point in time, the next cycle becomes an empty cycle, and wasted time Will occur.

In addition, a memory check process for confirming the normality of the memory provided in the apparatus is executed as a process that can be scheduled by the OS. At that time, as in normal processing, scheduling is performed based on the priority of the process. Therefore, the processing performance of the system and the reliability achieved by the memory check process are in a trade-off relationship.
“Sun Niagara and an Evaluation of SMT in IBM's Power5” http://www.cs.rice.edu/~johnmc/comp522/lecture-notes/Lecture4.pdf

  However, in the technique described in Non-Patent Document 1, all threads are not executable due to waiting for memory or completion of input / output (I / O) operations, and are effective in the next cycle of the pipeline. May not be able to be inserted. This cycle is a cycle in which processing intended by the user of the processing apparatus cannot be performed at all, and is not known from the user. Also, as mentioned above, there is a trade-off between system processing performance and reliability, so trying to increase system processing performance decreases system reliability and attempts to increase system reliability. There is a risk that the processing performance of the system will decrease.

  The present invention has been made in view of the problems of the conventional technology as described above, and is capable of efficiently constructing a highly reliable system without affecting normal processing performance. An object is to provide an apparatus, a process execution method, and a program.

In order to achieve the above object, the present invention provides:
A processing execution device having a memory and executing a plurality of threads in a pipeline in a predetermined cycle,
An execution decision unit that determines whether there is a thread that can be executed in the cycle following the cycle in which the thread is currently being executed;
A memory access thread activation unit that activates a memory access thread for confirming the normality of the memory, when the execution determination unit determines that there is no thread that can be executed in the next cycle;
A memory check unit that checks the normality of the memory after the memory access thread is activated by the memory access thread activation unit and puts the memory access thread into a dormant state when it is determined that the memory is normal And have.

  The memory check unit may generate an interrupt for notifying abnormality when it is determined that the memory is not normal.

  The processing execution device is a control processor.

In addition, a process execution method for cyclically processing a plurality of threads,
The process of determining whether there is a thread that can be executed in the cycle following the cycle in which the thread is currently executing;
When it is determined that there is no thread that can be executed in the next cycle, a process of starting a memory access thread for checking the normality of the memory; and
After the memory access thread is activated, a process for checking the normality of the memory;
And processing to put the memory access thread into a dormant state when it is determined that the memory is normal.

  Further, it is characterized in that when it is determined that the memory is not normal, a process for generating an interrupt for notifying abnormality is provided.

A program for cyclically processing a plurality of threads,
Steps to determine if there are any threads that can run in the next cycle after the current thread is running,
When it is determined that there is no thread that can be executed in the next cycle, the computer is caused to execute a procedure for starting a memory access thread for confirming the normality of the memory.

  In the present invention configured as described above, in order to pipeline execute a plurality of threads in a predetermined cycle, it is determined whether there is a thread that can be executed in the cycle following the cycle in which the current thread is executed. If it is determined that there is no thread that can be executed in the next cycle, the memory access thread that confirms the normality of the memory is activated, and after the memory access thread is activated, the normality of the memory is confirmed and the memory Is determined to be normal, the memory access thread is suspended.

  Thus, when an empty cycle occurs, effective use of the cycle can be realized by executing a memory access thread that checks the memory in the empty cycle.

  As described above, in the present invention, in order to pipeline execute a plurality of threads in a predetermined cycle, is there a thread that can be executed in the cycle following the cycle in which the execution determination unit is currently executing the thread? If it is determined that there is no thread that can be executed in the next cycle, the memory access thread activation unit activates the memory access thread to check the normality of the memory, and after the memory access thread is activated, the memory When the check unit checks the normality of the memory and it is determined that the memory is normal, the memory access thread is put into a dormant state, so that a highly reliable system can be efficiently used without affecting normal processing performance. Can be built.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing an embodiment of a processing execution apparatus according to the present invention.

  In this embodiment, as shown in FIG. 1, the execution determination unit 103, the memory access thread activation unit 104, the instruction decoding unit 105, the instruction execution unit 106, the memory access unit 107, the instruction completion confirmation unit 108, 109.

  The execution determining unit 103 selects a thread to be processed. In this embodiment, one thread is selected from the threads 101-1 to 101-4 based on the states of the threads 101-1 to 101-4. Here, data necessary for execution of the selected instruction is taken out from a register (not shown), and is carried around in the pipeline described below together with thread numbers given in advance to the respective threads 101-1 to 101-4. . In addition, it is determined whether there is a thread that can be executed in the cycle following the cycle in which the thread is currently being executed. Although the case where the number of threads 101-1 to 101-4 is four is taken as an example here, the number is not limited to four.

  The memory access thread activation unit 104 activates the memory access thread 102 when the execution determination unit 103 determines that there is no thread to be executed in the cycle next to the cycle in which the thread is currently being executed. This memory access thread 102 is a thread for confirming the normality of the memory 109. As a method for confirming the normality of the memory 109, a conventional method such as confirmation by writing predetermined data into the memory 109 and then comparing the data read from the memory 109 with the written data may be used. Well, not specified here. When the memory access thread 102 is activated, information indicating that the activated thread is the memory access thread 102 is carried around in the pipeline described below.

  The instruction decoding unit 105 decodes the instruction taken out by the execution determining unit 103 or the instruction of the memory access thread 102 and determines the operation of the instruction.

  The instruction execution unit 106 performs the operation (calculation execution) determined by the instruction decoding unit 105.

  The memory access unit 107 performs memory access necessary when the instruction execution unit 106 executes an operation on the memory 109.

  The instruction completion confirmation unit 108 is a memory check unit that confirms the end of memory access by the memory access unit 107.

  The memory 109 is a memory that stores data for processing. The memory access thread 102 is activated, the normality of the memory 109 is confirmed, and if it is normal, the thread suspend state is entered. If it is abnormal, an interrupt is notified to the OS or the like. Note that the memory 109 may be provided outside the processing execution apparatus.

  In the present invention, pipeline processing is performed as shown in FIG.

  FIG. 2 is a diagram schematically showing the pipeline processing of the threads 101-1 to 101-4 shown in FIG. Here, a case where there is no empty cycle in each cycle will be described as an example.

  First, in cycle 1, an instruction decoding process (ID: Instruction Decording) of the thread 101-1 is executed. This instruction decoding process is a process executed by the instruction decoding unit 105 shown in FIG.

  Thereafter, in cycle 2, instruction execution processing (EX: Execute) of the thread 101-1 is performed. This instruction execution process is a process executed by the instruction execution unit 106 shown in FIG. In cycle 2, the instruction decode process of the thread 101-2 is executed.

  Thereafter, in cycle 3, a memory access process (MA: Memory Access) of the thread 101-1 is executed. This memory access process is a process executed by the memory access unit 107. In cycle 3, the instruction execution process of the thread 101-2 is executed. In cycle 3, the instruction decoding process of the thread 101-3 is executed.

  Thereafter, in cycle 4, instruction completion confirmation processing (IC: Instruction Completion) of the thread 101-1 is executed. This instruction completion confirmation process is a process executed by the instruction completion confirmation unit 108 shown in FIG. In cycle 4, the memory access process of the thread 101-2 is executed. In cycle 4, the instruction execution process of the thread 101-3 is executed. In cycle 4, the instruction decoding process of the thread 101-4 is executed.

  Thereafter, in cycle 5, the instruction completion confirmation process of the thread 101-2 is executed. In cycle 5, the memory access process of the thread 101-3 is executed. In cycle 5, the instruction execution process of the thread 101-4 is executed.

  Thereafter, in cycle 6, instruction completion confirmation processing of the thread 101-3 is executed. In cycle 6, the memory access process of the thread 101-4 is executed.

  Thereafter, the processes of the threads 101-1 to 101-4 are executed.

  Below, the processing execution method in the form shown in FIG. 1 is demonstrated using a flowchart.

  FIG. 3 is a flowchart for explaining a process execution method in the process execution apparatus shown in FIG.

  First, the execution determination unit 103 determines whether there is a thread that can be executed in the next cycle (step S1). Here, based on the state of the threads 101-1 to 101-4, it is determined whether there is a thread that can be executed in the next cycle. That is, for example, when a next cycle in which one process is performed in a certain cycle is executed, it is determined that a thread that does not satisfy the predetermined process start timing is not an executable thread.

  For example, a case where it is determined in step S1 that the thread 101-2 can be executed by the execution determination unit 103 in the next cycle in which the processing of the thread 101-1 is performed will be described. If it is determined that the thread 101-2 can be executed, the instruction decoding unit 105 decodes the instruction of the thread 101-2 (ID processing described above), and determines the operation of the instruction (step S2). .

  Then, the operation of the decoded instruction is executed by the instruction execution unit 106 (EX process described above) (step S3). When this EX process is performed, the memory access unit 107 performs memory access (the above-described MA process) necessary for execution of the operation (step S4).

  Thereafter, whether or not the memory access to the memory 109 is normally completed is confirmed by the instruction completion confirmation unit 108 (IC processing described above) (step S5). The normal termination confirmation method may be a conventional memory access normal processing confirmation method such as determining whether or not predetermined normality confirmation is completed, and is not particularly defined here.

  On the other hand, when the execution determining unit 103 determines in step S1 that there is no thread that can be executed in the next cycle, the memory access thread starting unit 104 starts the memory access thread 102 (step S6).

  When the memory access thread 102 is activated, the instruction of the activated memory access thread 102 is decoded by the instruction decoding unit 105 (ID processing described above), and the operation of the instruction is determined (step S7).

  Then, the decoded instruction is executed (EX process described above) by the instruction execution unit 106 (step S8). Since the instruction of the memory access thread 102 is for confirming the normality of the memory 109, whether or not the memory 109 for that purpose is accessed by the memory access unit 107 (the above-described MA processing) and the memory 109 is abnormal. Whether or not the instruction completion confirmation unit 108 determines is determined (step S9).

  When it is determined that there is an abnormality in the memory 109, an interrupt is generated and notified to another OS (step S10).

  On the other hand, if it is determined that there is no abnormality in the memory 109, the memory access thread 102 enters a suspended (pause) state (step S11).

  FIG. 4 is a diagram schematically showing a process cycle when it is determined in step S1 that there is no thread that can be executed in the next cycle, and the memory access thread 102 is executed in an empty cycle.

  As shown in FIG. 4, for example, when there is no thread that can be executed in the next cycle in which the thread 101-2 is executed, the cycle becomes an empty thread, and the memory access thread 102 is inserted into the empty thread. Will be executed.

  As described above, in the present invention, when an empty cycle occurs, effective use of the cycle can be realized by executing a memory access thread that checks the memory in the empty cycle.

  In the present invention, a program for realizing the function is recorded on a recording medium readable by the processing execution device, and the program recorded on the recording medium is read by the processing execution device and executed. There may be. The recording medium readable by the processing execution device refers to a transfer medium such as a floppy disk (registered trademark), a magneto-optical disk, a DVD, and a CD, as well as an HDD built in the processing execution device. The program recorded on the recording medium is read by, for example, a control unit (not shown) included in the processing execution device, and the same processing as described above is performed under the control of the control unit. Here, the control unit included in the process execution device operates as a computer that executes a program read from a recording medium on which the program is recorded.

It is a figure which shows one Embodiment of the process execution apparatus of this invention. FIG. 2 is a diagram schematically illustrating a state of pipeline processing of a thread illustrated in FIG. 1. It is a flowchart for demonstrating the process execution method in the process execution apparatus shown in FIG. FIG. 10 is a diagram schematically showing a process cycle when it is determined in step S1 that there is no thread that can be executed in the next cycle, and a memory access thread is executed in an empty cycle.

Explanation of symbols

101-1 to 101-4 Thread 102 Memory Access Thread 103 Execution Determination Unit 104 Memory Access Thread Activation Unit 105 Instruction Decoding Unit 106 Instruction Execution Unit 107 Memory Access Unit 108 Instruction Completion Confirmation Unit 109 Memory

Claims (6)

A processing execution device having a memory and executing a plurality of threads in a pipeline in a predetermined cycle,
An execution decision unit that determines whether there is a thread that can be executed in the cycle following the cycle in which the thread is currently being executed;
A memory access thread activation unit that activates a memory access thread for confirming the normality of the memory, when the execution determination unit determines that there is no thread that can be executed in the next cycle;
A memory check unit that checks the normality of the memory after the memory access thread is activated by the memory access thread activation unit and puts the memory access thread into a dormant state when it is determined that the memory is normal And a process execution device. The process execution device according to claim 1,
The memory execution unit generates an interrupt for notifying an abnormality when it is determined that the memory is not normal. In the processing execution device according to claim 1 or 2,
The process execution apparatus is a control processor. A process execution method that cyclically pipelines multiple threads,
The process of determining whether there is a thread that can be executed in the cycle following the cycle in which the thread is currently executing;
When it is determined that there is no thread that can be executed in the next cycle, a process of starting a memory access thread for checking the normality of the memory; and
After the memory access thread is activated, a process for checking the normality of the memory;
A process execution method comprising: setting the memory access thread to a dormant state when it is determined that the memory is normal. In the processing execution method of Claim 4,
A process execution method comprising a process of generating an interrupt for notifying an abnormality when it is determined that the memory is not normal. A program for cyclically processing multiple threads,
Steps to determine if there are any threads that can run in the next cycle after the current thread is running,
A program for causing a computer to execute a procedure for starting a memory access thread for confirming normality of a memory when it is determined that there is no thread that can be executed in the next cycle.

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