JP5210188B2 - Imaging apparatus, control method thereof, and program - Google Patents

Description

  The present invention relates to a technique for reading out an output signal in an image sensor that is a component of an imaging apparatus.

  2. Description of the Related Art Conventionally, there are many imaging devices such as electronic cameras that record and reproduce still images and moving images captured by a solid-state imaging device such as a CCD or CMOS sensor using a memory card having a solid-state memory device as a recording medium.

  In these image pickup devices, the number of pixels of image pickup devices has increased in recent years, and the number of read-out pixels of still images has increased. In moving image recording, etc., a mode of reading a multi-pixel signal such as HD moving images at a high frame rate. Is required. For this reason, it is required to speed up reading of signals from the image sensor.

  Up to now, high-speed reading methods have been supported by increasing the number of signal output lines and increasing the reading frequency. However, in order to increase the number of signal output lines, it is necessary to increase the output terminals of the image sensor and the signal processing circuit of the output signal, and there is a problem that the scale and manufacturing cost of the image pickup apparatus increase. . On the other hand, when the readout frequency is increased, there are limitations due to a decrease in the accuracy of signal readout and the processing capability of the signal processing circuit at the subsequent stage. In addition, the signal readout period can be shortened by increasing the signal output line and increasing the readout frequency, and the horizontal blanking period can also be shortened in order to improve the still picture frame speed and the frame rate of the video. There is a need. Therefore, with the shortening of the signal reading period, it is important to shorten the horizontal blanking period.

  As a countermeasure against this point, for example, in Patent Document 1, a solid-state imaging device that reads out a plurality of pixel signals connected to one signal transfer line has a plurality of pixel signal storage units, and a pixel signal storage unit starts from a certain pixel. It has been proposed to simultaneously transfer data to and output signals already stored in another pixel signal storage unit.

In the imaging device having the above-described configuration, a signal read from a pixel in a row to the charge storage unit is read by the horizontal transfer unit, and at the same time, a signal charge transfer from the pixel in the next row to the charge storage unit is performed. Is possible. Therefore, the readout time can be shortened as compared with the conventional signal readout method in which the horizontal blanking period and the horizontal transfer period are sequentially performed for each row.
JP 2001-45378 A

However, in such a conventional solid-state imaging device such as an electronic camera, the reading method that absorbs the horizontal blanking period has the following problems.
That is, in the configuration in which a plurality of storage units are arranged in parallel as in the conventional technique and the storage units are alternately switched for each row reading, the plurality of storage units are arranged so that the output does not differ depending on the storage unit used. All must be designed to have the same configuration. Therefore, the chip layout design is restricted, and problems such as an increase in chip size have occurred.

  As a method for avoiding the above-described problem, a configuration in which the plurality of storage units are arranged in series and signal transfer is performed in stages can be considered. However, with such a configuration, there is another problem that the readout time increases because the number of signal transfers increases. In addition, if signal transfer of all the columns is performed simultaneously, there is a problem that noise due to power fluctuation and the like accompanying signal transfer increases and the output image is degraded.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide an imaging device that can be read at high speed without deteriorating an output image signal.

  In order to solve the above-described problems and achieve the object, an imaging apparatus according to the present invention holds image signals read from a plurality of pixels arranged in a two-dimensional shape. A first storage unit having a plurality of storage units provided for each column and an image signal transferred from the first storage unit are provided for each column of the plurality of pixels. A second storage unit having a plurality of storage units; an output unit for outputting an image signal held in the second storage unit; and the second storage unit is divided into a plurality of blocks, and the first storage unit Control means for controlling the first storage means and the second storage means so as to transfer image signals from the storage means to the second storage means at different timings for each of the plurality of blocks; It is characterized by providing.

  Further, the control method of the image pickup apparatus according to the present invention holds a plurality of pixels provided for each column of the plurality of pixels, which holds image signals read from the plurality of pixels arranged two-dimensionally. A first accumulator having an accumulator, and a second accumulator provided for each column of the plural pixels for holding an image signal transferred from the first accumulator. A method for controlling an imaging apparatus comprising storage means and output means for outputting an image signal held in the second storage means, the second storage means being divided into a plurality of blocks, The first storage unit and the second storage unit are controlled so that image signals are transferred from the first storage unit to the second storage unit at different timings for each of the plurality of blocks. A control process is provided.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the imaging device which can be read at high speed, without degrading the image signal to output.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of an imaging apparatus according to the first embodiment of the present invention.

  In FIG. 1, 101 is an optical system composed of a lens and a diaphragm, 102 is a mechanical shutter (shown as a mechanical shutter), and 103 is an image sensor in which pixels for converting incident light into an electrical signal are two-dimensionally arranged. An analog signal processing circuit 104 performs analog signal processing on the image signal output from the image sensor 103. Reference numeral 105 denotes a CDS circuit that performs correlated double sampling inside the analog signal processing circuit 104, and reference numeral 106 denotes a signal amplifier that amplifies the analog signal inside the analog signal processing circuit 104. A clamp circuit 107 performs horizontal OB clamping inside the analog signal processing circuit 104, and an A / D converter 108 converts an analog signal into a digital signal inside the analog signal processing circuit 104. Reference numeral 110 denotes a timing signal generation circuit that generates signals for operating the image sensor 103 and the analog signal processing circuit 104, and 111 denotes a drive circuit for the optical system 101 and the mechanical shutter 102. Reference numeral 112 denotes a digital signal processing circuit that performs digital signal processing necessary for photographed image data, and 113 denotes an image memory that stores the signal processed image data. Reference numeral 114 denotes an image recording medium (shown as a recording medium) that can be removed from the image pickup apparatus, and 115 denotes a recording circuit that records the signal processed image data on the image recording medium 114. Reference numeral 116 denotes an image display device that displays signal-processed image data, and 117 denotes a display circuit that displays an image on the image display device 116. Reference numeral 118 denotes a system control unit that controls the entire imaging apparatus. Reference numeral 119 denotes a nonvolatile memory for storing a program describing a control method executed by the system control unit 118, control data such as parameters and tables used when executing the program, and correction data such as a scratch address (ROM). Reference numeral 120 denotes a volatile memory (RAM) that is used to transfer and store the program, control data, and correction data stored in the non-volatile memory 119 and used when the system control unit 118 controls the imaging apparatus.

  Reference numeral 121 denotes a temperature detection circuit that detects the temperature of the image sensor 103 or its peripheral circuit, and 122 denotes an accumulation time setting unit that sets the accumulation time of the image sensor 103. Reference numeral 123 denotes a shooting mode setting unit for setting shooting conditions such as ISO sensitivity setting and switching between still image shooting and moving image shooting.

  Hereinafter, a photographing operation using the imaging apparatus configured as described above will be described.

  Prior to the shooting operation, necessary programs, control data, and correction data are transferred from the nonvolatile memory 119 to the volatile memory 120 and stored at the start of the operation of the system control unit 118 such as when the image pickup apparatus is turned on. Shall. These programs and data are used when the system control unit 118 controls the imaging apparatus, and additional programs and data are transferred from the nonvolatile memory 119 to the volatile memory 120 as necessary. Shall. Further, it is assumed that the system control unit 118 directly reads out and uses data in the nonvolatile memory 119.

  First, the optical system 101 drives a diaphragm and a lens according to a control signal from the system control unit 118, and forms a subject image set to an appropriate brightness on the image sensor 103. Next, during still image shooting, the mechanical shutter 102 is driven by the control signal from the system control unit 118 so that the image sensor 103 is shielded from light in accordance with the operation of the image sensor 103 so as to have a necessary exposure time. Is done. At this time, when the image sensor 103 has an electronic shutter function, it may be used together with the mechanical shutter 102 to secure a necessary exposure time. The mechanical shutter 102 is maintained in an open state during moving image shooting so that the image sensor 103 is always exposed during shooting by a control signal from the system control unit 118. The image sensor 103 is driven by a drive pulse based on the operation pulse generated by the timing signal generation circuit 110 controlled by the system control unit 118, and converts the subject image into an electrical signal by photoelectric conversion as an analog image signal. Output. From the analog image signal output from the image sensor 103, the clock synchronization noise is removed by the CDS circuit 105 by the operation pulse generated by the timing signal generation circuit 110 controlled by the system control unit 118. Further, the gain of the amplification factor set according to the amount of incident light is applied by the signal amplifier 106, the signal output in the horizontal OB region is clamped as a reference voltage by the clamp circuit 107, and converted into a digital image signal by the A / D converter 108. Is done.

  Next, in the digital signal processing circuit 112 controlled by the system control unit 118, various kinds of scratch detection processing and scratch correction processing in the digital image signal are performed. The digital image signal is also subjected to image processing such as color conversion, white balance, and gamma correction, resolution conversion processing, and image compression processing. The image memory 113 is used for temporarily storing a digital image signal during signal processing or for storing image data that is a digital image signal subjected to signal processing. The image data signal-processed by the digital signal processing circuit 112 and the image data stored in the image memory 113 are converted by the recording circuit 115 into data suitable for the image recording medium 114 (for example, file system data having a hierarchical structure). Is recorded on the image recording medium 114. In addition, after the resolution conversion process is performed by the digital signal processing circuit 112, the display circuit 117 converts the signal into a signal suitable for the image display device 118 (for example, an NTSC analog signal) and displays it on the image display device 118. To do.

  Here, the digital signal processing circuit 112 may output the digital image signal as it is as image data to the image memory 113 or the recording circuit 115 without performing signal processing by the control signal from the system control unit 118. Further, when requested by the system control unit 118, the digital signal processing circuit 112 outputs information on digital image signals and image data generated in the signal processing process to the system control unit 118. The information of the image data is, for example, information such as the spatial frequency of the image, the average value of the designated area, the data amount of the compressed image, or information extracted from them. Further, the recording circuit 115 outputs information such as the type and free capacity of the image recording medium 114 to the system control unit 118 when requested by the system control unit 118.

  Next, a reproduction operation when image data is recorded on the image recording medium 114 will be described.

  The recording circuit 115 reads image data from the image recording medium 114 in accordance with a control signal from the system control unit 118. In addition, when the image data is a compressed image, the digital signal processing circuit 112 performs an image expansion process according to a control signal from the system control unit 118 and stores it in the image memory 113. The image data stored in the image memory 113 is subjected to resolution conversion processing by the digital signal processing circuit 112, converted to a signal suitable for the image display device 116 by the display circuit 117, and displayed on the image display device 116. The

  Next, the signal readout method of the imaging apparatus according to the first embodiment of the present invention will be described in detail with reference to FIGS.

  FIG. 2 is a conceptual diagram illustrating the readout unit of the CMOS image sensor according to the first embodiment of the present invention.

  In FIG. 2, the readout unit of the CMOS image sensor according to the first embodiment reads out pixel signals from a plurality of pixels 301 (A11 to B28) that accumulate signals generated according to incident light and output signals. A vertical scanning circuit VSR which is a pixel control means for the above. In addition, a vertical output line for reading out the pixel signal, a first storage unit 323 connected to the vertical output line and storing the pixel signal, and a signal divided into a plurality of blocks in the horizontal direction and transferred from the first storage unit 323 Is stored. Further, a horizontal transfer unit 339 that transfers the signal stored in the second storage unit 328 to the output unit, and a horizontal scanning circuit HSR for reading the signal from the second storage unit 328 to the horizontal transfer unit 339 are also provided.

  FIG. 3 is a circuit diagram illustrating the configuration of the CMOS image sensor according to the first embodiment of the present invention.

  In FIG. 3, each unit pixel 301 includes a photodiode 302 that is a photoelectric conversion element, and a transfer switch 303 that transfers charges generated by photoelectric conversion of the photodiode 302 using a transfer pulse PTX. Further, a reset switch that resets the floating diffusion layer (floating diffusion) FD307 that accumulates the charges transferred by the transfer switch 303 and the floating diffusion layer FD307 connected to the gate of the pixel amplifier 306 to the level of the potential SVDD by the reset pulse PRES. 304 is provided. Furthermore, a pixel amplifier 306 that amplifies the charge accumulated in the floating diffusion layer FD307 as a source follower and a row selection switch 305 that selects a row pixel selected by the vertical scanning circuit VSR by a selection pulse PSEL are also provided.

  The charge of the row pixel selected by the row selection switch 305 is output to the vertical output line 322 by the source follower connected to the load current source 321 and transferred to the first accumulation unit 323.

  The first accumulation unit 323 is configured to transfer a noise component charge accumulated in the floating diffusion layer FD307 by the transfer pulse PTN1, and a transfer capacitor CTN1 (accumulating the noise component charge transferred by the transfer switch 324). 326). Further, the transfer switch 325 that transfers the signal + noise component charge accumulated in the floating diffusion layer FD307 by the transfer pulse PTS1, and the transfer capacitor CTS1 (327) that accumulates the signal + noise component charge transferred by the transfer switch 325. Is provided.

  The second storage unit 328 connected to the first storage unit 323 includes MOS transistors 329 and 330 and load current sources 331 and 332 that constitute a buffer amplifier. Further, a transfer switch 333 that transfers the charge of the noise component stored in the transfer capacitor CTN1 (326) by the transfer pulse PTN2 and a transfer capacitor CTN2 (335) that stores the charge of the noise component transferred by the transfer switch 333 are provided. . Further, a reset switch 337 for resetting the transfer capacitor CTN2 (335) to the GND level by the reset pulse PCTR is provided. Further, a transfer switch 334 that transfers the signal + noise component charge accumulated in the transfer capacitor CTS1 (327) by the transfer pulse PTS2, and a transfer capacitor CTS2 (accumulated signal + noise component charge transferred by the transfer switch 334). 336). Further, a reset switch 338 is provided for resetting the transfer capacitor CTS2 (336) to the GND level by the reset pulse PCTR.

  As described above, the second storage unit 328 is divided into a plurality of blocks in the horizontal direction. In the present embodiment, these blocks are controlled by different transfer pulses PTN2x and PTS2x, respectively. That is, the signal charges are transferred to the transfer capacitors CTN2 (335) and CTS2 (336) at different timings in each block.

  The horizontal transfer unit 339 connected to the second storage unit 328 transfers a noise component charge stored in the transfer capacitor CTN2 (335) by a control pulse PHN from a horizontal scanning circuit HSR (not shown). 340 is provided. Further, a transfer capacitor CHN 342 that accumulates the charge of the noise component transferred by the transfer switch 340 is provided. Further, a transfer switch 341 is provided for transferring the charge of the signal + noise component accumulated in the transfer capacitor CTS2 (336) by a control pulse PHS from a horizontal scanning circuit HSR (not shown). In addition, a transfer capacitor CHS 343 that accumulates the charge of the signal + noise component transferred by the transfer switch 341 is provided.

  The transfer capacities CHN342 and CHS343 are connected to a differential amplifier 344 that outputs the difference between the two as an image signal. The differential amplifier 344 inputs the noise component and the optical signal + noise component accumulated in the capacitors CHN 342 and CHS 343 to output (optical signal + noise component) −noise component, that is, an optical signal.

  FIG. 4 is a timing chart showing drive timing at the time of reading in the imaging apparatus according to the present embodiment.

  First, in accordance with the fall of the signal HD indicating the start of one horizontal scanning period, the transfer of signal charges in the pixels A11 to A18 is started. First, the vertical output line 322 is reset to a constant potential by a circuit (not shown). Thereafter, the MOS transistor 304 is turned on by the PRES signal, so that the charge accumulated in the floating capacitor 307 provided at the gate of the MOS transistor 306 is reset to the constant potential SVDD. Subsequently, the PRES signal is set to the high level, the MOS transistor 304 is turned off, and then the PSEL signal is set to the high level, so that the source follower circuit constituted by the MOS transistor 305 and the load current source 321 is activated. A noise output corresponding to the floating gate reset potential of the MOS transistor 306 is output on the vertical output line 322. By setting the PTN1 signal to the high level during the period when the PSEL is at the high level, the storage capacitor CTN1 (326) for storing the noise component is connected to the vertical output line 322, and the storage capacitor CTN1 (326) is a signal of the noise component. Will come to hold.

  Subsequently, accumulation of the mixed signal of the photoelectric charge and noise component generated in the photoelectric conversion element 302 is performed. First, the vertical output line 322 is reset to a constant potential by a circuit (not shown). After that, the PTX signal is set to the high level, and the photocharge accumulated in the photoelectric conversion element 302 is transferred to the floating gate of the MOS transistor 306 when the transfer MOS transistor 303 is turned on. At this time, since the PSEL signal remains at the high level, the source follower circuit is in an operating state, and the output of “light signal + noise signal” corresponding to the potential of the floating gate of the MOS transistor 306 is output on the vertical output line 322. Made. During this period when the PTX signal is at a high level, the storage capacitor CTS1 (327) that accumulates “photo charge component + noise component” is connected to the vertical output line 322 by setting the PTS1 signal to a high level this time. The storage capacitor CTS1 (327) holds the signal of the photocharge component + noise component.

  As described above, the noise component for one row and the optical signal + noise component generated by the photodiode are accumulated in the storage capacitors CTN1 (326) and CTS1 (327), respectively. A period for transferring the signal charges generated in the unit pixel 301 to the first accumulation unit 323 is referred to as a transfer period HBLK1.

  Next, the signal charges stored in the storage capacitors CTN1 (326) and CTS1 (327) are transferred to the second storage unit 328. This transfer period is referred to as a transfer period HBLK2. Here, in the transfer period HBLK2, transfer is performed at different timings for each of the four blocks divided in the horizontal direction.

  First, signal charges from the pixels A11 and A12 are transferred to the second accumulation unit (1) in the transfer period HBLK2_ (1). First, the MOS transistors 337 and 338 are turned on by the signal PCTR_1, whereby the transfer capacitors CTN2 (335) and CTS2 (336) are reset. Thereafter, the MOS transistors 333 and 334 are turned on by the PTN2_1 signal and the PTS2_1 signal, so that the signal charges stored in the storage capacitors CTN1 (326) and CTS1 (327) are the MOS transistors 329 and 330 and the load current sources 331 and 332, respectively. Are transferred to the storage capacitors CTN2 (335) and CTS2 (336), respectively.

  Similarly, signal charges from the pixels A13 and A14 are transferred to the second accumulation unit (2) in the transfer period HBLK2_ (2), and signal charges from the pixels A15 and A16 are transferred in the transfer period HBLK2_ (3). It is transferred to the second storage unit (3). In addition, signal charges from the pixels A17 and A18 are transferred to the second accumulation unit (4) in the transfer period HBLK2_ (4).

  On the other hand, the signal charges stored in the storage capacitors CTN2 (335) and CTS2 (336) are turned on by the MOS transistors 340 and 341 by the transfer pulses PHN and PHS generated from the control pulse PH controlled by the horizontal shift register HSR. Are transferred to the capacities CHN342 and CHS343, respectively.

  The period during which the signal charges accumulated in the second accumulation unit are transferred to the horizontal transfer unit and output is referred to as a transfer period HSR.

  Here, since the signal charge transfer from the second accumulation unit (1) to the horizontal transfer unit can be started at the end of the transfer period HBLK2_ (1), the start time of the transfer period HSR is: It is possible to make it coincide with the start time of the transfer period HBLK2_ (2).

  Simultaneously with the end of the transfer period HBLK2_ (4) of the row composed of the pixels A11 to A18, reading of the next row composed of the pixels B11 to B18 is started. Also in this case, the configuration of the readout timing is the same as the readout timing of the row composed of the pixels A11 to A18 described above. At this time, the transfer period HBLK1 of the pixels B11 to B18 and the transfer period HSR of the pixels A11 to A18 are performed simultaneously. However, since the transfer period HBLK1 is a transfer period from the pixel 301 to the first accumulation unit 323, and the transfer period HSR is a transfer period from the second accumulation unit 328 to the horizontal transfer unit 339, both are simultaneously performed. There is no problem even if it is done.

  Similarly, readout of signals from the rows composed of the pixels A21 to A28 and the rows composed of the pixels B21 to B28 is sequentially performed, and the readout of one frame is completed.

  FIG. 5 is a timing block diagram showing a simplified readout timing in the imaging apparatus according to the first embodiment of the present invention.

  Of the drive timings in the imaging apparatus according to the first embodiment described with reference to FIG. 4, the reading order of each block will be briefly described with reference to the timing block diagram of FIG.

  In FIG. 5, at time T51, a transfer period (HBLK1) from the pixel 301 in the first row including the pixels A11 to A18 to the first accumulation unit 323 is started. At the time T52, the transfer period HBLK1 ends, and at the same time, the transfer period (HBLK2_ (1)) of the signals from the pixels A11 and A12 from the first accumulation unit 323 to the block (1) of the second accumulation unit 328 is started. The At time T53 when the transfer period HBLK2_ (1) is completed, a transfer period (HBLK2_ (2)) of signals from the pixels A13 and A14 to the block (2) of the second accumulation unit 328 is subsequently started. At the same time, the transfer period (HSR_ (1)) of the signal of the block (1) of the second storage unit 328 to the horizontal transfer unit 339 is also started. Thereafter, the transfer period HBLK2_ (2) ends at time T54, and the transfer period HSR_ (1) ends at time T55. Here, in this embodiment, the transfer from the second storage unit 328 to the horizontal transfer unit is longer than the transfer period (HBLK2_ (X)) from the first storage unit 323 to the second storage unit 328 in each block. It is assumed that the number of divisions of the second storage unit 328 is set so that the transfer period (HSR) takes a longer time, and the time T55 does not come before the time T54. As a result, the transfer period (HBLK2_ (HBLK2_ ()) of the signals from the pixels A15, A16, A17, and A18 from the first storage unit 323 to the blocks (3) and (4) of the second storage unit 328 is performed. 3) and HBLK2_ (4)) are continuously performed so as not to overlap with the transfer periods (HSR (3), HSR (4)) of the respective blocks to the horizontal transfer unit, as shown in FIG. It becomes possible.

  At time T56 when the transfer period HBLK2_ (4) ends, all the signals in the first accumulation unit have been transferred, so at time T56, from the pixels 301 in the second row including the pixels B11 to B18, The transfer period (HBLK1) to the first accumulation unit 323 can be started.

  In FIG. 5, the transfer period HBLK1 for the second row starts at time T56, the transfer period HBLK1 for the second row ends at time T57, and the transfer period HBLK2_ (1) for the second row starts. It was time. However, at the time T58 when the transfer period (HSR_ (4)) from the block (4) of the second storage unit 328 to the horizontal transfer unit 339 ends, the transfer period HBLK2_ (1) of the second row also ends at the same time. If the timing is correct, the horizontal transfer of each row can be performed continuously without any gap, so the total time required for signal readout can be reduced to the total time required for horizontal transfer. Become. Therefore, depending on the relationship between the length of the transfer period HBLK1 and the transfer period HSR, the start time of the transfer period HBLK1 in the second row can be later than the time T56.

  Similarly to the above, by reading the third row and the fourth row, as described above, the total time required for signal reading can be reduced to the total time required for horizontal transfer.

  As a condition for setting the number of block divisions necessary for reducing the total time required for signal reading to the total time required for horizontal transfer, the transfer period HSR is longer than the transfer period HBLK2_ (X) described above. In addition to the following, it is necessary to: That is, the sum of the lengths of all blocks in the transfer period HBLK1 and the transfer period HBLK2, that is, the length from time T51 to T56 is shorter than the length of the transfer period HSR of all blocks, that is, the length from time T53 to T58. To be.

  Incidentally, if the second storage unit is not divided into blocks and is configured to transfer signals of all columns to the second storage unit at the same time, the transfer period HBLK2 and the transfer period HSR cannot be overlapped. Disappear. Therefore, the transfer period HBLK2 must be sandwiched between the transfer periods HSR of the two rows. This increases the time required to read one row by the transfer period HBLK2.

(Second Embodiment)
The second embodiment of the present invention is configured to switch the number of blocks of the second storage unit 328 described in the first embodiment according to the shooting mode. Note that the configuration of the imaging apparatus is the same as that described with reference to the block diagram of FIG.

  FIG. 6 is a conceptual diagram illustrating a readout unit of a CMOS image sensor according to the second embodiment of the present invention.

  The pixel 301 of the CMOS image sensor in FIG. 6 is configured by a pixel group of 4 rows and 16 columns of pixels A1 to A16, B1 to B16, C1 to C16, and D1 to D16, and each of the second accumulation units 328 includes two columns. It is divided into 8 blocks corresponding to every minute. The other components are the same as those described in the conceptual diagram of FIG. The details of each component are the same as those described in the circuit diagram of FIG.

  Next, the signal readout timing of the imaging apparatus according to the second embodiment will be described in detail with reference to the timing charts of FIGS.

  FIG. 7 is a timing diagram showing in a simplified manner the readout timing when all the pixels are read out in the imaging apparatus according to the second embodiment of the present invention.

  In FIG. 7, the transfer period (HBLK1) from the pixel 301 to the first accumulation unit 323 in the first row including the pixels A1 to A16 is started at time T71. At the time T72, the transfer period HBLK1 ends, and at the same time, the transfer period (HBLK2_ (1)) of the signals from the pixels A1 and A2 from the first accumulation unit 323 to the block (1) of the second accumulation unit 328 is started. The At time T73 when the transfer period HBLK2_ (1) is completed, a transfer period (HBLK2_ (2)) of signals from the pixels A3 and A4 to the block (2) of the second accumulation unit 328 is subsequently started. At the same time, the transfer period (HSR_ (1)) of the signal of the block (1) of the second storage unit 328 to the horizontal transfer unit 339 is also started.

  Thereafter, similarly to the first embodiment described with reference to FIG. 5, at time T74, the signal from the pixels A15 and A16 is transferred from the first storage unit 323 to the block (8) of the second storage unit 328. The transfer period (HBLK2_ (8)) ends.

  After time T74, the transfer period HBLK1 in the second row is started. At that time, at the time T75 when the transfer period (HSR_ (8)) from the block (8) of the second storage unit 328 of the first row to the horizontal transfer unit 339 ends, the transfer period HBLK2_ (1 ) Is also set to a start time that ends.

  Similarly to the above, by reading out the third row and the fourth row, the total time required for signal readout can be reduced to the total time required for horizontal transfer.

  FIG. 8 is a timing chart showing a simplified read timing when a part of columns is extracted and read in the imaging apparatus according to the second embodiment.

  The partial readout mode in the imaging apparatus according to the second embodiment, which will be described with reference to FIG. 8, is assumed to be a mode in which half the entire column is read out here. In FIG. 8, a pixel group of 4 rows and 8 columns of pixels A5 to A12, B5 to B12, C5 to C12, and D5 to D12 near the center of the screen is read out.

  In FIG. 8, a transfer period (HBLK1) from the pixel 301 to the first accumulation unit 323 in the first row including the pixels A5 to A12 is started at time T81. Note that the lengths of the transfer period HBLK1, the transfer period HBLK2, and the transfer period HSR of each block are the same as the length of each transfer period in the all-pixel readout mode in the imaging device of the second embodiment described with reference to FIG. Suppose they are the same.

  At the same time as the transfer period HBLK1 ends at time T82, the signals from the pixels A5 and A6 are transferred from the first storage unit 323 to the block (3) of the second storage unit 328, and the signals from the pixels A7 and A8 are transferred. The transfer from the first storage unit 323 to the block (4) of the second storage unit 328 is started simultaneously (HBLK2_ (3), (4)). At time T83 when the transfer periods HBLK2_ (3) and (4) are completed, the signals from the pixels A9 and A10 are transferred from the first storage unit 323 to the block (5) of the second storage unit 328. Then, the transfer of the signals from the pixels A11 and A12 from the first storage unit 323 to the block (6) of the second storage unit 328 is started simultaneously (HBLK2_ (5), (6)). At the same time, the transfer period (HSR_ (3), (4)) of the signals of the block (3) and the block (4) of the second storage unit 328 to the horizontal transfer unit 339 is also started at time T83.

  Thereafter, the transfer period HBLK1 of the second row starts after time T84 when the transfer periods HBLK2_ (5) and (6) end. At that time, at the time T85 when the transfer period (HSR_ (5), (6)) from the block (5) and the block (6) of the second accumulation unit 328 in the first row to the horizontal transfer unit 339 ends at the same time. The transfer time HBLK2_ (3), (4) in the second row is set to a start time that is the end timing.

  Similarly to the above, by reading out the third row and the fourth row, the total time required for signal readout can be reduced to the total time required for horizontal transfer.

  As described with reference to FIGS. 7 and 8, the optimum number of columns of the divided blocks of the second storage unit 328 for reducing the total time required for signal readout to the total time required for horizontal transfer is It can be seen that the readout modes differ in the number of readout columns.

  Note that the detailed setting of various drive pulses at the drive timing of the imaging apparatus according to the second embodiment described with reference to FIGS. 7 and 8 will be described with reference to FIG. 4 according to the first embodiment. Since this is the same as the drive timing in FIG.

(Third embodiment)
In the third embodiment, there are two first accumulation units 323, two second accumulation units 328, and two horizontal transfer units 339 described in the first embodiment, and pixels in even columns of the pixels 301. And signals from odd-numbered columns of pixels are read out by different transfer paths. That is, it has a configuration of two-channel reading (having a plurality of signal output paths). Note that the configuration of the imaging apparatus is the same as that described with reference to the block diagram of FIG.

  FIG. 9 is a conceptual diagram illustrating a readout unit of a CMOS image sensor according to the third embodiment.

  The pixel 301 of the CMOS image sensor in FIG. 9 is composed of a pixel group of 4 rows and 16 columns of pixels A1 to A16, B1 to B16, C1 to C16, and D1 to D16. Two each of the first accumulation unit 323, the second accumulation unit 328, and the horizontal transfer unit 339 are arranged. Note that the components used in FIG. 9 are the same as those described in the conceptual diagram of FIG. The details of each component are the same as those described in the circuit diagram of FIG.

  The transfer path of the pixels A1 to A16 in the first row will be described with reference to FIG.

  The signals in the odd columns of the pixels A1, A3, A5, A7, A9, A11, A13, A15 are transferred to the first accumulation unit A. Thereafter, the signals of the pixels A1 and A3 are transferred to the horizontal transfer unit A via the second storage unit A (1). Similarly, the signals of the pixels A5 and A7 pass through the second storage unit A (2), the signals of the pixels A9 and A11 pass through the second storage unit A (3), and the signals of the pixels A13 and A15 pass through the second storage unit A (2). The data is transferred to the horizontal transfer unit A through the storage unit A (4). The signal transferred to the horizontal transfer unit A is output to the output unit A. The signals in the even columns of the pixels A2, A4, A6, A8, A10, A12, A14, A16 are transferred to the first accumulation unit B. Thereafter, similarly to the odd-numbered columns, the signals of the pixels A2 and A4 pass through the second storage unit B (1), and the signals of the pixels A6 and A8 pass through the second storage unit B (2), and the pixels A10 and A12. Are transferred to the horizontal transfer section B through the second storage section B (3), and the signals of the pixels A14 and A16 are transferred to the horizontal transfer section B through the second storage section B (4). The signal transferred to the horizontal transfer unit B is output to the output unit B. The signals in the second and subsequent lines are also output through the same transfer path as that in the first line.

  In FIG. 9, the signal reading of the two output channels can be performed at independent timings. Therefore, the signal readout of the pixels A1 and A3 via the second accumulation unit A (1) and the signal readout of the pixels A2 and A4 via the second accumulation unit B (1) can be performed simultaneously. is there. Similarly, the second storage unit A (2) and the second storage unit B (2), the second storage unit A (3), the second storage unit B (3), and the second storage unit A ( 4) and the signal reading through the second storage unit B (4) can be performed simultaneously. For this reason, the signal readout unit of the imaging apparatus has a second storage unit A (1), a second storage unit B (1), a second storage unit A (2), and a second storage unit. The unit B (2), the second storage unit A (3) and the second storage unit B (3), the second storage unit A (4) and the second storage unit B (4) are in the same block. You may think together. In such a case, it is considered that signals from a total of four pixels of two pixels for each channel are transferred to each block of the second accumulation unit.

  Note that, by considering the two output channels together as described above, the configuration of the overall signal readout unit is that the readout of the imaging apparatus according to the first embodiment in which the second storage unit is divided into four. This is considered to be equivalent to the configuration of the part. That is, the overall signal readout timing is the same as the drive timing of the imaging apparatus of the first embodiment described with reference to FIGS.

  As described above, the image pickup apparatus according to the embodiment of the present invention has been described with reference to FIGS. 1 to 9, but the present invention is not limited to this and can take various forms.

  For example, in the second embodiment described with reference to FIGS. 6 to 8, the readout mode includes a mode for reading out all pixels and a mode for reading out a part of the second storage unit in two modes. The block division is switched. However, the present invention is not limited to this. For example, the block division of the second storage unit is performed in a mode in which all pixels are read and a mode in which the number of read columns is reduced by performing addition in the horizontal direction. It is also possible to adopt a configuration that switches between. In addition, it is possible to adopt a configuration in which the block division of the second storage unit is switched when various modes with different numbers of read columns are switched and used.

  Further, in the third embodiment described with reference to FIG. 9, a two-channel reading configuration in which there are two transfer paths of the signal reading unit is adopted. However, the present invention is not limited to this, and a configuration may be adopted in which a plurality of transfer paths are arranged in accordance with a necessary reading speed and an allowable size and cost of the imaging apparatus. In this case, if the configuration of the plurality of transfer paths is the same, the number of columns of pixel signals transferred to each block of the second accumulation unit is a multiple of the output channel.

  In the first to third embodiments, the configuration of the block that divides the second storage unit is a configuration in which rows adjacent in the horizontal direction are bundled for each output channel. However, the present invention is not limited to this, and it may be configured such that columns located at different positions are combined into one block, or a block is formed by a random combination having no regularity. It doesn't matter.

(Other embodiments)
The object of each embodiment is also achieved by the following method. That is, a storage medium (or recording medium) in which a program code of software that realizes the functions of the above-described embodiments is recorded is supplied to the system or apparatus. Then, the computer (or CPU or MPU) of the system or apparatus reads and executes the program code stored in the storage medium. In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention. Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but the present invention includes the following cases. That is, an operating system (OS) running on a computer performs part or all of actual processing based on an instruction of a program code, and the functions of the above-described embodiments are realized by the processing.

  Furthermore, the following cases are also included in the present invention. That is, the program code read from the storage medium is written into a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer. Thereafter, based on the instruction of the program code, the CPU or the like provided in the function expansion card or function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.

  When the present invention is applied to the above storage medium, the storage medium stores program codes corresponding to the procedure described above.

1 is a block diagram illustrating a configuration of an imaging apparatus according to a first embodiment of the present invention. It is a conceptual diagram explaining the read-out part of the image sensor concerning 1st Embodiment. It is a circuit diagram explaining the structure of the image pick-up element concerning 1st Embodiment. 3 is a timing chart illustrating drive timings at the time of reading in the imaging apparatus according to the first embodiment. FIG. 3 is a timing diagram showing simplified readout timing in the imaging apparatus according to the first embodiment. It is a conceptual diagram explaining the read-out part of the image pick-up element concerning 2nd Embodiment. FIG. 10 is a timing diagram showing, in a simplified manner, readout timing at the time of all-pixel readout in the imaging apparatus according to the second embodiment. FIG. 9 is a timing diagram showing simplified readout timing at the time of partial readout in the imaging apparatus according to the second embodiment. It is a conceptual diagram explaining the read-out part of the CMOS image sensor which concerns on 3rd Embodiment.

DESCRIPTION OF SYMBOLS 101 Optical system 102 Mechanical shutter 103 Image pick-up element 104 Analog signal processing circuit 105 CDS circuit 106 Signal amplifier 107 Clamp circuit 108 A / D converter 110 Timing signal generation circuit 111 Drive circuit 112 Digital signal processing circuit 113 Image memory 114 Image recording medium 115 Recording circuit 116 Image display device 117 Display circuit 118 System control unit 119 Non-volatile memory (ROM)
120 Volatile memory (RAM)
Reference Signs List 121 temperature detection circuit 122 accumulation time setting means 123 photographing mode setting means 301 unit pixel 302 photodiode 303 transfer switch 304 reset switch 305 row selection switch 306 amplification amplifier 307 floating diffusion layer (floating diffusion)
321 Load current source 322 Vertical output line 323 First accumulation unit 328 Second accumulation unit 324, 325, 333, 334, 340, 341 Transfer switch 326, 327, 335, 336, 342, 343 Capacitance 337, 338 Reset switch 339 Horizontal transfer unit 344 Differential amplifier

Claims (6)

A first accumulation unit having a plurality of accumulation units provided for each column of the plurality of pixels, which holds image signals read from the plurality of pixels arranged two-dimensionally;
A second accumulator having a plurality of accumulators provided for each column of the plurality of pixels, which holds an image signal transferred from the first accumulator;
Output means for outputting an image signal held in the second storage means;
The second storage unit is divided into a plurality of blocks, and the image signal is transferred from the first storage unit to the second storage unit at different timings for each of the plurality of blocks. Control means for controlling one storage means and the second storage means;
An imaging apparatus comprising:   2. The imaging according to claim 1, wherein the control unit changes a combination of a plurality of blocks of the second accumulation unit in accordance with the number of columns read by the plurality of pixels arranged in the two-dimensional shape. apparatus.   The control means includes a time required to transfer the image signal from the plurality of pixels to the first storage means, a time required to transfer from the first storage means to the second storage means, and the second time. 2. The control unit according to claim 1, wherein a time obtained by adding the product of the number of divided blocks of the storage unit is controlled to be shorter than a time required for the output unit to output a signal of the second storage unit. The imaging device described in 1.   The imaging apparatus according to claim 1, further comprising a plurality of signal output paths including the first storage unit, the second storage unit, and the output unit. A first accumulating unit having a plurality of accumulating units provided for each column of the plurality of pixels, which holds image signals read out from a plurality of pixels arranged in a two-dimensional manner; A second storage unit having a plurality of storage units provided for each column of the plurality of pixels, which holds an image signal transferred from one storage unit, and held in the second storage unit Output means for outputting the image signal, and a method for controlling the imaging apparatus,
The second storage unit is divided into a plurality of blocks, and the image signal is transferred from the first storage unit to the second storage unit at different timings for each of the plurality of blocks. A control method for an imaging apparatus, comprising a control step of controlling one storage means and the second storage means.   A program for causing a computer to execute the control method according to claim 5.

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