JP5210071B2 - Packet receiver - Google Patents

Description

  The present invention relates to a packet receiving apparatus that receives a packet transmitted by digital broadcasting.

Currently, various transmission methods are standardized as methods for transmitting digital signals. For example, in satellite digital broadcasting, there is ISDB-S (Integrated Services Digital Broadcasting for Satellite; see Non-Patent Document 1) developed in Japan.
ISDB-S transmits a signal in slot units in a transmission frame composed of a plurality of slots. In this ISDB-S, BPSK / QPSK / TCM8PSK as a modulation method, Viterbi code having a variable coding rate as an error correction code (inner code), and RS (188, 204) having a fixed coding rate as an error correction code (outer code) [Reed-Solomon] code is adopted. In ISDB-S, a different modulation method can be used for each slot in a transmission frame.

Here, with reference to FIG. 12, the structure of the transmission frame at the time of using the some modulation system in ISDB-S is demonstrated. FIG. 12 is a frame configuration diagram showing an arrangement example of slots of different modulation schemes in the conventional ISDB-S.
As shown in FIG. 12, in ISDB-S, different modulation schemes (BPSK, QPSK, TCM8PSK) can be used for each slot (# 1 to # 48). In ISDB-S, one or more slots (slot groups) are assigned in advance according to each modulation method in order to maintain an interface signal at a constant data rate. For example, in TC8PSK, one slot is allocated per transmission unit. On the other hand, for example, in QPSK (r [coding rate] = 1/2), two slots are allocated, one being a valid slot and the other being a dummy (invalid) slot. Further, for example, in BPSK (r = 1/2), four slots are allocated, one being an effective slot and the other three being dummy slots.

  In ISDB-S, when a plurality of modulation schemes are used, they are arranged in order from the first slot in the transmission frame in the order of modulation schemes with the largest number of phases and in descending order of coding rate. Further, in the ISDB-S, when a dummy slot is used, an effective slot is arranged at the head of the assigned slot group, and a dummy slot is arranged thereafter.

  Based on this rule, in ISDB-S, for example, as shown in FIG. 12 (a), the slot of QPSK (r = 1/2) is arranged after the slot of TC8PSK and is assigned to QPSK. Of the two slots (# 47, # 48) as a group, the effective slot of QPSK is arranged in the first slot # 47, and the dummy slot is arranged in slot # 48.

  Further, for example, as shown in FIG. 12B, the slot of BPSK (r = 1/2) is arranged behind the slot of TC8PSK, and four slots (# 45 which are slot groups assigned to BPSK) ˜ # 48), the BPSK effective slot is arranged in the first slot # 45, and the dummy slots are arranged in the other slots # 46 to # 48.

Further, for example, as shown in FIG. 12C, when two slot groups of QPSK (r = 1/2) are arranged, two slots (# that are slot groups allocated to the first QPSK) 45, # 46), a valid slot of QPSK is arranged in the first slot # 45, and a dummy slot is arranged in slot # 46. Of the two slots (# 47, # 48), which are slots assigned to the second QPSK, the first slot # 47 has a valid QPSK slot, and the slot # 48 has a dummy slot. Is done.
ISDB-S: ARIB (Association of Radio Industries and Businesses) STD-B20, “Transmission System for Satellite Digital Broadcasting”, May 31, 2001, version 3.0

In the conventional ISDB-S, adjustment of the data rate according to the modulation scheme and coding rate is performed by a dummy slot. Further, in the conventional ISDB-S, an RS code is added to one packet (MPEG-2 TS packet [188 bytes]), and the packet is arranged and transmitted in one slot.
On the other hand, in recent years, error correction codes such as LDPC (Low Density Parity Check) codes having a very high error correction capability have attracted attention.

  However, since the LDPC code has a long code length (for example, several tens of thousands of bits), a plurality of packets are arranged in the information bits, and the coding rate, that is, the number of packets can be selected. It cannot be handled with one packet per slot. In other words, there is a problem that packets cannot be handled at a fixed period only with dummy slots, and the conventional ISDB-S technology cannot handle them.

  The present invention has been made to solve the above problems, and when transmitting a transmission frame composed of a plurality of slots, an error correction code having a different coding rate for each slot is used. An object of the present invention is to provide a packet receiving apparatus that can handle packets at a constant cycle.

  The present invention was devised to achieve the above object. First, the packet receiving apparatus according to claim 1 is configured to arrange packets at the highest coding rate of a plurality of error correction code systems. A packet receiving device that receives a packet encoded by arranging a number of packets specified by a predetermined error correction encoding method in a temporary storage unit having an area equal to or greater than the maximum number of packets. The likelihood information extracting unit, the error protecting unit, the packet rearrangement unit, and the output unit are provided.

  In such a configuration, the packet reception device extracts likelihood information of the bits constituting the symbol from the symbols mapped on the modulation axis of the carrier by the likelihood information extraction means. Then, the packet reception device decodes the likelihood information extracted by the likelihood information extraction unit by the error protection unit using an error correction code method predetermined for the slot from which the likelihood information is extracted.

Then, the packet receiver re-packets the packet decoded by the error protection unit by the packet re-arranging unit for each equally spaced packet candidate position indicating a candidate position for arranging the packet on the temporary storage unit for each slot. Deploy. As a result, even packets encoded by error correction code systems with different encoding rates are arranged with the same period.
Further, the packet receiving apparatus reads out and outputs the packet rearranged by the packet rearrangement means at a constant clock by the output means.

Also, packet receiver, packet rearrangement unit has a configuration further comprising a dummy packet arranging means.

  In such a configuration, the packet receiving device has a predetermined number of packets arranged in the temporary storage unit that is predetermined based on the coding rate of the error correction code system of the temporary storage unit by the dummy packet arrangement, and the maximum number of packets is satisfied. If there is no packet, a dummy packet is placed at a packet candidate position where no packet is placed.

Further, the packet reception device according to claim 2 is the packet reception device according to claim 1, further comprising dummy slot arrangement means.

In such a configuration, the packet receiving apparatus sets the number of slots in the slot group, which is a unit for changing the modulation scheme, as the maximum value of the number of transmission bits per modulation symbol in the plurality of modulation schemes, On the other hand, when the number of slots allocated in advance is less than the predetermined maximum number of slots, a dummy slot to which no valid packet is allocated is arranged in the slot that does not satisfy the predetermined number.
As a result, the number of slots in the slot group is kept constant regardless of the modulation method of the slot group.

According to a third aspect of the present invention , in the packet receiving device according to the first or second aspect , the output means determines the packet rearranged by the packet rearrangement means and the period of the packet candidate position. It is characterized in that it is read and output at a period divided by the packet length.

In such a configuration, the packet receiving apparatus can arrange and output packets arranged at a packet candidate position period without any gap.
The packet reception device according to claim 4 is the packet reception device according to claim 1, wherein the packet is a TS packet, and the packet is arranged at the highest coding rate of a plurality of error correction code systems. The number equal to or greater than the maximum number of packets is 28, and the interval between equally spaced packet candidate positions is 207.5 bytes with an interval of 19.5 bytes for each 188-byte TS packet.

The present invention has the following excellent effects.
According to the first , third , and fourth aspects of the present invention, the packet reception device can use a gap after arranging packets at equally spaced packet candidate positions even when using error correction codes with different coding rates. Packets can be output.

Further, according to the invention described in claim 1, the packet receiving apparatus, even when using a modulation method number of transmission bits per modulation symbol is different, as slot cycle is constant, to operate at the same clock frequency Therefore, it is possible to dynamically switch and use the modulation method.

According to the second aspect of the present invention, the packet receiving apparatus can detect the packet candidate position and the slot even when using an error correction code with a different coding rate or a modulation scheme with a different number of transmission bits per modulation symbol. The period becomes constant, and it can be operated at the same clock frequency. As a result, the packet receiving apparatus can dynamically switch between error correction codes and modulation schemes, and can further simplify the apparatus configuration.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Configuration of transmission system]
First, a configuration of a transmission system to which a packet transmission device and a packet reception device according to the present invention are applied will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of a transmission system to which a packet transmitting apparatus and a packet receiving apparatus according to the present invention are applied.
The transmission system 1 transmits an MPEG-2 TS obtained by encoding an information source such as video, audio, data, etc., using a digital modulation signal modulated by a digital broadcasting transmission method.

A transmission-side system that transmits a digital modulation signal includes a plurality of information source encoding devices 2, a multiplexing device 3, a remultiplexing device 4, and a packet transmission device 5.
The information source encoding device 2 encodes an information source (baseband data) such as input video, audio, and data. The information source encoding device 2 includes a video encoding unit, an audio encoding unit, and a data encoding unit (not shown), and encodes the input information source into an MPEG-2 signal. Note that there are a plurality of information source encoding devices 2 for each information source, and MPEG-2 signals encoded by the respective information source encoding devices 2 (2a, 2b,...) Are transmitted to the multiplexing device 3. Is output.

  The multiplexing device 3 multiplexes the MPEG-2 signals encoded by the plurality of information source encoding devices 2 (2a, 2b,...). The MPEG-2 transport stream (hereinafter referred to as TS) multiplexed by the multiplexing device 3 is output to the remultiplexing device 4.

  The remultiplexing device 4 remultiplexes the TS multiplexed by the multiplexing device 3 for each organized channel and resets the PCR (Program Clock Reference) in accordance with the timing of the TS of the packet transmission device 5. Is. As a result, TSs of a plurality of organization channels are combined into one TS. The synthesized TS is output to the packet transmission device 5.

  The packet transmission device 5 performs transmission path coding on the TS, arranges the packet in a transmission frame slot composed of a plurality of slots, and transmits the packet as a digital modulation signal. The digital modulation signal transmitted from the packet transmitter 5 is received by the packet receiver 6 on the receiving side. The packet transmission device 5 will be described in detail later.

A receiving-side system that receives a digitally modulated signal includes a packet receiving device 6, a demultiplexing device 7, and a plurality of information source decoding devices 8.
The packet receiving device 6 receives the digital modulation signal transmitted from the packet transmitting device 5 and decodes the TS arranged in the transmission frame. The TS decoded by the packet receiving device 6 is output to the demultiplexing device 7. The packet receiving device 6 will be described in detail later.

  The demultiplexer 7 separates the multiplexed TS output from the packet receiver 6 for each element signal. The element signals separated by the demultiplexer 7 are output to the information source decoder 8 for each information source.

  The information source decoding device 8 decodes the element signals separated by the demultiplexing device 7 into information sources such as video, audio, and data. Here, the receiving side is configured to include a plurality of information source decoding devices 8 (8a, 8b,...). For example, the receiving side system is a general home digital broadcasting television receiver. In this case, the information source decoding device 8 normally includes three for video, audio, and data. However, if a special receiver dedicated to audio broadcasting is used, the channel of the channel selected by the viewer is selected. There may be provided only one that decodes only speech.

[Configuration of each part signal]
Next, referring to FIG. 2 (refer to FIG. 1 as appropriate), in the packet transmission device 5 and the packet reception device 6 in the transmission system according to the embodiment of the present invention, the TS is channel-coded and transmitted as a digital modulation signal. The configuration of various signals until the digital modulation signal is decoded into TS will be described. FIG. 2 is a schematic diagram illustrating a signal configuration of the transmission system according to the embodiment of the present invention. Here, an example is shown in which a slot group SA is constituted by five slots S. 2A, 2B, and 2C, signals are expressed in time order from first to left (slots) and then from top to bottom (in units of slots). Each of the diagrams (a), (b), and (c) represents a certain frame. Also, between the diagrams of (b) and (c), one slot group (SA) of (b) is multi-level modulated and corresponds to one row of (c).

  As shown in FIG. 2A, the packet transmission device 5 inputs an interface signal in which packets P are arranged at equally spaced packet candidate positions PA (in this case, input from the remultiplexing device). The packet signal sequence (TS) of the interface signal may or may not have a gap between packets.

Then, after placing the packet P in the slot, the packet transmission device 5 further places a dummy packet PD (null packet) in the slot according to the coding rate. As a result, the packet transmission device 5 can keep the packet transmission rate constant even when there is a change in the coding rate of the error correction code (change in the effective transmission rate).
Note that, when the modulation scheme differs for each slot group SA, the packet transmission device 5 places the dummy packet PD in the interface signal corresponding to the dummy slot SD according to the modulation scheme. As a result, a constant transmission rate can be maintained.

  Although illustration is omitted, the packet transmission device 5 sets the PCR in a state where the packets P are arranged at the packet candidate positions PA at equal intervals. Thus, time information can be transmitted by specifying the position of the PCR.

  Then, as shown in FIG. 2 (b), the packet transmission device 5 encodes the interface signal with an error correction code for each slot S to obtain an error protection code, and a synchronization / control signal or the like (for carrier synchronization or frame synchronization). The internal processing signal (logical frame) is generated by adding a synchronization signal, a pilot signal serving as a reference for amplitude and phase, a control signal called TMCC, and the like. At this time, each slot S includes information bits in which the packet P is encoded and redundant bits according to the coding rate. Here, the error correction code, the error detection code, and the like are collectively referred to as an error protection code.

Then, as shown in FIG. 2 (c), the packet transmission device 5 converts the logical frames in FIG. 2 (b) into the transmission frames in the order of the modulation scheme with the largest number of phases and in the descending order of the coding rate. Then, modulation signals (physical frames) are generated and transmitted by arranging and modulating in order from the first slot.
The order in which the slots are arranged is merely an example following the conventional ISDB-S, and is not the essence of the present invention, and is not limited thereto. Further, here, 32APSK, 16APSK, 8PSK, and QPSK are illustrated as modulation schemes, but the modulation scheme is not limited thereto.
On the other hand, the packet reception device 6 receives the modulated signal shown in FIG. 2C and reproduces the TS by performing inverse conversion of the signal conversion performed by the packet transmission device 5.
As described above, according to the present invention, it is possible to change the modulation scheme in units of slots and further change the coding rate of the error correction code in units of slots.

[Signal condition]
Here, various signal conditions in the transmission system 1 will be listed and described.
≪Condition 1≫
In a plurality of modulation schemes, a bit clock obtained by multiplying the symbol clock fsym by Mmax is used, where Mmax is the number of transmission bits / maximum modulation symbol. Since Mmax is the maximum value of the number of modulation bits per modulation symbol (number of modulation bits / modulation symbol), if this bit clock is used, bit transmission can be performed in all modulation schemes.

≪Condition 2≫
The slots for the modulation period are equally divided by Mmax, and the slot group SA is configured by Mmax slots S. At this time, M slots where modulation bits actually exist are set as valid slots, and the remaining Mmax-M slots are set as dummy slots SD where no data exists.

≪Condition 3≫
A position where the packet P may be transmitted, that is, a packet candidate position PA is set to a certain number. By changing the ratio of actually arranging packets P among the packet candidate positions PA, it is possible to cope with changes in coding rate (changes in effective transmission rate).

≪Condition 4≫
The intervals between the packet candidate positions PA are equal intervals including between adjacent slots. At this time, the packet candidate position PA appears periodically. Note that the number Np (packets / slot) of candidate packet positions per slot is equal to or greater than the maximum number of packets that can actually be placed in one slot.

≪Condition 5≫
Under the above << Condition 4 >>, the packet candidate position number Np is set so that the cycle of the packet candidate position PA is an integral multiple of the bit clock. That is, when the slot period (the slot length plus the synchronization / control code etc.) is Ls and the packet candidate position period is also Lp, the packet candidate position number Np is , Ls = Np × Lp (where Lp = N [N: integer]).

≪Condition 6≫
If the packet candidate position cycle (packet cycle) Lp is smaller than the packet bit number Bp, the processing (transfer) is not completed with the transfer clock, and therefore Lp ≧ Bp.

≪Condition 7≫
Although not an indispensable condition, if a relationship of Lp = 8N [N: integer] is established, the relationship becomes an integer multiple with respect to the byte clock (transfer clock in units of bytes). It can be said.

[Specific example of signal]
Here, the premise of the transmission system 1 for satisfying each of the conditions will be described with reference to FIGS. This is an example in which BPSK, QPSK, 8PSK, 16APSK, etc. are used as modulation schemes and 32 APSK is used at the maximum. FIG. 3 is a frame configuration diagram showing an example of slot arrangement in the transmission system. FIG. 4 is a slot configuration diagram showing the configuration of slots in the transmission system. FIG. 5 is a diagram illustrating a format of a modulation signal in the transmission system.

As shown in FIG. 3, in the transmission system 1, the slot length is 44880 bits (5610 bytes), and the transmission system 1 includes 120 slots including dummy slots. The synchronization signal / control signal (TMCC) and the like are composed of 1600 bits (200 bytes). Note that the synchronization signal, the control signal, and the like vary in the range of 24 to 120 depending on the combination of modulation methods.
In the frame configuration shown in FIG. 3, each slot (# 1 to # 120) is encoded with a BCH code as an outer code and an LDPC code (variable coding rate) as an inner code.

Also, as shown in FIG. 4, in the slots handled by the transmission system 1, TS packets are stored in 8/10/12/15/18/20/22/24/25/26 according to the inner code rate. / 27 There is a mode to transmit.
Then, the transmission system 1 generates a modulation signal as shown in FIG. 5 by modulating the slot having the configuration shown in FIG. 4 excluding the dummy slot. Note that the 200-byte synchronization signal, pilot signal, and control signal (TMCC, etc.) shown in FIG. 3 are distributed in the data and transmitted.

In such a transmission system 1, as a specific example satisfying << Condition 1 >> to << Condition 6 >>, the number of slots in the slot group Mmax = 5 (slots), slot period Ls = 46480 (bits) [5810 bytes] Packet candidate position number Np = 28 (pieces), packet candidate position period Lp = 1660 (bits) [207.5 bytes], packet bit number Bp = 1504 (bits) [188 bytes]. In this example, << Condition 7 >> is not satisfied, but the packet candidate position period Lp (207.5 bytes) becomes an integral multiple of the byte clock when doubled, so the meaning of << Condition 7 >> is also considered. It has become.
Hereinafter, the packet transmission device 5 and the packet reception device 6 for realizing the transmission system 1 that satisfies these conditions will be described in detail by taking the case of the specific parameters as an example.

[Configuration of packet transmitter]
First, the configuration of the packet transmission device according to the embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram showing the configuration of the packet transmission apparatus according to the embodiment of the present invention. Here, the packet transmission device 5 includes a clock generation / distribution means C, a speed conversion means 50, a packet placement means 51, a control information generation means 52, an error protection coding means 53 (53a, 53b), an interleaver. 54, a buffer 55 (55a, 55b), a synchronization signal generating means 56, a mapping means 57 (57a, 57b, 57c), and a modulating means 58.

The clock generation / distribution means C generates an internal clock, generates a symbol clock, a bit clock, and a TS clock, and distributes them to each means.
Here, the symbol clock is a reference clock for the modulated symbol in the modulation scheme. The bit clock is a clock (Mmax × fsym) obtained by multiplying the symbol clock (fsym) by the number of slots (Mmax) in the slot group. Since Mmax is the maximum number of modulation bits / symbol, bit transmission is possible in all modulation schemes by using the bit clock as a reference clock for bit transmission.

  The TS clock is a reference clock for transferring a packet (TS packet). Here, the TS clock is a clock ((Bp / LP) × Mmax × fsym) obtained by multiplying the bit clock (Mmax × fsym) by the number of packet bits (Bp) / packet candidate position period (Lp).

  The speed conversion means 50 converts the speed of the input signal sequence (TS). Here, the speed converting means 50 converts the speed of a packet signal sequence without a gap transmitted by the TS clock into a packet signal sequence (with a gap between packets) transmitted by the bit clock.

  This speed conversion means 50 is an interface function block for handling a packet signal sequence (in the case of TS packets, TS according to a strict definition) having no gap as an input signal. For example, when the remultiplexing device 4 (see FIG. 1) can interface with a packet signal sequence having a certain gap, the speed conversion means 50 can be omitted. Note that the effect of the present invention is not affected because there is no change in packet time management for handling packets at equal intervals regardless of whether there is a gap in the packet signal sequence.

  The packet placement unit 51 places a packet in a temporary storage unit (not shown). When a packet is arranged and fixed data such as a synchronization byte is included, the fixed data may be deleted and arranged.

  The control information generating means 52 generates a transmission control signal (TMCC: Transmission and Multiplexing Configuration Control) indicating control information such as the number of slots and modulation scheme. The control information generating unit 52 outputs the generated transmission control signal to the error protection encoding unit 53b.

  The error protection encoding means 53 encodes data by an error correction code system predetermined for the slot. Here, the error protection encoding unit 53a encodes the data of the slot arranged by the packet arrangement unit 51 by an error correction code method predetermined for the slot. The slot data encoded by the error protection encoding means 53a is output to the interleaver 54.

  Further, the error protection encoding unit 53b receives the transmission control signal generated by the control information generating unit 52 and encodes the slot by a predetermined error correction code method. The data (encoding control signal) encoded by the error protection encoding unit 53b is temporarily stored in the buffer 55b.

  The interleaver 54 bit-interleaves the data encoded by the error protection encoding means 53a for each slot. Bit interleaving is an operation of exchanging data according to a certain rule. By exchanging data according to a certain rule in advance on the transmission side and returning it to the original on the reception side, errors (or correction capability) can be diffused and the correction capability of the error correction code can be sufficiently extracted.

  The buffer 55 temporarily stores data and is a general storage unit such as a memory. Here, the buffer 55a receives data from the interleaver 54 with reference to the bit clock, and outputs symbol data to the mapping means 57a with reference to the symbol clock. The buffer 55b receives data from the error protection encoding unit 54b with reference to the bit clock, and outputs symbol data to the mapping unit 57b with reference to the symbol clock. It should be noted that the buffers 55a and 55b may be arranged upstream of the error protection coding means 53a and 53b.

  The synchronization signal generating means 56 generates a synchronization signal with reference to the symbol clock. This synchronization signal is a signal for synchronizing the transmission frame. The synchronization signal generation unit 56 outputs the generated synchronization signal to the mapping unit 57c.

  The mapping means (symbol mapping means) 57 performs mapping on orthogonal axes (modulation axes) such as an I / Q axis and a phase / amplitude axis for modulating data of a symbol to be transmitted in accordance with a preset slot modulation method. To do.

  Here, the mapping means 57a reads the data (encoded packet) from the buffer 55a on the basis of the symbol clock and maps it on the I / Q axis or the like. The mapping unit 57b reads data (encoding control signal) from the buffer 55b with reference to the symbol clock, and maps it on the I / Q axis or the like. The mapping unit 57c maps the data (synchronization signal) output from the synchronization signal generation unit 56 on the I / Q axis or the like with reference to the symbol clock.

  The modulation means 58 modulates a carrier wave with signals of orthogonal axes such as I / Q axis and phase / amplitude axis mapped by the mapping means 57 (57a, 57b, 57c).

By configuring the packet transmission device 5 in this manner, the packet transmission device 5 is interfaced with a signal in which packets are arranged in slots at regular intervals when transmitting a transmission frame composed of a plurality of slots. Even if error correction codes having different coding rates for each slot are used, packets can be handled at a constant signal rate (packet rate including null packets).
Note that the PCR resetting function for resetting the PCR of a packet according to the period in which the packet is arranged may be performed as a function of the remultiplexing device 4. Since the packet cycles are equally spaced, the PCR can be easily reset.

[Operation of packet transmitting device]
Next, the operation of the packet transmission apparatus according to the embodiment of the present invention will be described with reference to FIG. 7 (refer to FIG. 6 as appropriate for the configuration). FIG. 7 is a flowchart showing the operation of the packet transmission apparatus according to the embodiment of the present invention. Here, TS arrangement and transmission operation, which are main operations of the present invention, will be described.

First, the packet transmission device 5 uses the speed conversion means 50 to convert the speed of the input signal sequence (TS) so that the cycle of the packet becomes a cycle of the slot cycle Ls / the number of packet bits Bp (step S1). .
Then, the packet transmission device 5 places the packet in the slot by the packet placement unit 51 (step S2).

Then, the packet transmission device 5 performs coding by the error protection coding means 53a on the slot arranged by the operation up to step S2 by the error correction coding method predetermined for the slot (step S3).
Then, the packet transmission device 5 performs bit interleaving on the data encoded in step S3 by the interleaver 54 (step S4), and the mapping unit 57a matches the symbol to be transmitted according to the preset modulation scheme of the slot. Mapping is performed on orthogonal axes such as an I / Q axis and a phase / amplitude axis for modulating data (step S5).

After that, the packet transmission apparatus 5 modulates the carrier wave by the signal of the orthogonal axis such as the I / Q axis and the phase / amplitude axis mapped in step S5 by the modulation unit 58 (step S6).
With the above operation, the packet transmission device 5 can handle packets at a constant period even when using an error correction code having a different coding rate when transmitting a transmission frame composed of a plurality of slots. .

The configuration of the packet transmission device 5 according to the embodiment of the present invention has been described above, but the present invention is not limited to this configuration. For example, although not shown here, the packet placement unit 51 and the error protection coding unit 53 are provided with a coding method setting unit that sets an error correction coding method for each slot from the outside. Alternatively, the error coding scheme may be changed. Further, the modulation means 58 may be configured to dynamically change the error modulation system by including a modulation system setting means for setting the modulation system for each slot group from the outside.
Note that the packet transmission device 5 can handle packets at a constant signal rate (packet rate including null packets) even when the error encoding method and the modulation method are changed as described above.

[Configuration of packet receiver]
Next, the configuration of the packet reception device according to the embodiment of the present invention will be described with reference to FIG. FIG. 8 is a block diagram showing a configuration of the packet receiving apparatus according to the embodiment of the present invention. Here, the packet receiver 6 includes a clock recovery means CA, a clock distribution means CB, a demodulation means 60, likelihood information extraction means 61 (61a, 61b, 61c), a buffer 62 (62a, 62b), Synchronous reproduction means 63, deinterleaver 64, error protection means 65 (65a, 65b), control information decoding means 66, packet rearrangement means 67, and speed conversion means 68 are provided.

  The clock recovery means CA recovers a clock synchronized with a digital modulation signal input to the demodulation means 60 described later. The clock regenerated by the clock regenerating means CA is output to the clock distributing means CB.

  The clock distribution means CB generates a symbol clock, a bit clock, and a TS clock based on the clock regenerated by the clock regenerating means CA and distributes them to each means. The symbol clock, bit clock, and TS clock correspond to the clocks distributed by the clock generation / distribution means C described with reference to FIG.

  The demodulating means 60 demodulates the digital modulation signal transmitted from the packet transmission device 5 (see FIG. 6) using the I / Q axis or the like. The demodulated signal demodulated by the demodulating means 60 is output to the likelihood information extracting means 61.

The likelihood information extraction means 61 extracts likelihood information of bits constituting the symbol from the demodulated orthogonal component in accordance with a preset slot modulation method.
Here, the likelihood information extraction unit 61a uses the symbol clock as a reference and the likelihood information (encoded packet [error protection code on the slot encoded with the error correction code]) mapped on the demodulated signal. (Likelihood information) is extracted and output to the buffer 62a.
Further, the likelihood information extraction unit 61b extracts likelihood information (likelihood information of the encoded control signal) mapped on the demodulated signal with reference to the symbol clock, and outputs it to the buffer 62b.
The likelihood information extraction unit 61 c extracts the likelihood information of the synchronization signal mapped on the demodulated signal on the basis of the symbol clock, and outputs it to the synchronization reproduction unit 63.

  The likelihood information extraction unit 61 is a functional block on the premise that a soft decision is performed in the subsequent synchronous reproduction unit 63 or the error protection unit 65. When performing a hard decision, the likelihood information extraction unit 61 becomes a symbol demapping unit.

  The buffer 62 temporarily stores data and is a general storage unit such as a memory. Here, the buffer 62a inputs data in units of symbols from the likelihood information extraction unit 61a with reference to the symbol clock, and outputs the data to the deinterleaver 64 with reference to the bit clock.

  Further, the buffer 62b receives data in units of symbols from the likelihood information extraction unit 61b with reference to the symbol clock, and outputs the data to the error protection unit 65b with reference to the bit clock. Note that the buffers 62a and 62b may be configured to be arranged downstream of error protection means 65a and 65b described later.

  The synchronous reproduction means 63 inputs a synchronous signal in symbol units from the likelihood information extraction means 61c on the basis of the symbol clock and reproduces it. Although not shown, the synchronization signal output by the synchronization reproducing means 63 is output to the outside and used for synchronization in units of slots of the signal sequence (TS) output by the packet reception device 6.

  The deinterleaver 64 receives data likelihood information from the buffer 62a with reference to the bit clock, and deinterleaves each slot. The deinterleaver 64 performs reverse conversion to the bit interleaving performed by the interleaver 54 described with reference to FIG. 6, thereby restoring the likelihood information sequence of the data in the slots in which the encoded packets are continuously arranged. Process.

The error protection means 65 decodes the data encoded by the error correction code system predetermined for the slot.
Here, the error protection means 65a inputs data likelihood information from the deinterleaver 64 with reference to the bit clock, and decodes it with an error correction code predetermined in the slot. The data (packet) decoded by the error protection unit 65 a is output to the packet rearrangement unit 67.

  Further, the error protection means 65b receives data likelihood information (encoding control signal likelihood information) from the buffer 62b with reference to the bit clock, and decodes it by a predetermined error correction code system for the slot. To do. The data (control signal) decoded by the error protection unit 65 b is output to the control information decoding unit 66.

  The control information decoding unit 66 receives the data (control signal) decoded from the error protection unit 65b on the basis of the bit clock, and analyzes the configuration of the control signal, so that the number of slots, the modulation method, etc. Decoding into control information. Although the control information output by the control information decoding unit 66 is not shown, it is also used as information in slot units of the signal sequence (TS) output by the packet reception device 6 by being output to the outside. The

  The packet rearrangement unit 67 rearranges the packet decoded by the error protection unit 65a to the packet candidate positions at equal intervals in the packet period for each slot.

Here, the configuration of the packet rearrangement unit 67 will be described with reference to FIG. FIG. 9 is a block diagram showing the configuration of the packet rearrangement means.
As shown in FIG. 9, the packet rearrangement unit 67 includes an equally spaced packet arrangement unit 67a, a dummy packet arrangement unit 67b, a dummy slot arrangement unit 67c, and a rearrangement storage unit 67d.

  The equally-spaced packet placement unit 67a places the TS at equally-spaced packet candidate positions in the rearrangement storage unit 67d. Here, the equally-spaced packet placement unit 67a places 1504 bits (188 bytes) of TS packets and 156 bits (19.5 bytes) of null data every packet candidate position period Lp = 1660 (bits).

  The dummy packet placement unit 67b, when the number of packets to be placed in the rearrangement storage unit 67d is less than the predetermined maximum number of packets when a packet with the largest coding rate of a plurality of error correction coding schemes is placed, A dummy packet is arranged at a packet candidate position where no packet is arranged. Here, the dummy packet placement unit 67b places 1504 bits (188 bytes) of null packets and 156 bits (19.5 bytes) of null data in the rearrangement storage unit 67d as dummy packets.

  When the number of slots allocated in advance for each modulation scheme is less than the predetermined maximum number of slots (here, Mmax = 5), the dummy slot arrangement unit 67c does not allocate a valid packet to the slots that do not satisfy the number. A dummy slot is arranged. Here, the dummy slot arrangement unit 67c arranges null packets and null data for the slot period in the rearrangement storage unit 67d as dummy slots.

The rearrangement storage means (temporary storage means) 67d temporarily stores slot group data, and is a general storage means such as a memory. The rearrangement storage unit 67d sets Mmax (the number of modulation bits / the maximum value of symbols) as the maximum number of packets when packets are arranged at the highest coding rate of a plurality of error correction code systems handled by the packet transmission device 5. It has a storage capacity more than doubled. Here, the rearrangement storage unit 67d temporarily stores 46480 (bit) data (the interface signal described in FIG. 2A) as the slot period Ls.
Returning to FIG. 8, the description of the configuration of the packet receiving device 6 will be continued.

  The speed conversion means (output means) 68 converts the speed of the packet signal sequence. Here, the speed conversion means 68 reads the packet with a cycle of packet cycle (packet candidate position cycle Lp clock) / packet length (packet bit number Bp) with reference to the bit clock, and sets the packet length with the TS clock. Data (TS) is output.

  This speed conversion means 68 is an interface function block for outputting a packet signal sequence (in the case of TS packets, TS according to a strict definition) having no gap as an output signal. For example, when the multiplexer / demultiplexer 7 (see FIG. 1) can interface with a packet signal sequence having a certain gap, the speed converting means 68 can be omitted. Note that the effect of the present invention is not affected because there is no change in packet time management for handling packets at equal intervals regardless of whether there is a gap in the packet signal sequence.

  By configuring the packet reception device 6 in this way, the packet reception device 6 can receive a constant amount from the packet transmission device 5 without considering the coding rate of packets arranged at predetermined intervals in the slot of the transmission frame. Packets can be output at a signal rate (packet rate including null packets).

[Operation of packet receiving device]
Next, referring to FIG. 10 (refer to FIG. 8 and FIG. 9 for the configuration as appropriate), the operation of the packet receiving apparatus according to the embodiment of the present invention will be described. FIG. 10 is a flowchart showing the operation of the packet reception apparatus according to the embodiment of the present invention. Here, a TS reception operation which is a main operation of the present invention will be described.

First, the packet receiver 6 demodulates the digital modulation signal by the demodulator 60 (step S11).
Then, the packet reception device 6 extracts likelihood information of each bit constituting the symbol from the demodulated signal demodulated in step S11 by the likelihood information extraction unit 61a (step S12).

Then, the packet reception device 6 deinterleaves the likelihood information of the data extracted in step S12 by the deinterleaver 64 (step S13).
Thereafter, the packet reception device 6 decodes the data deinterleaved in step S13 by the error protection means 65a using an error correction code having a coding rate predetermined for the slot (step S14).
Then, the packet receiving device 6 extracts the packet from the data decoded in step S14 by the packet rearrangement unit 67 and arranges the packet at the equally spaced packet candidate positions in the rearrangement storage unit 67d (step S15).

Then, the packet receiving device 6 converts the speed of the packet arranged in step S15 by the speed conversion means 68 by reading it at a period of packet period (packet candidate position period Lp) / packet length (number of packet bits Bp). The packet signal sequence (TS) is output (step S16).
With the above operation, the packet reception device 6 can output TSs at a constant cycle even when the coding rates of the error correction codes arranged in the slots of the transmission frame are different.

[Flow of MPEG2-TS transmission / reception]
Next, referring to FIG. 11 (refer to FIG. 1, FIG. 6, FIG. 8 and FIG. 9 as appropriate for the configuration), the flow of transmission and reception of MPEG-2 TS transmitted and received in the transmission system 1 (see FIG. 1) will be described in detail. I will explain it. FIG. 11 is an explanatory diagram for explaining a series of flows from when the MPEG-2 TS is input to the packet transmission device to when it is output from the packet reception device. The signal condition satisfies the above-described << condition 1 >> to << condition 6 >>.

  Here, it is assumed that the slot is modulated by 16 APSK. In this case, four slots are effective slots and one slot is a dummy slot for five slot groups. Here, it is assumed that the slot is encoded with an LDPC code. In this case, as shown in FIG. 4, the coding rate (inner code coding rate) varies between 1/4 and 9/10, and the number of packets stored in the slot is between 8 and 27. Change. Therefore, here, a case where the number of packets becomes 10 is illustrated.

  11A shows the time relationship of the TS signal sequence between the multiplexing device 3 and the remultiplexing device 4, and FIG. 11B shows the speed conversion means 50 and the packet placement means 51 in the packet transmission device 5. FIG. 11C shows the time relationship of the signal sequence for storing the TS in the transmission frame. In the packet transmission device 5, the packet sequence between the packet placement means 51 and the buffer 55a is shown in FIG. In the packet reception device 6, the time relationship of each signal sequence between the buffer 62 a and the packet rearrangement unit 67, FIG. 11D shows the relationship between the packet rearrangement unit 67 and the speed conversion unit 68 in the packet reception device 6. The time relationships of the signal trains in FIG.

  Here, the TS (188-byte TS packet) shown in FIG. 11 (a) is divided into 10 regions per slot in the area shown in FIG. 11 (b) divided into 28 packet candidate positions. Arranged one by one. In addition, dummy packets PD are arranged for the remaining packets in one slot. Further, a dummy slot SD is arranged in a slot where no TS is arranged. Note that the area (28 areas in one slot) divided by the number of packet candidate positions has a fixed length of 188 bytes + 19.5 bytes, and all packets are arranged at equal intervals. When the remultiplexing device 4 converts the signal sequence from (a) to (b), the PCR is reset for these packets according to the interval at which the packets are arranged.

  The packets arranged as shown in FIG. 11 (b) are arranged by the packet arrangement means 51, arranged as shown in FIG. 11 (c), subjected to error protection coding by the error protection coding means 53a, and the interleaver 54. (Interleaving may be omitted in some cases), and finally, the buffer 55a matches the timing of the modulation signal. In FIG. 11C, the first synchronization byte is omitted from the 188-byte TS packet and stored in the slot at 187 bytes.

Then, in the packet reception device 6, the timing of the modulated signal is converted into the time relationship of FIG. 11C by the buffer 62a, the interleaving is returned by the deinterleaver 64 (interleaving may be omitted), and error protection means Error protection such as error correction is performed by 65a, arranged by the packet rearrangement means 67, and arranged as shown in FIG. In addition, FIG.11 (d) is the arrangement | positioning (188 bytes + 19.5 bytes) similar to FIG.11 (b).

  In this way, by satisfying the above-mentioned signal conditions, the packet transmission device 5 and the packet reception device 6 can perform the same packet period (here, 188 + 19 in units of bit clock) regardless of the coding rate in internal processing. .5 byte cycle TS packets).

Although the packet transmission device 5 and the packet reception device 6 according to the present invention have been described above, the present invention is not limited to this.
Here, the case where one packet stream (TS) is configured by all slots of a frame has been described as a reference, but one packet stream (TS) may be configured by some slots. In this case, when the number of all slots is N _all and the number of slots of one part is N _part , the packet transmission device 5 performs N _all / N _part times speed conversion, and the packet reception device 6 uses N _part / N _What is necessary is just to add the conversion means which performs speed conversion of _all times.

  Although an example has been described here in which valid packets are arranged in the first half of the slot and null packets are arranged in the second half of the slot, the present invention is not limited to this arrangement. For example, valid packets may be placed in the second half of the slot and null packets in the first half of the slot. Alternatively, the packet candidate positions where the valid packets are arranged may be selected so that the valid packets are distributed as evenly as possible in the slot. Furthermore, it is also possible to select a packet candidate position that requires the shortest temporary storage time by the buffer 55a of the packet transmission device 5 or the buffer 62a of the packet reception device 6.

  Further, the packet candidate positions may be selected in the same manner as described above, with the slot group including the dummy slots as one group. That is, it is possible to select packet candidate positions where valid packets are arranged so that valid packets are distributed as evenly as possible in the slot group, and the buffer 55a of the packet transmission device 5 and the packet reception device 6 It is also possible to select a candidate packet position that requires the shortest temporary storage time by the buffer 62a.

  In addition, here, an example in which BPSK, QPSK, 8PSK, 16APSK, etc. are used as modulation schemes and 32 APSK is used at maximum is described. However, the transmission system 1 includes BPSK, QPSK, etc., and 8PSK at maximum. When used, it can be designed with various variations, including BPSK, QPSK, 8PSK, etc., and a maximum of 16APSK. Hereinafter, other variations will be described.

(First variation)
First, an example in which 8PSK is used at the maximum including BPSK, QPSK, etc. as modulation schemes will be described. In this case, the frame configuration diagram corresponding to FIG. 3 is the same except that the maximum slot is slot # 72 and the pilot signal is changed between 24-72. The slot configuration diagram corresponding to FIG. 4 and the modulation signal format corresponding to FIG. 5 are completely the same.

  In this case, the slot length is 44880 bits (5610 bytes), 72 slots including dummy slots, and 1600 bits (200 bytes) for the synchronization signal / control signal (TMCC) and the like. Note that the synchronization signal, control signal, and the like vary in the range of 24-72 depending on the combination of modulation methods. In the frame configuration, each slot (# 1 to # 72) is encoded with a BCH code as an outer code and an LDPC code (variable coding rate) as an inner code. (Equivalent to Fig. 3)

Similarly to FIG. 4, as the first variation, in the slot handled by the transmission system 1, a TS packet is transferred to an 8/10/12/15/18/20/22 according to the inner code coding rate. There are modes that transmit 24/25/26/27.
Then, the transmission system 1 generates a modulated signal similar to that in FIG. 5 by modulating a slot having the same structure as in FIG. 4 except for the dummy slot. Note that the 200-byte synchronization signal, pilot signal, and control signal (TMCC, etc.) corresponding to FIG. 3 are transmitted dispersed in the data.

  In such a first variation, specific examples that satisfy the above-mentioned << Condition 1 >> to << Condition 6 >> include the number of slots Mmax = 3 (slots) and the slot period Ls = 46480 (bits) [ 5810 bytes], packet candidate position number Np = 28 (pieces), packet candidate position period Lp = 1660 (bits) [207.5 bytes], and packet bit number Bp = 1504 (bits) [188 bytes].

(Second variation)
Next, an example in which 16 APSK is used at the maximum including BPSK, QPSK, 8PSK, etc. as modulation schemes will be described. In this case, the frame configuration diagram corresponding to FIG. 3 is the same except that the maximum slot is slot # 96 and the pilot signal is changed between 24-96. The slot configuration diagram corresponding to FIG. 4 and the modulation signal format corresponding to FIG. 5 are completely the same.

  In this case, the slot length is 44880 bits (5610 bytes), and it is composed of 96 slots including dummy slots. Further, the synchronization signal / control signal (TMCC) and the like are composed of 1600 bits (200 bytes). Note that the synchronization signal, the control signal, and the like vary in a range of 24 to 96 depending on the combination of modulation methods. In the frame configuration, each slot (# 1 to # 96) is encoded by a BCH code as an outer code and an LDPC code (variable coding rate) as an inner code. (Equivalent to Fig. 3)

Similarly to FIG. 4, as the second variation, in the slot handled by the transmission system 1, a TS packet is transferred to an 8/10/12/15/18/20/22 according to the inner code coding rate. There are modes that transmit 24/25/26/27.
And the 2nd variation of the transmission system 1 produces | generates the modulation signal similar to FIG. 5 by modulating the slot which has the structure similar to FIG. 4 except a dummy slot. Note that the 200-byte synchronization signal, pilot signal, and control signal (TMCC, etc.) corresponding to FIG. 3 are transmitted dispersed in the data.

  In such a second variation, as a specific example satisfying the above-mentioned << Condition 1 >> to << Condition 6 >>, the number of slots in the slot group Mmax = 4 (slots) and the slot period Ls = 46480 (bits) [ 5810 bytes], packet candidate position number Np = 28 (pieces), packet candidate position period Lp = 1660 (bits) [207.5 bytes], and packet bit number Bp = 1504 (bits) [188 bytes].

It is a block diagram which shows the structure of the transmission system which concerns on embodiment of this invention. It is the schematic diagram which showed the structure of the signal of the transmission system which concerns on embodiment of this invention. It is a frame block diagram which shows the example of arrangement | positioning of the slot in the transmission system which concerns on embodiment of this invention. It is a slot block diagram which shows the structure of the slot in the transmission system which concerns on embodiment of this invention. It is a figure which shows the format of the modulation signal in the transmission system which concerns on embodiment of this invention. It is a block diagram which shows the structure of the packet transmitter which concerns on embodiment of this invention. It is a flowchart which shows operation | movement of the packet transmission apparatus which concerns on embodiment of this invention. It is a block diagram which shows the structure of the packet receiver which concerns on embodiment of this invention. It is a block diagram which shows the structure of the packet rearrangement means in this invention. It is a flowchart which shows operation | movement of the packet receiver which concerns on embodiment of this invention. In this invention, it is explanatory drawing for demonstrating a series of flow until MPEG-2TS is input into a packet transmitter, and is output from a packet receiver. It is a frame block diagram which shows the example of arrangement | positioning of the slot of a different modulation system in the conventional ISDB-S.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Transmission system 2 Information source encoding apparatus 3 Multiplexing apparatus 4 Remultiplexing apparatus 5 Packet transmission apparatus 50 Rate conversion means 51 Packet arrangement means 52 Control information generation means 53 Error protection encoding means 54 Interleaver 55 Buffer 56 Synchronization signal generation means 57 Mapping means (symbol mapping means)
58 Modulation means C Clock generation / distribution means 6 Packet receiver 60 Demodulation means 61 Likelihood information extraction means 62 Buffer 63 Synchronous reproduction means 64 Deinterleaver 65 Error protection means 66 Control information decoding means 67 Packet rearrangement means 67a Equally spaced packets Arrangement means 67b Dummy packet arrangement means 67c Dummy slot arrangement means 67d Relocation storage means (temporary storage means)
68 Speed conversion means (output means)
CA clock recovery means CB clock distribution means 7 Demultiplexing device 8 Information source decoding device

Claims (4)

The temporary storage means having an area equal to or larger than the maximum number of packets when packets are arranged at the highest coding rate of a plurality of error correction coding systems is specified by the error correction coding system predetermined in the temporary storage means A packet receiving apparatus for receiving a packet in which a number of packets are arranged and encoded;
Likelihood information extracting means for extracting likelihood information of bits constituting the symbol from symbols mapped on the modulation axis of the carrier;
Error protection means for decoding the likelihood information extracted by the likelihood information extraction means by a predetermined error correction code scheme in the slot from which the likelihood information is extracted;
A packet rearrangement means for rearranging the packets decoded by the error protection means for each equally spaced packet candidate position indicating a candidate position for placing the packet on the temporary storage means for each slot;
An output means for reading out and outputting the packet rearranged by the packet rearrangement means at a constant clock;
The packet rearrangement means includes:
The packet candidate position where the packet is not arranged when the number of packets arranged in the temporary storage means is less than the maximum number of packets, which is predetermined based on the coding rate of the error correction code scheme of the temporary storage means features and to Rupa packet receiving apparatus further comprising a dummy packet arranging means for arranging the dummy packets. The number of slots in the slot group, which is a unit for changing the modulation scheme, is the maximum number of transmission bits per modulation symbol in a plurality of modulation schemes,
The packet rearrangement means includes:
For each of the modulation schemes, when the number of slots allocated in advance is less than a predetermined maximum number of slots, dummy slot arrangement means is provided that arranges a dummy slot to which no valid packet is allocated in the less than the predetermined number of slots. The packet receiver according to claim 1 . And the output means, wherein the rearranged packets by the packet rearrangement unit, in claim 1 or claim 2, characterized in that the output is read at a period obtained by dividing the period of the packet candidate positions in the packet length Packet receiver. The packet is a TS packet;
The number equal to or greater than the maximum number of packets when the packets are arranged at the highest coding rate of the plurality of error correction code systems is 28,
The packet reception apparatus according to claim 1, wherein the interval between the equally spaced packet candidate positions is 207.5 bytes with an interval of 19.5 bytes for each 188-byte TS packet.

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