JP5197010B2 - マルチコアプロセッサの格納命令の順序づけ - Google Patents
マルチコアプロセッサの格納命令の順序づけ Download PDFInfo
- Publication number
- JP5197010B2 JP5197010B2 JP2007531266A JP2007531266A JP5197010B2 JP 5197010 B2 JP5197010 B2 JP 5197010B2 JP 2007531266 A JP2007531266 A JP 2007531266A JP 2007531266 A JP2007531266 A JP 2007531266A JP 5197010 B2 JP5197010 B2 JP 5197010B2
- Authority
- JP
- Japan
- Prior art keywords
- write buffer
- ordering
- entry
- queue
- external memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US60921104P | 2004-09-10 | 2004-09-10 | |
| US60/609,211 | 2004-09-10 | ||
| US11/002,728 US7606998B2 (en) | 2004-09-10 | 2004-11-30 | Store instruction ordering for multi-core processor |
| US11/002,728 | 2004-11-30 | ||
| PCT/US2005/031710 WO2006031511A2 (en) | 2004-09-10 | 2005-09-01 | Store instruction ordering for multi-core processor |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008512785A JP2008512785A (ja) | 2008-04-24 |
| JP2008512785A5 JP2008512785A5 (enExample) | 2013-01-31 |
| JP5197010B2 true JP5197010B2 (ja) | 2013-05-15 |
Family
ID=36000925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007531266A Expired - Fee Related JP5197010B2 (ja) | 2004-09-10 | 2005-09-01 | マルチコアプロセッサの格納命令の順序づけ |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7606998B2 (enExample) |
| EP (1) | EP1787194B1 (enExample) |
| JP (1) | JP5197010B2 (enExample) |
| WO (1) | WO2006031511A2 (enExample) |
Families Citing this family (55)
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| US8959311B2 (en) * | 2006-08-25 | 2015-02-17 | Texas Instruments Incorporated | Methods and systems involving secure RAM |
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| CN101174202B (zh) * | 2006-10-31 | 2010-09-15 | 扬智科技股份有限公司 | 具多指令流的录像译码器快取装置及其控制方法 |
| US8059532B2 (en) * | 2007-06-21 | 2011-11-15 | Packeteer, Inc. | Data and control plane architecture including server-side triggered flow policy mechanism |
| US8279885B2 (en) * | 2007-09-25 | 2012-10-02 | Packeteer, Inc. | Lockless processing of command operations in multiprocessor systems |
| US7813277B2 (en) * | 2007-06-29 | 2010-10-12 | Packeteer, Inc. | Lockless bandwidth management for multiprocessor networking devices |
| US8111707B2 (en) | 2007-12-20 | 2012-02-07 | Packeteer, Inc. | Compression mechanisms for control plane—data plane processing architectures |
| US9419867B2 (en) * | 2007-03-30 | 2016-08-16 | Blue Coat Systems, Inc. | Data and control plane architecture for network application traffic management device |
| US20090198994A1 (en) * | 2008-02-04 | 2009-08-06 | Encassa Pty Ltd | Updated security system |
| FI20085217A0 (fi) * | 2008-03-07 | 2008-03-07 | Nokia Corp | Tietojenkäsittelyjärjestely |
| US8230117B2 (en) * | 2009-04-09 | 2012-07-24 | International Business Machines Corporation | Techniques for write-after-write ordering in a coherency managed processor system that employs a command pipeline |
| US9280343B2 (en) * | 2009-08-10 | 2016-03-08 | Oracle America, Inc. | Store queue with token to facilitate efficient thread synchronization |
| US9251097B1 (en) | 2011-03-22 | 2016-02-02 | Amazon Technologies, Inc. | Redundant key management |
| US9767098B2 (en) | 2012-08-08 | 2017-09-19 | Amazon Technologies, Inc. | Archival data storage system |
| US9213709B2 (en) | 2012-08-08 | 2015-12-15 | Amazon Technologies, Inc. | Archival data identification |
| US9563681B1 (en) | 2012-08-08 | 2017-02-07 | Amazon Technologies, Inc. | Archival data flow management |
| JP5732953B2 (ja) * | 2011-03-24 | 2015-06-10 | 日本電気株式会社 | ベクトル処理装置、ベクトル処理方法、及び、プログラム |
| US9639591B2 (en) * | 2011-06-13 | 2017-05-02 | EMC IP Holding Company LLC | Low latency replication techniques with content addressable storage |
| US9330002B2 (en) * | 2011-10-31 | 2016-05-03 | Cavium, Inc. | Multi-core interconnect in a network processor |
| CN104823168B (zh) | 2012-06-15 | 2018-11-09 | 英特尔公司 | 用于实现从由加载存储重新排序和优化导致的推测性转发遗漏预测/错误中恢复的方法和系统 |
| CN107220032B (zh) | 2012-06-15 | 2020-12-15 | 英特尔公司 | 无消歧乱序加载存储队列 |
| EP2862062B1 (en) | 2012-06-15 | 2024-03-06 | Intel Corporation | A virtual load store queue having a dynamic dispatch window with a distributed structure |
| WO2013188705A2 (en) | 2012-06-15 | 2013-12-19 | Soft Machines, Inc. | A virtual load store queue having a dynamic dispatch window with a unified structure |
| CN104583957B (zh) | 2012-06-15 | 2018-08-10 | 英特尔公司 | 具有无消歧乱序加载存储队列的重新排序的推测性指令序列 |
| EP2862072B1 (en) * | 2012-06-15 | 2022-09-07 | Intel Corporation | A load store buffer agnostic to threads implementing forwarding from different threads based on store seniority |
| CN104583936B (zh) * | 2012-06-15 | 2019-01-04 | 英特尔公司 | 具有组成按序从存储器进行读取的加载的存储器一致性模型中的乱序加载的信号量方法和系统 |
| KR101826399B1 (ko) | 2012-06-15 | 2018-02-06 | 인텔 코포레이션 | Load store 재정렬 및 최적화를 구현하는 명령어 정의 |
| US9092441B1 (en) | 2012-08-08 | 2015-07-28 | Amazon Technologies, Inc. | Archival data organization and management |
| US9830111B1 (en) | 2012-08-08 | 2017-11-28 | Amazon Technologies, Inc. | Data storage space management |
| US10120579B1 (en) | 2012-08-08 | 2018-11-06 | Amazon Technologies, Inc. | Data storage management for sequentially written media |
| US8805793B2 (en) | 2012-08-08 | 2014-08-12 | Amazon Technologies, Inc. | Data storage integrity validation |
| US8959067B1 (en) | 2012-08-08 | 2015-02-17 | Amazon Technologies, Inc. | Data storage inventory indexing |
| US9225675B2 (en) | 2012-08-08 | 2015-12-29 | Amazon Technologies, Inc. | Data storage application programming interface |
| US9354683B2 (en) | 2012-08-08 | 2016-05-31 | Amazon Technologies, Inc. | Data storage power management |
| US9250811B1 (en) * | 2012-08-08 | 2016-02-02 | Amazon Technologies, Inc. | Data write caching for sequentially written media |
| US9652487B1 (en) | 2012-08-08 | 2017-05-16 | Amazon Technologies, Inc. | Programmable checksum calculations on data storage devices |
| US9779035B1 (en) | 2012-08-08 | 2017-10-03 | Amazon Technologies, Inc. | Log-based data storage on sequentially written media |
| US9904788B2 (en) | 2012-08-08 | 2018-02-27 | Amazon Technologies, Inc. | Redundant key management |
| JP6105307B2 (ja) * | 2013-02-07 | 2017-03-29 | Necプラットフォームズ株式会社 | 命令実行制御装置、命令実行制御システム、命令実行制御方法、及び、命令実行制御プログラム |
| US10558581B1 (en) | 2013-02-19 | 2020-02-11 | Amazon Technologies, Inc. | Systems and techniques for data recovery in a keymapless data storage system |
| US10489158B2 (en) | 2014-09-26 | 2019-11-26 | Intel Corporation | Processors, methods, systems, and instructions to selectively fence only persistent storage of given data relative to subsequent stores |
| JP5917678B1 (ja) | 2014-12-26 | 2016-05-18 | 株式会社Pfu | 情報処理装置、方法およびプログラム |
| US11386060B1 (en) | 2015-09-23 | 2022-07-12 | Amazon Technologies, Inc. | Techniques for verifiably processing data in distributed computing systems |
| US10521351B2 (en) * | 2017-01-12 | 2019-12-31 | International Business Machines Corporation | Temporarily suppressing processing of a restrained storage operand request |
| US10621090B2 (en) | 2017-01-12 | 2020-04-14 | International Business Machines Corporation | Facility for extending exclusive hold of a cache line in private cache |
| US10929308B2 (en) * | 2017-11-22 | 2021-02-23 | Arm Limited | Performing maintenance operations |
| US10572387B2 (en) | 2018-01-11 | 2020-02-25 | International Business Machines Corporation | Hardware control of CPU hold of a cache line in private cache where cache invalidate bit is reset upon expiration of timer |
| US12086450B1 (en) | 2018-09-26 | 2024-09-10 | Amazon Technologies, Inc. | Synchronous get copy for asynchronous storage |
| US11507513B2 (en) | 2019-05-24 | 2022-11-22 | Texas Instruments Incorporated | Methods and apparatus to facilitate an atomic operation and/or a histogram operation in cache pipeline |
| WO2020257976A1 (en) * | 2019-06-24 | 2020-12-30 | Intel Corporation | Apparatus and method for scheduling graphics processing resources |
| JP2021015384A (ja) * | 2019-07-10 | 2021-02-12 | 富士通株式会社 | 情報処理回路、情報処理装置、情報処理方法及び情報処理プログラム |
| CN113326020B (zh) * | 2020-02-28 | 2025-04-25 | 昆仑芯(北京)科技有限公司 | 缓存器件、缓存器、系统、数据处理方法、装置及介质 |
| US20220382546A1 (en) * | 2021-05-31 | 2022-12-01 | Andes Technology Corporation | Apparatus and method for implementing vector mask in vector processing unit |
| KR20230049858A (ko) * | 2021-10-07 | 2023-04-14 | 에스케이하이닉스 주식회사 | 메모리 컨트롤러 및 메모리 컨트롤러의 동작 방법 |
| US20230137769A1 (en) * | 2021-11-03 | 2023-05-04 | Intel Corporation | Software thread-based dynamic memory bandwidth allocation |
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| US5265233A (en) * | 1991-05-17 | 1993-11-23 | Sun Microsystems, Inc. | Method and apparatus for providing total and partial store ordering for a memory in multi-processor system |
| JPH07302200A (ja) * | 1994-04-28 | 1995-11-14 | Hewlett Packard Co <Hp> | 順次付けロード動作および順序付け記憶動作を強制する命令を有するコンピュータのロード命令方法。 |
| US5524220A (en) | 1994-08-31 | 1996-06-04 | Vlsi Technology, Inc. | Memory subsystems having look-ahead instruction prefetch buffers and intelligent posted write buffers for increasing the throughput of digital computer systems |
| US5857097A (en) | 1997-03-10 | 1999-01-05 | Digital Equipment Corporation | Method for identifying reasons for dynamic stall cycles during the execution of a program |
| US5956503A (en) * | 1997-04-14 | 1999-09-21 | International Business Machines Corporation | Method and system for front-end and back-end gathering of store instructions within a data-processing system |
| US5990913A (en) | 1997-07-30 | 1999-11-23 | Intel Corporation | Method and apparatus for implementing a flush command for an accelerated graphics port device |
| JPH11167557A (ja) * | 1997-12-02 | 1999-06-22 | Hitachi Ltd | 共有メモリアクセス順序保証方法及びマルチプロセッサシステム |
| US6073210A (en) * | 1998-03-31 | 2000-06-06 | Intel Corporation | Synchronization of weakly ordered write combining operations using a fencing mechanism |
| US6209073B1 (en) * | 1998-04-27 | 2001-03-27 | International Business Machines Corp. | System and method for interlocking barrier operations in load and store queues |
| JP3858492B2 (ja) * | 1998-12-28 | 2006-12-13 | 株式会社日立製作所 | マルチプロセッサシステム |
| US6594741B1 (en) * | 2001-02-23 | 2003-07-15 | Lsi Logic Corporation | Versatile write buffer for a microprocessor and method using same |
| US20020188817A1 (en) | 2001-06-08 | 2002-12-12 | Norden Erik K. | Store buffer pipeline |
| US6587929B2 (en) | 2001-07-31 | 2003-07-01 | Ip-First, L.L.C. | Apparatus and method for performing write-combining in a pipelined microprocessor using tags |
| US20060026371A1 (en) * | 2004-07-30 | 2006-02-02 | Chrysos George Z | Method and apparatus for implementing memory order models with order vectors |
-
2004
- 2004-11-30 US US11/002,728 patent/US7606998B2/en not_active Expired - Lifetime
-
2005
- 2005-09-01 JP JP2007531266A patent/JP5197010B2/ja not_active Expired - Fee Related
- 2005-09-01 WO PCT/US2005/031710 patent/WO2006031511A2/en not_active Ceased
- 2005-09-01 EP EP05795368.9A patent/EP1787194B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US7606998B2 (en) | 2009-10-20 |
| EP1787194A2 (en) | 2007-05-23 |
| JP2008512785A (ja) | 2008-04-24 |
| WO2006031511A3 (en) | 2006-11-23 |
| US20060095741A1 (en) | 2006-05-04 |
| EP1787194B1 (en) | 2017-10-25 |
| WO2006031511A2 (en) | 2006-03-23 |
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