JP5192284B2 - Circuit equipment - Google Patents

Description

  The present invention relates to a circuit device in which a plurality of circuits such as a drive circuit for driving a load mounted on a vehicle are mounted, and these circuits can be selectively operated in parallel.

  An IC (Integrated Circuit) chip is often encapsulated in a synthetic resin package and mounted on a circuit board, and an allowable loss is defined for each IC chip package. The allowable loss is determined from the amount of heat generated when the circuit mounted on the IC chip is operated and the resistance to heat of the package. The generated heat amount is the amount of electricity consumed when the circuit is operated ( Therefore, the maximum power consumption of the circuit is limited by the allowable loss of the package.

  In recent years, with the development of semiconductor manufacturing technology, IC chips can be highly integrated and enlarged. Accordingly, a large number of circuits can be mounted on one IC chip, and a large number of functions can be provided on a single IC chip. However, as described above, since the maximum power consumption of the circuit is limited by the allowable loss of the package enclosing the IC chip, there is a problem that the number of circuits or the circuit scale that can be mounted on the IC chip is limited. .

  In recent years, the number of electronic devices mounted on vehicles tends to increase, and the electronic control of vehicles is progressing. Accordingly, a drive circuit for driving a load such as a motor or an actuator, a communication circuit for transmitting and receiving information between a plurality of devices, a power supply circuit for supplying power from the battery to each circuit, and accepting a user operation Therefore, various circuits such as a switch input processing circuit and a control circuit for controlling them are required. By mounting these various circuits on a single chip, advantages such as a reduction in manufacturing cost and a reduction in circuit mounting space can be obtained. . In particular, since a drive circuit that drives a load such as a motor or an actuator consumes a large amount of power, it is difficult to mount a large number of drive circuits on one IC chip.

Patent Document 1 proposes a load driving device that can reliably suppress a intensive increase in load current when driving a plurality of loads. In this load driving device, for example, for three loads, the control circuit outputs a PWM (Pulse Width Modulation) signal so that there is no period of simultaneous driving. Specifically, the control circuit causes the delay circuit to change the phase of the common carrier signal by 1/3 of the period, and changes the output phase of the PWM signal equally according to the number of loads.
JP 2006-294694 A

  However, the load driving device described in Patent Document 1 is configured to uniformly change the output phase of the PWM signal by delaying the phase of the carrier wave signal, and is easily applied when driving about three loads. Yes, but it is difficult to apply when driving more loads. Further, since it is intended only for a drive circuit that outputs a PWM signal, it cannot be applied when various circuits are mounted on one chip.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a circuit device capable of operating a large number of mounted circuits without exceeding an allowable amount of consumed electricity. Is to provide.

  The circuit device according to the present invention is a circuit device including a plurality of circuits that can be selectively operated, a receiving unit that receives an operation instruction from the outside for each circuit, a combination of circuits operated in parallel, and each circuit Storage means for storing the waiting time of each circuit from the reception of the operation instruction by the receiving means to the start of operation and the operation time for which each circuit operates, the combination stored by the storage means, the amount of consumed electricity, An operation start timing determining means for determining an operation start timing of a circuit according to an operation instruction received by the receiving means, based on a waiting time and an operating time, and an allowable total electricity consumption; and the operation start timing determining means And circuit operation control means for starting the operation of each circuit in accordance with the operation start timing determined by.

  In the present invention, a circuit device mounted with a plurality of circuits operates in parallel, a combination of circuits to be operated in parallel, an amount of electricity consumed by each circuit, a waiting time of each circuit from reception of an operation instruction to an operation start, and each circuit operating. The operation time is stored in advance. When receiving operation instructions for a plurality of circuits and operating a plurality of circuits in parallel, the stored combination, the amount of electricity consumed by each circuit, the waiting time and operation time of each circuit, and the allowable total consumption The operation start timing of each circuit is determined according to the amount of electricity. By determining the operation start timing in consideration of the power consumption of each circuit, a plurality of circuits can be operated without exceeding the allowable total power consumption. Further, by determining the operation start timing in consideration of the waiting time and the operation time until the operation of each circuit is started, the operation of each circuit can be started without delay. Therefore, since the number of circuits that operate simultaneously can be reduced by shifting the operation timing of each circuit, it is possible to reduce the total amount of electricity consumed by the circuit device without causing a problem in the operation of each circuit.

  The circuit device according to the present invention is a circuit device including a plurality of circuits that are mounted on a vehicle and can be selectively operated. Vehicle state acquisition means for acquiring a vehicle state related to the traveling of the vehicle, A combination of a reception unit that receives an operation instruction from the outside with respect to the circuit and a circuit that operates in parallel according to the vehicle state, an amount of electricity consumed by each circuit, and each circuit from the reception of the operation instruction by the reception unit to the start of the operation Storage means storing the waiting time of each circuit and the operation time for which each circuit operates, the vehicle state acquired by the vehicle state acquisition means, the combination stored by the storage means, the amount of electricity consumed, the waiting time and the operation time, and the allowable The operation start timing determination for determining the operation start timing of the circuit related to the operation instruction received by the receiving means based on the total electricity consumption. And means, in response to the operation start timing of said operating start timing determining means decides, characterized in that it comprises a circuit operation control means for starting operation of the respective circuits.

  In the present invention, when the circuit device is mounted on a vehicle, the circuit device is provided with means for acquiring the vehicle state, and the combination of circuits operated in parallel, the amount of electricity consumed by each circuit, and the operation instruction The waiting time of each circuit from the acceptance of the operation to the start of operation and the operation time during which each circuit operates are stored in advance in association with the vehicle state. For example, the circuit device stores a combination of circuits in advance according to whether the vehicle is running, whether the engine of the vehicle is operating, or the vehicle state such as the rotation operation position of the ignition key. Can do. When operating multiple circuits in parallel, depending on the acquired vehicle state, the stored combination, the amount of electricity consumed for each circuit, the total amount of electricity consumed allowed, the waiting time for each circuit and the operating time, The operation start timing of each circuit is determined. By determining the operation start timing in consideration of the vehicle state, it is possible to reliably operate only necessary circuits according to the vehicle state. Therefore, each circuit can be appropriately operated according to the vehicle state without causing any trouble in the operation of each circuit, and the operation amount of each circuit can be shifted to reduce the total amount of electricity consumed by the circuit device. .

  In the circuit device according to the present invention, when the operation start timing determining unit is configured such that when the total amount of electricity consumed by a plurality of circuits included in the combination exceeds a predetermined amount of electricity, The operation start timing of each circuit is shifted so that the total amount does not exceed the predetermined amount of electricity.

  In the present invention, the circuit device selects one combination from a plurality of combinations according to, for example, the operation state of the circuit and the vehicle state, and operates a plurality of circuits included in the combination, but is included in the selected combination. If the total amount of electricity consumed by the circuit does not exceed a predetermined amount of electricity (for example, the amount of electricity consumed as a whole circuit device), multiple circuits included in this combination can be operated simultaneously without adjusting the timing. Can be made. However, if the total amount of electricity consumed by the circuit exceeds a predetermined amount of electricity, a plurality of circuits included in this combination cannot be operated simultaneously, so that the circuit device does not exceed the predetermined amount of electricity. Shift the operation start timing of the circuit.

  In the circuit device according to the present invention, the operation start timing determining unit may determine the operation start timing of each circuit so that the circuit having a short waiting time and a long operation time is preferentially started. It is characterized by being.

  In the present invention, a circuit with a short waiting time (that is, a circuit that requires a quick response) cannot delay the start of operation, so the circuit device needs to preferentially start the circuit. In particular, since a circuit with a short waiting time and a long operation time is difficult to adjust the timing, the circuit device sets the operation start timing of a plurality of circuits included in the combination so that the circuit is started with the highest priority. decide.

  Further, in the circuit device according to the present invention, the operation start timing determining unit causes the circuit having a short waiting time and a short operation time to start operating within a predetermined time after the receiving unit receives the operation instruction. The operation start timing of each circuit is determined.

  In the present invention, a circuit with a short waiting time needs to be preferentially started, but a circuit with a short operating time is delayed within a certain amount of time if the operation start time is within the waiting time. Can be operated. Therefore, the circuit device determines the operation start timing of each circuit so that the circuit with a short waiting time and a short operation time is started within a predetermined time. Here, for example, a time of about 100 ms (milliseconds) that cannot be recognized by a human can be set as the predetermined time.

  In the circuit device according to the present invention, the operation start timing determining unit may determine the operation start timing of each circuit so that a plurality of circuits having a long waiting time and a short operation time do not operate simultaneously. It is characterized by being.

  In the present invention, a circuit with a long waiting time can be delayed and started to operate, and a circuit with a shorter operating time can be easily adjusted in timing such as changing the operation order. Therefore, the circuit device determines the operation start timing so as not to operate simultaneously for a plurality of circuits having a long waiting time and a short operation time, and sequentially operates each circuit.

  In the circuit device according to the present invention, the operation start timing determining means determines the operation start timing of each circuit so that a circuit having a long waiting time and a long operation time starts operating later than other circuits. It is made to do so.

  In the present invention, a circuit with a long waiting time can be started after a delay, but it is difficult to adjust timing such as changing the operation order of a circuit with a long operation time. Therefore, the circuit device determines the operation start timing so that the operation of a circuit having a long waiting time and a long operation time is started later than the other circuits.

  In the case of the present invention, by appropriately determining the operation start timing of a plurality of circuits, the circuit device can reduce the number of circuits that operate simultaneously without causing problems in the operation of each circuit, The amount of electricity consumed by the entire circuit device can be reduced. Therefore, the circuit device can operate a large number of mounted circuits without exceeding the total allowable power consumption, so that a large number of circuits can be integrated into one chip without exceeding the allowable loss of the package. It becomes possible.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof. FIG. 1 is a block diagram showing a configuration of a load driving system using a circuit device according to the present invention. In the figure, reference numeral 1 denotes an ASIC (Application Specific Integrated Circuit), which corresponds to the circuit device according to the present invention. The ASIC 1 includes a plurality of various circuits such as a control circuit 10, a load driving unit 20 having a plurality of driving circuits A to H, a communication circuit 31, a power supply circuit 32, and a switch (hereinafter abbreviated as SW) input processing circuit 33. Is manufactured as an IC chip mounted on one chip and enclosed in a synthetic resin package (not shown).

  The ASIC 1 applies a drive voltage or a drive current to a load 52 such as an actuator for locking and unlocking a vehicle door, a motor for operating a vehicle power window, and a motor for adjusting the angle of a vehicle door mirror, for example. A load driving unit 20 is provided. The load driving unit 20 is configured by a plurality of driving circuits A to H suitable for the plurality of loads 52 to be driven, and the driving circuits A to H can selectively operate independently. The ASIC 1 drives the load 52 in accordance with an operation instruction given from the microcomputer 51 that controls the illustrated load driving system. The operation instruction given from the microcomputer 51 to the ASIC 1 is received by the control circuit 10 of the ASIC 1, and the control circuit 10 controls the operations of the drive circuits A to H of the load driving unit 20 in accordance with the operation instruction, whereby the ASIC 1 The load 52 is driven.

  The microcomputer 51 is an IC equipped with a processing device such as a CPU (Central Processing Unit) or MPU (Micro Processing Unit) and a storage device such as a RAM (Random Access Memory) or ROM (Read Only Memory). For example, the microcomputer 51 and the ASIC 1 are mounted on a circuit board provided in an ECU (Electronic Control Unit) that controls various electronic devices of the vehicle, and are connected to each other by metal wiring or the like.

  The ASIC 1 includes a communication circuit 31 connected to a network provided in the vehicle. The communication circuit 31 is a circuit for causing the microcomputer 51 to have a communication function. The microcomputer 51 does not have a communication function, and when data is transmitted / received to / from other ECUs or electronic devices mounted on the vehicle, communication is performed using the communication circuit 31 mounted on the ASIC 1. Do. The communication circuit 31 can transmit and receive data according to a communication protocol such as CAN (Controller Area Network), for example. When data is received from another ECU or an electronic device, the received data is given to the microcomputer 51. When transmission data is given from the microcomputer 51, this transmission data is transmitted to other ECUs or electronic devices.

  Further, the control circuit 10 of the ASIC 1 can transmit and receive data to and from other devices such as the starter 55 and the vehicle speed sensor 56 connected to the network using the communication circuit 31. The control circuit 10 can acquire various traveling states related to traveling of the vehicle by transmitting and receiving data to and from the starter 55 and the vehicle speed sensor 56.

  The starting device 55 is a device that includes a mounting portion (not shown) for mounting an ignition key possessed by the user, and starts the engine by rotating the mounted ignition key. In addition, the rotation operation of the ignition key by the user includes a start position for starting the engine, an engine on position for maintaining the engine operating state, and an accessory on position for supplying electric power from the battery to the in-vehicle device with the engine stopped. , And a key-off position for stopping power supply from the battery. The control circuit 10 of the ASIC 1 can acquire the rotation operation position of the ignition key as the vehicle state by transmitting and receiving data to and from the starter 55 via the communication circuit 31.

  The vehicle speed sensor 56 is a sensor that detects the traveling speed of the vehicle. The control circuit 10 of the ASIC 1 can acquire the traveling speed of the vehicle from the vehicle speed sensor 56 by communication via the communication circuit 31, and determines whether the vehicle is traveling or stopped from the acquired traveling speed. can do.

  The ASIC 1 is equipped with a power circuit 32, and the power circuit 32 is connected to a battery 53 mounted on the vehicle via a power cable or the like, and power from the battery 53 is supplied. The power supply circuit 32 converts, for example, 12V power supplied from the battery 53 into 5V power, and supplies the converted power to each circuit in the microcomputer 51 and the ASIC 1. In FIG. 1, only the power supply path from the battery 53 to the power supply circuit 32 and the power supply path from the power supply circuit 32 to the microcomputer 51 are shown, and the other power supply paths are not shown.

  Further, the ASIC 1 is equipped with a SW input processing circuit 33. The SW input processing circuit 33 is a circuit that processes user input to various switches disposed on an instrument panel or a door of the vehicle. The microcomputer 51 performs processing such as giving an operation instruction for driving the load 52 to the ASIC 1 according to a switch input by the user. The SW input processing circuit 33 is connected to various switches via cables and the like, performs processing for detecting user input to the switches, and notifies the microcomputer 51 of the detection result.

  For example, when the user operates a switch that locks the door, an input to the switch is detected by the SW input processing circuit 33 and notified to the microcomputer 51. In order to drive a load 52 such as an actuator for locking the door, the microcomputer 51 gives an operation instruction to the ASIC 1 to operate the drive circuits A to H that drive the load 52. The ASIC 1 to which the operation instruction is given operates the drive circuits A to H of the load driving unit 20 corresponding to the operation instruction, so that the corresponding load 52 is driven and the vehicle door is locked.

  Next, details of control of the drive circuits A to H by the control circuit 10 will be described. FIG. 2 is a block diagram showing the configuration of the control circuit 10 of the ASIC 1 according to the present invention. The control circuit 10 includes a control unit 11, a reception unit 12, a storage unit 13, a vehicle state acquisition unit 14, and the like. The vehicle state acquisition unit 14 communicates with the starter 55 and the vehicle speed sensor 56 via the communication circuit 31 to acquire the vehicle state such as the rotation operation position of the ignition key and whether or not the vehicle is running. To do. The vehicle state acquisition unit 14 notifies the control unit 11 of the acquired vehicle state.

  The microcomputer 51 gives a 1-bit digital signal associated with each of the drive circuits A to H to the control circuit 10 as an operation instruction. For example, in the operation instruction signal, the H (high) level of the potential is an instruction to operate the driving circuits A to H, and the L (low) level of the potential is associated with an instruction not to operate the driving circuits A to H. . These plural signals are given to the reception unit 12 of the control circuit 10, and the reception unit 12 detects a change in the level of the signal and notifies the control unit 11.

  The control unit 11 determines whether or not the drive circuits A to H can be operated in response to the notification from the reception unit 12, and outputs a drive signal to each of the drive circuits A to H based on the determination result. The drive signal output from the control unit 11 to each of the drive circuits A to H is a 1-bit digital signal. When the potential of the drive signal is H level, the drive circuits A to H drive the load 52 and L level. In this case, the load 52 is not driven. The control unit 11 determines whether or not the drive circuits A to H are operable based on the vehicle state given from the vehicle state acquisition unit 14 and the operation availability determination table 13 a stored in the storage unit 13.

  The storage unit 13 is composed of a ROM, a rewritable nonvolatile memory element or the like, and stores an operation availability determination table 13a determined in the design stage or the manufacturing stage of the ASIC 1 in advance. FIG. 3 is a schematic diagram illustrating an example of the operation availability determination table 13a. In this example, the current consumption in each circuit when the drive circuit A or B is operated is 300 mA, the current consumption when the drive circuit C is operated is 350 mA, and the drive circuit D or E is The current consumption when operated is 250 mA, the current consumed when the drive circuit F or G is operated is 200 mA, and the current consumed when the drive circuit H is operated is 250 mA. The current consumption allowed in the entire ASIC 1 (the load driving unit 20 thereof) is 1200 mA. Therefore, when all the drive circuits A to H are operated simultaneously, the current consumption is 2100 mA. However, since the allowable current consumption of the ASIC 1 is 1200 mA, all the drive circuits A to H are operated simultaneously. It is not possible.

  The current consumption of each of the drive circuits A to H is acquired in advance by a method such as calculating by simulation during the design of the ASIC 1, or actually measuring with a prototype or mass-produced ASIC 1. Note that the current consumption of each of the drive circuits A to H may be obtained in consideration of the usage environment (temperature, power supply voltage, etc.) of the ASIC 1 under the worst conditions (the environment where the current consumption is the highest). desirable. The current consumption allowed for the entire ASIC 1 can be acquired in advance from the allowable loss of the package of the ASIC 1.

  In this example, the drive circuits A to E may be slow in response, and the drive circuits F to H are required to have fast response. Here, the responsiveness of the drive circuits A to H is a waiting time that is allowed after the drive instruction is given from the microcomputer 51 until the operation of the drive circuits A to H is started. In the illustrated operation availability determination table 13a, the responsiveness of the drive circuits A to H is shown in two stages, “slow” or “fast”. However, the present invention is not limited to this. It is good. Alternatively, a specific time may be set such as an allowable waiting time such as 10 ms, 100 ms, or 500 ms.

  The drive circuits A to C and H are circuits with a short operation time, and the drive circuits D to G are circuits with a long operation time. The circuit having a short operation time is a circuit that receives an operation instruction from the microcomputer 51, operates only for a short time of, for example, several hundred ms, and then stops operation. A circuit having a long operation time receives an operation instruction, operates for a long time of, for example, several thousand ms, or stops, or operates after receiving an operation start instruction from the microcomputer 51 and starting to operate until an operation stop instruction is received. This is a continuous circuit. In the illustrated operation availability determination table 13a, the operation time of the drive circuits A to H is shown in two stages, “short” or “long”. It is good. Alternatively, the operation time may be set to a specific time such as 100 ms, 1000 ms, or 5000 ms.

  The operation availability determination table 13a stores operation combinations that can be selected for each of the four vehicle states of key-off, accessory-on / engine-off, engine-on / stop, and engine-on / running. Note that the key-off state is the state where the ignition key is turned to the key-off position, and the accessory-on / engine-off state is the state where the ignition key is turned to the accessory-on / engine-off position. In this state, the ignition key is turned to the engine-on position and the vehicle running speed is below the predetermined speed. In the engine-on / running state, the ignition key is turned to the engine-on position and the vehicle is running. The speed has exceeded a predetermined speed.

  In this example, the drive circuit A drives an actuator for locking the vehicle door, and the drive circuit B drives an actuator for unlocking the door. It is prohibited to operate the circuits A and B simultaneously. The drive circuit C drives an actuator for automatically opening the trunk of the vehicle and is prohibited from driving while the vehicle is running. The drive circuit D is for lighting the front fog lamp of the vehicle and is prohibited from driving while the engine is stopped. The drive circuits E to G are for lighting the rear fog lamp, the head lamp, and the tail lamp of the vehicle, respectively, and are prohibited from driving when the ignition key is in the key-off position. Further, the drive circuit H is for lighting a hazard lamp of the vehicle, and can be driven in all vehicle states.

  For example, in the illustrated operation propriety determination table 13a, when the vehicle state is key-off, the control circuit 10 is the operation combination 1 that can operate the three circuits of the drive circuits A, C, and H, or the drive circuits B, C, and H. Any one of the operation combinations 2 capable of operating these three circuits can be selected. Regardless of the operation combination 1 or 2, the total current consumption when all three circuits are operated simultaneously is 900 mA, which is within the allowable current consumption 1200 mA for the entire ASIC 1. All three circuits can be started simultaneously.

  When the vehicle state is accessory-on / engine-off, the control circuit 10 operates the operation combination 3 that can operate the six circuits of the drive circuits A, C, and E to H, or the six of the drive circuits B, C, and E to H. Any one of the operation combinations 4 capable of operating the circuit can be selected. Regardless of the operation combination 3 or 4, the total current consumption when all six circuits are operated simultaneously is 1550 mA, which exceeds the allowable current consumption 1200 mA for the entire ASIC 1. For this reason, the control circuit 10 adjusts the operation of each circuit so that the total current consumption of the simultaneously operating circuits is within 1200 mA by appropriately shifting the operation start timing of the six circuits.

  When the vehicle state is engine on / stop, the control circuit 10 is an operation combination 5 that can operate the seven circuits of the drive circuits A and C to H, or an operation combination that can operate the seven circuits of the drive circuits B to H. Any one of 6 can be selected. Regardless of the operation combination 5 or 6, the total current consumption when all seven circuits are operated simultaneously is 1800 mA, which exceeds the allowable current consumption 1200 mA for the entire ASIC 1. For this reason, the control circuit 10 adjusts the operation of each circuit so that the total current consumption of simultaneously operating circuits is within 1200 mA by appropriately shifting the operation start timing of the seven circuits.

  When the vehicle state is engine on / running, the control circuit 10 can select only the operation combination 7 capable of operating the six circuits of the drive circuits A and D to H. In the operation combination 7, the total current consumption when all the six circuits are operated simultaneously is 1450 mA, which exceeds the allowable current consumption of 1200 mA for the entire ASIC 1. For this reason, the control circuit 10 adjusts the operation of each circuit so that the total current consumption of the simultaneously operating circuits is within 1200 mA by appropriately shifting the operation start timing of the six circuits.

  When the control unit 11 of the control circuit 10 receives an operation instruction from the microcomputer 51 by the reception unit 12, the control unit 11 reads the operation availability determination table 13 a from the storage unit 13 and acquires the vehicle state by the vehicle state acquisition unit 14. . The control unit 11 determines whether or not the combination of the driving circuits A to H that are in operation and the driving circuits A to H that need to be newly operated in response to an operation instruction matches the combination according to the vehicle state. Check out. When the operation combination according to the vehicle state is matched, the control unit 11 outputs a drive signal to the drive circuits A to H related to the given operation instruction to operate. At this time, the control unit 11 adjusts the operation start timing of each circuit, and operates each circuit so that the current consumption is within 1200 mA that is allowed for the entire ASIC 1. If the operation combination according to the vehicle state is not met, the control unit 11 returns an error signal to the microcomputer 51 without operating the drive circuits A to H related to the operation instruction. 1 and 2, the error signal return path from the control unit 11 to the microcomputer 51 is not shown.

  For example, when the receiving unit 12 receives an operation instruction for the driving circuit B from the microcomputer 51 when the driving circuits A, F, and G are operating and the vehicle state is accessory on / engine off, the control unit 11 Since the combination of the drive circuits A, B, F, and G does not match the operation combinations 3 and 4 of the operation enable / disable determination table 13a, the drive circuit B is determined to be inoperable and an error signal is returned to the microcomputer 51. .

  Further, for example, when the drive circuits A, F and G are operating and the vehicle state is accessory on / engine off, when the operation instruction for the drive circuit C is received from the microcomputer 51, the control unit 11 Since the combination of A, C, F, and G matches the operation combination 3, the drive circuit C is determined to be operable, and a drive signal is output to the drive circuit C. At this time, the total consumption current when the four circuits of the drive circuits A, C, F, and G are operated is 1050 mA, and does not exceed the allowable consumption current 1200 mA of the entire ASIC 1. The four circuits A, C, F, and G can be started simultaneously.

  Also, for example, when the vehicle state is the engine on / stop, when the operation instruction for the drive circuits A and C to H is received from the microcomputer 51, the control unit 11 changes the combination of the drive circuits A and C to H to the operation combination 5. Since they match, a drive signal is output to these circuits. However, since the total current consumption when all the seven circuits of the drive circuits A and C to H are operated simultaneously is 1800 mA, which exceeds the allowable current consumption 1200 mA for the entire ASIC 1, The operation start timing is adjusted, and a drive signal is output in accordance with each operation start timing.

  FIG. 4 is a schematic diagram illustrating an example of the operation start timing of the drive circuit, and illustrates drive signals supplied from the control circuit 10 to the drive circuits A to H, respectively. Further, this example is a case where an operation instruction for operating the drive circuits A and C to H is given from the microcomputer 51 when the vehicle state is engine on / stop (that is, in the case of the operation combination 5). In the illustrated driving signal output from the control circuit 10, the H level period indicates that the circuit is operating, and the L level period indicates that the circuit is stopped. The control unit 11 of the control circuit 10 receives an operation instruction from the microcomputer 51 and selects one operation combination according to the vehicle state, and then the total current consumption of the circuit to be operated is a current consumption 1200 mA that is permitted for the ASIC 1 as a whole. Is exceeded, the operation start timing of each circuit is determined based on the responsiveness and operation time of each circuit obtained from the operation availability determination table 13a.

The control unit 11 determines the operation start timing of each circuit according to the following rules.
(1) The drive circuit whose response is “fast” and whose operation time is “long” is determined to be the timing for starting the operation with the highest priority (that is, immediately after receiving the operation instruction).
(2) A drive circuit having a response speed of “fast” and an operation time of “short” does not exceed a current consumption of 1200 mA within a predetermined time such as about 100 ms that cannot be recognized by a person. The operation start timing of each circuit is shifted (delayed). The timing for starting the operation earlier than the driving circuit of (1) is determined.
(3) The drive circuit whose response is “slow” and whose operation time is “short” shifts the operation start timing of each circuit so that the consumption current does not exceed 1200 mA. The priority of the operation start is lower than that of the drive circuit (2).
(4) The drive circuit having the response time of “slow” and the operation time of “long” has the lowest priority for the operation start, and starts the operation later than the circuits (1) to (3). Determine the timing.

  For example, when an operation instruction for the drive circuits A and C to H is received from the microcomputer 51 at the time indicated by the solid line arrow (A) in FIG. 4, the control unit 11 first has a responsiveness of “fast”, and The operation start timing of the drive circuits F and G whose operation time is “long” is determined to be the earliest operation start timing. Since the total consumption current of the drive circuits F and G is 400 mA and satisfies the allowable consumption current of 1200 mA, the control unit 11 has “fast” responsiveness and “short” operation time. The drive circuit H is determined to be the earliest timing to start the operation together with the drive circuits F and G. The total current consumption of the drive circuits F to H is 650 mA, which satisfies the allowable current consumption of 1200 mA.

  Here, when the drive circuits A and C whose response is “slow” and whose operation time is “short” are started at the same timing, the total current consumption of the drive circuits A, C and FH Is 1300 mA, which exceeds the allowable current consumption of 1200 mA. Therefore, the control unit 11 delays the operation start timing of either the drive circuit A or C. In the illustrated example, the drive circuit C is delayed, and the total current consumption of the drive circuits A and F to H at this time is 950 mA (see the broken line arrow (a)), which satisfies the allowable current consumption of 1200 mA. .

  Further, the control unit 11 determines the operation start timing of the drive circuit C after the operation of the drive circuits A and / or H is completed. In the illustrated example, the operation start timing of the drive circuit C is after the operation of the drive circuits A and H ends, and the drive circuits C, F, and G operate simultaneously. The total current consumption of the drive circuits C, F and G at this time is 750 mA (see the broken line arrow (b)), which satisfies the allowable current consumption of 1200 mA.

  Further, the control unit 11 determines the operation start timing of the drive circuits D and E whose response time is “slow” and whose operation time is “long”, and the operation ends of the drive circuits A, C and H whose operation time is short. Decide at a later timing. At this time, the drive circuits D to G operate simultaneously, and the total current consumption is 900 mA (see the broken arrow (c)), which satisfies the allowable current consumption of 1200 mA. Thus, the control unit 11 can operate all of the drive circuits A and C to H related to the operation instruction received at the time of the arrow (A).

  Next, when an operation instruction for operating the drive circuits B and H is received from the microcomputer 51 at, for example, the time indicated by the solid arrow (B) (when the drive circuits D to G are operating), first, the control unit 11 The drive circuit H whose response is “fast” and whose operation time is “short” is determined as the earliest timing to start the operation. At this time, the drive circuits D to H operate simultaneously and the total consumption current is 1150 mA (see the broken line arrow (d)), which satisfies the allowable consumption current of 1200 mA.

  Further, the control unit 11 determines the operation start timing of the drive circuit B as the timing after the operation of the drive circuit H ends. At this time, the drive circuits B and D to G operate simultaneously, and the total current consumption is 1200 mA (see the broken arrow (e)), which satisfies the allowable current consumption of 1200 mA. Thus, the control unit 11 can operate the drive circuits B and H related to the operation instruction received at the time of the arrow (B).

  FIG. 5 is a schematic diagram showing another example of the operation availability determination table 13a. In this example, the current consumption in each circuit when the drive circuits I to K are operated is 300 mA, the current consumption when the drive circuit L is operated is 250 mA, and the drive circuit M or N is Each of the current consumption when operated is 200 mA. The current consumption allowed for the entire ASIC 1 (the load driving unit 20 thereof) is 600 mA. Therefore, when all the drive circuits I to N are operated simultaneously, the current consumption is 1550 mA. However, since the allowable current consumption of the entire ASIC 1 is 600 mA, all the drive circuits I to N are operated simultaneously. It is not possible. The drive circuits I to K may be slow in response, and the drive circuits L to N are required to have fast response. The drive circuits I, J, M and N are circuits with a short operation time, and the drive circuits K and L are circuits with a long operation time.

  In addition, the motion availability determination table 13a illustrated in FIG. 5 stores motion combinations that can be selected for the vehicle states of states 1 to 3, respectively. When the vehicle state is state 1, the control circuit 10 can select only the operation combination 1 capable of operating the four circuits of the drive circuits I to L. In the operation combination 1, the total current consumption when all four circuits are operated simultaneously is 1150 mA, which exceeds the allowable current consumption 600 mA for the ASIC 1 as a whole. When the vehicle state is state 2, the control circuit 10 can select the operation combination 2 capable of operating all the drive circuits I to N. In the operation combination 2, the total consumption current when all the six circuits are operated simultaneously is 1550 mA, which exceeds the allowable consumption current of 600 mA for the entire ASIC 1.

  Further, when the vehicle state is state 3, the control circuit 10 is an operation combination 3 capable of operating five circuits of drive circuits I to K, M, and N, or five circuits of drive circuits I, J, and L to N. Any one of the operation combinations 4 capable of operating can be selected. The total current consumption when all five circuits are operated simultaneously in operation combination 3 is 1300 mA, and the total current consumption when all five circuits are operated simultaneously in operation combination 4 is 1250 mA. Even the combination of these operations exceeds the allowable current consumption 600 mA for the entire ASIC 1.

  FIG. 6 is a schematic diagram illustrating another example of the operation start timing of the drive circuit, and illustrates an operation example of the drive circuits I to N of the operation availability determination table 13a illustrated in FIG. Further, in this example, when the vehicle state is the state 2, an operation instruction for operating the drive circuits I to N is given from the microcomputer 51 (that is, in the case of the operation combination 2).

  For example, when the operation instruction of the drive circuits I to N is received from the microcomputer 51 at the time point indicated by the solid line arrow (C) in FIG. 6, the control unit 11 of the control circuit 10 has a response speed of “fast”. In addition, the operation start timing of the drive circuit L whose operation time is “long” is determined to be the earliest operation start timing.

  Next, the control unit 11 determines the operation start timing of the drive circuits M and N whose response is “fast” and whose operation time is “short”. When the three drive circuits L to N are operated simultaneously, the total consumption current is 650 mA, which exceeds the allowable consumption current 600 mA. Therefore, the control unit 11 delays the operation start timing of either the drive circuit M or N. In this example, the operation start timing of the drive circuit N is delayed, but the control unit 11 determines the operation start timing of the drive circuits M and N so that the time Ta for delaying the drive circuit N does not exceed a predetermined time. The predetermined time, which is the maximum value of the time Ta, is set in advance to a time of about 100 ms that cannot be recognized by humans. At this time, the total current consumption when the drive circuits L and M are operated simultaneously is 450 mA (see the broken line arrow (g)), and after the operation of the drive circuit M is completed, the drive circuits L and N are operated simultaneously. In this case, the total current consumption is 450 mA (see the broken arrow (h)), and in both cases, the allowable current consumption of 600 mA is satisfied.

  Next, the control unit 11 determines the operation start timing of the drive circuits I and J whose responsiveness is “slow” and whose operation time is “short”. The total current consumption when the drive circuits L and N and the drive circuit I or J are simultaneously operated is 750 mA, which exceeds the allowable current consumption of 600 mA. The total current consumption when the drive circuit L and the drive circuits I and J are simultaneously operated is 850 mA, which exceeds the allowable current consumption of 600 mA. Therefore, the control unit 11 determines the operation start timing so that either the drive circuit I or J starts operating after the operation of the drive circuit N ends. In this example, the control unit 11 delays the operation start timing of the drive circuit J. At this time, the total current consumption when the drive circuits L and I are simultaneously operated is 550 mA (see the broken line arrow (i)), and after the operation of the drive circuit I is completed, the drive circuits L and J are simultaneously operated. In this case, the total current consumption is 550 mA (see the broken line arrow (j)), and in both cases, the allowable current consumption 600 mA is satisfied.

  Next, the control unit 11 determines the operation start timing of the drive circuit K whose response is “slow” and whose operation time is “long”. When the drive circuits L and J and the drive circuit K are operated simultaneously, the total current consumption is 850 mA, which exceeds the allowable current consumption of 600 mA. Therefore, the control unit 11 determines the operation start timing so that the drive circuit K starts operating after the operation of the drive circuit J ends. At this time, the total current consumption when the drive circuits L and K are operated simultaneously is 550 mA (see the broken line arrow (k)), which satisfies the allowable current consumption of 600 mA. As a result, the control unit 11 can operate the drive circuits I to J related to the operation instruction received at the time of the arrow (C) without exceeding the allowable current consumption of 600 mA.

  7 and 8 are flowcharts showing the procedure of the operation timing determination process of the drive circuit performed by the ASIC 1 according to the present invention, which is a process performed by the control unit 11 provided in the control circuit 10 of the ASIC 1. Also, the variables i and n used in the illustrated process are secured in a storage area such as a register or a memory provided in the control unit 11. First, the control unit 11 checks whether or not the operation instruction of the drive circuit from the microcomputer 51 has been received by the reception unit 12 (step S1), and if not received (S1: NO), until the operation instruction is received. stand by.

  When the operation instruction is received (S1: YES), the control unit 11 acquires the vehicle state obtained from the starting device 55, the vehicle speed sensor 56, and the like in the vehicle state acquisition unit 14 (step S2), and stores in the storage unit 13. The stored operation availability determination table 13a is read (step S3). The control unit 11 selects one operation combination from the read operation availability determination table 13a based on the drive circuit related to the received operation instruction and the acquired vehicle state (step S4). Although illustration is omitted, if the operation combination suitable for the operation circuit and the vehicle state does not exist in the operation determination table 13a, the control unit 11 returns an error signal to the microcomputer 51 for processing. finish.

  The control unit 11 that has selected one operation combination acquires the responsiveness of each drive circuit included in the operation combination (step S5), acquires the operation time (step S6), and acquires the current consumption (step S7). ). The control unit 11 calculates the total current consumption of the drive circuits included in the selected operation combination, and checks whether the total current consumption exceeds the allowable current consumption of the ASIC 1 (step S8). When the total current consumption exceeds the allowable current consumption (S8: YES), the control unit 11 performs a circuit determination process for determining the type of each drive circuit included in the operation combination (step S9).

  FIG. 9 is a flowchart showing the procedure of the circuit determination process performed by the ASIC 1 according to the present invention, and is the process performed in step S9 of the flowcharts shown in FIGS. First, the control unit 11 selects one circuit (drive circuit) included in the operation combination (step S31), and checks whether or not the response of the selected circuit is “fast” (step S32). When the response of the selected circuit is “fast” (S32: YES), the control unit 11 further checks whether or not the operation time of this circuit is “long” (step S33). When the operation time of the selected circuit is “long” (S33: YES), the control unit 11 determines that this circuit is the “first circuit” (step S35), and the operation time of the selected circuit. If it is not “long” (S33: NO), it is determined that this circuit is the “second circuit” (step S36).

  When the response of the selected circuit is not “fast” (S32: NO), the control unit 11 further checks whether the operation time of this circuit is “long” (step S34). When the operation time of the selected circuit is not “long” (S34: NO), the control unit 11 determines that this circuit is the “third circuit” (step S37) and the operation time of the selected circuit. If it is “long” (S34: YES), it is determined that this circuit is the “fourth circuit” (step S38). That is, the control unit 11 determines that the drive circuit having a fast response and a long operation time is the first circuit, determines that the drive circuit having the quick response and the short operation time is the second circuit, and has a slow response and A drive circuit having a short operation time is determined as the third circuit, and a drive circuit having a slow response and a long operation time is determined as the fourth circuit.

  The control unit 11 that has determined the circuits in steps S35 to S38 checks whether or not the determination has been completed for all the circuits included in the operation combination (step S39). S39: NO), the process returns to step S31, and the above-described processing is repeated for other circuits included in the operation combination. When the determination is completed for all the circuits (S39: YES), the control unit 11 ends the circuit determination processing and returns to the processing of the flowcharts shown in FIGS.

  The control unit 11 that has performed the circuit determination process in step S9 proceeds to the process of step S11. When the total current consumption does not exceed the allowable current consumption in step S8 (S8: NO), the control unit 11 determines that all the drive circuits included in the operation combination are “first circuits” (step S10). ), The process proceeds to step S11.

  The control unit 11 initializes the value of the variable n to 1 (step S11), and determines the operation start timing of the drive circuit determined to be the first circuit as the nth operation start timing for starting the nth operation ( Step S12). That is, the operation start timing of the first circuit is determined as the first operation start timing at which the operation starts first. Next, the control unit 11 sets the value of the variable i to 2 (step S13), and determines the operation start timing of the i-th circuit that determines the operation start timing of the drive circuit determined to be the i-th circuit (second circuit). Processing is performed (step S14).

  FIG. 10 is a flowchart showing a procedure of the operation start timing determination process of the i-th circuit performed by the ASIC 1 according to the present invention, and is a process performed in steps S14, S17, and S20 of the flowcharts shown in FIGS. is there. First, the control unit 11 selects one i-th circuit from a plurality of circuits determined to be the i-th circuit (step S51). Next, the control unit 11 calculates a total current consumption obtained by adding the current consumption of the selected i-th circuit to the total current consumption of the circuit already determined to start operation at the n-th operation start timing (step S52). It is checked whether or not the total consumption current exceeds the allowable consumption current of the ASIC 1 (step S53).

  When the calculated total consumption current exceeds the allowable consumption current (S53: YES), the control unit 11 adds 1 to the value of the variable n (step S54), and the calculated total consumption current exceeds the allowable consumption current. If not (S53: NO), the process proceeds to step S55 without changing the value of the variable n. Here, the variable n indicates the order of the operation start timing, and the n-th operation start timing indicates that it is the n-th operation start timing after receiving the operation instruction.

  The control unit 11 determines the operation start timing of the i-th circuit selected in step S51 as the n-th operation start timing (step S55). Next, the control unit 11 checks whether or not the operation start timing has been determined for all the i-th circuits (step S56). If all the circuits have not been determined (S56: NO), Returning to S51, the above process is repeated for all i-th circuits. When the process is completed for all the circuits (S56: YES), the control unit 11 ends the operation start timing determination process and returns to the process of the flowcharts shown in FIGS.

  After completing the operation start timing determination process for the i-th circuit (second circuit) in step S14, the control unit 11 determines the operation start timings of the respective circuits already determined as the first and second circuits as the first to n-th operations. The start timing is determined. Since the second circuit is a fast responsive circuit, it is desirable that the n-th operation start timing, which is the last operation start timing of the second circuit, is within a predetermined time after the drive instruction from the microcomputer 51 is received. Therefore, the control unit 11 adjusts the operation start timing of the i-th circuit (second circuit) so that the time until the n-th operation start timing is within a predetermined time (step S15).

  Next, the control unit 11 sets the value of the variable i to 3 (step S16), and determines the operation start timing of the i-th circuit that determines the operation start timing of the drive circuit determined to be the i-th circuit (third circuit). (See step S17, FIG. 10). After completing this process, the control unit 11 adds 1 to the value of the variable n (step S18), sets the value of the variable i to 4 (step S19), and is determined as the i-th circuit (fourth circuit). The operation start timing determination process of the i-th circuit that determines the operation start timing of the drive circuit is performed (see step S20, FIG. 10), and the operation timing determination process is ended.

  Note that by adding 1 to the value of the variable n in step S18, the operation start timing of the drive circuit determined to be the third circuit and the drive circuit determined to be the fourth circuit can be shifted. However, this process is not necessarily required. If the operation start timing of the last drive circuit of the third circuit may be the same as the operation start timing of the first drive circuit of the fourth circuit, the process of step S18 Processing may be omitted.

  Through the above processing, the control unit 11 can determine the operation start timing for all the drive circuits of the first circuit to the fourth circuit. For example, in the case of the drive circuits A to H shown in FIG. 4, the drive circuits F and G determined as the first circuit, the drive circuit H determined as the second circuit, and the drive circuit A determined as the third circuit Is determined as the first operation start timing, and the operation starts at the earliest timing. The drive circuit C determined as the third circuit is determined at the second operation start timing, and starts operating at the timing after the operations of the drive circuits H and A are completed. Further, the drive circuits D and E determined to be the fourth circuit are determined at the third operation start timing, and the operation starts at the timing after the operation of the drive circuit C of the third circuit is completed.

  In the case of the drive circuits I to N shown in FIG. 6, the drive circuit L determined to be the first circuit and the drive circuit M determined to be the second circuit are determined as the first operation start timing. The operation has started at an early timing. The drive circuit N determined to be the second circuit is determined at the second operation start timing, starts operating at the timing after the operation of the drive circuit M is completed, and receives an operation instruction from the microcomputer 51. The operation has started within a predetermined time. The drive circuit I determined to be the third circuit is determined at the third operation start timing, and starts operating at the timing after the operation of the drive circuit N is completed. The drive circuit J determined to be the third circuit is determined at the fourth operation start timing, and starts operating at the timing after the operation of the drive circuit I ends. The drive circuit K determined as the fourth circuit is determined at the fifth operation start timing, and starts operating at the timing after the operation of the drive circuit J of the third circuit is completed.

  In the ASIC 1 configured as described above, a combination of drive circuits that are operated in parallel in the operation determination table 13a is stored in advance in association with the vehicle state, and when an operation instruction from the microcomputer 51 is received, the vehicle state and operation The operation start timing of each drive circuit is determined according to the combination, the current consumption of each drive circuit, the current consumption allowed by the ASIC 1, the response (waiting time) of each drive circuit, and the operation time of each circuit. Thus, the control unit 11 of the control circuit 10 can appropriately determine the operation start timings of the plurality of drive circuits. As a result, the number of drive circuits that operate simultaneously can be reduced without causing problems in the operation of each drive circuit, and the overall power consumption of the ASIC 1 can be reduced. Therefore, the ASIC 1 can operate a large number of drive circuits mounted without exceeding the total allowable power consumption, and a large number of circuits can be integrated into one chip without exceeding the allowable loss of the package. Therefore, it is possible to reduce the size and cost of the system that drives the load 52.

  In the present embodiment, a system for driving a load 52 such as a motor or an actuator mounted on the vehicle has been described as an example. However, the present invention is not limited to this, and other than the load 52 mounted on the vehicle. The present invention may be applied to a system that drives a load. Further, although the circuit that controls the operation of the control circuit 10 is a drive circuit, the circuit is not limited to this, and the operation of other circuits such as the communication circuit 31, the power supply circuit 32, and the SW input processing circuit 33 shown in FIG. It is also possible to control the operation of other circuits such as a constant current circuit, a constant voltage circuit, an oscillation circuit, an amplifier circuit or various digital circuits (not shown).

  Further, the operation instruction is given from the microcomputer 51 to the control circuit 10 for each of the drive circuits A to E. However, the present invention is not limited to this. For example, the operation instruction is given from the microcomputer 51 to the control circuit 10 in the form of command input or the like. For example, the operation instruction may be given by other methods. 1 includes the communication circuit 31, the power supply circuit 32, the SW input processing circuit 33, and the like. However, the ASIC 1 is not limited thereto, and may be configured not to include these circuits. A configuration in which other circuits are further mounted may be used.

  Further, in the operation availability determination table 13a shown in FIG. 3, the vehicle state is set to key off, accessory on / engine off, engine on / stop, and engine on / running. Absent. Further, although the vehicle state acquisition unit 14 acquires the vehicle state based on the rotation operation position of the ignition key and the traveling speed of the vehicle, the present invention is not limited to this. For example, when a switch for switching lighting control such as a head lamp and a tail lamp is mounted on the vehicle, and the manual lighting or automatic lighting of the lamp can be switched by the switch, the vehicle state based on the switching position of the switch is changed to the vehicle. The state acquisition part 14 may acquire. When the lamp is automatically turned on, a sensor that detects ambient brightness and the like is mounted on the vehicle, but the vehicle state acquisition unit 14 may further acquire the vehicle state based on the detection result of the sensor. Further, for example, the vehicle state acquisition unit 14 may acquire a vehicle state based on an operation state of a switch that lights interior lights such as a room lamp and a courtesy lamp. By combining the operation states of the plurality of switches and the detection results of the sensors, various vehicle states can be acquired and circuit control can be performed.

  Further, the drive target of the drive circuits A to H shown in FIG. 3 is an example and is not limited to this. Moreover, the operation availability determination table 13a shown in FIGS. 3 and 5 is an example, and is not limited to this. What is necessary is just to set the operation | movement combination of the operation | movement availability determination table 13a suitably according to the consumption current which ASIC1 accept | permits, the function of a vehicle, etc. Moreover, the timing shown in FIG.4 and FIG.6 is an example, Comprising: It does not restrict to this.

It is a block diagram which shows the structure of the load drive system using the circuit apparatus which concerns on this invention. It is a block diagram which shows the structure of the control circuit of ASIC which concerns on this invention. It is a schematic diagram which shows an example of an operation availability determination table. It is a schematic diagram which shows an example of the operation start timing of a drive circuit. It is a schematic diagram which shows the other example of an operation availability determination table. It is a schematic diagram which shows the other example of the operation start timing of a drive circuit. It is a flowchart which shows the procedure of the operation timing determination process of the drive circuit which ASIC concerning this invention performs. It is a flowchart which shows the procedure of the operation timing determination process of the drive circuit which ASIC concerning this invention performs. It is a flowchart which shows the procedure of the circuit determination process which ASIC which concerns on this invention performs. It is a flowchart which shows the procedure of the operation start timing determination process of the i-th circuit which ASIC concerning this invention performs.

Explanation of symbols

1 ASIC (circuit equipment)
10 control circuit 11 control unit (operation start timing determining means, circuit operation control means)
12 Reception part (reception means)
13 Storage unit (storage means)
13a Operation availability determination table 14 Vehicle state acquisition unit (vehicle state acquisition means)
DESCRIPTION OF SYMBOLS 20 Load drive part 31 Communication circuit 32 Power supply circuit 33 SW input processing circuit 51 Microcomputer 52 Load 53 Battery 55 Starter 56 Vehicle speed sensor A-N Drive circuit (circuit)

Claims (7)

In a circuit device including a plurality of circuits that can be selectively operated,
Accepting means for accepting external operation instructions for each circuit;
A storage means for storing a combination of circuits to be operated in parallel, an amount of electricity consumed by each circuit, a waiting time of each circuit from reception of an operation instruction by the reception means to an operation start, and an operation time for each circuit to operate,
An operation for determining the operation start timing of the circuit according to the operation instruction received by the receiving unit based on the combination, the amount of electricity consumed, the waiting time and the operating time stored in the storage unit, and the total amount of consumed electricity allowed. Start timing determination means;
A circuit device comprising: circuit operation control means for starting operation of each circuit in accordance with the operation start timing determined by the operation start timing determination means. In a circuit device including a plurality of circuits that are mounted on a vehicle and can be selectively operated,
Vehicle state acquisition means for acquiring a vehicle state relating to travel of the vehicle;
Accepting means for accepting external operation instructions for each circuit;
Stores the combination of circuits that operate in parallel according to the vehicle state, the amount of electricity consumed by each circuit, the waiting time of each circuit from the reception of an operation instruction by the receiving means to the start of operation, and the operating time for which each circuit operates. Storage means
The operation instruction received by the receiving means based on the vehicle state acquired by the vehicle state acquisition means, the combination stored by the storage means, the amount of electricity consumed, the waiting time and the operating time, and the total amount of electricity consumed allowed. Operation start timing determining means for determining the operation start timing of the circuit according to
A circuit device comprising: circuit operation control means for starting operation of each circuit in accordance with the operation start timing determined by the operation start timing determination means. The operation start timing determining unit is configured to cause the total amount of electricity consumed by simultaneously operating circuits to exceed the predetermined amount of electricity when the total amount of electricity consumed by a plurality of circuits included in the combination exceeds a predetermined amount of electricity. The circuit device according to claim 1 or 2, wherein the operation start timing of each circuit is shifted so as not to occur. 2. The operation start timing determining means determines an operation start timing of each circuit so that a circuit with a short waiting time and a long operation time is preferentially started. The circuit device according to claim 3. The operation start timing determining means determines an operation start timing of each circuit so that a circuit having a short waiting time and a short operation time is started within a predetermined time after the receiving means receives the operation instruction. 5. The circuit device according to claim 1, wherein the circuit device is configured as follows. 2. The operation start timing determining means determines the operation start timing of each circuit so that a plurality of circuits having a long waiting time and a short operation time do not operate simultaneously. The circuit device according to claim 5. The operation start timing determining means determines the operation start timing of each circuit so that a circuit having a long waiting time and a long operation time is started later than other circuits. The circuit device according to any one of claims 1 to 6.

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