JP5179923B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to an anomaly detection technique in a semiconductor integrated circuit device, in particular, a semiconductor integrated circuit device including a storage unit that can store information.

  A microcomputer that is an example of a semiconductor integrated circuit device has a function that eliminates factors that cause memory errors (detectors such as abnormal voltage, abnormal frequency, and abnormal temperature), or a function that prevents chip malfunction after a memory error occurs. (Illegal access detection, undefined instruction detection, etc.) are installed. Memory error countermeasures include hardware countermeasures and software countermeasures.

(1) Memory error countermeasures by hardware As a countermeasure to prevent memory errors, a circuit that detects abnormal voltage, abnormal voltage application, abnormal temperature, laser irradiation, etc. is provided. Further, as a measure for preventing a malfunction of the chip when a memory error occurs during instruction fetch, a circuit for monitoring memory access by an FMU (Firewall Management Unit) and normal execution of a program by a WDT (Watch Dog Timer) is provided. Further, an illegal instruction detection function that detects when the instruction code is not defined and an address error detection circuit that detects access to an undefined address are provided.

(2) Countermeasures for memory errors by software If memory access is not performed normally, the data will be incorrect when data is read. In addition, when instruction fetch at the time of program execution is not normally performed, various chip malfunctions due to changes in instruction codes are assumed. Therefore, as a software measure, it is recommended to check the validity of read data such as a checksum when reading important data such as an encryption key. It is also recommended to take measures to prevent deviations from the regular program flow due to instruction code changes, and to restrict access areas within the program.

  Patent Document 1 discloses a storage device equipped with a security function, a host device into which the storage device can be inserted, and a host device provided with the storage device, particularly a memory card having a flash memory chip and a controller, and a memory card thereof. An information processing apparatus that can be inserted and a security processing technique in the information processing apparatus including the memory card are described.

JP 2004-104539 A

  The inventors of the present application have examined the memory error countermeasures by the hardware and the memory errors countermeasures by the software, and the following problems have been found.

(1) Issues related to countermeasures for memory errors caused by hardware Microcomputers (called “security microcomputers”) that are optimal for security-sensitive fields include hardware that prevents memory errors before they occur, and chips after memory errors occur. Hardware that prevents malfunctions is installed, but at present, it cannot be prevented 100%. For example, for a laser attack, it is difficult to detect local irradiation even if a detector is mounted. In addition, the illegal instruction detection function and undefined address detection function cannot be detected if the fetched instruction or address is altered due to a memory error and cannot be detected. Will be executed.

  A technique using a parity bit is known as a memory error countermeasure. The parity bit is, for example, a 1-bit parity calculated for 8-bit data, written to the memory as a total of 9 bits, and a parity check is performed at the time of reading. However, in the case of parity check, it is possible to detect odd-bit data anomalies, but even-bit data anomalies may not be detected, so the detection rate is low.

(2) Issues in measures against memory errors by software Various measures against software are recommended as measures against memory errors. However, the measures taken by software decrease the execution performance, increase the program area, or increase the software development burden on the customer. In addition, there is no guarantee that malfunctions can be prevented 100% by measures against memory errors by software.

  An object of the present invention is to provide a technique for improving the detection rate of a memory error caused by an attack.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A representative one of the inventions disclosed in the present application will be briefly described as follows.

  That is, a storage unit that can store information is provided. The storage unit includes a memory mat and a first abnormality detection circuit for forming an error signal. The memory mat includes a first abnormality detection line and a second abnormality detection line that can output information used for determination by the first abnormality detection circuit when information is read from the memory mat. A first memory cell for setting the first abnormality detection line to a logical value “0” is coupled to the first abnormality detection line, and the second abnormality detection power line is connected to the second abnormality detection line. The second memory cells for setting the detection line to the logical value “1” are coupled. When the logical value of the abnormality detection line cannot be obtained correctly, an error signal is asserted to improve the memory error detection rate.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, it is possible to improve the detection rate of memory errors caused by attacks.

1. Representative Embodiment First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals of the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor integrated circuit device (120) according to a representative embodiment of the present invention includes a storage unit (123) capable of storing information. The storage unit forms an error signal by determining whether or not information reading from the memory mat is normal, and a memory mat (33) in which a plurality of memory cells each capable of storing information are arranged. And a first abnormality detection circuit (36). The memory mat includes a first abnormality detection line (RL0) and a second abnormality detection line (in which information used for determination by the first abnormality detection circuit can be output when information is read from the memory mat. RL1). The first abnormality detection line (RL0) is coupled to a first memory cell for setting the first abnormality detection line to a logical value “0”, and is connected to the second abnormality detection line (RL1). Are coupled to the second memory cell for setting the second abnormality detection line to the logical value “1”.

  [2] The first abnormality detection line and the second abnormality detection line can be arranged at an end of the memory mat.

  [3] The first abnormality detection line or the second abnormality detection line can be arranged for each of a plurality of bits in the memory mat.

  [4] The first abnormality detection circuit includes a first determination circuit (25) for determining whether or not a logical value of a signal obtained from the first abnormality detection line is as expected, and A second determination circuit (27) for determining whether or not the logical value of the signal obtained from the second abnormality detection line is as expected can be configured.

  [5] The memory unit includes a row decoder (31) for decoding an input address signal, and a first decoder for driving a word line included in the memory mat based on an output signal of the row decoder. 1 driver (71) and a second abnormality detection circuit (81, 82, 83) for comparing the input-side logic level and the output-side logic level of the first driver to form an error signal are provided. be able to.

  [6] The memory unit compares the operation power supply voltage formed by the power supply circuit (102) for forming the operation power supply voltage of the main part of the memory unit with a predetermined reference voltage. And a third abnormality detection circuit (113, 114) for forming an error signal.

  [7] The semiconductor integrated circuit device may further include a CPU (125) capable of accessing the memory unit and a system controller (124) capable of controlling the operation of the CPU based on the error signal. it can.

2. Next, the embodiment will be described in more detail.

<Embodiment 1>
FIG. 12 shows an IC card microcomputer as an example of a semiconductor integrated circuit device according to the present invention.

  The IC card microcomputer 120 shown in FIG. 12 includes, but is not limited to, a port (PORT) 122, a memory 123, a system controller 124, a CPU (central processing unit) 125, and modules 126, 127, and 128. Are coupled by a bus 129. The IC card microcomputer 120 is not particularly limited, but is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

  The CPU 125 performs a predetermined calculation process by executing a preset program. The memory 123 is a mask ROM (Read Only Memory) in which a program executed by the CPU 125 is stored, an EEPROM (Electrically Erasable and Programmable Read Only Memory), or the like. Although not shown, a RAM (Random Access Memory) used as a work area for the CPU may be included. When a memory error is detected in the memory 123, the error detection result (ERR) is transmitted to the system controller 124. A reset terminal 121 is coupled to the port 122. When the reset terminal 121 is set to a low level, for example, the terminal reset signal RST1 is asserted via the port 122. The system controller 124 generates an internal reset signal RST2 and an NMI (Non-Maskable Interrupt) signal that is an interrupt signal. The internal reset signal RST2 is supplied to the memory 123, the CPU 125, and the modules 126 to 128. The NMI signal is supplied to the CPU 125.

  When a memory error is detected, it is assumed that an attack is being performed for some reason. In such a case, it is necessary to immediately stop the current processing and protect the chip operation. Therefore, when a memory error is detected, the system controller 124 immediately asserts an internal reset signal, thereby transitioning the system to the reset state and stopping the subsequent processing. Note that the chip operation may be protected by generating an NMI interrupt to the CPU 125 and making a transition to a predetermined interrupt process. When the internal reset signal is asserted by the system controller 124, the state (reset state) is held. In order to resume the system operation, a reset instruction from the reset terminal 121 or initialization by turning on the system power again is required.

  Next, the detailed configuration of each part will be described.

  FIG. 1 shows a configuration example of the memory 123.

  As shown in FIG. 1, the memory 123 includes a row decoder 31, a column decoder 32, a column selection circuit 34, a sense amplifier circuit 35, and a memory mat 33. The memory mat 33 includes a plurality of word lines WL and a plurality of bit lines arranged so as to intersect with the word lines WL. Eight bit lines are provided for each byte of the memory mat 33. The row decoder 31 decodes the input address signal and forms a selection signal for selecting one word line from the plurality of word lines WL. The column decoder 32 decodes the input address signal to form a column selection signal. The column selection circuit 34 selects a bit line based on the column selection signal. The signal of the selected bit line is amplified by the sense amplifier circuit 35 and then output to the bus 129 via the output circuit 38 (OUT). In addition, an abnormality detection circuit 36 is provided, and this abnormality detection circuit 36 determines whether or not information reading from the memory mat is normal and generates an error signal ERR. If the information reading from the memory mat is not normal, the error signal ERR is asserted. Further, a controller 37 is provided, and this controller 37 controls the overall operation of the memory 123.

  The memory mat 33 is provided with two abnormality detection lines RL0 and RL1 separately from normal bit lines. The two abnormality detection lines RL0 and RL1 are arranged at the right end in FIG. The abnormality detection line RL0 is provided for detecting an abnormality of a logical value “0”, and a logical value “0” is obtained. The abnormality detection line RL1 is provided for detecting an abnormality of the logical value “1”, and a logical value “1” is obtained. During the read operation of the memory 123, the signals of the abnormality detection lines RL0 and RL1 are always selected by the column selection circuit 34, and the abnormality value can be detected by the abnormality detection circuit 36. If the logical value “0” of the abnormality detection line RL0 and the logical value “1” of the abnormality detection line RL1 are obtained correctly, it is determined that the memory 123 is operating normally. However, if the logical value “0” of the abnormality detection line RL0 or the logical value “1” of the detection line RL1 cannot be obtained correctly, it is determined that the operation is abnormal, and the error signal ERR is asserted.

  Here, as shown in FIG. 1, in the configuration in which the abnormality detection lines RL0 and RL1 are arranged at the end of the memory mat 33, an attack (abnormal voltage, abnormal frequency application or abnormality that affects the entire memory mat 33). (Operation at temperature) is effective. However, it is conceivable that a local attack that causes a malfunction of a partial area on the memory mat, such as laser irradiation, cannot be detected. Therefore, in order to cope with a local attack, as shown in FIG. 2, apart from the abnormality detection lines RL0 and RL1 at the end of the memory mat 33, every several bits of the memory mat 33, for example, 1 byte ( It is desirable to arrange the abnormality detection lines RL0 and RL1 for each byte. In this way, since a large number of abnormality detection lines RL0 and RL1 are densely arranged in the memory mat 33, it is possible to sufficiently cope with a local attack of the memory mat 33.

  As shown in FIG. 2, if the abnormality detection lines RL0 and RL1 are densely arranged in the memory mat 33, the area and current consumption of the memory mat 33 increase accordingly, and thus the required security level. It is desirable to determine the number of abnormality detection lines RL0 and RL1 according to the characteristics of the memory. The characteristic of the memory is that, for example, a change in read data due to an attack occurs only from a logical value “0” to a logical value “1” or a logical value “1” to a logical value “0” opposite to the logical value “0”. If it is clear that this is the case, only one of the logical value “0” or the logical value “1” is sufficient as the abnormality detection line to be arranged. For example, it is considered effective that the abnormality detection lines RL0 and RL1 at the end of the memory mat 33 are provided as they are, and only one of the abnormality detection lines RL0 and RL1 is provided for every several bits of the memory mat 33. It is done. For example, if a memory cell with a potential holding state of “1” is irradiated with a laser, the read data changes from “1” to “0” if the bit line is not discharged but it is discharged due to a malfunction. End up. When the data garbled by laser irradiation is the main “0”, the attack detection efficiency by laser irradiation can be improved by providing a larger number of RL1 than the number of RL0. On the other hand, if the memory cell in which the potential holding state is “0” is changed to “1” (which should be discharged but not discharged) is the main data change, it is effective to provide a larger number of RL0.

  Next, the formation of the abnormality detection lines RL0 and RL1 will be described.

  When the memory 123 is a mask ROM, the abnormality detection lines RL0 and RL1 can be formed by an implantation method or a via method.

  For example, in the case of the implantation method, as shown in FIG. 3A, the logic value “0” is written to all the memory cells MC coupled to the abnormality detection line RL0 by ion implantation. All the memory cells MC coupled to the abnormality detection line RL1 may be written with a logical value “1” by non-ion implantation. Further, in the case of the via method, as shown in FIG. 3B, all the memory cells MC coupled to the abnormality detection line RL0 are coupled to the low potential side power supply VSS line, so that Writing the value “0” and writing the logical value “1” to all the memory cells MC coupled to the abnormality detection line RL1 by omitting wiring to the low potential side power supply VSS line. Just do it. In any case, the normal bit line BL that is the object of data retention has a common abnormality detection line and word line, and any data of “0” or “1” is stored in each memory cell MC. It is configured to be able to hold.

  When the memory 123 is an EEPROM, as shown in FIG. 4, the abnormality detection line RL0 may be written with a logical value “0” to all the memory cells MC coupled thereto. In the abnormality detection line RL1, all the memory cells MC coupled thereto may be left erased (logical value “1”). Although not shown, as in FIG. 3, the normal bit line in FIG. 4 has a common abnormality detection line and word line, and each memory cell MC has an arbitrary value of “0” or “1”. It is configured to be able to hold data.

  FIG. 5 shows a more detailed configuration of the abnormality detection circuit 36 in FIG. 1 and FIG. 2 and its surroundings.

  As shown in FIG. 5, a transfer gate 301 and an inverter 302 are provided for each abnormality detection line RL0. The transfer gate 301 is formed by connecting a p-channel MOS transistor and an n-channel MOS transistor in parallel. The transfer gate 301 is ON / OFF controlled by a column selection signal SEL from the column decoder 32. Inverting the column selection signal SEL by the inverter 302 is performed to simultaneously turn on or off the p-channel MOS transistor and the n-channel MOS transistor constituting the transfer gate 301. The transfer gate 301 and the inverter 302 are part of the column selection circuit 34 in FIG. An n-channel MOS transistor 24 whose operation is controlled by a read signal RED is provided, and a signal transmission line between the transfer gate 301 and the n-channel MOS transistor 24 is connected to a high potential according to a precharge signal CHG. A p-channel MOS transistor 23 for precharging to the side power supply Vdd level is provided. The precharge signal CHG and the read signal RED are generated by the controller 37. The reason why the n-channel MOS transistor 24 is provided and the operation of the n-channel MOS transistor 24 is controlled by the read signal RED is that the abnormality detection only needs to be performed during the read operation. The sense amplifier SA amplifies the signal transmitted via the n-channel MOS transistor 24 and is a part of the sense amplifier circuit 35 shown in FIG. The output signal of the sense amplifier SA is transmitted to the abnormality detection circuit 36. The abnormality detection circuit 36 includes OR circuits 25 and 26, a NAND circuit 27, and a flip-flop circuit (FF) 28. The output signal of the sense amplifier SA is transmitted to one input terminal in the OR circuit 25. The output signal of the sense amplifier corresponding to the other abnormality detection line RL0 is transmitted to the other input terminal in the OR circuit 25. That is, the OR circuit 25 obtains the OR logic of the output signals of the sense amplifiers corresponding to all the abnormality detection lines RL0 in the memory mat 33, so that whether or not the logic value of the input signal is as expected. A determination is made. For example, when all of the output signals of the sense amplifiers corresponding to all of the abnormality detection lines RL0 arranged in the memory mat 33 are set to the low level, it is as expected, and the output signal of the OR circuit 25 is Low level. However, if the logical value “0” cannot be read from at least one of all abnormality detection lines RL0 in the memory mat 33 due to the attack on the memory mat 33, it is different from the expected value. The output signal of the OR circuit 25 is set to a high level. The output of the OR circuit 25 is transmitted to the set terminal S of the flip-flop circuit 28 and held in the flip-flop circuit 28. Although the output of the OR circuit 25 is normally at a low level, when the output of the OR circuit 25 is at a high level, the error signal ERR is asserted to a high level by the flip-flop circuit 28. The flip-flop circuit 28 has a reset terminal R. By asserting a reset signal supplied to the reset terminal R, the flip-flop circuit 28 can be initialized.

  Although omitted in FIG. 5, the circuit corresponding to the abnormality detection line RL1 can be configured similarly to the circuit corresponding to the abnormality detection line RL0. However, the output signals of the sense amplifiers SA corresponding to all the abnormality detection lines RL1 are transmitted to the NAND circuit 27, where NAND logic is obtained, and whether or not the logic value of the input signal is as expected. Is determined. In this case, if the logical value “1” cannot be read from at least one of all abnormality detection lines RL1 in the memory mat 33 due to the attack on the memory mat 33, the output signal of the NAND circuit 27 Is held at the flip-flop circuit 28 via the OR circuit 26, and the error signal ERR is asserted to the high level.

  Next, a technique for improving the detection sensitivity of the abnormality detection lines RL0 and RL1 will be described.

  If the configuration of the abnormality detection line is the same as the normal memory area, an error will occur in the normal data storage area even though the logical value of the abnormality detection line is normal due to process variations and biased influences of attack. It can also occur. For this reason, it is conceivable that the characteristics of the abnormality detection line are made bad (error is likely to occur) in advance. For example, as shown in FIG. 6, by adjusting the driving capability of the MOS transistors constituting the memory cell, the precharge capability of the abnormality detection lines RL0 and RL1 is changed to a bit line for holding arbitrary data in the memory mat 33. It is good to make it lower than the precharge ability of BL. In addition, by adjusting the driving capability of the precharge MOS transistor 61 corresponding to the bit line BL and the precharge MOS transistor 23 corresponding to the abnormality detection lines RL0 and RL1, it is coupled to the abnormality detection lines RL0 and RL1. It is preferable that the discharge capacity of the memory cell MC formed is lower than the discharge capacity of the memory cell MC coupled to the bit line BL in the memory mat 33. In this way, appropriate abnormality detection can be performed regardless of process variations and biased influences of attacks.

  According to the above example, the following operational effects can be obtained.

  (1) Two abnormality detection lines RL0 and RL1 are provided at the right end portion of the memory mat 33 separately from the normal bit lines. The abnormality detection line RL0 is provided for detecting the abnormality of the logical value “0”, and the abnormality detection line RL1 is provided for detecting the abnormality of the logical value “1”. During the read operation of the memory 123, the signals of the abnormality detection lines RL0 and RL1 are always selected by the column selection circuit 34, and abnormality detection is performed by the logical value being judged by the abnormality detection circuit 36. If the logical value “0” of the abnormality detection line RL0 and the logical value “1” of the abnormality detection line RL1 are obtained correctly, it is determined that the memory 123 is operating normally. However, if the logical value “0” of the abnormality detection line RL0 or the logical value “1” of the detection line RL1 cannot be obtained correctly, an abnormality is assumed and the error signal ERR is asserted. Thereby, it is possible to improve the detection rate of the memory error caused by the attack.

  (2) Apart from the abnormality detection lines RL0 and RL1 at the end of the memory mat 33, the abnormality detection lines RL0 and RL1 are arranged for every several bits of the memory mat 33, for example, for every 1 byte. In this manner, since a large number of abnormality detection lines RL0 and RL1 are densely arranged in the memory mat 33, it is possible to sufficiently cope with a local attack of the memory mat 33. The detection rate can be further improved.

  (3) If the abnormality detection lines RL0 and RL1 are densely arranged in the memory mat 33, the area and current consumption of the memory mat 33 increase correspondingly, so that depending on the required security level and memory characteristics. It is desirable to determine the number of the abnormality detection lines RL0 and RL1. The characteristic of the memory is that, for example, a change in read data due to an attack occurs only from a logical value “0” to a logical value “1” or a logical value “1” to a logical value “0” opposite to the logical value “0”. If it is clear that this is the case, only one of the logical value “0” or the logical value “1” is sufficient as the abnormality detection line to be arranged. For example, it is considered effective that the abnormality detection lines RL0 and RL1 at the end of the memory mat 33 are provided as they are, and only one of the abnormality detection lines RL0 and RL1 is provided for every several bits of the memory mat 33. It is done.

  (4) By adjusting the drive capability of the MOS transistors constituting the memory cell, the precharge capability of the abnormality detection lines RL0 and RL1 is made lower than the precharge capability of the bit line BL in the memory mat 33. In addition, by adjusting the driving capability of the precharge MOS transistor 61 corresponding to the bit line BL and the precharge MOS transistor 23 corresponding to the abnormality detection lines RL0 and RL1, it is coupled to the abnormality detection lines RL0 and RL1. The discharge capability of the memory cell MC formed is made lower than the discharge capability of the memory cell MC coupled to the bit line BL in the memory mat 33. As a result, appropriate abnormality detection can be performed regardless of process variations and biased influences of attacks, so that the memory error detection rate can be improved.

<Embodiment 2>
In the first embodiment, countermeasures against attacks in the memory mat unit have been described. In the second embodiment, countermeasures against attacks in the row decoder will be described.

  It has been confirmed by the present inventor that the row decoder 31 malfunctions due to laser irradiation and causes a memory error. As shown in FIG. 7, the occurrence location of the malfunction is presumed to be a driver unit for driving the word line WL to the selected level, and the word line that should not be selected is selected by the error of the driver unit. It is thought that. For example, even when the word line WL-A is selected according to the decoding result of the address, since the memory cell corresponding to the word line WL-A is not connected, the level of the bit line BL remains at the high (H) level. It does not change. However, if the driver malfunctions due to an attack such as laser irradiation, the word line WL-B that should not be selected may be driven to a selected level. At this time, since the bit line BL is discharged by the memory cell coupled to the word line WL-B, the bit line BL changes from the high level to the low level, and the logical value of the read data is different from the expected value. It becomes a thing.

  Therefore, as shown in FIG. 8, a monitor circuit 81 that enables monitoring of the input side logic and the output side logic is mounted for each driver 71. The monitor circuit 81 is configured by an exclusive OR circuit for comparing the input side logic and the output side logic of the corresponding driver 71. It is normal when the input side logic and the output side logic of the driver 71 are different, and abnormal when the input side logic and the output side logic of the driver 71 match. The output signals of all the monitor circuits 81 are transmitted to the subsequent flip-flop circuit 83 through the OR circuit 82, and the error signal ERR is formed by the flip-flop circuit 83. When the input side logic and the output side logic of the driver 71 coincide with each other, the output signal of the monitor circuit 81 corresponding to the driver 71 becomes high level, and this is transmitted to the flip-flop circuit 83 via the OR circuit 82. The flip-flop circuit 83 asserts an error signal ERR.

  According to the configuration described above, the monitor circuit 81 determines whether or not the force-side logic and the output-side logic of the corresponding driver 71 coincide with each other, so that the unselected word line is set to the selection level by the laser. In addition to the case, an error can be detected not only when the selected word line is unselected by the laser.

  FIG. 9 shows another configuration example of the monitor circuit 81.

  The monitor circuit 81 shown in FIG. 9 includes two n-channel MOS transistors 91 and 92 connected in series. The gate electrode of n channel type MOS transistor 91 is coupled to the input terminal of corresponding driver 71, and the gate electrode of n channel type MOS transistor 92 is coupled to the output terminal of corresponding driver 71. The source electrode of n channel type MOS transistor 91 is coupled to low potential side power source Vss, and the drain electrode of n channel type MOS transistor 92 is coupled to high potential side power source Vdd via pull-up resistor R1 and inverter 93 Is coupled to the flip-flop circuit 83. In such a configuration, when the input side logic and the output side logic of the driver 71 coincide with each other, in the monitor circuit 81 corresponding to the driver 71, both the two n-channel MOS transistors 91 and 92 are turned on. On the input terminal side of the inverter 93, the stored charge is extracted and the high (H) level is changed to the low (L) level. As a result, the output of the inverter 93 is changed from the low level to the high level, and the error signal ERR is asserted by the flip-flop circuit 83.

  In the circuit configuration described above, only the erroneous selection state of the unselected word line can be detected, but the circuit scale of the monitor circuit 81 can be reduced as compared with the configuration shown in FIG.

  As described above, the method of detecting the abnormality of the row decoder has been described, but it is considered that the malfunction detection of the column decoder can be handled by the same method.

<Embodiment 3>
In the memory 123, a dedicated power supply voltage may be generated internally in order to improve performance such as shortening the reading time. For example, in order to make the transfer gate 301 for bit line selection conductive, the power supply circuit 102 generates a voltage Vdd_e that is higher than the high potential side power supply Vdd. The voltage Vdd_e is used as an operation power supply voltage for the driver 101 based on the selection signal SEL from the column decoder 32. The high level voltage level output from the driver 101 is the Vdd_e level, which is higher than the high potential side power supply Vdd, and thus the on-resistance of the conductive transfer gate 301 can be kept small. By suppressing the on-resistance of the transfer gate 301 to be small, the charge and discharge of the bit line BL are speeded up. In such a configuration, the inventors of the present application have confirmed that the output voltage level fluctuates due to laser irradiation of the power supply circuit 102. In addition, due to the voltage fluctuation, the transfer gate 301 may not be conducted. In such a case, the bit line BL is not discharged, so that data cannot be read correctly.

  Therefore, by providing a detector capable of detecting voltage fluctuation in the power supply circuit 102, the memory error detection rate can be improved. FIG. 11 shows a configuration example of the power supply circuit 102 in that case.

  11 includes a reference voltage generation unit 111 that generates a reference voltage Vref, a power supply voltage generation unit 112 that generates a power supply voltage Vdd_e, and a comparator that compares the reference voltage Vref and the power supply voltage Vdd_e. 113 and a flip-flop circuit 114 that forms an error signal ERR based on the output signal of the comparator 113. When the reference voltage Vref is generated and the fluctuation of the power supply voltage Vdd_e exceeds the reference voltage Vref, the output of the comparator 113 becomes a high level and is held in the flip-flop circuit 114, so that the error signal ERR is asserted. The At this time, the reference voltage Vref should be set to a level that can be detected earlier than the voltage fluctuation that causes an actual read error. In addition, the reference voltage generation unit 111 that generates the reference voltage Vref is prevented from being unable to detect voltage fluctuation due to being affected simultaneously with the power supply voltage generation unit 112 in a local attack (laser irradiation or the like). Therefore, it is preferable to ensure a sufficient distance from the power supply voltage generation unit 112 so that the reference voltage Vref does not fluctuate. Further, as indicated by 50 in FIG. 11, the voltage fluctuation caused by the attack is made to have the opposite phase between the reference voltage Vref and the power supply voltage Vdd_e, so that the comparison by the comparator 113 can be performed with higher sensitivity. it can.

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

1 is a block diagram illustrating a configuration example of a memory in an IC card microcomputer as an example of a semiconductor integrated circuit device according to the present invention; FIG. It is another example block diagram of a configuration of the memory. FIG. 3 is a circuit diagram illustrating a configuration example of a main part of a memory mat included in the memory. FIG. 5 is a circuit diagram illustrating another configuration example of a main part in the memory mat. FIG. 2 is a circuit diagram of a configuration example of an abnormality detection circuit and its periphery included in the memory. FIG. 5 is a circuit diagram illustrating another configuration example of a main part in the memory mat. It is an example block diagram of the principal part in the said memory. It is another example block diagram of a configuration of the main part in the memory. It is another example block diagram of a configuration of the main part in the memory. It is another example block diagram of a configuration of the main part in the memory. FIG. 11 is a block diagram illustrating a configuration example of a power supply circuit illustrated in FIG. 10. It is a block diagram of an example of the overall configuration of the IC card microcomputer.

Explanation of symbols

31 row decoder 32 column decoder 33 memory mat 34 column selection circuit 35 sense amplifier circuit 36 abnormality detection circuit 37 controller 38 output circuit 71 driver 81 monitor circuit 83 flip-flop circuit 111 reference voltage generator 112 power supply voltage generator 113 comparator 114 flip-flop Circuit 121 Reset terminal 122 Port 123 Memory 124 System controller 125 CPU
126 to 128 modules RL0, RL1 Abnormality detection line WL Word line BL Bit line

Claims (10)

A semiconductor integrated circuit device including a storage unit capable of storing information,
The memory unit includes a memory mat formed by arranging a plurality of transistors each capable of storing information,
A first abnormality detection circuit for determining whether or not information reading from the memory mat is normal and forming an error signal,
The memory mat includes a first abnormality detection line and a second abnormality detection line capable of outputting information used for determination by the first abnormality detection circuit when reading information from the memory mat,
A first transistor for setting the first abnormality detection line to a logical value “0” is coupled to the first abnormality detection line, and the second abnormality detection line is connected to the second abnormality detection power line. A second transistor is coupled to set the logic line to logic “1” ,
The memory formed Ru by the first abnormality detection line or the second abnormality detection line is arranged for each of the plurality of bits in the mat semiconductors integrated circuit device.   2. The semiconductor integrated circuit device according to claim 1, wherein the first abnormality detection line and the second abnormality detection line are arranged at an end portion of the memory mat. The first abnormality detection circuit includes a first determination circuit for determining whether or not a logical value of a signal obtained from the first abnormality detection line is as expected.
The semiconductor integrated circuit device according to claim 1 , further comprising: a second determination circuit configured to determine whether a logical value of a signal obtained from the second abnormality detection line is as expected . The storage unit includes a row decoder for decoding an input address signal;
A first driver for driving a word line included in the memory mat based on an output signal of the row decoder;
The semiconductor integrated circuit device according to claim 1, further comprising: a second abnormality detection circuit configured to compare an input side logic level and an output side logic level of the first driver to form an error signal . The storage unit includes a power supply circuit for forming a power supply voltage for operation of a main part of the storage unit;
The semiconductor integrated circuit device according to claim 1, further comprising: a third abnormality detection circuit configured to compare an operation power supply voltage formed by the power supply circuit with a predetermined reference voltage to form an error signal . A CPU accessible to the storage unit;
The semiconductor integrated circuit device according to claim 1, further comprising: a system controller capable of controlling the operation of the CPU based on the error signal . A semiconductor integrated circuit device including a memory unit capable of storing information,
The memory unit includes a memory mat in which a plurality of transistors each capable of storing information are arranged,
An abnormality detection circuit for determining whether information reading from the memory mat is normal and generating an error signal;
The memory mat is connected to a plurality of bit lines, a plurality of word lines, a column selection circuit for selecting the bit lines, and the abnormality detection circuit, and a first abnormality for obtaining a first logic value. Including a detection line and a second abnormality detection line for obtaining a second logical value different from the first logical value;
The first abnormality detection line and the second abnormality detection line are arranged in parallel to the bit line,
The first abnormality detection line and the second abnormality detection line are selected by the column selection circuit for each read of the memory mat,
A plurality of first transistors connected to the bit line and the word line are coupled to the first abnormality detection line,
A plurality of second transistors connected to the bit line are coupled to the second abnormality detection line,
A semiconductor integrated circuit device in which the first abnormality detection line or the second abnormality detection line is arranged for each of the plurality of bit lines .   The memory unit includes a power supply circuit for forming a power supply voltage for operation of a main part of the memory unit;
  8. A semiconductor integrated circuit device according to claim 7, further comprising: a voltage fluctuation detecting circuit for comparing said operating power supply voltage formed by said power supply circuit with a predetermined reference voltage to form an error signal.   9. The semiconductor integrated circuit device according to claim 8, wherein the memory unit is an EEPROM.   In the first transistor, the wiring to the low potential side power supply is omitted,
  10. The semiconductor integrated circuit device according to claim 9, wherein the second transistor is coupled to a low potential side power source.

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