JP5173491B2 - Signal processing device - Google Patents

Description

  The present invention relates to a signal processing apparatus, and more particularly to an apparatus that irradiates a disk-shaped recording medium with a light beam and converts the reflected light into an electrical signal for processing.

  2. Description of the Related Art Conventionally, an apparatus for recording and reproducing information signals such as video data on an optical disk such as a DVD is known.

  A track (wobble) that wobbles in a predetermined cycle is formed in advance on the DVD, and data recorded on the disk needs to be synchronized with this wobble cycle (wobble cycle).

For this reason, when recording data on a DVD, a reflected light of the light beam with respect to the disk is used to generate a clock that is phase-synchronized with the wobble, and the data is recorded on the disk using this clock. (For example, see Patent Document 1)
In addition, a drive device that writes and reads data to and from a DVD generates a clock synchronized with the data read from the disk and processes the digital data reproduced according to this reproduction clock.

  Further, in this type of apparatus, during recording, the disk is controlled to rotate at a predetermined rotational speed.

  A PLL circuit is used when generating a clock synchronized with the reproduction signal.

  In addition, a PLL circuit is used for the clock generation described above, but when the PLL circuit is designed with a conventional analog circuit, it is greatly influenced by clock fluctuations due to temperature changes, aging changes, and manufacturing variations. It is desirable.

Therefore, a minimum analog signal processing such as signal amplification or AD conversion is executed by the analog dedicated IC, and the subsequent processing is executed by the digital signal processing LSI.
JP 2002-230757 A

  However, as the number of types of signals passed between the analog dedicated IC and the digital signal processing LSI increases, the number of IC pins required for this tends to increase. This increase in the number of pins leads to mounting restrictions and an increase in chip cost.

  In addition, since the frequency of recorded data is originally high in DVD, and in recent years, high-speed writing and reading such as double speed are common, there is a problem in accurate data transfer between an analog dedicated IC and a large-scale LSI. It has become.

  The present invention has been made in view of the above points, and an object of the present invention is to provide an apparatus capable of processing a reproduction signal from an optical disc with a low-cost configuration while suppressing a circuit scale.

  The present invention provides an irradiating means for irradiating a disk-shaped recording medium on which tracks meandering with a predetermined period are formed, light reflected from the disk-shaped recording medium, and an electric signal. In accordance with the wobble phase error signal, the light receiving unit that converts and outputs the wobble signal, the wobble signal generation unit that generates a wobble signal having a frequency related to the meandering cycle of the track based on the output signal from the light receiving unit, In accordance with the first sampling clock, the first oscillation unit that generates the first operation clock, the first frequency division unit that divides the first operation clock to generate the first sampling clock, and the wobble according to the first sampling clock. A first AD converter for converting a signal into a digital signal, and a digital wobble signal output from the first AD converter in accordance with the first operation clock. RF signal generation for generating data for detecting data recorded on the disk-shaped recording medium based on an output signal from the light receiving unit and a first serial conversion unit that converts the data into real data and transmits it A second oscillation unit that generates a second operation clock according to the RF phase error signal, and a second frequency division unit that divides the second operation clock to generate a second sampling clock. A second AD converter that converts the RF signal into a digital signal in accordance with the second sampling clock; and a digital RF signal output from the second AD converter in accordance with the second operation clock. A second serial conversion unit that converts the data into data and transmits the data; a clock having a frequency lower than that of the first operation clock and the second operation clock; The third operation clock is input, and the third operation clock is divided to generate a third sampling clock having a frequency lower than that of the first sampling clock and the second sampling lock. A peripheral part, a third AD converter for converting a plurality of output signals from the light receiving part into digital signals according to the third sampling clock, and a third AD converter according to the third operation clock. A third serial converter that converts the output digital signal into serial data and transmits the serial data; the serial data output from the first serial converter is received in accordance with the first operation clock; and the digital wobble signal The first wobbling signal output from the first wobbling signal based on the digital wobble signal output from the first receiving unit. A wobble processing unit that generates a phase-synchronized wobble clock and outputs a wobble phase error signal indicating a phase difference between the digital wobble signal and the wobble clock; and a wobble phase error signal from the wobble processing unit A first output unit that outputs to the oscillation unit; a second reception unit that receives serial data output from the second serial conversion unit according to the second operation clock; and outputs the serial data as the digital RF signal; Based on the digital RF signal output from the second receiver, an RF clock phase-synchronized with the RF signal is generated, and an RF phase error signal indicating a phase difference between the digital RF signal and the RF clock is output. And the disc-shaped recording based on the digital RF signal output from the second receiving unit. A reproduction processing unit for detecting data recorded on the body, a second output unit for outputting an RF phase error signal from the reproduction processing unit to the second oscillation unit, and an output from the third serial conversion unit The received serial data is received according to the third operation clock and output as a digital signal, and a tracking error signal is generated based on the digital signal output from the third receiver. A servo processing unit; a clock generation unit that generates the third operation clock and outputs the third operation clock to the third frequency division unit and the third serial conversion unit; and the wobble signal generation unit, An oscillation unit, the first frequency division unit, the first AD conversion unit, the first serial conversion unit, the RF signal generation unit, the second oscillation unit, the second frequency division unit, the first frequency division unit, 2 AD converters, the first The serial converter, the third frequency divider, the third AD converter, and the third serial converter are configured as one analog integrated circuit, and the first receiver and the wobble processor The first output unit, the second reception unit, the RF processing unit, the reproduction processing unit, the second output unit, the third reception unit, the servo processing unit, and the clock generation unit. It was configured as one digital integrated circuit.

  By using the present invention, the number of pins between the analog integrated circuit and the digital signal processing IC can be reduced, and accurate data transfer between the analog IC and the digital LSI can be realized.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of a disk device according to an embodiment of the present invention. In the apparatus shown in FIG. 1, an optical signal is irradiated onto an optical disk D on which a meandering track has been formed in advance to record and reproduce information signals. In this embodiment, a DVD-R is used as the optical disc D.

  In FIG. 1, 101 is an input unit for inputting information data such as video data, and 102 is an output unit for outputting reproduced data. A signal processing unit 103 processes input information data at the time of recording and converts it into a form suitable for recording. At the time of reproduction, the signal processing unit 103 processes reflected light from the disc and processes and outputs the reproduced data. It is. Reference numeral 104 denotes a laser driver, and reference numeral 105 denotes a laser diode that emits a laser beam.

  Reference numeral 106 denotes a beam splitter, and 107 denotes a lens. A front monitor 112 measures the output power of the laser diode 105. The laser diode 105, the beam splitter 106, the lens 107, and the front monitor 112 constitute an optical pickup unit (OPU) 113. A spindle servo circuit 108 rotates the optical disc D and includes a known spindle motor. The spindle servo circuit 108 controls the rotation of the disk D according to the spindle error signal output from the signal processing unit 103 as will be described later.

  Reference numeral 109 denotes a pickup servo circuit. The pickup servo circuit 109 has a pickup motor that moves the OPU 113 and an actuator that moves the position of the lens. The pickup servo circuit 109 controls the irradiation position and focus of the laser beam on the disk D in accordance with the focus error and tracking error signal output from the signal processing unit 103 as will be described later.

  Reference numeral 110 denotes a system control unit including a CPU, which controls each unit according to instructions from the operation unit 111. Reference numeral 111 denotes an operation unit having various switches such as a power switch and a recording / reproducing switch.

  At the time of recording, necessary processing is performed by the signal processing unit 103 on the input information data. Then, NRZI modulation processing is performed on the recording data, and a modulation signal (write strategy signal) for driving the laser driver is generated according to the mark lengths of 1 and 0 of the recording data after the NRZI modulation processing. Output to. The LDD 104 outputs a current corresponding to the output signal 103 to control the amount of laser beam emitted from the laser diode 105 and irradiates the disk D with a beam via the beam splitter 106 and the lens 107.

  In DVD-R, it is necessary to perform data recording with a clock synchronized with the wobble cycle on the disk during recording. In addition, physical address information indicating position information on the disk is embedded in the wobble. For this reason, it is necessary to reproduce the wobble signal from the disc reflected light to generate a recording clock synchronized with the wobble signal and to reproduce the address information embedded in the wobble during both reproduction and recording.

  Specifically, the laser diode 105 irradiates the disk D with a laser beam. Then, the reflected light from the disk D is received by the beam splitter 102 and sent to the signal processing unit 103. The signal processing unit 103 processes reflected light from the disk to generate a wobble signal, generates a recording clock using the wobble signal, and performs address reproduction.

  At the time of reproduction, reflected light from the disk D is sent to the signal processing unit 103 to generate a clock synchronized with the reproduced data. Then, information data already recorded on the disk D is detected and output in accordance with the reproduction clock.

  Next, the signal processing unit 103, which is a characteristic configuration of the present embodiment, will be described.

  FIG. 2 is a diagram illustrating a configuration of the signal processing unit 103, and the signal processing unit 103 includes three integrated circuits. Reference numeral 201 denotes a photoelectric conversion IC (OEIC), 202 denotes an analog front end (AFE), and 203 denotes a digital processing circuit. The OEIC 201 and the AFE 202 each function as an analog signal processing circuit, and the digital processing circuit 203 functions as a digital signal processing circuit. Each circuit of the AFE 202 is configured as one analog integrated circuit, and each circuit of the digital processing circuit 203 is configured as one digital integrated circuit.

  In FIG. 2, the reflected light from the beam splitter 102 is output to the light receiving sensor 201a. The light receiving sensor 201a receives the reflected light, performs light-current conversion, and outputs a current value corresponding to the amount of received light to the I / V converter amplifier 201b. The I / V converter 201 b converts the current value output from the light receiving sensor 201 a into a voltage value and outputs the voltage value to the AFE 202.

  FIG. 3 shows a state of the light receiving sensor 201a. The light receiving sensor 201a is arranged as shown in FIG. 3 with respect to the track 301 of the disk D moving in the arrow 302 direction. As shown in FIG. 3, the light receiving sensor 201a has eight light receiving portions A to H. That is, the main sensors A to D and the sub sensors E to H.

  Then, an electrical signal is output from each light receiving unit. Further, a signal (A + B + C + D) obtained by adding the main sensor for data reproduction RF signal processing described later is also output separately. Returning to FIG. 2, output signals from the light receiving units A to D of the light receiving sensor 201 a are output to the pre-processing units 205 and 215 in the AFE 202. Further, output signals from the light receiving portions A to H of the light receiving sensor 201a are output to 215, and a signal obtained by adding the main sensor is output to the pre-processing portion 210.

  Further, some signals in the beam splitter 102 are output to a front monitor IC (FM) 112, and an electric signal is output to the signal processing unit 103.

  Next, wobble signal processing will be described.

  The pre-processing unit 205 performs pre-processing such as noise removal by filtering and amplification processing on the output signal of the light receiving sensor 204. Then, by calculating the output of the light receiving sensor 204a by a known push-pull method (A + D-B-C), a wobble signal synchronized with the meandering cycle of the track on the disk D is generated and sent to the AD converter (ADC) 206. Output. The ADC 206 samples the wobble signal according to the sampling clock supplied from the frequency divider 208, converts it into a 1-sample N-bit digital signal, and outputs the digital signal to the parallel-serial conversion unit (P / S) 207. For example, in FIG. 2, N = 8.

  The frequency divider 208 divides the frequency of the clock output from the VCO 209 and supplies it to the ADC 206. The VCO 209 is supplied with a wobble phase error signal from the digital processing circuit 203. Based on the phase error signal, the VCO 209 generates an operation clock having a predetermined frequency related to the frequency of the wobble signal. Here, the output of the VCO 209 is a clock centered on 416 MHz that fluctuates due to a wobble phase error. The output of the frequency divider 208 is a signal obtained by dividing the output of the VCO 209 by 1/8 and is 52 MHz.

  The P / S 207 converts the N-bit digital signal from the ADC 206 into a serial signal in accordance with the clock from the VCO 209, and further multiplexes synchronous data at a predetermined timing and sends it to the digital processing circuit 203. The clock from the VCO 209 is sent to the digital processing circuit 203 independently of the digital data of the wobble signal from the P / S 207.

  In the digital processing circuit 203, the serial-parallel converter (S / P) 219 uses the clock from the VCO 209 to capture the digital data of the wobble signal output from the P / S 207 and convert it into parallel data for each sample. To the wobble (WBL) processing unit 220. The S / P 219 outputs the timing signal for each sample to the WBL process 220 and the recording system process 230 as WBLCLK (52 MHz in FIG. 2). The WBL process 220 and the recording process 230 operate in synchronization with WBLCLK.

  The S / P 219 has a shift register that holds input serial data in accordance with the clock from the VCO 209 and a timing control unit that detects synchronization data from the input serial data string and controls the output timing of parallel data. Also, WBLCLK output from the S / P 219 is in phase synchronization with the output of the frequency divider 208.

  The WBL processing unit 220 generates a wobble clock based on the wobble signal from the S / P 219 and detects a land pre-pit. In DVD-R, land pre-pits (LPP) are formed at predetermined positions on tracks on the disc. The land prepit has a predetermined phase relationship with the wobble signal, and the physical address position on the disc is detected by detecting the land prepit.

  FIG. 4A is a diagram illustrating a configuration of the WBL processing unit 220.

  In FIG. 4A, the WBL signal from the S / P 219 is output to the phase detector 401 and the LPP detector 404. A sine wave is generated by the sine wave generator 403 based on the WBLCLK output from the S / P 219 described above. The sine wave generator is, for example, a generator using a sine wave table. In DVD-R, WBLCLK and sine wave have a frequency relationship of 1: 186.

  The phase detection unit 401 detects the phase difference between the WBL signal and the output of the sine wave generator 403 by known heterodyne detection, and outputs it to the loop filter 402. The loop filter 402 filters the phase difference signal from the phase detector 401 and outputs it as a WBL phase error signal to the DA converter (DAC) 221 and the servo processor 227 in FIG. A PLL circuit configured by the VCO 209, the phase detector 401, the loop filter 402, and the DAC 221 generates a WBL clock synchronized with the wobble signal reproduced from the optical disc.

  Further, the LPP detection unit 404 detects an LPP signal included in the input WBL signal and outputs the detection result to the address demodulation unit 405. The address demodulator demodulates the physical address information from the detected LPP data pattern and outputs it to the system controller shown in FIG.

  Returning to FIG. 2, the DAC 221 converts the wobble phase error signal output from the WBL processing unit 220 into an analog signal and outputs the analog signal to the VCO 209.

  Next, processing of the reproduction RF signal will be described.

  The pre-processing unit 210 performs pre-processing such as filtering processing and amplification processing on the output signal of the light receiving sensor 204 and outputs the result to the ADC 211. The ADC 211 samples the RF signal in accordance with the clock supplied from the frequency divider 213, converts it into a 1-sample M-bit digital signal, and outputs it to the P / S 212. For example, in FIG. 2, M = 10.

  The frequency divider 213 divides the frequency of the clock output from the VCO 214 and supplies it to the ADC 211. An RF phase error signal from the digital processing circuit 203 is supplied to the VCO 214. Based on this phase error signal, the VCO 214 generates a clock that fluctuates due to the RF phase error around a predetermined frequency related to the RF signal, here, 520 MHz, and supplies the clock to the frequency divider 213 and the P / S 212. In FIG. 2, the output of the frequency divider 213 is 52 MHz.

  The P / S 212 converts the M-bit digital signal from the ADC 211 into a serial signal according to the clock from the VCO 214, and further multiplexes the synchronization data at a predetermined timing and sends it to the digital processing circuit 203. The clock from the VCO 214 is sent to the digital processing circuit 203 independently of the digital data of the RF signal from the P / S 212.

  In the digital processing circuit 203, the S / P 222 receives the digital data of the RF signal output from the P / S 212 in accordance with the clock from the VCO 214, and converts it into parallel data for each sample.

  Then, the parallel data is sent to the RF processing unit 223 and the reproduction system processing unit 225, and the timing signal for each sample is output to the RF processing 223 as RFCLK (52 MHz in FIG. 2). The RF processing unit 223 operates in synchronization with this RCLKC.

  The S / P 222 has a shift register that holds input serial data according to a clock from the VCO 214, and a timing control unit that detects synchronization data from the input serial data string and controls the output timing of parallel data.

  The RF processing unit 223 detects and outputs the phase difference between the RF signal from the S / P 222 and the RF clock.

  FIG. 4B is a diagram illustrating the configuration of the RF processing unit 223.

  In FIG. 4B, the RF signal from the S / P 222 is output to the phase detection unit 406. The phase detection unit 406 detects a difference from the zero level of the input RF signal at the edge timing of the RF clock from the SP 222 as a phase difference and outputs it to the loop filter 407. The loop filter 407 filters the phase difference signal from the phase detection unit 406 and outputs it as an RF phase error signal to the DAC 224 in FIG.

  Returning to FIG. 2, the DAC 224 converts the RF phase error signal output from the RF processing unit 223 into an analog signal and outputs the analog signal to the VCO 214.

  The ADC 211, the phase detection unit 406, the loop filter 407, and the VCO 214 constitute an RF-PLL circuit, thereby generating an RF clock synchronized with the reproduction data.

  Further, the reproduction processing unit 225 detects original digital data from the reproduction RF signal output from the S / P 222 according to the reproduction RF clock from the RF processing unit 223. The detected digital data is subjected to signal processing necessary for data decoding, such as demodulation processing and error correction processing, and is output to the output unit 102 as reproduced data.

  Next, processing of the servo system will be described.

  Eight output signals from the light receiving units A to H of the light receiving sensor 204 are independently supplied to the pre-processing unit 215. The pre-processing unit 215 performs pre-processing such as filtering processing and amplification processing on the output signal from the light receiving sensor 204 and outputs the result to the ADC 216.

  The ADC 216 includes eight AD converters that convert the eight output signals of the light receiving units A to H into digital signals, respectively. The ADC 216 includes eight ΔΣ AD converters. Each ΔΣ ADC samples the input signal according to the clock supplied from the frequency divider 218, converts it into a known ΔΣ 1-bit digital signal, and outputs it to the P / S 217.

  The frequency divider 218 divides the fixed frequency supplied from the fixed clock generation unit 229 of the digital processing circuit 203, here a 108 MHz clock, by 8 and supplies it to the ADC 218 and the P / S 217.

  The P / S 217 converts the eight digital signals output from the ADC 216 into serial signals and multiplexes them in accordance with a fixed frequency clock from the digital processing circuit 203. Further, the P / S 2217 multiplexes the synchronization data at a predetermined timing and sends it to the digital processing circuit 203. In the present embodiment, since the light receiving sensor 204 has eight outputs, the ADC 218 includes eight ΔΣ ADCs, but the number of ΔΣ ADCs may be changed according to the number of outputs of the light receiving sensors 204.

  In the digital processing circuit 203, the S / P 226 receives the digital data output from the P / S 217 in accordance with the clock from the fixed clock generation unit 229, converts it into parallel data for each sample, and sends it to the servo processing unit 227. Further, the timing signal for each sample is output to the servo processing unit 207 as SRVCLK (13.5 MHz in FIG. 2). The servo processing unit 207 operates in synchronization with SRVCLK. The S / P 226 has a shift register that holds serial data input according to the clock from the fixed clock generation unit 229. Then, the synchronization data is detected from the input serial data string, and the output timing of the parallel data is determined.

  The servo processing unit 227 performs matrix calculation based on a known operation push-pull method on the output data of each of the light receiving units A to H output from the S / P 226. Then, as a calculation result, a tracking error signal for tracking control indicating a positional deviation between the OPU 113 and the target track is generated. The servo processing unit 227 performs matrix calculation based on a known critical aberration method on the output data of each light receiving unit A to H output from the S / P 226. Then, as a calculation result, a focus error signal indicating a laser beam defocus with respect to the disk D is generated.

  Further, the servo processing unit 227 generates a spindle error signal indicating the deviation of the actual rotational speed from the target speed of the disk D based on the phase error signal from the WBL processing unit 220.

  Then, the tracking error signal, the focus error signal, and the spindle error signal are subjected to signal processing such as filtering by the DSP in the servo processing, and output to the DAC 228, respectively. The DAC 228 includes three AD converters that convert the input tracking error signal, focus error signal, and spindle error signal into analog signals. Then, the tracking error signal and the focus error signal are converted into analog signals, respectively, and output to the pickup servo circuit 109 in FIG. Also, the spindle error signal is converted into an analog signal and output to the spindle servo circuit 108 in FIG.

  Finally, the recording system processing unit 230 will be described.

  The recording system processing unit 230 performs necessary processing such as encoding processing and error correction encoding processing on the information data input from the input unit 101. Data is modulated in accordance with WBLCLK output from the S / P 219 and output to the power control circuit 231 in the AFE 202. The power control circuit measures the output power of the laser diode 105 from the output of the front monitor 112, and drives the laser driver 104 so that the output power becomes optimum.

  As described above, in the present embodiment, irradiation means for irradiating a disk-shaped recording medium on which tracks meandering with a predetermined period are formed, and reflected light of the light beam from the disk-shaped recording medium. A light receiving unit that receives and converts the light into an electrical signal and outputs the wobble signal generation unit that generates a wobble signal having a frequency related to the meandering cycle of the track based on the output signal from the light receiving unit; A first clock generation unit that generates a first operation clock and a first sampling clock according to the control signal, and a first AD conversion unit that converts the wobble signal into a digital signal according to the first sampling clock; The first wobble signal output from the first AD converter is transmitted as serial data in accordance with the first operation clock. In accordance with the second control signal, a real conversion unit, an RF signal generation unit that generates an RF signal for detecting data recorded on the disc-shaped recording medium, based on an output signal from the light receiving unit, A second clock generation unit that generates two operation clocks and a second sampling clock, a second AD conversion unit that converts the RF signal into a digital signal in accordance with the second sampling clock, and the second operation A second serial converter that transmits the digital RF signal output from the second AD converter according to the clock as serial data, a third operation clock, and a third operation clock based on the third operation clock. A third clock generating unit for generating a sampling clock of the first and a plurality of output signals from the light receiving unit according to the third sampling clock A third AD converter for converting to a digital signal, a third serial converter for transmitting a digital signal output from the third AD converter in accordance with the third operation clock as serial data, and the first Based on the first receiving unit that receives the serial data output from the first serial conversion unit according to the operation clock and outputs the serial data as the digital wobble signal, and the digital wobble signal output from the first receiving unit Generating a wobble clock phase-synchronized with the wobble signal and outputting a wobble phase error signal indicating a phase difference between the digital wobble signal and the wobble clock; and the wobble phase error signal as the first wobble signal. A wobble phase error output unit that outputs to the first clock generation unit as a control signal for A second reception unit that receives serial data output from the second serial conversion unit according to the second operation clock and outputs the serial data as the digital RF signal; and a digital RF output from the second reception unit An RF processing unit that generates an RF clock phase-synchronized with the RF signal based on a signal, and outputs an RF phase error signal indicating a phase difference between the digital RF signal and the RF clock; and the second receiving unit Reproduction processing means for detecting data recorded on the disc-shaped recording medium based on the digital RF signal output from the signal, and the RF phase error signal as the second control signal to the second clock generator. An RF phase error output unit for output and serial data output from the third serial conversion unit according to the third operation clock are received. A wobble signal generator, and a servo processor that generates a tracking error signal based on the digital signal output from the third receiver. Clock generation unit, first AD conversion unit, first serial conversion unit, RF signal generation unit, second clock generation unit, second AD conversion unit, second serial conversion unit The third clock generation unit, the third AD conversion unit, and the third serial conversion unit are configured as one analog integrated circuit, and the first reception unit, the wobble processing unit, and the wobble error The output unit, the second receiving unit, the RF processing unit, the RF error output unit, the third receiving unit, and the servo processing unit are configured as one digital integrated circuit.

  That is, the wobble signal, the RF signal, and the output of each light receiving unit for servo processing are converted into digital signals, and then output as serial data to the digital processing circuit.

  Therefore, compared to the case where each signal is transmitted as parallel digital data, the data can be transmitted to the digital signal processing circuit more accurately.

  In addition, the number of pins between the analog IC and the digital IC can be reduced.

It is a figure which shows the structure of the disc apparatus as embodiment of this invention. It is a figure which shows the structure of a signal processing part. It is a figure which shows arrangement | positioning of a light-receiving part. It is a figure which shows the structure of a digital processing circuit.

Claims (3)

Irradiating means for irradiating a light beam onto a disc-shaped recording medium on which tracks meandering with a predetermined period are formed;
A light receiving unit that receives reflected light of the light beam from the disk-shaped recording medium, converts the light into an electric signal, and outputs the electric signal;
A wobble signal generation unit that generates a wobble signal having a frequency related to the meandering cycle of the track based on an output signal from the light receiving unit;
A first oscillation unit for generating a first operation clock according to a wobble phase error signal;
A first frequency divider that divides the first operating clock to generate a first sampling clock;
A first AD converter that converts the wobble signal into a digital signal in accordance with the first sampling clock;
A first serial conversion unit that converts the digital wobble signal output from the first AD conversion unit into serial data and transmits the serial data according to the first operation clock;
An RF signal generation unit that generates an RF signal for detecting data recorded on the disc-shaped recording medium based on an output signal from the light receiving unit;
A second oscillation unit for generating a second operation clock according to the RF phase error signal;
A second frequency divider that divides the second operating clock to generate a second sampling clock;
A second AD converter for converting the RF signal into a digital signal in accordance with the second sampling clock;
A second serial conversion unit that converts the digital RF signal output from the second AD conversion unit into serial data and transmits the serial RF signal according to the second operation clock;
A third operation clock having a fixed frequency that is lower than the first operation clock and the second operation clock is input, the third operation clock is divided, and the first sampling clock and the second operation clock are divided. A third frequency divider for generating a third sampling clock having a lower frequency than the sampling lock of 2;
A third AD converter for converting a plurality of output signals from the light receiving unit into digital signals according to the third sampling clock;
A third serial conversion unit that converts the digital signal output from the third AD conversion unit into serial data and transmits the serial signal in accordance with the third operation clock;
A first receiving unit that receives serial data output from the first serial conversion unit according to the first operation clock and outputs the serial data as the digital wobble signal;
Based on the digital wobble signal output from the first receiver, a wobble clock that is phase-synchronized with the wobble signal is generated, and a wobble phase error signal that indicates a phase difference between the digital wobble signal and the wobble clock is output. A wobble processing unit,
A first output unit that outputs a wobble phase error signal from the wobble processing unit to the first oscillation unit ;
A second receiving unit that receives serial data output from the second serial conversion unit according to the second operation clock and outputs the serial data as the digital RF signal;
Based on the digital RF signal output from the second receiver, an RF clock phase-synchronized with the RF signal is generated, and an RF phase error signal indicating a phase difference between the digital RF signal and the RF clock is output. An RF processing unit,
A reproduction processing unit for detecting data recorded on the disc-shaped recording medium based on the digital RF signal output from the second receiving unit;
A second output unit for outputting an RF phase error signal from the reproduction processing unit to the second oscillation unit ;
A third receiving unit that receives serial data output from the third serial conversion unit according to the third operation clock and outputs the serial data as a digital signal;
A servo processing unit that generates a tracking error signal based on the digital signal output from the third receiving unit;
A clock generation unit that generates the third operation clock and outputs the third operation clock to the third frequency division unit and the third serial conversion unit ;
The wobble signal generation unit, the first oscillation unit, the first frequency division unit, the first AD conversion unit, the first serial conversion unit, the RF signal generation unit, the second oscillation unit, The second divider, the second AD converter, the second serial converter, the third divider, the third AD converter, and the third serial converter are combined into one Configured as an analog integrated circuit,
The first receiving unit, the wobble processing unit, the first output unit, the second receiving unit, the RF processing unit, the reproduction processing unit, the second output unit, the third receiving unit, A signal processing apparatus, wherein the servo processing unit and the clock generation unit are configured as one digital integrated circuit.   2. The signal processing apparatus according to claim 1, wherein the third AD conversion unit includes a plurality of ΔΣ AD converters that respectively convert output signals from the plurality of light receiving units into digital signals according to the sampling clock. . The first AD conversion unit converts the wobble signal generated by the wobble signal generation unit into an N-bit digital signal, and the second AD conversion unit generates an RF signal generated by the RF signal generation unit. The signal processing apparatus according to claim 1, wherein the signal is converted into an M-bit digital signal.

Images