JP5173256B2 - Busbar protection relay - Google Patents

Description

  The present invention relates to a bus protection relay for protecting a double bus configuration that takes in an auxiliary (pallet) contact signal (pallet condition) of a disconnector and executes a bus protection operation, and more particularly, an erroneous bus due to an abnormality of a pallet contact signal. The present invention relates to pallet condition monitoring control for preventing protection.

  In substations, etc., a plurality of transmission lines (lines) are connected to double buses (Kobus, Otobusu) via disconnectors, and between one line and double buses is for Kobus. Disconnectors and for Otomo Line are provided. Each line is provided with a circuit breaker. When a line is electrically connected to the Koubus line, the disconnector for the Koubus line is closed and the disconnector for the Otobus line is opened. On the other hand, in the trip circuit of the bus protection relay, the disconnector condition indicating the open / close state of the disconnector is taken in, and a disconnection command is given to the circuit breaker only for the line connected to the accident bus. When the disconnector condition is bad, the line connected to the accident bus cannot be determined, and trip failure occurs. Therefore, a system for monitoring each disconnector is provided. When the disconnector condition is bad, the entire double bus The function is switched to a function that collectively protects and an alarm is issued.

  In the disconnector monitoring circuit disclosed in Patent Document 1, the pallet contact of the disconnector on the side of the bus is composed of a contact and b contact per line, and the pallet contact of the disconnector on the side of the bus is connected to the a contact A circuit configuration is employed in which the operation of the two pallet contacts (a and b contacts) is monitored for consistency. As described above, in Patent Document 1, two pallet contacts (a and b contacts) are provided per disconnector, and signals from these two pallet contacts (a and b contacts) are used as disconnector pallet conditions. Input to the bus protection relay. When the pallet contact is a contact, the main contact of the disconnector and the pallet contact are the same, that is, the pallet contact is closed when the main contact is closed. When the pallet contact is a b contact, the pallet contact is opened when the main contact and the pallet contact of the disconnector are reversed, that is, when the main contact is closed.

JP-A-11-262166 (FIG. 12)

  However, in the conventional method shown in Patent Document 1, it is necessary to capture the signal of two pallet contacts per disconnector as a disconnector pallet condition into the bus protection relay, so in the protective relay that captures these pallet conditions Two input circuits (DI circuit (digital input)) are required per disconnector. For this reason, especially in the case of a bus protection relay with a large number of lines that need to be switched by a disconnector, the number of DI circuits becomes several tens or more, which is a major factor in terms of cost and hardware, resulting in low cost and small size. It will be a problem.

  The present invention has been made in view of the above, and can reliably monitor disconnector pallet conditions, and, for example, only the signal from the contact a is taken in as an isolator pallet condition. An object of the present invention is to obtain a bus protection relay that can halve the number of input circuits to one circuit and can be reduced in cost and size.

  In order to solve the above-described problems and achieve the object, the first and second buses connected via the bus connection breaker, a plurality of lines each provided with a circuit breaker, In a bus protection relay that performs bus protection of a system configuration including a plurality of first bus side disconnectors connected to a bus and a disconnector having a plurality of second bus side disconnectors connecting each line to a second bus, A first input circuit that inputs a pallet contact signal of any one of the a-contact and b-contact of each disconnector as a disconnector pallet condition, all line currents, and first detected on the first and second bus side A second input circuit to which the first and second bus contact currents are input, and first and second buses for controlling the circuit breakers based on all line currents output from the second input circuit. Bus protection performance in a collective area including the area And a collective bus protection arithmetic unit that detects abnormal disconnector connection based on all line currents and outputs a first abnormal LS connection detection signal, and the line current on the side connected to the first bus and the first In order to control the circuit breaker based on the two bus contact currents, a bus protection calculation in the first bus side region is performed, and an abnormal disconnector connection is detected based on each input current to detect a second abnormal LS connection A first bus protection calculation unit for outputting a detection signal; and a bus protection calculation in a second bus side region for controlling the circuit breaker based on the line current on the side connected to the second bus and the first bus connection current A second bus protection arithmetic unit that detects an abnormal disconnector connection based on each input current and outputs a third abnormal LS connection detection signal, the disconnector pallet condition, and the first to first 3 differences A plurality of switching signals for switching whether or not to output each line current output from the second input circuit to the first and second bus protection operation units based on the LS connection detection signal and disconnecting Disconnector monitoring control that corrects the disconnector pallet condition and outputs it as the switching signal when an abnormal pallet condition change is detected based on the first to third abnormal LS connection detection signals when the container pallet condition is closed A circuit and a line switching circuit that performs a switching operation to switch whether or not to output each line current output from the second input circuit to the first and second bus protection arithmetic units based on the switching signal. It is characterized by providing.

  According to the present invention, in addition to the disconnector pallet condition, each of the first bus and the second bus based on the first to third abnormal LS connection detection signals using the differential current of the respective line currents for the bus protection calculation. Since the switching signal for selecting and switching the line current input for protection calculation is generated, the disconnector pallet condition can be monitored with high reliability, and the number of input circuits for the disconnector pallet condition can be reduced. It can be reduced to one circuit per disconnector, and there is an effect of cost reduction and size reduction. In addition, when an abnormal pallet condition change is detected based on the first to third abnormal LS connection detection signals when the disconnector pallet condition is closed, the disconnector pallet condition is corrected and output as a switching signal. As a result, busbar protection can be continued regardless of erroneous pallet condition changes.

  Embodiments of a busbar protection relay according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a system configuration to which a busbar protection relay according to the present invention is applied. In this system configuration, a double bus configuration comprising # 1 Bus (first bus) 10 and # 2 Bus (second bus) 20 communicated by a bus communication breaker (CB) 30 is adopted. A plurality of power transmission lines including the first line L1 to the Nth line LN are connected to the double bus. Each of the lines L1 to LN is provided with circuit breakers CB1 to CBN. These circuit breakers CB1 to CBN are separated from the line side when a bus side failure occurs or are disconnected from a connection bus line when a line side failure occurs. is set up.

  The first line L1 is connected to the first bus 10 via the disconnector 1LS1, and is connected to the second bus 20 via the disconnector 1LS2. The second line L2 is connected to the first bus 10 via the disconnector 2LS1, and is connected to the second bus 20 via the disconnector 2LS2. The third line L3 is connected to the first bus 10 via the disconnector 3LS1, and is connected to the second bus 20 via the disconnector 3LS2. The Nth line LN is connected to the first bus 10 via the disconnector NLS1, and is connected to the second bus 20 via the disconnector NLS2. Each of the disconnectors 1LS1, 1LS2, 2LS1, 2LS2,..., NLS1, NLS2 is appropriately opened and closed by user control.

  Each line L1 to LN is provided with current transformers CT1 to CTN for detecting currents I1 to IN of each line. Further, a current transformer CTB1 for detecting a bus contact current IB1 when an accident occurs in the first bus 10 side region is disposed on the second bus 20 side of the bus contact breaker 30, and the bus contact disconnection is performed. A current transformer CTB2 for detecting a bus connection current IB2 when an accident occurs in the region on the second bus 20 side is disposed on the first bus 10 side of the generator 30. The first bus side region refers to equipment including the first bus 10 and the disconnectors 1LS1 to NLS1 on the first bus 10 side. The second bus side region refers to equipment including the second bus 20 and the disconnectors 1LS2 to NLS2 on the second bus 20 side.

  FIG. 2 is a block diagram showing the configuration of the busbar protection relay 1. The bus protection relay 1 takes in the line currents I1, I2,..., IN from the current transformers CT1 to CTN, CTB1 and CTB2, and the bus connection currents IB1 and IB2 and is connected to the lines L1 to LN. The signal from each pallet contact (either a contact or b contact) for each of the disconnectors 1LS1 to NLS1 on the first bus 10 side and the disconnectors 1LS2 to NLS2 on the second bus 20 side is taken in as an LS pallet condition. Based on these input signals, the first bus 10 is protected, the second bus 20 is protected, and the area including both the buses 10 and 20 is collectively protected. The failure of the first bus 10 or the second bus 20 It has a function to detect and isolate the fault location.

  The busbar protection relay 1 includes a data converter 2, a pallet condition input circuit 3, a line switching circuit 4, a protection arithmetic circuit 5, an output circuit 6, and an LS monitoring control circuit 7. The data converter 2 performs analog / digital conversion on the input line currents I1 to IN and the bus connection currents IB1 and IB2 and outputs the result as digital line current data (hereinafter abbreviated as line current data). The pallet condition input circuit 3 is composed of a DI (digital input) circuit, and inputs a pallet contact signal composed only of a contact signals of the disconnectors 1LS1 to NLS1, 1LS2 to NLS2 as LS pallet conditions, and monitors LS. Output to the control circuit 7.

  As shown in FIG. 3, the line switching circuit 4 is composed of switching switches 411 to 4N2 corresponding to the number of disconnectors 1LS1, 1LS2, 2LS1, 2LS2,..., NLS1, NLS2 connected to the lines L1 to LN. In each changeover switch, whether or not to output the line current data I1 to IN from the data converter 2 is switched based on the output of the LS monitoring control circuit 7. As shown in FIG. 3, the protection arithmetic circuit 5 is configured to perform a protection operation on the first bus side region and a second bus based on the bus connection current data IB1 and IB2 and the line current data I1 to IN from the line switching circuit 4. The first bus internal fault signal DO # 1bus and the second bus indicating that the first bus side area is an internal fault by performing the protection calculation of the side area and the batch bus protection calculation including the first and second bus sides. A second bus internal fault signal DO # 2bus indicating that the bus side area is an internal fault is output to the output circuit 6, and the bus connection current data IB1 and IB2 and the line current data I1 to IN from the line switching circuit 4 are output. To determine abnormal LS connection such as abnormal pallet contact connection in each protection area (first bus side area, second bus side area, batch area including first and second bus side), and 3 Abnormal LS connection detection signal Is output to the LS monitoring control circuit 7. The output circuit 6 is composed of a DO (digital output) circuit, and inputs the first bus internal fault signal DO # 1bus and the second bus internal fault signal DO # 2bus, and cuts off the trip signal that separates each bus by that signal. Output to the instrument.

  The LS monitoring control circuit 7 controls on / off of each changeover switch of the line switching circuit based on the LS palette condition input via the palette condition input circuit 3 and the three abnormal LS connection detection signals output from the protection arithmetic circuit 5. Switching signals (first bus selection signal SL # 1bus, second bus selection signal SL # 2bus) are output.

  FIG. 3 shows the internal configuration of the line switching circuit 4 and the protection arithmetic circuit 5. Line current data I <b> 1 to IN digitally converted by the data converter 2 is input to the line switching circuit 4. The line switch circuit 4 includes switch switches 411, 412, .about.4N1, and 4N2 corresponding to the number of disconnectors 1LS1, 1LS2,..., NLS1, and NLS2, and each switch 411 to 4N2 is controlled by LS monitoring control. It is turned on / off based on a switching signal from the circuit 7. The changeover switch 411 corresponds to the disconnector 1LS1 on the first bus 10 side, and receives line current data I1. The changeover switch 412 corresponds to the disconnector 1LS2 on the second bus 20 side, and receives line current data I1. The changeover switch 421 corresponds to the disconnector 2LS1 on the first bus 10 side, and receives line current data I2. The changeover switch 422 corresponds to the disconnector 2LS2 on the second bus 20 side, and receives line current data I2. The changeover switch 4N1 corresponds to the disconnector NLS1 on the first bus 10 side, and receives line current data IN. The changeover switch 4N2 corresponds to the disconnector NLS2 on the second bus 20 side, and receives line current data IN. These change-over switches 411 to 4N2 are turned on / off in response to the closing / opening of the corresponding disconnector by the switching signal from the LS monitoring control circuit 7 when the device is normal.

  The protection arithmetic circuit 5 includes a collective bus protection arithmetic circuit 51, a first bus protection arithmetic circuit 52, and a second bus protection arithmetic circuit 53. The collective bus protection arithmetic circuit 51 receives all the line current data I1 to IN except the bus contact current data IB1 and IB2, and uses the first bus 10 side and the second bus 20 side as protection areas. Execute. The first bus protection arithmetic circuit 52 passes through the bus contact current data IB1 and the changeover switches 411, 421,..., 4N1, thereby closing the pallet among the pallet contacts of the disconnectors 1LS1 to NLS1 on the first bus 10 side. The line current data corresponding to the contact is used as an input, and a predetermined protection operation is performed using the first bus 10 side area as a protection area. The second bus protection arithmetic circuit 53 is a closed pallet contact among the pallet contacts of the disconnectors 1LS2 to NLS2 on the second bus 10 side by passing through the bus connection current IB2 and the changeover switches 412, 422, ..., 4N2. The line current data corresponding to is input, and a predetermined protection operation is executed using the second bus 20 side area as a protection area.

The collective bus protection arithmetic circuit 51 calculates the difference current Idc by adding the total line current data I1 to IN taken in accordance with the following equation (1) to calculate the effective value Idcrms of the difference current Idc. Further, the collective bus protection arithmetic circuit 51 obtains an effective value Ircrms of the suppression current Irc according to the following equation (2). Equation (2) indicates that the maximum value of effective values I1rms, I2rms,..., INrms of each line current I1, I2,.
Idc = I1 + I2 +... + IN (1)
Ircrms = MAX (I1rms, I2rms,..., INrms) (2)

And in the collective bus protection arithmetic circuit 51,
Idcrms ≧ K1, and Idcrms ≧ ρc · Ircrms
When the relationship of K1: set value and ρc: ratio set value is established, it is determined that the accident is in the protection area (both the first bus 10 side and the second bus 20 side), and a trip command TPt is generated. .

In the collective bus protection arithmetic circuit 51,
Idcrms ≧ K2 (K2 <K1)
Is established under a steady state, it is determined that an abnormal LS connection such as an abnormal pallet contact connection has occurred in the protection region, and an abnormal LS connection detection signal Idc> is output.

Next, the first bus protection arithmetic circuit 52 adds the vector of the bus contact current data IB1 and each line current data connected to the first bus 10 side as shown in the following equation (3), thereby obtaining the difference current. Id1 is obtained, and an effective value Id1rms of the difference current Id1 is calculated. Further, the first bus protection arithmetic circuit 52 obtains the effective value Ir1rms of the suppression current Ir1 according to the following equation (4). In the following formulas (3) and (4), it is assumed that only the lines corresponding to the line current data I1 and I2 are connected to the first bus.
Id1 = IB1 + I1 + I2 (3)
Ir1rms = MAX (IB1, I1rms, I2rms) (4)

In the first bus protection arithmetic circuit 52,
Id1rms ≧ K3 and Id1rms ≧ ρ1 · Ir1rms
When the relationship of K3: set value and ρ1: ratio set value is established, it is determined that the accident is in the protection area (first bus 10 side), and a trip command TP1 is generated. In the first bus protection arithmetic circuit 52,
Id1rms ≧ K4 (K3 <K4)
Is established under a steady state, it is determined that an abnormal LS connection such as an abnormal pallet contact connection has occurred on the first bus 10 side, and an abnormal LS connection detection signal Id1> is output.

In the second bus protection arithmetic circuit 53, the difference current Id2 is obtained by vector addition of the bus connection current data IB2 and the line current connected to the second bus 20 as shown in the following equation (5). The effective value Id2rms of the difference current Id2 is calculated. Further, the second bus protection arithmetic circuit 53 obtains the effective value Ir2rms of the suppression current Ir2 according to the following equation (6). In the following formulas (5) and (6), it is assumed that only the lines corresponding to the line currents I3, I4,..., IN except the line currents I1 and I2 are connected to the first bus.
Id2 = IB2 + I3 + I4 + ... + IN (5)
Ir2rms = MAX (IB2, I3rms, I4rms,..., INrms) (6)

In the second bus protection arithmetic circuit 53,
Id2rms ≧ K5 and Id2rms ≧ ρ2 · Ir2rms
When the relationship of K5: set value and ρ2: ratio set value is established, it is determined that the accident is in the protection area (second bus 20 side), and a trip command TP2 is generated. In the second bus protection arithmetic circuit 53,
Id2rms ≧ K6 (K5 <K6)
Is established under a steady state, it is determined that an abnormal LS connection such as an abnormal pallet contact connection has occurred on the second bus 20 side, and an abnormal LS connection detection signal Id2> is output.

  The AND circuit 54 calculates the logical product of the trip command TPt from the collective bus protection arithmetic circuit 51 and the trip command TP1 from the first bus protection arithmetic circuit 52, and outputs the first bus internal fault signal DO # 1bus. . The first bus internal fault signal DO # 1bus is turned on when the first bus side has an internal fault. By this signal, the circuit breaker CB and the bus bar breaker 30 connected to the first bus 10 are connected. Open controlled.

  The AND circuit 55 calculates the logical product of the trip command TPt from the collective bus protection arithmetic circuit 51 and the trip command TP2 from the second bus protection arithmetic circuit 52, and outputs the second bus internal fault signal DO # 2bus. . This second bus internal fault signal DO # 2bus is turned on when the second bus side has an internal fault, and the circuit breaker CB and the bus bar breaker 30 connected to the second bus 20 by this signal are turned on. Open controlled.

  Here, the collective bus protection operation circuit 51 has a feature that it does not erroneously output even if an LS abnormality occurs because it is a protection operation that takes in all the line current data I1 to IN regardless of the LS condition of the disconnector.

  FIG. 4 shows an internal configuration example of the LS monitoring control circuit 7 in the first embodiment. The configuration shown in FIG. 4 shows an internal configuration corresponding to a certain line, and the LS monitoring control circuit 7 has a plurality of configurations similar to those in FIG. 4 corresponding to a plurality of lines. The LS1a signal is an input signal from one pallet contact (a contact) of the disconnector on the first bus side of a certain line, and the LS2a signal is one pallet of the disconnector on the second bus side of the same line. It is an input signal from a contact (a contact). In addition, when inputting the signal from the pallet b contact of a disconnector, it can respond by using the reverse signal.

  The LS supervisory control circuit 7 includes delay circuits A06 and A07 that perform signal delay of the T1 time period, one-shot circuits A08 and A09 that generate a one-shot pulse of T2 time, and an AND circuit A10 that ANDs two signals. A11, A12, OR circuit A13 that takes the logical sum of the two signals, AND circuits A14 and A20 that take the logical product of the three signals, AND circuits A15 and A17 that take the logical product of the two signals, and NOT that performs the signal inversion A circuit A19, a delay circuit A21 that delays the signal in the T3 period, a set-reset type flip-flops A16, A18, and A22, a delay circuit A23 that delays the signal in the T4 period, and an AND circuit that takes the logical product of the two signals A25, A26, an OR circuit A27 that takes a logical sum of two signals, and an AND circuit A28 that takes a logical product of two signals. In the figure, the O symbol at the AND circuit input indicates the logical product of the signal and NOT (inverted signal).

  Delay circuits A06 and A07 respectively delay the rising of the first bus pallet contact signal LS1a signal and the second bus pallet contact signal LS2a signal by a predetermined time T1. Output. When the LS1a signal and the LS2a signal fall (open change), the delay circuits A06 and A07 output the fall without delay. The delay time T1 of the delay circuits A06, A07 is such that the abnormal LS connection detection signals Idc>, Id1>, Id2> that are the sources of signals to be input to the inverting inputs of the AND circuits A25, A26, A28 are LS1a signals, Since it is delayed compared to the LS2a signal, the time is set in consideration of the delay. For example, T1 is set to 200 msec or more.

  The one-shot circuit A08 detects the rising edge of the LS1a signal, and generates a one-shot pulse having a predetermined time width T2 after the detection. The one-shot circuit A09 detects the rising edge of the LS2a signal, and generates a one-shot pulse having a predetermined time width T2 after the detection. As this pulse width T2, abnormal LS connection detection signals Idc>, Id1>, Id2>, which are the sources of signals input to one input side of the AND circuits A15, A17, are delayed as compared with the LS1a signal and the LS2a signal. Therefore, the time is set in consideration of the delay. T2 is set to 100 msec or more, and T1> T2.

  The AND circuit A10 receives the LS1a signal and the LS2a signal, and the AND circuit A10 is configured such that both the disconnector on the first bus side and the disconnector on the second bus side of the same line are closed. A disconnector bridge state (hereinafter referred to as LS bridge) connected to both the first bus 10 and the second bus is detected. The output of the one-shot circuit A08 and the output of the AND circuit A10 are input to the AND circuit A11. When the LS bridge is generated by the rising of the pallet contact signal LS1a signal on the first bus 10 side, A pulse signal having a time width T2 is output. The output of the one-shot circuit A09 and the output of the AND circuit A10 are input to the AND circuit A12. When the LS bridge is generated by the rising of the pallet contact signal LS2a signal on the second bus 20 side, A pulse signal having a time width T2 is output.

  The OR circuit A13 sets the output to ‘1’ when either the abnormal LS connection detection signal Id1> on the first bus side or the abnormal LS connection detection signal Id2> on the second bus side is ‘1’. The AND circuit A14 outputs “1” when the LS bridge is detected by the AND circuit A10 and none of the three abnormal LS connection detection signals Idc>, Id1>, Id2> is output. Thus, although the main contact of the disconnector is normal, an abnormality is detected in which the pallet contact of the disconnector is accidentally closed for some reason. Further, the AND circuit A20 is configured such that when the LS bridge is detected by the AND circuit A10, the abnormal LS connection detection signal Idc> is not output, and either Id1> or Id2> is output. The output is set to “1”, so that both the main contact of the disconnector on the first bus side and the main contact of the disconnector on the second bus side of the same line are actually closed. Find the bridge correctly. That is, the state where Idc> is ‘0’ and Id1> or Id2> is ‘1’ occurs only when a change in the main contact of the disconnector LS actually occurs. The delay circuit A21 is a circuit in which the output becomes “1” when the output of the AND circuit A21 is inputted and the input is “1” for a predetermined time T3 or more after the input becomes “1”. Since the delay circuit A21 performs a delay for ignoring the output of the AND circuit A20 generated at the time of normal LS switching shown in FIG. 5, T3 is set to, for example, 100 msec or more. T1> T3 is set. Further, when the delay circuit A23 detects the LS bridge by the AND circuit A10, the delay circuit A23 outputs an LS bridge alarm T4 hours after the detection time. T4 is set to about 10 seconds, for example.

  Next, the operation of the LS monitoring control circuit 7 when the disconnector is normally switched will be described with reference to FIG. The main contact of the disconnector on the first bus side of the line is kept closed and the LS1a signal connected to the first bus 10 side is “1”, and at time t0, Assume that the main contact of the disconnector on the 2-bus side is closed and the LS2a signal rises to “1”, and an LS bridge is generated. As a result, at time t0, a one-shot pulse having a time width T2 is generated from the one-shot circuit A09, the output of the AND circuit A10 becomes ‘1’, and the output of the AND circuit A12 becomes ‘1’. At this time t0, the three abnormal LS connection detection signals Idc>, Id1>, Id2> are all “0”, and the output of the AND circuit A14 is also “1”. Therefore, the logical product condition of the AND circuit A17 is satisfied, and the output of the flip-flop A18 rises to '1' at time t0. The LS bridge outputs an abnormal LS connection detection signal Id1> or Id2> from the first bus protection arithmetic circuit 51 or 52 with a slight delay. Thus, at time t1, the output of the OR circuit A13 becomes “1”, and the output of the AND circuit A20 also becomes “1”. However, in a normal LS switching operation, the output of the OR circuit A13 is as described later. Since the signal falls to “0” before the delay time T3 of the delay circuit A21, the flip-flop A22 is not set.

  At time t2, when the main contact of the disconnector on the first bus side of the line is opened and the line is disconnected from the first bus 10 side, the LS1a signal correspondingly becomes “0” at time t2. It becomes. As a result, the first bus selection signal SL # 1bus as the switching signal output from the OR circuit A27 becomes “0” at time t2, and the first bus corresponding to the line among the changeover switches in the line switching circuit 4 is displayed. The changeover switch corresponding to the side is turned off, and the line current data is not input to the first bus protection arithmetic circuit 52 thereafter. Further, when the LS1a signal becomes “0” at time t2, the output of the AND circuit A10 becomes “0” at time t2, the output of the NOT circuit A19 becomes “1”, and the output of the flip-flop A18 becomes Reset at time t2.

  Since the LS bridge has been eliminated, the abnormal LS connection detection signal Id1> or Id2> becomes “0” with a slight delay. On the other hand, at time t0, at the time t3 when the LS2a signal becomes “1” for T1 time, the output of the delay circuit A07 rises to “1”, thereby the second bus line output from the AND circuit A28. The selection signal SL # 2bus becomes “1” at time t3, and among the changeover switches in the line changeover circuit 4, the changeover switch corresponding to the line and corresponding to the second bus side is turned on, and the line current data is Thereafter, it is input to the 2-bus protection circuit 52. When the LS bridge is detected by the AND circuit A10 and the LS bridge duration time is longer than T4 hours, the LS bridge alarm is output from the delay circuit A23 after T4 hours, so that no alarm is output at the time of normal LS switching. Thus, T4 is set long.

  Next, with reference to FIG. 6, the operation of the LS monitoring control circuit 7 when the pallet contact of the disconnector is abnormal will be described. In this case, first, the line is connected to the first bus 10 (that is, the LS1a signal is closed ('1') and the LS2a signal is opened ('0')). Assume that the main contact of the disconnector remains unchanged, and that the pallet contact is accidentally closed ('1') at time t0. Therefore, the LS2a signal rises to '1' at time t0, and an LS bridge is generated. As a result, at time t0, a one-shot pulse having a time width T2 is generated from the one-shot circuit A09, the output of the AND circuit A10 becomes ‘1’, and the output of the AND circuit A12 becomes ‘1’. At this time t0, the three abnormal LS connection detection signals Idc>, Id1>, Id2> are all “0”, and the output of the AND circuit A14 is also “1”. Therefore, the logical product condition of the AND circuit A17 is satisfied, and the output of the flip-flop A18 rises to '1' at time t0.

  Here, since the LS bridge detection in this case is an erroneous detection due to a pallet contact abnormality, the first bus protection arithmetic circuit 52 or the second bus protection arithmetic circuit 53 receives an abnormal LS connection detection signal Id1> or an abnormal LS connection. The detection signal Id2> is not output. Since the AND circuit A10 continues to detect the LS bridge until the pallet contact abnormality is recovered thereafter, the output of the flip-flop A18 is output from the NOT circuit A19 until the delay time T1 of the delay circuit A07 elapses from the time t0. It is not reset by the output of. Therefore, at time t3 when the time T1 has elapsed from time t0, the output of the delay circuit A07 rises to “1”, but the output of the flip-flop A18 continues to output “1”. The condition is not satisfied, and the second bus selection signal SL # 2bus output from the AND circuit A28 does not rise to “1”. As a result, the changeover switch corresponding to the line among the changeover switches in the line changeover circuit 4 is not turned on, and an erroneous protection calculation due to a pallet contact abnormality can be prevented. . Note that an LS bridge alarm is output from the delay circuit A23 after T4 time from the time point t0 when the LS bridge is detected by the AND circuit A10.

  As described above, when a pallet contact abnormality occurs, the AND circuit A10 erroneously recognizes that both the first bus and the second bus are bridged. In this case, the batch bus protection arithmetic circuit 51, the first bus protection Detection of false recognition by logic using the abnormal LS connection detection signals Idc>, Id1>, Id2> from the arithmetic circuit 52 and the second busbar protection arithmetic circuit 53 to prevent erroneous protection arithmetic and unnecessary bus switching Is prevented from occurring.

  Next, with reference to FIG. 7, the operation of the LS monitoring control circuit 7 when the pallet contact is not abnormal but the bridge of both the first bus and the second bus is actually generated will be described. The main contact of the disconnector on the first bus side of the line is kept closed and the LS1a signal connected to the first bus 10 side is “1”, and at time t0, Assume that the main contact of the disconnector on the 2-bus side is closed and the LS2a signal rises to “1”, and an LS bridge is generated. As a result, at time t0, a one-shot pulse having a time width T2 is generated from the one-shot circuit A09, the output of the AND circuit A10 becomes ‘1’, and the output of the AND circuit A12 becomes ‘1’. At this time t0, the three abnormal LS connection detection signals Idc>, Id1>, Id2> are all “0”, and the output of the AND circuit A14 is also “1”. Therefore, the logical product condition of the AND circuit A17 is satisfied, and the output of the flip-flop A18 rises to '1' at time t0. The LS bridge outputs an abnormal LS connection detection signal Id1> or Id2> from the first bus protection arithmetic circuit 51 or 52 with a slight delay. As a result, the output of the OR circuit A13 becomes “1” and the output of the AND circuit A20 also becomes “1” at time t1, but the output of the AND circuit A20 is delayed by the time T3 by the delay circuit A21. At this time t1, the flip-flop A22 is not set.

  In this case, since it is a true LS bridge, the state in which the output of the OR circuit A13 becomes “1” and the AND circuit A20 becomes “1” is continued from the time t1 to the time t2 after the time T3. Therefore, at time t2, the output of the delay circuit A21 rises to “1”, and at the time t2, the output of the flip-flop A22 rises to “1”. Due to the rise of the output of the flip-flop A22, the first bus selection signal SL # 1bus output from the OR circuit A27 is forcibly set to “1” at time t2 regardless of the LS condition (this line). As a result, the '1' state is maintained), and the second bus selection signal SL # 2bus output from the AND circuit A28 is forcibly set to '0' at time t2 (this In the case of the line, as a result, the “0” state is maintained). Note that the output of the delay circuit A07 rises to '1' at time t3 after the lapse of T1 time from t0 due to the rise of the LS2a signal at time t0, but before that, the output of the flip-flop A22 rises. Due to the operation of the AND circuit A28, the second bus selection signal SL # 2bus does not rise to '1' after time t3. Further, in the case of such a true LS bridge, the first bus selection signal SL # 1bus for all lines becomes “1” and the second bus selection signal SL # 2bus becomes “0”. As a result, the abnormal LS connection detection signal Id1> or Id2> becomes “0” slightly later than the time point t2. In addition, an LS bridge alarm is output from the delay circuit A23 after T4 time from the time point t0 when the AND circuit A10 detects the LS bridge.

  In this way, in the case of a true LS bridge, after the LS bridge is detected and after the T3 time limit, the switch of each line in the line switching circuit 4 according to the LS condition is connected to, for example, the first bus side so that protection can be continued. It is composed.

  Thus, in the bus protection relay according to the first embodiment, in addition to the disconnector pallet condition, the differential current calculated by the collective bus protection arithmetic circuit 51, the first bus protection arithmetic circuit 52, and the second bus protection arithmetic circuit 53 Line currents I1 to IN input to the first bus protection arithmetic circuit 52 and the second bus protection arithmetic circuit 53 using the abnormal LS connection detection signals Idc>, Id1>, Id2> detected using Idc, Id1, Id2 Since the switching signals (first and second bus selection signals SL # 1bus, SL # 2bus) for selecting and switching are generated, it is possible to monitor the disconnector pallet condition with high reliability and disconnection. The number of input circuits in the container pallet condition can be reduced to one circuit (either a contact or b contact) per disconnector, which has the effect of reducing cost and size. When the disconnector pallet condition is closed, the change of the switching signals (first and second bus selection signals SL # 1bus and SL # 2bus) based on the change of the disconnector pallet condition is changed for a predetermined time T1. If there is no change in Id>, Id1>, Id2> during the predetermined time T1, it is determined that there is no change in the main contact of the disconnector, it is determined that the pallet condition is abnormal, and the pallet condition is closed. Since the change of the switching signal based on the change is prevented, an erroneous protection operation on the first bus side and the second bus side due to the LS pallet abnormality can be prevented, and correct bus protection can be continued.

Embodiment 2. FIG.
The second embodiment will be described with reference to FIGS. FIG. 8 shows an internal configuration example of the LS monitoring control circuit 7 ′ according to the second embodiment. In the first embodiment, when the disconnector pallet contact is closed, the connection under the DI input condition is delayed by the time limit T1, and the abnormal LS connection detection signal Idc>, Id1> is delayed while the connection is delayed by T1 time. , Id2> is not “1”, it is determined that the main contact of the disconnector has not changed, and the state before the change of the pallet contact is continued as it is. Then, when the pallet contact signal of the disconnector on one bus side from the DI input changes from “0” to “1”, the bus selection signal corresponding to the other bus side is temporarily set to “0” without delay, and The bus selection signal corresponding to the bus side in which the pallet contact signal is closed from “0” to “1” without delay is temporarily set to “1”. At this time, the abnormal LS connection detection signal Idc> is not detected, and Abnormal LS connection detection signal Id1> or Id2> is in the detection state In such a case, it is determined that the bus selection signal is erroneous and the original connection configuration is restored.

  The LS monitoring control circuit 7 ′ shown in FIG. 8 also has an internal configuration corresponding to one certain line, as in FIG. 8 that achieve functions equivalent to those of the components shown in FIG. 4 are denoted by the same reference numerals. In FIG. 8, one-shot circuits A08, A09 that generate a one-shot pulse of time T2, AND circuits A10, A11, A12 that take the logical product of two signals, an OR circuit A13 that takes the logical sum of the two signals, 3 An AND circuit A20 that takes a logical product of signals, a NOT circuit A19 that performs signal inversion, a delay circuit A21 that performs signal delay in the T3 period, a set-reset type flip-flop A22, and a delay circuit that performs signal delay in the T4 period The A23, the OR circuit A27 that takes the logical sum of the two signals, and the AND circuit A28 that takes the logical product of the two signals achieve the same function as shown in FIG.

  In the LS monitoring control circuit 7 ′ shown in FIG. 8, the delay circuits A06 and A07 and the AND circuit A14 shown in FIG. 4 are deleted, and AND circuits A31 and A32 and OR circuits A33 and A34 are added. . Further, the AND circuits A40 and A41 in FIG. 8 have different input signals from the AND circuits A25 and A26 in FIG. Also, the AND circuits A42 and A43 in FIG. 8 have different input signals from the AND circuits A15 and A17 in FIG. The outputs of the AND circuits A42 and A43 are input to the flip-flops A44 and A46, respectively.

  The AND circuit A20 receives the output of the AND circuit A10 that detects the LS bridge, the output of the OR circuit A13 to which the abnormal LS connection detection signals Id1> and Id2> are input, and the inverted signal of the abnormal LS connection detection signal Idc>. Thus, the AND circuit A20 raises its output to “1” when there is no Idc> output and there is an output of Id1> or Id2> under the LS bridge detection state.

  The flip-flop A44 is when the LS bridge is generated by the rising of the pallet contact signal LS1a signal on the first bus 10 side, the abnormal LS connection detection signal Idc> is in the undetected state, and the abnormal LS connection detection signal Id1> Alternatively, when Id2> is in the detection state, the output is raised to “1”, and when the end of the LS bridge is detected by the AND circuit A10, the output is lowered to “0”. The flip-flop A46 is when the LS bridge is generated by the rising of the pallet contact signal LS2a signal on the second bus 20 side, and the abnormal LS connection detection signal Idc> is in the undetected state and the abnormal LS connection detection signal Id1>. Alternatively, when Id2> is in the detection state, the output is raised to “1”, and when the end of the LS bridge is detected by the AND circuit A10, the output is lowered to “0”.

  The AND circuit A40 receives the inverted output of the OR circuit A33, and prevents the palette contact signal LS1a signal from passing when the output of the OR circuit A33 is 1. The output of the OR circuit A33 becomes ‘1’ when the output of the flip-flop A44 becomes ‘1’ or when the output of the AND circuit A31 becomes ‘1’. The AND circuit A31 takes the logical product of the output of the AND circuit A12 and the inverted output of the flip-flop A46, so that the LS bridge is generated by the rise of the pallet contact signal LS2a signal on the second bus 20 side. Thus, when the output of the flip-flop A46 is “0”, it becomes “1”.

  The AND circuit A41 receives the inverted output of the OR circuit A34, thereby preventing the palette contact signal LS2a from passing when the output of the OR circuit A34 is 1. The output of the OR circuit A34 becomes ‘1’ when the output of the flip-flop A46 becomes ‘1’ or when the output of the AND circuit A32 becomes ‘1’. The AND circuit A32 takes the logical product of the output of the AND circuit A11 and the inverted output of the flip-flop A44, so that the LS bridge is generated by the rise of the pallet contact signal LS1a signal on the first bus 20 side. Thus, when the output of the flip-flop A44 is “0”, it becomes “1”.

  Next, with reference to FIG. 9, the operation of the LS monitoring control circuit 7 ′ when the disconnector is normally switched will be described. The main contact of the disconnector on the first bus side of the line is kept closed and the LS1a signal connected to the first bus 10 side is “1”, and at time t0, Assume that the main contact of the disconnector on the 2-bus side is closed, the LS2a signal rises to '1', and an LS bridge is generated. As a result, at time t0, a one-shot pulse having a time width T2 is generated from the one-shot circuit A09, the output of the AND circuit A10 becomes ‘1’, and the output of the AND circuit A12 becomes ‘1’. At time t0, since all of the three abnormal LS connection detection signals Idc>, Id1>, Id2> are “0”, the output of the AND circuit A20 remains “0”. Therefore, the logical product condition of the AND circuits A42 and A43 is not satisfied, and the outputs of the flip-flops A44 and A46 remain '0' at time t0.

  Accordingly, the output of the AND circuit A31 rises to “1” at time t0, and the output of the AND circuit A31 is input to the inverting input of the AND circuit A40 via the OR circuit A33 at time t0. As a result, the passage of the pallet contact signal LS1a is blocked at time t0, and the output of the AND circuit A40 falls to '0' at time t0. As a result, the first bus selection signal SL # 1bus output from the OR circuit A27 becomes “0” at time t0. On the other hand, since the output of the AND circuit A11 remains “0” at time t0, the output of the AND circuit A32 also remains “0”. Further, at time t0, the output of the flip-flop A46 is “0”. Therefore, at time t0, the output of the OR circuit A34 also remains “0”, and this signal is input to the inverting input of the AND circuit A41. Therefore, the AND condition on the AND circuit A41 side is satisfied at time t0, and the palette contact signal LS2a that rises at time t0 passes through the AND circuit A41 as it is at time t0. As a result, the second bus selection signal SL # 2bus output from the AND circuit A28 becomes “1” at time t0.

  Also, the abnormal LS connection detection signal Id1> or Id2> is output with a slight delay from the first bus protection arithmetic circuit 52 or 53 by the LS bridge generated at time t0. As a result, at time t1, the output of the OR circuit A13 becomes “1”. Therefore, at time t1, the output of the AND circuit A20 becomes “1”, and the output of the AND circuit A43 also becomes “1”. Thereby, at time t1, the output of the flip-flop A46 rises to “1”, the output of the AND circuit 31 falls to “0”, the output of the OR circuit A33 falls to “0”, and the output of the OR circuit A34 Rises to '1'. As a result, the passage of the pallet contact signal LS1a is permitted at time t1, and the output of the AND circuit A40 rises to “1” at time t1. Therefore, the first bus selection signal SL # 1bus output from the OR circuit A27 becomes “1” at time t1. On the other hand, the passage of the pallet contact signal LS2a is blocked at time t1, and the output of the AND circuit A40 falls to '0' at time t1. As a result, the second bus selection signal SL # 2bus output from the AND circuit A28 becomes “0” at time t1. At time t1, the output of the AND circuit A20 becomes “1”, but in a normal LS switching operation, the output of the OR circuit A13 is “0” before the delay time T3 of the delay circuit A21, as will be described later. Therefore, flip-flop A22 is never set.

  At time t2, when the main contact of the disconnector on the first bus side of the line is opened and the line is disconnected from the first bus 10 side, the LS1a signal correspondingly becomes “0” at time t2. It becomes. As a result, the first bus selection signal SL # 1bus output from the OR circuit A27 becomes “0” at time t2. Further, when the LS1a signal becomes “0” at time t2, the output of the AND circuit A10 becomes “0” at time t2, the output of the NOT circuit A19 becomes “1”, and the output of the flip-flop A46 becomes Reset at time t2. As a result, the output of the OR circuit A34 becomes “0” at time t2, the logical product condition on the AND circuit A41 side is satisfied, and the palette contact signal LS2a passes through the AND circuit A41 as it is after time t2. Become. As a result, the second bus selection signal SL # 2bus output from the AND circuit A28 becomes “1” after time t2. Since the LS bridge has been eliminated, the abnormal LS connection detection signal Id1> or Id2> output from the first bus protection arithmetic circuit 52 or 53 becomes “0” with a slight delay. The output of the OR circuit A13 is also “0”.

  Next, the operation of the LS monitoring control circuit 7 'when the pallet contact of the disconnector is abnormal will be described with reference to FIG. In this case, as in FIG. 6, the first bus 10 is first connected (ie, the LS1a signal is closed ('1') and the LS2a signal is open ('0')). It is assumed that the main contact of the disconnector on the 2 bus 20 side remains as it is, and the pallet contact on the 2nd bus 20 is accidentally closed ('1') at time t0. Therefore, the LS2a signal rises to '1' at time t0, and an LS bridge is generated. As a result, at time t0, a one-shot pulse having a time width T2 is generated from the one-shot circuit A09, the output of the AND circuit A10 becomes ‘1’, and the output of the AND circuit A12 becomes ‘1’. At time t0, since all of the three abnormal LS connection detection signals Idc>, Id1>, Id2> are “0”, the output of the AND circuit A20 remains “0”. Therefore, the logical product condition of the AND circuits A42 and A43 is not satisfied, and the outputs of the flip-flops A44 and A46 remain '0' at time t0.

  Accordingly, the output of the AND circuit A31 rises to “1” at time t0, and the output of the AND circuit A31 is input to the inverting input of the AND circuit A40 via the OR circuit A33 at time t0. As a result, the passage of the pallet contact signal LS1a is blocked at time t0, and the output of the AND circuit A40 falls to '0' at time t0. As a result, the first bus selection signal SL # 1bus output from the OR circuit A27 becomes “0” at time t0. On the other hand, since the output of the AND circuit A11 remains “0” at time t0, the output of the AND circuit A32 also remains “0”. Further, at time t0, the output of the flip-flop A46 is “0”. Therefore, at time t0, the output of the OR circuit A34 also remains “0”, and this signal is input to the inverting input of the AND circuit A41. Therefore, the AND condition on the AND circuit A41 side is satisfied at time t0, and the palette contact signal LS2a that rises at time t0 passes through the AND circuit A41 as it is at time t0. As a result, the second bus selection signal SL # 2bus output from the AND circuit A28 becomes “1” at time t0.

  By switching the first bus selection signal SL # 1bus and the second bus selection signal SL # 2bus at this time t0 (the first bus side that is actually connected is turned off, and the second bus side that is not actually connected) Of the changeover switch in the line changeover circuit 4 is turned off, and the changeover switch corresponding to the first bus side is turned off, and the changeover switch corresponding to the second bus side is turned on. The current data of the line is not input to the first bus protection arithmetic circuit 52 but is input to the second bus protection arithmetic circuit 53. As a result, at time t1 slightly delayed from time t0, the first bus protection arithmetic circuit 52 or the second bus protection arithmetic circuit 53 outputs an abnormal LS connection detection signal Id1> or an abnormal LS connection detection signal Id2>. At time t1, the output of the OR circuit A13 becomes “1”, the output of the AND circuit A20 becomes “1”, and the output of the AND circuit A43 also becomes “1”. Thereby, at time t1, the output of the flip-flop A46 rises to “1”, the output of the AND circuit 31 falls to “0”, the output of the OR circuit A33 falls to “0”, and the output of the OR circuit A34 Rises to '1'. As a result, the passage of the pallet contact signal LS1a is permitted at time t1, and the output of the AND circuit A40 rises to “1” at time t1. Therefore, the first bus selection signal SL # 1bus output from the OR circuit A27 becomes “1” at time t1. On the other hand, the passage of the pallet contact signal LS2a is blocked at time t1, and the output of the AND circuit A40 falls to '0' at time t1. As a result, the second bus selection signal SL # 2bus output from the AND circuit A28 becomes “0” at time t1.

  By switching the first bus selection signal SL # 1bus and the second bus selection signal SL # 2bus at this time t1, the first bus side that is actually connected is turned on, and the second bus side that is not actually connected The abnormal LS connection detection signals Id1> and Id2> output from the first bus protection arithmetic circuit 52 or the second bus protection arithmetic circuit 53 at time t2 slightly delayed from time t1 are The output of the OR circuit A13 becomes “0”. On the other hand, since the AND circuit A10 continues to detect the LS bridge until the pallet contact abnormality is recovered, the output of the flip-flop A46 is not reset by the output of the NOT circuit A19. At time t1, the output of the AND circuit A20 becomes “1”. In this case, the output of the OR circuit A13 falls to “0” before the delay time T3 of the delay circuit A21. A22 is never set. In addition, an LS bridge alarm is output from the delay circuit A23 after T4 time from the time point t0 when the AND circuit A10 detects the LS bridge.

  Next, with reference to FIG. 11, the operation of the LS monitoring control circuit 7 ′ when the LS bridges of both the first bus and the second bus are actually generated will be described as in FIG. The main contact of the disconnector on the first bus side of the line is kept closed and the LS1a signal connected to the first bus 10 side is “1”, and at time t0, Assume that the main contact of the disconnector on the 2-bus side is closed and the LS2a signal rises to “1”, and an LS bridge is generated. Thus, as in the case shown in FIGS. 9 and 10, the pallet contact signal LS1a is blocked from passing at time t0, and the output of the AND circuit A40 falls to '0' at time t0. The first bus selection signal SL # 1bus output from A27 becomes “0” at time t0. On the other hand, the AND condition on the AND circuit A41 side is satisfied at time t0, and the pallet contact signal LS2a rising at time t0 passes through the AND circuit A41 as it is at time t0. As a result, the second bus selection signal SL # 2bus output from the AND circuit A28 becomes “1” at time t0.

  Also, the abnormal LS connection detection signal Id1> or Id2> is output with a slight delay from the first bus protection arithmetic circuit 52 or 53 by the LS bridge generated at time t0. As a result, at time t1, the output of the OR circuit A13 becomes “1”. Therefore, at time t1, the output of the AND circuit A20 becomes “1”, and the output of the AND circuit A43 also becomes “1”. Thereby, at time t1, the output of the flip-flop A46 rises to “1”, the output of the AND circuit A31 falls to “0”, the output of the OR circuit A33 falls to “0”, and the output of the OR circuit A34 Rises to '1'. As a result, the passage of the pallet contact signal LS1a is permitted at time t1, and the output of the AND circuit A40 rises to “1” at time t1. Therefore, the first bus selection signal SL # 2bus output from the OR circuit A27 becomes “1” at time t1. On the other hand, since the output of the OR circuit A34 rises to “1”, the passage of the pallet contact signal LS2a is blocked at time t1, and the output of the AND circuit A41 falls to “0” at time t1. As a result, the second bus selection signal SL # 2bus output from the AND circuit A28 becomes “0” at time t1.

  On the other hand, since the AND circuit A10 continues to detect the LS bridge thereafter, the output of the flip-flop A46 is not reset by the output of the NOT circuit A19, and thereafter, the first bus selection signal SL # 2bus is 1 is maintained, and the second bus selection signal SL # 2bus is maintained at “0”. Further, in this case, since it is a true LS bridge, the state in which the output of the OR circuit A13 becomes “1” and the AND circuit A20 becomes “1” is from the time t1 to the time point t4 that is left for T3 time. Therefore, at time t4, the output of the delay circuit A21 rises to “1”, and at the time t4, the output of the flip-flop A22 rises to “1”. Due to the rise of the output of the flip-flop A22, the first bus selection signal SL # 1bus output from the OR circuit A27 is forcibly set to “1” at time t4 regardless of the LS condition (this line). As a result, the '1' state is maintained), and the second bus selection signal SL # 2bus output from the AND circuit A28 is forcibly set to '0' at time t4 (this In the case of the line, as a result, the “0” state is maintained). Further, in the case of such a true LS bridge, the first bus selection signal SL # 1bus for all lines becomes “1” and the second bus selection signal SL # 2bus becomes “0”. As a result, the abnormal LS connection detection signal Id1> or Id2> becomes “0” slightly later than the time point t4. In addition, an LS bridge alarm is output from the delay circuit A23 after T4 time from the time point t0 when the AND circuit A10 detects the LS bridge.

  As described above, according to the second embodiment, in addition to the disconnector pallet condition, the abnormal LS connection detection signals Idc>, Id1>, Id2> are used to switch the switching signals (first and second second bus selection signals SL). # 1bus, SL # 2bus), as in the first embodiment, the disconnector pallet condition can be monitored with high reliability, and the number of input circuits for the disconnector pallet condition can be set to one disconnector. It can be reduced to one circuit per contact (either a contact or b contact), and there is an effect of cost reduction and downsizing. In addition, when the disconnector pallet condition is closed, a switching signal is immediately output so that one bus side that has changed and selected is not selected, and then Idc> is not detected, but Id1> Or Id2> is detected, it is determined that the LS pallet is abnormal, and the switching signal is returned to the state immediately before the closing change. Side protection operation is prevented and correct busbar protection can be continued. Further, if the state of detecting Idc> not detected and Id1> or Id2> continues for a predetermined time T3 or more, it is determined that the LS pallet is not abnormal and is caused by a true bridge of the disconnector, and the switching signal of the LS pallet condition The control is stopped and all lines are connected to the first bus side, for example, so that the protection can be continued.

Embodiment 3 FIG.
Next, Embodiment 3 of the present invention will be described with reference to FIG. In the first and second embodiments, the case of preventing erroneous bridge detection due to a pallet contact abnormality of the disconnector (LS) has been described. It tries to prevent recognition.

  First, the line is connected to the first bus 10 (that is, the pallet contact signal LS1a is closed ('1') and the pallet contact signal LS2a is opened ('0')), and corresponds to the pallet contact signal LS1a. When the pallet contact signal LS1a is accidentally opened ('0') while the main contact is closed, both buses of the first bus 10 and the second bus 20 are opened, and the corresponding line is not connected to both buses. It will be mistakenly recognized as having become. That is, in the line connected to one of the bus lines, when the disconnector on the connection side is changed to open, this line is originally disconnected from the bus line, so the line current flowing through the line becomes zero. Therefore, in the third embodiment, when the line current is not zero, the line whose LS has been changed as a misrecognition is reconnected and the protection is continued.

  The current detection circuit A50 is provided for each line, and outputs a detection signal IN> when the current flowing through the line is greater than or equal to a set value. The NOT circuit A51 outputs a detection signal when the pallet contact signal LS1a is open. The NOT circuit A52 outputs a detection signal when the pallet contact signal LS2a is open. The one-shot circuit A53 detects the rising edge of the NOT circuit A51, and outputs a one-shot pulse having a predetermined pulse width T5 from this detection time. The one-shot circuit A54 detects the rising edge of the NOT circuit A52, and outputs a one-shot pulse having a predetermined pulse width T5 from this detection time. The AND circuit A55 outputs a detection signal when both LS1a and LS2a are open, that is, when both LS are open.

  The AND circuit A56 outputs a detection signal when both LS1a and LS2a are open and the current of the corresponding line is equal to or greater than a predetermined value. The delay circuit A57 is a circuit in which the output becomes “1” when the output of the AND circuit A56 is input, and the input is “1” for a predetermined time T6 or more after the input becomes “1”. T6 is set in consideration of the time difference between the time when LS1a and LS2a are input to the DI circuit 3 and the time when the detection signal IN> from the current detection circuit A50 is input. Note that T5> T6 is set. That is, the erroneous recognition of both LS open due to the pallet contact abnormality is detected by the output of the delay circuit A57. An LS switching abnormality alarm is generated by the output of the delay circuit A57.

  The AND circuit A58 receives the outputs of the one-shot circuit A53 and the delay circuit A57, and when it detects misrecognition of both LS opens when the LS1a changes to open, sets the output to ‘1’. The AND circuit A58 receives the outputs of the one-shot circuit A54 and the delay circuit A57, and when it detects misrecognition of both LS opens when the LS2a is changed to open, sets its output to "1". The flip-flop circuits A60 and A61 are set when the outputs of the AND circuits A58 and A59 become ‘1’, and are reset when both LS opens are not detected by the output signal of the NOT circuit A62. That is, the "1" output of the flip-flop circuits A60 and A61 continues until the open state of both LSs of the line by the DI circuit is released.

  OR circuit A63 outputs the logical sum of the LS1a signal and the output of flip-flop circuit A60 as first bus selection signal SL # 1bus. Therefore, when erroneous recognition of both LS opens is detected when the LS1a is opened, the first bus selection signal SL # 1bus is returned to “1” after a predetermined time T6 from the time when the LS1a is opened, and the first bus side The protection operation continues. OR circuit A64 outputs the logical sum of the LS2a signal and the output of flip-flop circuit A61 as second bus selection signal SL # 2bus. Therefore, when an erroneous recognition of both LS opens is detected when the LS2a is opened, the second bus selection signal SL # 2bus is returned to '1' after a predetermined time T6 from the time when the LS2a is opened, and the second bus side The protection operation will continue.

  As described above, according to the third embodiment, when the open of both disconnectors is detected, the line current at that time is detected, and when the line current exceeds a predetermined value, the detection of the open of both disconnectors is Since it was judged that the detection error was caused by a pallet contact error and the bus side that had changed LS was reconnected to continue the bus protection calculation, the bus protection calculation was stopped due to an incorrect LS pallet condition input. The protection operation can be continued.

Embodiment 4 FIG.
A fourth embodiment of the present invention will be described with reference to FIG. In the third embodiment, when the line current flowing through the line is greater than or equal to a predetermined value even after the LS changes to open, the line that has changed LS is reconnected as a false recognition and the protection is continued. It was assumed that LS open detection disappeared. However, in this method, once the opening of both LSs is detected, there is a possibility that a problem that cannot be reset when the main contact is actually opened may occur. In order to avoid this, in the fourth embodiment, only when the current of the line continues to flow over a predetermined value, logic to be connected to the bus that has been detected to open LS is added.

  In FIG. 13, AND circuits A66 and A67 are added to the circuit configuration shown in FIG. The AND circuit A66 takes the logical product of the output of the flip-flop circuit A60 and the detection signal IN> of the output of the current detection circuit A50, and inputs the output to the OR circuit A63. Only when the flow continues, the output of the flip-flop circuit A60 is valid and output. The AND circuit A67 takes the logical product of the output of the flip-flop circuit A61 and the detection signal IN> of the output of the current detection circuit A50, and inputs the output to the OR circuit A64. Only when the flow continues, the output of the flip-flop circuit A61 is valid and output.

  When the main contact of both disconnectors is opened, the line current of the line should be zero, so the detection signal IN> becomes “0”. In this case, in this case, the AND circuit A66 and A67 block the output of the flip-flop circuits A60 and A61.

  As described above, according to the fourth embodiment, the logic for connecting to the bus that has been detected to open LS is added to the configuration of the third embodiment only when the current of the line continuously flows over a predetermined value. Therefore, the open operation of the main contact can be dealt with, and the configuration becomes more reliable.

Embodiment 5 FIG.
In the first to fourth embodiments, the LS pallet contact abnormality is detected when the LS pallet condition changes. In the fifth embodiment, the main contact changes, but the LS pallet condition changes correspondingly. The configuration is such that misrecognition can be detected when no change occurs. Three cases that can actually be assumed will be described as an example.

・ Case A
In case A, when operating with the pallet contact signal LS1a = closed “1” and the pallet contact signal LS2a = open “0”, these pallet contact signals are not changed, and the main contacts of both disconnectors are both opened “0”. This is the case. In this case A, the line current suddenly changes to zero, but since the main contacts of both disconnectors are disconnected from both bus lines, the input current is also zero, so that the input is correct. In the configurations described in 1-4, the abnormal LS connection detection signals Idc>, Id1>, Id2> do not become “1” and no malfunction occurs, so that the protection can be continued as it is.

・ Case B
In case B, while operating with the pallet contact signal LS1a = closed “1” and the pallet contact signal LS2a = open “0”, these pallet contact signals do not change, and the main contacts of both disconnectors are both closed “1”. This is the case. In this case B, in the configuration described in the first to fourth embodiments, there is a high possibility that a sudden change in the line current is not detected, and the LS pallet abnormal line cannot be specified. Therefore, in case B, Idc> due to LS pallet abnormality is “0”, and Id1> or Id2> is detected as “1” so that the entire line current is connected to the first bus 10 side. The first bus selection signal SL # 1bus and the second bus selection signal SL # 1bus are output.

・ Case C
Case C is a case in which while the pallet contact signals LS1a and LS2a are both in operation with open '0', these pallet contact signals do not change and the main contact of either disconnector is closed to '1'. In this case C, the current is detected even though the line current should be zero, and Idc> is “0” and Id1> or Id2> is “1” due to LS palette abnormality. It is determined that the phenomenon is caused by an abnormality in the LS pallet, and it is considered that the bus contact of the main contact of the disconnector has been made on the line where the line current is detected. Then, the current of the line is connected to the first bus line 10 or the second bus line 20 and connected to the bus side where Id1> and Id2> are both “0”, and the protection is continued.

  Thus, it is necessary to deal with the cases B and C which are problematic, and the correspondence is shown in the flowchart of FIG. In the fifth embodiment, as inputs to the LS monitoring control circuit, LS palette conditions for each line, abnormal LS connection detection signals Idc>, Id1>, Id2>, and detection signal IN> for each line Is assumed. The detection signal IN> is output from the current detection circuit A50 shown in FIG. 12, and is output when the current flowing through the line is greater than or equal to a set value.

  FIG. 14 will be described. First, with no change in the LS pallet condition (with no change in the pallet contact signals LS1a and LS2a), Idc> is '0' and Id1> or Id2> is '1' while protection is continued. If not detected, the first bus selection signal SL # 1bus and the second bus selection signal SL # 1bus are output as they are based on the LS palette conditions (step S190). However, if Idc> is '0' and Id1> or Id2> is '1' when there is no change in the LS pallet condition, it is connected to the bus based on the detection signal IN> for each line. It is determined whether there is a change in all the line currents (step S110), and if there is no change in all the line currents connected to the bus, all lines are connected to, for example, the first bus 10 side after a certain period of time. The first bus selection signal SL # 1bus and the second bus selection signal SL # 1bus are output so as to be connected to (step S180).

  If a change in the line current is detected in the determination in step S110, it is next determined whether or not both disconnectors of the line that has detected the change in the line current are open (open) based on the pallet contact signals LS1a and LS2a. If the determination result is NO, the first bus selection signal SL # 1bus and the second bus selection signal SL are connected so that all the lines are connected to, for example, the first bus 10 side after a certain time period. # 1 bus is output (step S180).

  However, if it is determined in step S120 that both disconnectors of the line that detected the change in the line current detect open (open), the current change occurred regardless of which line is open. First, the first bus selection signal SL # 1bus and the second bus selection signal SL # 1bus are output so as to connect the line to the first bus 10 side. As a result, when “0” in both Id1> and Id2> is detected (step S130), the first bus selection signal SL # 1bus and the second bus so as to connect the line to the first bus 10 side thereafter. The bus selection signal SL # 1bus is continuously output (step S140).

  If “0” in both Id1> and Id2> is not detected in the determination in step S130, the first bus selection signal SL # 1bus and the second bus are connected so as to connect the line to the second bus 10 side. Try outputting the bus selection signal SL # 1bus (step S150). As a result, when “0” in both Id1> and Id2> is detected (step S160), the first bus selection signal SL # 1bus and the second bus so as to connect the line to the second bus 10 side thereafter. The bus selection signal SL # 1bus is continuously output (step S170). Further, in the determination in step S160, if neither “0” of Id1> and Id2> is detected, the first bus selection signal SL is connected so that all the lines are connected to, for example, the first bus 10 side after a certain time period. # 1bus and second bus selection signal SL # 1bus are output (step S180).

  As described above, in the fifth embodiment, the LS pallet condition abnormality in the state where the LS pallet condition does not change based on the abnormal LS connection detection signals Idc>, Id1>, Id2> and the current detection signal IN> for each line. When an abnormality such as case C is detected, the appropriate line side is selected. Therefore, avoiding the case where all lines are connected to the first bus side, for example, the first bus side and the second line are avoided. Separation protection on the bus side can be continued, and reliable bus bar protection can be realized.

  As described above, the busbar protection relay according to the present invention is useful as a busbar protection relay for protecting a double busbar configuration that takes in the pallet condition of the disconnector and executes a busbar protection calculation by the line current.

It is a figure which shows the double bus system configuration | structure which applies the protection relay of this invention. It is a block diagram which shows the internal structure of the protection relay concerning this invention. It is a block diagram which shows the internal structure of the line switching circuit and protection arithmetic circuit in a protection relay. FIG. 3 is a logic circuit diagram showing an internal configuration of an LS monitoring control circuit of the protective relay according to the first embodiment. 4 is a time chart showing signal states of respective parts when the disconnector is normally switched in the LS monitoring control circuit according to the first embodiment. 4 is a time chart showing signal states of respective parts when the LS pallet condition is abnormal in the LS monitoring control circuit according to the first embodiment. 4 is a time chart showing signal states of respective parts when a true LS bridge is generated in the LS monitoring control circuit according to the first embodiment. FIG. 6 is a logic circuit diagram showing an internal configuration of an LS monitoring control circuit of a protective relay according to a second embodiment. 6 is a time chart showing signal states of respective parts at the time of normal switching of the disconnector of the LS monitoring control circuit according to the second embodiment. 10 is a time chart showing signal states of respective parts when the LS pallet condition is abnormal in the LS monitoring control circuit according to the second embodiment. 10 is a time chart illustrating signal states of respective parts when a true LS bridge is generated in the LS monitoring control circuit according to the second embodiment. FIG. 6 is a logic circuit diagram showing an internal configuration of an LS monitoring control circuit of a protective relay according to a third embodiment. FIG. 10 is a logic circuit diagram showing an internal configuration of an LS monitoring control circuit of a protective relay according to a fourth embodiment. 10 is a flowchart illustrating the operation of the LS monitoring control circuit of the protective relay according to the fifth embodiment.

Explanation of symbols

1LS1 to NLS2 Disconnector 1 Bus protection relay 2 Data converter 3 Pallet condition input circuit (DI circuit)
4 circuit switching circuit 5 protection arithmetic circuit 6 output circuit 7 LS supervisory control circuit 10 first bus 20 second bus 30 bus connection breaker 51 collective bus protection arithmetic circuit 52 first bus protection arithmetic circuit (# 1 Bus protection arithmetic circuit)
53 Second bus protection arithmetic circuit (# 2 Bus protection arithmetic circuit)
411 to 4N2 changeover switch A50 Current detection circuit CB1 to CBN Breaker CT1 to CTN Current transformer CTB1 Current transformer CTB2 Current transformer I1 to IN Line current (data)
IB1, IB2 Bus contact current (data)
Idc>, Id1>, Id2> Abnormal LS connection detection signal
IN> Current detection signal LS1a, LS2a Pallet contact signal SL # 1bus First bus selection signal (switching signal)
SL # 2bus 2nd bus selection signal (switching signal)

Claims (6)

First and second busbars connected via a busbar breaker, a plurality of lines each provided with a breaker, a plurality of first bus side disconnectors connecting each line to the first busbar, and each In a bus protection relay for performing bus protection of a system configuration including a disconnector having a plurality of second busbar side disconnectors connecting a line to a second busbar,
A first input circuit for inputting a pallet contact signal of each disconnector as a disconnector pallet condition;
A second input circuit to which all line currents and first and second bus contact currents detected on the first and second buses side are input;
In order to control each of the circuit breakers based on all line currents output from the second input circuit, a bus protection operation is performed in a collective region including the first and second bus regions, and based on all line currents. A collective bus protection calculation unit for detecting an abnormal disconnector connection and outputting a first abnormal LS connection detection signal;
In order to control the circuit breaker based on the line current on the side connected to the first bus and the second bus contact current, the bus protection calculation in the first bus side region is performed, and abnormalities are detected based on the input currents. A first bus protection arithmetic unit that detects a disconnector connection and outputs a second abnormal LS connection detection signal;
In order to control the circuit breaker based on the line current on the side connected to the second bus and the first bus contact current, the bus protection calculation in the second bus side region is performed, and abnormal operation is performed based on each input current. A second bus protection calculation unit that detects disconnector connection and outputs a third abnormal LS connection detection signal;
Whether or not to output each line current output from the second input circuit to the first and second bus protection operation units based on the disconnector pallet condition and the first to third abnormal LS connection detection signals When the disconnector bridge state is detected when the disconnector is not operating based on the disconnector pallet condition, the first to third abnormal LS connection detections are output. Based on the signal, it is determined whether or not the detection of the disconnector bridge state is an erroneous detection due to an abnormality of the pallet contact. When the erroneous detection is determined, the disconnector pallet condition is corrected and output as the switching signal Monitoring and control circuit,
A line switching circuit that performs a switching operation to switch whether or not to output each line current output from the second input circuit to the first and second bus protection arithmetic units based on the switching signal;
A busbar protective relay comprising: When the disconnector pallet condition is closed, the disconnector monitoring control circuit holds the change of the switching signal based on the closed change of the disconnector pallet condition for a predetermined time, and the disconnector pallet during the predetermined time When the disconnector bridge state is detected when the disconnector is not operating based on the conditions, the disconnector bridge state is detected based on the first to third abnormal LS connection detection signals. The bus protection relay according to claim 1, wherein it is determined whether or not it is detected, and when the erroneous detection is determined, the disconnector pallet condition is corrected and output as the switching signal. First and second busbars connected via a busbar breaker, a plurality of lines each provided with a breaker, a plurality of first bus side disconnectors connecting each line to the first busbar, and each In a bus protection relay for performing bus protection of a system configuration including a disconnector having a plurality of second busbar side disconnectors connecting a line to a second busbar,
A first input circuit for inputting a pallet contact signal of each disconnector as a disconnector pallet condition;
A second input circuit to which all line currents and first and second bus contact currents detected on the first and second buses side are input;
In order to control each of the circuit breakers based on all line currents output from the second input circuit, a bus protection operation is performed in a collective region including the first and second bus regions, and based on all line currents. A collective bus protection calculation unit for detecting an abnormal disconnector connection and outputting a first abnormal LS connection detection signal;
In order to control the circuit breaker based on the line current on the side connected to the first bus and the second bus contact current, the bus protection calculation in the first bus side region is performed, and abnormalities are detected based on the input currents. A first bus protection arithmetic unit that detects a disconnector connection and outputs a second abnormal LS connection detection signal;
In order to control the circuit breaker based on the line current on the side connected to the second bus and the first bus contact current, the bus protection calculation in the second bus side region is performed, and abnormal operation is performed based on each input current. A second bus protection calculation unit that detects disconnector connection and outputs a third abnormal LS connection detection signal;
Whether or not to output each line current output from the second input circuit to the first and second bus protection operation units based on the disconnector pallet condition and the first to third abnormal LS connection detection signals When the disconnector pallet condition is changed to be closed, the switching signal in which one of the busbars changed in a closed state is selected and the other side of the busbar is not selected is output immediately, When the disconnector bridge state is detected when the disconnector is not operating based on the disconnector pallet condition, the disconnector bridge state is detected based on the first to third abnormal LS connection detection signals. It is determined whether it is a false detection due to an abnormality, and when it is determined that the false detection, a disconnector monitoring control circuit that returns the switching signal to a state immediately before the closing change,
A line switching circuit that performs a switching operation to switch whether or not to output each line current output from the second input circuit to the first and second bus protection arithmetic units based on the switching signal;
A busbar protective relay comprising: First and second busbars connected via a busbar breaker, a plurality of lines each provided with a breaker, a plurality of first bus side disconnectors connecting each line to the first busbar, and each In a bus protection relay for performing bus protection of a system configuration including a disconnector having a plurality of second busbar side disconnectors connecting a line to a second busbar,
A first input circuit for inputting a pallet contact signal of each disconnector as a disconnector pallet condition;
A second input circuit to which all line currents and first and second bus contact currents detected on the first and second buses side are input;
In order to control each of the circuit breakers based on all line currents output from the second input circuit, a bus protection operation is performed in a collective region including the first and second bus regions, and based on all line currents. A collective bus protection calculation unit for detecting an abnormal disconnector connection and outputting a first abnormal LS connection detection signal;
In order to control the circuit breaker based on the line current on the side connected to the first bus and the second bus contact current, the bus protection calculation in the first bus side region is performed, and abnormalities are detected based on the input currents. A first bus protection arithmetic unit that detects a disconnector connection and outputs a second abnormal LS connection detection signal;
In order to control the circuit breaker based on the line current on the side connected to the second bus and the first bus contact current, the bus protection calculation in the second bus side region is performed, and abnormal operation is performed based on each input current. A second bus protection calculation unit that detects disconnector connection and outputs a third abnormal LS connection detection signal;
A line current detector for detecting that each line current is equal to or greater than a predetermined value;
Whether or not to output each line current output from the second input circuit to the first and second bus protection operation units based on the disconnector pallet condition and the first to third abnormal LS connection detection signals When a simultaneous opening of the first bus side disconnector and the second bus side disconnector on the same line is detected based on the open change of the pallet condition, When a detection signal is output from the corresponding line current detector, it is determined that the detection is an erroneous detection due to a pallet contact abnormality, and the disconnector pallet condition is corrected so that the opened bus side is selected, and the switching signal Disconnector monitoring and control circuit that outputs as
A line switching circuit that performs a switching operation to switch whether or not to output each line current output from the second input circuit to the first and second bus protection arithmetic units based on the switching signal;
A busbar protective relay comprising:   5. The disconnector monitoring control circuit corrects the disconnector pallet condition and outputs it as the switching signal only when the line current detector continuously outputs a detection signal. Busbar protection relay as described. First and second busbars connected via a busbar breaker, a plurality of lines each provided with a breaker, a plurality of first bus side disconnectors connecting each line to the first busbar, and each In a bus protection relay for performing bus protection of a system configuration including a disconnector having a plurality of second busbar side disconnectors connecting a line to a second busbar,
A first input circuit for inputting a pallet contact signal of each disconnector as a disconnector pallet condition;
A second input circuit to which all line currents and first and second bus contact currents detected on the first and second buses side are input;
In order to control each of the circuit breakers based on all line currents output from the second input circuit, a bus protection operation is performed in a collective region including the first and second bus regions, and based on all line currents. A collective bus protection calculation unit for detecting an abnormal disconnector connection and outputting a first abnormal LS connection detection signal;
In order to control the circuit breaker based on the line current on the side connected to the first bus and the second bus contact current, the bus protection calculation in the first bus side region is performed, and abnormalities are detected based on the input currents. A first bus protection arithmetic unit that detects a disconnector connection and outputs a second abnormal LS connection detection signal;
In order to control the circuit breaker based on the line current on the side connected to the second bus and the first bus contact current, the bus protection calculation in the second bus side region is performed, and abnormal operation is performed based on each input current. A second bus protection calculation unit that detects disconnector connection and outputs a third abnormal LS connection detection signal;
A line current detector for detecting that each line current is equal to or greater than a predetermined value;
Whether or not to output each line current output from the second input circuit to the first and second bus protection operation units based on the disconnector pallet condition and the first to third abnormal LS connection detection signals A plurality of switching signals for switching, and the disconnector pallet conditions,
When an abnormality in the disconnector pallet condition is detected in a state where the disconnector pallet condition does not change based on the first to third abnormal LS connection detection signals and the detection signals of the respective line current detectors, the disconnector A disconnector monitoring control circuit that corrects the pallet condition and outputs it as the switching signal;
A line switching circuit that performs a switching operation to switch whether or not to output each line current output from the second input circuit to the first and second bus protection arithmetic units based on the switching signal;
A busbar protective relay comprising:

Images