JP5172250B2 - Semiconductor device, display device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device, a display device, and a manufacturing method thereof. More particularly, the present invention relates to a semiconductor device used for an active matrix driving display device, a display device, and a manufacturing method thereof.

Conventionally, in order to perform high-quality display on a liquid crystal display panel, an organic electroluminescence (hereinafter referred to as “organic EL”) panel, etc., driving is performed by a thin film transistor (TFT) using amorphous silicon or the like formed on a glass substrate. Active matrix driving has been performed. In addition, for the integration of peripheral drivers, peripheral drive circuits using polycrystalline silicon TFTs that operate at a higher speed than when amorphous silicon is used have been developed. Panels for liquid crystal projectors with finer pixels have been made.

However, in the production of liquid crystal display panels, etc. driven by active matrix, the mother glass substrate has been increasing in size in order to respond to the improvement of productivity and the increase in the display screen. There is a demand to suppress the increase. Therefore, as a solution, a method has been proposed in which a large panel is formed from a small substrate by transferring (transferring) a high-density TFT or the like to an intermediate substrate and then transferring the TFT to the final substrate. Yes. For example, an active element is formed on an element formation substrate, transferred to an intermediate substrate, and further transferred to a transfer destination substrate on which a height control member and an adhesive surrounded by the height control member are formed, thereby forming wirings and the like. A method of forming an active matrix substrate is disclosed (for example, see Patent Document 1 and Non-Patent Document 1).

In addition, the surfaces of the single crystal semiconductor substrate and the insulating substrate on which the integrated circuit (IC) driver for driving is formed are cleaned with cleaning water such as SC1 containing hydrogen peroxide, or plasma containing oxygen is used. A method of performing a substrate bonding step after activation by exposure is disclosed (see, for example, Patent Document 2).

Further, in order to effectively use a material such as a glass substrate and improve the yield rate, a predetermined number of a plurality of electrode portions (display portions) are arranged on the mother substrate, and the plurality of electrodes are driven in other regions. A method is disclosed in which a predetermined number of drive circuit units are arranged, and after both of the plurality of electrode units and the drive circuit are completed, each is divided into individual parts, non-defective products are connected to each other, and an electrode substrate is completed. (For example, refer to Patent Document 3).
JP 2005-242380 A JP 2005-285850 A JP 2000-10111 A Y. Onozuka, et. al. "SID Digest", 2006, p. 1254-1257

However, in the methods of Patent Document 1 and Non-Patent Document 1, an adhesive is used for bonding the active element and the element forming substrate, and the bonding strength difference between the intermediate substrate and the final substrate is transferred to the final substrate. Since the separation is performed by using, there is room for improvement in terms of reliability such as heat resistance and bonding strength.

In the method of Patent Document 2, since an IC driver formed on a single crystal semiconductor substrate can be transferred only to one insulating substrate, only one active matrix substrate can be manufactured from one single crystal semiconductor substrate. There was room for improvement in terms of productivity.

Furthermore, in the method of Patent Document 3, when applied to the display unit, glass cutting accuracy, edge linearity, shell cracks and chipping, or joints appear in the display, and thus it is difficult to apply to the display unit. There was room for improvement in that. Since only one active matrix substrate can be obtained from one element formation substrate, there is room for improvement in terms of productivity.

The present invention has been made in view of the above-described situation, and provides a semiconductor device, a display device, and a method for manufacturing the same that can improve reliability such as heat resistance and bonding strength and can obtain high productivity. It is intended to provide.

The inventors of the present invention have made various studies on a semiconductor device having a semiconductor element on a substrate, and have paid attention to the arrangement relationship between the semiconductor element and the substrate. Then, an intermediate member in which semiconductor elements or components thereof are arranged in parallel by providing a convex part on the surface on the side where the semiconductor element is arranged with respect to the substrate and arranging the semiconductor element on the upper surface of the convex part. As a result, it is possible to transfer a semiconductor element or its constituent elements to the upper surface of the convex portion of the substrate, and as a result, it is possible to manufacture a plurality of semiconductor devices from one intermediate member, resulting in high productivity. It was. Further, by activating the upper surface of the intermediate member and the upper surface of the convex portion of the substrate, the semiconductor element or its component can be bonded to the upper surface of the convex portion of the substrate without any adhesive. It has also been found that the reliability such as the property and the bonding strength can be improved, and the inventors have arrived at the present invention by conceiving that the above problems can be solved brilliantly.

That is, the present invention is a semiconductor device having a semiconductor element on a substrate, wherein the substrate has a convex portion on a surface on which the semiconductor element is disposed, and the semiconductor element is an upper surface of the convex portion of the substrate. It is a semiconductor device arranged in.
The present invention is described in detail below.

The semiconductor device of the present invention has a semiconductor element on a substrate. Examples of the substrate include a transparent insulating substrate such as a glass substrate and a quartz substrate, but the surface on which the semiconductor element is disposed may include an insulating material. For example, the semiconductor element is disposed. A metal substrate or the like in which an insulating layer is disposed on the surface on the other side can also be used. When heat resistance is required, the glass substrate preferably has a high strain point from the viewpoint of heat resistance. For example, since a heat resistance of about 400 to 600 ° C. is generally required to form a device such as polycrystalline silicon, a glass substrate having a high strain point that can withstand this is preferable. When used in a process similar to IC production, a quartz substrate is preferable from the viewpoint of heat resistance, and in the case of a flexible display, a flexible substrate is preferable from the viewpoint of ease of bending. A substrate, a stainless steel substrate, or the like is preferable. In the present specification, the “semiconductor element” refers to a solid active element that utilizes an electronic characteristic of electrical conduction of a semiconductor, or a solid inactive element such as a capacitor. Examples of the solid active element include a 2-terminal element typified by MIM (Metal Insulator Metal) and a diode, and a 3-terminal element typified by a transistor. A transistor is more preferable from the viewpoint of switching performance. Examples of the solid inactive element include a capacitor such as a memory capacity of a pixel.

The said board | substrate has a convex part in the surface by which the semiconductor element is arrange | positioned, and the said semiconductor element is arrange | positioned at the upper surface of the convex part of a board | substrate. That is, in the present specification, the “upper surface of the convex portion” is a surface of the substrate on the side where the semiconductor element is disposed. According to this, since it is possible to transfer the semiconductor element or its component from the intermediate member in which the semiconductor element or its component is arranged in parallel to the upper surface of the convex portion of the substrate, a plurality of semiconductor devices can be formed from one intermediate member. As a result of being manufactured, high productivity can be obtained. Further, in this specification, “parallel arrangement” refers to a form in which they are arranged side by side without overlapping.

In the present specification, the term “convex portion” refers to a portion having a relatively high height from the bottom surface of the substrate (the surface on which the semiconductor element is not disposed). A convex part is comprised from an upper surface and a side surface, and a semiconductor element is arrange | positioned at the upper surface of a convex part. The number of convex portions may be single or plural on the upper surface of one substrate. When there are a plurality of convex portions, all the upper surfaces of the convex portions are usually at the same height from the bottom surface, but the heights of the upper surfaces of the portions other than the convex portions (concave portions) are not necessarily the same. The minimum value of the step between the upper surface of the convex portion and the upper surface of other portions is preferably 10 to 50 nm in a region of 5 μm × 5 μm. If the thickness is less than 10 nm, the portion other than the convex portion is also joined to the upper surface of the intermediate member in the joining step, so that selective transfer may not be performed. When the thickness is 50 nm or more, etching or the like takes time when forming the convex portion using an etching method or the like, and the throughput may be reduced. Further, if it is 50 nm or more, it may cause a disconnection of wiring or a short circuit due to an etching residue in a later process, or, for example, when a semiconductor substrate is used for a liquid crystal display device, there is a risk of deterioration in liquid crystal display quality in the display unit. There is. The method for forming the convex portion is not particularly limited, but is preferably formed by etching from the viewpoint of maintaining the flatness of the upper surface, and dry etching, wet etching, or the like can be used.

The semiconductor device of the present invention is not particularly limited as long as it has the substrate and the semiconductor element as constituent elements and may or may not have other constituent elements. Examples of the semiconductor device of the present invention include an active matrix substrate and an image sensor.

A preferred embodiment of the semiconductor device of the present invention will be described in detail below.
The semiconductor element is preferably bonded to the upper surface of the convex portion of the substrate without an adhesive. In this manner, reliability such as heat resistance and bonding strength can be improved by bonding the semiconductor element to the upper surface of the substrate without using an adhesive that is weak against heat. In the present specification, the “adhesive” is a substance used for bonding objects of the same kind or different kinds, and includes an adhesive.

The semiconductor element preferably includes a pixel switching element, or a pixel switching element and an auxiliary capacitance element. Currently, in the production of display devices driven by an active matrix, the phenomenon that the mother glass continues to increase in size and the investment amount of production equipment expands tremendously in order to respond to the improvement of productivity or the increase in the size of the display screen. Is happening. According to the present invention, the pixel switching element (or its component), or both the pixel switching element (or its component) and the auxiliary capacitance element (or its component) are simultaneously formed in the intermediate member at high density. By distributing and arranging on a plurality of substrates, a plurality of large active matrix substrates can be formed from one small intermediate member, so that an increase in the investment amount of production equipment can be suppressed. The auxiliary capacitance element is provided for improving the holding characteristics of the voltage applied to the liquid crystal when the semiconductor device is provided in the liquid crystal display device, and is usually added in parallel with the liquid crystal capacitance. It has another dielectric capacitance. For example, an auxiliary capacitance electrode and an auxiliary capacitance common line can be used. A drain lead line or the like drawn from a TFT is used as the auxiliary capacity electrode and a gate bus line is formed as the auxiliary capacity common line. It can also be formed by using the formed metal film or the like and superposing these via a gate insulating film or the like.

In the present specification, the “pixel switching element” is a switching element provided for each pixel. As the pixel switching element, a thin film transistor (TFT) formed by processing a thin film deposited on an insulating substrate such as a glass substrate, a thin film transistor using a part of a silicon single crystal substrate as a semiconductor active layer material, or the like can be used. . That is, the pixel switching element is preferably a TFT. The TFT structure is not particularly limited, and may be a bottom gate structure (a structure in which the gate electrode is below the active layer) or a top gate structure (a structure in which the gate electrode is above the active layer). May be. Note that a bottom-gate TFT and a top-gate TFT may be mixed in one semiconductor device. The material constituting the active layer of the TFT is not particularly limited, and examples thereof include amorphous silicon, polycrystalline silicon, continuous grain boundary crystal (CG) silicon, and single crystal silicon.

The semiconductor element preferably includes a pixel array. That is, the semiconductor device is preferably an active matrix substrate. According to this, a plurality of active matrix substrates can be formed from one intermediate member by simultaneously forming the pixel array or its constituent elements in the intermediate member at a high density and dispersively arranging them on the plurality of substrates. The increase in the investment amount of production equipment can be suppressed. In this specification, the “pixel array” means a gate wiring and a source wiring arranged in a matrix and an intersection of the gate wiring and the source wiring and electrically connected to the gate wiring and the source wiring. The pixel switching element includes a pixel switching element and a pixel electrode connected to the pixel switching element.

The semiconductor element preferably includes a peripheral drive circuit. According to this, it is possible to simultaneously form a peripheral drive circuit or its constituent elements in the intermediate member at a high density and to disperse and arrange them on a plurality of substrates to form a plurality of large active matrix substrates from one small intermediate member. Therefore, an increase in the investment amount of production equipment can be suppressed. In this specification, the “peripheral drive circuit” is a circuit for driving a display panel such as a liquid crystal display panel or an organic EL display panel, and two types of scan electrode drivers and data signal electrode drivers are given as typical examples. It is done. The peripheral drive circuit preferably includes a TFT, and the TFT included in the peripheral drive circuit is not particularly limited, and is configured with the same structure and material as the TFT that can be used as the pixel switching element. A thing etc. can be used.

The semiconductor element preferably includes a pixel array and a peripheral drive circuit. That is, the semiconductor device is preferably a driver monolithic active matrix substrate. According to this, an intermediate member is manufactured by simultaneously forming two sets of pixel arrays or components thereof and peripheral drive circuits or components thereof on a substrate, and one set of pixel arrays or configurations thereof is formed from the intermediate members. By transferring the element and a set of peripheral driver circuits or components thereof to another substrate, two driver monolithic active matrix substrates can be manufactured at the same time, so that productivity can be improved. In addition, the driver monolithic structure can simplify the panel mounting process and can be expected to reduce the cost. Furthermore, the mounting area can be reduced and the frame can be narrowed by the driver monolithic. Further, high definition can be realized without being limited by the mounting pitch, and reliability can be improved.

In this specification, “driver monolithic” means that the pixel portion and the peripheral driving circuit are formed on the same substrate. The driver monolithic active matrix substrate includes (1) an amorphous silicon driver monolithic active matrix substrate in which the pixel switching element is an amorphous silicon TFT, and (2) a polycrystalline silicon driver monolithic in which the pixel switching element is a polycrystalline silicon TFT. And a (3) single crystal silicon driver monolithic active matrix substrate in which the pixel switching element is a single crystal silicon TFT. Note that the semiconductor element may include a peripheral circuit other than the peripheral driver circuit, and examples of the peripheral circuit other than the peripheral driver circuit include a memory, a control logic, and a micro processor unit (MPU).

The semiconductor element preferably includes a single crystal silicon device. For example, in a projection type liquid crystal display device such as a projection, when polycrystalline silicon is used as an active layer material of a semiconductor element, display unevenness reflecting a grain boundary is generated (the entire screen is rough). Sometimes. Therefore, such display unevenness (roughness of the screen) can be eliminated by using single crystal silicon having no grain boundary as the active layer material of the semiconductor element. In addition, two or more wafers can be manufactured from a circuit and a pixel transistor on one silicon wafer, so that cost reduction can be realized. Further, since it can be transferred to a transparent substrate, a transmissive liquid crystal display panel can be easily manufactured. The semiconductor device is more preferably a driver monolithic single crystal silicon device.

Preferably, the pixel array includes a pixel switching element including amorphous silicon, and the peripheral driver circuit includes a thin film transistor including polycrystalline silicon. Amorphous silicon is preferably used as a semiconductor active layer material for a pixel switching element, and polycrystalline silicon is preferably used as a semiconductor active layer material for a thin film transistor constituting a peripheral driver circuit. A pixel switching element including amorphous silicon has an extremely low off-leakage current under dark conditions, and further has better transistor characteristics uniformity than a thin film transistor including polycrystalline silicon. In addition, a thin film transistor including polycrystalline silicon has higher mobility and higher current driving capability than a pixel switching element including amorphous silicon. High performance can be achieved. As described above, a pixel switching element including amorphous silicon is used as the pixel switching element, and a thin film transistor including polycrystalline silicon that can reduce the area to be formed is used as the thin film transistor constituting the peripheral driver circuit. By doing so, it is possible to obtain a semiconductor device utilizing each feature.

The pixel array and the peripheral driver circuit preferably include a thin film transistor including polycrystalline silicon. According to this, since the manufacturing process of the pixel array including the polycrystalline silicon and the peripheral driving circuit can be made common, the manufacturing process can be simplified. In addition, both the pixel array and the thin film transistor included in the peripheral driver circuit can operate at high speed because of high mobility and high current driving capability, and the formation area can be reduced. The performance can be improved, and in the pixel array, the aperture ratio of the pixel can be increased.

The present invention is also a display device including the semiconductor device. According to the semiconductor device of the present invention, since high productivity can be obtained, a display device with high reliability and high productivity can be provided. The display device is not particularly limited, but a liquid crystal display device and an organic EL display device are preferable from the viewpoint of thin and light weight and low power consumption, and an active matrix drive display device is more preferable from the viewpoint of preventing crosstalk. From the viewpoint of improving reliability, a driver monolithic active matrix drive display device is more preferable.

The display device of the present invention is not particularly limited as long as it has the above-described semiconductor device as a component and may or may not have other components. Examples of the form of the liquid crystal display device of the present invention include a form having an active matrix substrate (semiconductor device), a counter substrate, and a liquid crystal layer disposed between the active matrix substrate and the counter substrate. Examples of the form of the organic EL display device of the present invention include a form in which a cathode, an organic light emitting layer and an anode are laminated on an active matrix substrate (semiconductor device).

The present invention further relates to a method for manufacturing the semiconductor device, wherein the manufacturing method is a method for manufacturing a semiconductor device including a step of transferring a semiconductor element or a component thereof onto an upper surface of a convex portion of a substrate. In this way, by adopting a method of transferring a semiconductor element or a component thereof to a substrate instead of directly forming it on the substrate, it is possible to flexibly cope with an increase in the size of the semiconductor device. In addition, since high heat resistance is not required for the substrate, it is possible to use a substrate having low heat resistance, to reduce the cost, and to use a flexible substrate.

In the present specification, the “component of the semiconductor element” refers to an incomplete product of the semiconductor element. That is, in the manufacturing method of the present invention, after the semiconductor element is completed, the completed semiconductor element may be transferred to the substrate. After forming the semiconductor element halfway, the unfinished semiconductor element is transferred to the substrate, Thereafter, the semiconductor element may be completed on the substrate.

The semiconductor device manufacturing method of the present invention is not particularly limited as long as it includes the above-described transfer step as an essential step, and may or may not include other steps. For example, the semiconductor device manufacturing method of the present invention preferably includes a step of forming a substrate for transferring a semiconductor element or a component thereof by etching the substrate.

A preferred embodiment of the method for manufacturing a semiconductor device of the present invention will be described in detail below.
In the transfer step, at least one of the upper surface of the intermediate member on which two or more sets of semiconductor elements or components thereof are arranged and the upper surface of the convex portion of the substrate is activated, and at least one of them is activated. The process of joining the upper surface of the intermediate member and the upper surface of the convex portion of the substrate, and the process of joining the upper surface of the intermediate member joined to the upper surface of the convex portion of the substrate (the intermediate member in the region joined to the upper surface of the convex portion) It is preferable to include a process of separating a set of semiconductor elements or components thereof from the upper surface to the bottom surface of the intermediate member. By activating the upper surface of the intermediate member and the upper surface of the convex portion of the substrate, one of the semiconductor elements provided on the intermediate member or a component thereof can be utilized by using the force between atoms without using an adhesive. Since the portion can be bonded to the upper surface of the convex portion of the substrate, reliability such as heat resistance and bonding strength of the semiconductor device can be improved. Further, by arranging two or more sets of semiconductor elements or their constituent elements in parallel on one intermediate member, a plurality of semiconductor devices can be manufactured from one intermediate member, resulting in high productivity. Further, by separating a set of semiconductor elements or components thereof under the upper surface of the intermediate member bonded to the upper surface of the convex portion of the substrate from the intermediate member, the semiconductor elements or components thereof on the upper surface of the convex portion of the substrate. Can be transferred as a thin film. And it is preferable that the upper surface of the intermediate member and the upper surface of the convex part of the substrate are flattened before being activated, whereby the bonding strength can be further increased.

The upper surface of the intermediate member is a surface on the side bonded to the upper surface of the convex portion of the substrate. The activation treatment refers to treatment for activating (modifying) the surfaces so that bonding can be performed without using an adhesive. For example, activating the surface of an insulating film containing SiO ₂ or SiO ₂ as a main component means that the surface is terminated with a hydroxyl group (OH group) to make it hydrophilic. In addition, you may perform the removal of the hydrocarbon of the surface of the convex part of an insulated substrate, etc. by an activation process. For the intermediate member, it is only necessary to activate only the upper surface of the region in contact with the upper surface of the convex portion of the substrate, but from the viewpoint of reducing the step of covering the upper surface other than that region with a mask, the entire upper surface of the intermediate member is It may be activated. Also, for the substrate, only the upper surface of the convex portion may be activated. However, from the viewpoint of reducing the step of covering the upper surface other than the convex portion with a mask, the entire upper surface of the substrate may be activated.

When both the upper surface of the intermediate member and the upper surface of the convex portion of the substrate are clean, flat and highly hydrophilic, only one of the upper surface of the intermediate member and the upper surface of the convex portion of the substrate is activated. Can be joined, but this is exceptional. That is, from the viewpoint of joining the upper surface of the intermediate member and the upper surface of the convex portion of the substrate, it is preferable that the transfer step activates both the upper surface of the intermediate member and the upper surface of the convex portion of the substrate. From the same point of view, after flattening both the upper surface of the intermediate member and the upper surface of the convex portion of the substrate by CMP or the like, both the upper surface of the intermediate member and the upper surface of the convex portion of the substrate are activated. It is more preferable. Incidentally, the upper surface of the intermediate member, and, as the material constituting the top surface of the convex portion of the _substrate, those based on SiO 2, SiO ₂ is preferable. According to this, by immersing in an aqueous solution containing hydrogen peroxide (H ₂ O ₂ ) such as SC1, the upper surface of the intermediate member and the upper surface of the convex portion of the substrate are obtained using van der Waals force and hydrogen bonding. Can be joined.

The intermediate member is not particularly limited as long as two or more sets of semiconductor elements or components thereof are arranged in parallel in the in-plane direction of the upper surface of the intermediate member. When the upper surface of the intermediate member and the upper surface of the convex portion of the substrate are joined, the semiconductor element or the component thereof is provided at a position facing the upper surface of the convex portion of the substrate and the upper surface other than the convex portion. May be. It is preferable that the intermediate member has a recess (at least an alignment margin or more) on the outer periphery of the semiconductor element to be transferred or its constituent elements so as not to cause a transfer failure in the end area of the transferred area. Further, the number of semiconductor elements or components thereof provided per one upper surface of the convex portion of the substrate is not particularly limited.

The two or more sets of semiconductor elements or components thereof may be physically separated from each other or may be connected. Usually, those physically connected are in the same transfer step. It is transferred to the same substrate. Therefore, when the upper surface of the intermediate member and the upper surface of the convex portion of the substrate are joined, the semiconductor elements or the components facing the respective surfaces of the convex portion of the substrate may be physically separated from each other and connected. However, the semiconductor element or the component facing the upper surface of the convex portion of the substrate and the semiconductor element or the component facing the upper surface other than the convex portion of the substrate are physically separated from each other. Preferably it is. Moreover, it is preferable that the semiconductor element or its component is arrange | positioned with high density. According to this, since the semiconductor element or its component transferred to a large number of substrates can be provided on one intermediate member, the cost is reduced by the density ratio of the semiconductor element between the intermediate member and the semiconductor device. Can do. The semiconductor element provided on the intermediate member or the component thereof may be one type or a plurality of types.

The upper surface of the intermediate member and the upper surface of the convex portion of the substrate are preferably substantially flat so that sufficient bonding energy can be obtained. In this specification, “substantially flat” includes not only a completely flat state but also a state that can be regarded as flat in view of the operational effects of the present invention. In a region of 5 μm × 5 μm, It is preferably 0.4 nm (rms value) or less. If it exceeds 0.4 nm (rms value), there is a possibility that sufficient bonding strength cannot be obtained. In order to increase the bonding strength, it is more preferably 0.3 nm (rms value) or less. As a method for measuring the flatness of the surface, an automatic film thickness measuring apparatus for FPD (trade name: Nanospec 6500A, manufactured by Nanometrics) using light interference, or an atomic force microscope (Atomic Force Microscope): Scanning Probe Microscope (SPM) such as AFM) and the like. For example, SPI4000 manufactured by Seiko Instruments Inc. can be used as the SPM.

The activation treatment is preferably performed by an aqueous solution treatment containing hydrogen peroxide, or an aqueous plasma treatment containing hydrogen peroxide is combined with an atmospheric pressure plasma treatment. According to this, the intermediate member is immersed in an aqueous solution treatment containing hydrogen peroxide such as an SC1 solution or exposed to plasma under atmospheric pressure after being immersed in an aqueous solution treatment containing hydrogen peroxide such as an SC1 solution. And / or foreign substances such as hydrocarbons adhering to the upper surface of the convex portion of the substrate can be removed and the hydrophilicity of the surface can be improved (modified). By hydrogen bonding, the upper surface of the intermediate member and the upper surface of the convex portion of the substrate can be more firmly bonded without using an adhesive. Note that an aqueous solution treatment containing hydrogen peroxide may be performed after the atmospheric pressure plasma treatment, and the order of these is not particularly limited. In addition, when the activation process is performed using atmospheric pressure plasma, the process is simpler than the plasma process performed under reduced pressure, and it is considered that the damage due to high energy particles is small. The composition of the SC1 solution is not particularly limited because it is changed depending on the influence on silicon, organic matter removal, particle removal, etc., but usually NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 1: 5 to 1: 2: 7 is used.

The transfer step is preferably performed by heat treatment (annealing). The heat treatment is preferably performed between the bonding process and the separation process. For example, when the upper surface of the intermediate member and the upper surface of the convex portion of the substrate are configured to include silicon oxide, after immersing both surfaces in a hydrogen peroxide solution such as SC1 solution and activating both surfaces, a bonding process is performed. Then, heat treatment can be performed to convert into a strong Si—O bond, so that the bonding strength can be further increased. From the viewpoint of bonding strength, the heat treatment temperature is preferably 100 to 200 ° C. or more and 800 to 900 ° C. or less, but 100 to 600 ° C. is appropriate from the heat resistance temperature of the glass substrate or the heat resistance temperature of the device. Conceivable. The heat treatment may be performed in a vacuum, under reduced pressure, or in the air. Note that the heat treatment time is determined in consideration of individual circumstances such as the material constituting the upper surface of the intermediate member, the material constituting the upper surface of the convex portion of the substrate, and the activation treatment method.

In the intermediate member, two or more sets of semiconductor elements or components thereof are arranged in parallel on an insulating substrate, and the semiconductor element or components thereof are inserted from the intermediate member between the insulating substrate and the semiconductor elements or components thereof. A separation layer for separating, wherein the separation treatment is performed by using the separation layer to form a set of semiconductor elements or components thereof immediately below the upper surface of the intermediate member bonded to the upper surface of the convex portion of the substrate Is preferably separated from the intermediate member. In this way, by performing the separation process using the separation layer formed in advance on the intermediate member, a set of semiconductor elements under the upper surface of the intermediate member bonded to the upper surface of the convex portion of the substrate or the configuration thereof The element can be easily separated from the intermediate member, and the intermediate member from which the semiconductor element or its component is separated can be used for a new transfer. The insulating substrate for the intermediate member is not particularly limited, and examples thereof include an opaque substrate such as stainless steel and a transparent substrate such as glass.

The separation layer is preferably made of hydrogenated amorphous silicon (a-Si: H), and the separation treatment preferably liquefies the separation layer by laser ablation or generates gas from the separation layer. According to this, since the position to irradiate the laser beam can be specified, the separation region can be arbitrarily selected, so when separating a large-area semiconductor element or its component, or a pattern containing the semiconductor element or its component Also in the case of separation into a shape, the semiconductor element or a component thereof can be easily separated from the intermediate member. Here, by irradiating the part to be separated with laser light, the separation layer is locally heated and liquefied, or the elements contained in the separation layer are abruptly released to generate bubbles, and the separation layer To destroy. For example, when the separation layer is formed of an a-Si: H film, a large amount of hydrogen contained in the a-Si: H film is rapidly desorbed by heating with a laser. Thereby, separation can be performed by generating bubbles from the a-Si film and causing the destruction of the a-Si film. Note that as a method for forming the separation layer formed of hydrogenated amorphous silicon (a-Si: H), a plasma CVD method or the like can be given. When formed by the plasma CVD method, since hydrogen is contained in a large amount, it is not necessary to inject hydrogen ions. However, it may be injected, and by injecting hydrogen ions, it may be easier to perform a separation process.

The intermediate member includes two or more sets of semiconductor elements having active regions in the single crystal silicon substrate or components thereof arranged in parallel, and in the single crystal silicon substrate on the bottom side of the single crystal silicon substrate from the active region, It has a separation region for separating the semiconductor element or its component from the intermediate member, and the separation process is performed immediately below the upper surface of the intermediate member bonded to the upper surface of the convex portion of the substrate using the separation region. It is preferable to separate a set of semiconductor elements or components thereof from the intermediate member. Even in this case, by using the separation region formed in advance in the intermediate member, a set of semiconductor elements or components thereof immediately below the upper surface of the intermediate member joined to the upper surface of the convex portion of the substrate The intermediate member from which the semiconductor element or its component is separated can be used for a new transfer.

The separation region is preferably formed by implanting hydrogen ions and / or rare gas ions into a single crystal silicon substrate. By injecting hydrogen ions and / or rare gas ions, a separation region having a sufficient separation function can be formed. The isolation region is more preferably formed by implanting hydrogen ions and rare gas ions into a single crystal silicon substrate. For example, when forming a separation region having a sufficient separation function with hydrogen ions alone, it is better to perform ion implantation of about 5 to 6 (× 10 ¹⁶ ions / cm ² ) for the formation of the separation region. when performing the formation of isolation regions with hydrogen ions and helium ions, hydrogen ions ^{1~1.5 (× 10 16 ion / cm} 2), ions 1~1.5 (× ¹⁰ 16 ion / Since an isolation region having a sufficient isolation function can be formed with an ion implantation amount of about cm ² ), the ion implantation amount can be reduced to about ½. Therefore, the separation process can be easily performed, and the cost can be reduced. Moreover, the influence on device characteristics, such as undesirable acceptor deactivation, can be reduced by reducing the hydrogen ion and / or rare gas ion implantation amount. Examples of rare gas ions include helium (He). Note that the separation region is more preferably heat-treated after hydrogen ions and / or rare gas ions are implanted into the single crystal silicon substrate. According to this, at the same time as increasing the bonding strength, microbubbles can be generated in the separation region, and separation can be performed more easily.

The separation layer or the separation region has a structure with a gap (fragile structure), and the separation treatment applies a shear stress, a tensile stress, or a torsional stress to the separation layer or the separation region, or the separation layer or It is preferable to etch the isolation region. According to this, by applying shearing stress, tensile stress, torsional stress, or etching, a set of semiconductor elements below the upper surface of the intermediate member bonded to the upper surface of the convex portion of the substrate or the semiconductor device In order to mechanically separate the constituent elements from the intermediate member, a large-area semiconductor element or a constituent element thereof is separated, or the semiconductor element or the constituent elements are formed in a complicated pattern (for example, two sets of pixels shown in FIG. Even when separating the array into a translationally symmetrical pattern or a pattern in which the two pixel arrays shown in FIG. 9-1 are rotationally symmetrical, etc., the semiconductor element or its components can be easily separated from the intermediate member. can do. The fragile structure is not particularly limited, but a pillar structure (mushroom cross-section, for example, the cross-sectional structure shown in FIG. 6-5), a form composed of porous silicon, or a gap in a lattice shape when seen in plan view. The formed form (for example, the planar structure shown in FIG. 6A) and the like can be mentioned. The shape of the separation layer is not particularly limited, and may be a random shape. However, when separation is performed by applying etching or stress, when the intermediate member is viewed in plan, the separation layers are separated from each other. It is preferable that they are formed at intervals.

The isolation layer or isolation region is made of at least one selected from the group consisting of molybdenum oxide, germanium oxide, zinc oxide, and aluminum, or silicon, and the isolation treatment may etch the isolation layer or isolation region. preferable. According to this, it is suitable at the point which can perform a separation process gently, without producing the influence (a crack, heat damage, etc.) to a device. When the separation layer or the separation region is composed of at least one selected from the group consisting of molybdenum oxide, germanium oxide, zinc oxide, and aluminum, the hydrochloric acid solution, the phosphoric acid solution, or the alkali is used as the etching solution. By using a solution, the separation process can be easily performed. When the separation layer or the separation region is made of silicon, the separation process can be easily performed by using an alkaline solution as an etching solution. it can.

The intermediate member is formed by arranging two or more sets of pixel switching elements or components thereof, and the two or more sets of pixel switching elements or components thereof are rotationally symmetric, translationally symmetric, or within the pixel region. The mirrors are preferably arranged symmetrically. The intermediate member includes two or more sets of pixel switching elements or components thereof and two or more sets of auxiliary capacitance elements or components thereof arranged in parallel, and the two or more sets of pixel switching elements. Alternatively, it is preferable that the constituent elements and two or more sets of auxiliary capacitive elements and auxiliary capacitive elements or constituent elements thereof are arranged in a rotational symmetry, a translational symmetry, or a mirror symmetry in the pixel region. Further, the intermediate member has two or more sets of pixel arrays or components thereof arranged in parallel, and the two or more sets of pixel arrays or components thereof are arranged in rotational symmetry, translational symmetry, or mirror symmetry. It is preferable. In the case of rotational symmetry or translational symmetry, the transferred ones have the same symmetry and no difference in display characteristics occurs. In the case of mirror symmetry, the transferred image and the non-transferred image have the same symmetry, and there is no difference in display characteristics. According to these, for example, as shown in FIG. 8 and FIG. 9A, since the patterns do not interfere with each other, the area utilization efficiency is good. In this specification, “rotation symmetry” means that the two are overlapped when rotating around a certain axis. “Translational symmetry” means that the two are overlapped when translated in a certain direction. “Mirror symmetry” means that when they are reversed (inverted) and translated in a certain direction or rotated around a certain axis, they overlap each other.

The pixel switching element or a component thereof is preferably a thin film transistor or a component thereof. According to this, the manufacturing method of the semiconductor device of this invention can be used suitably for the manufacturing method of an active matrix substrate. As a preferable aspect of the method for manufacturing a semiconductor device of the present invention, (1) an aspect in which a pixel array is formed up to a gate electrode and a gate wiring, then transferred to a substrate, and then a source wiring and a pixel electrode are formed. ) After the pixel array is formed up to the semiconductor layer (polycrystalline silicon layer, etc.), it is transferred to the substrate, and then the gate electrode, the gate wiring, the source wiring, the pixel electrode, etc. are formed.

It is preferable that the intermediate member has two sets of peripheral drive circuits arranged side by side, and the two sets of peripheral drive circuits are arranged rotationally symmetrically. According to this, for example, when the semiconductor device is used for a display device that performs display by active matrix driving, two sets of gate (scanning) driver circuits and source (data) driver circuits are arranged without difficulty. Can do.

The intermediate member includes two sets of pixel switching elements or components thereof, two sets of auxiliary capacitance elements or components thereof, and two sets of peripheral drive circuits or components thereof, respectively. The two sets of pixel switching elements or components thereof, and the two sets of auxiliary capacitance elements or components thereof are arranged rotationally symmetrical in the pixel region, respectively, and the two sets of peripheral drive circuits or configurations thereof The elements are preferably arranged in rotational symmetry. According to this, the manufacturing method of the semiconductor device of this invention can be used suitably for the manufacturing method of a driver monolithic type active matrix substrate.

The intermediate member includes a pixel switching element containing amorphous silicon or a first intermediate member in which two or more pixel arrays having the component thereof, or a component thereof, and a thin film transistor containing polycrystalline silicon or a component thereof. And a second intermediate member in which two or more sets of peripheral drive circuits or components thereof are juxtaposed, and the manufacturing method of the semiconductor device includes the pixel array or the component from the first intermediate member to the first of the substrate. Preferably, the method includes a step of transferring to the upper surface of the convex portion, and a step of transferring the peripheral drive circuit or a component thereof from the second intermediate member to the upper surface of the second convex portion of the substrate. According to this, the pixel switching element including amorphous silicon formed in different intermediate members or the component thereof and the thin film transistor including polycrystalline silicon or the component thereof can be transferred to one substrate, and each advantage can be obtained. It is possible to make a semiconductor device utilizing the above. Further, a display device using the semiconductor device can be obtained. Furthermore, since the pixel switching element containing amorphous silicon can be formed by a process having a smaller number of masks than a thin film transistor containing polycrystal, the pixel switching element can be efficiently formed by forming each on a separate intermediate member. Alternatively, the component and the peripheral driver circuit or the component can be formed. In addition, the 1st convex part and the 2nd convex part may be connected, may not be, and are not specifically limited. In the case where the semiconductor active layer of the thin film transistor included in the pixel array and the thin film transistor included in the peripheral driver circuit is formed of a common material (for example, polycrystalline silicon, amorphous silicon, etc.), the manufacturing process is shared. From the viewpoint of simplification, it is preferable to form the pixel array and the peripheral drive circuit in one intermediate member.

According to the method for manufacturing a semiconductor device of the present invention, since it has the above-described configuration, reliability such as heat resistance and bonding strength can be improved, and high productivity can be obtained.

EXAMPLES Although an Example is hung up below and this invention is demonstrated still in detail with reference to drawings, this invention is not limited only to these Examples.

Example 1
FIGS. 1-1 to 1-10 are schematic cross-sectional views illustrating the manufacturing flow of the semiconductor device according to the first embodiment.
First, as shown in FIG. 1A, the separation layer 11 is provided on the substrate 10, and the silicon oxide film 12 is provided on the separation layer 11. In this embodiment, alkaline earth-aluminoborosilicate glass (trade name: code 1737, manufactured by Corning), which is a high strain point glass, is used for the substrate 10. Examples of the separation layer 11 include a structure having a gap, a hydrochloric acid and / or phosphate-soluble substance such as molybdenum oxide (MoO ₃ ), germanium oxide (GeO), zinc oxide (ZnO), and aluminum (Al). Alternatively, a material composed of an alkali-soluble substance such as silicon (Si) is formed. The method for forming the separation layer 11 will be described in detail in Examples 6 and 7. Hereinafter, the substrate in which the silicon oxide film 12 is formed on the separation layer 11 provided on the substrate 10 is also referred to as a first substrate 100.

In this embodiment, two sets of TFT arrays (a set of TFTs and auxiliary capacitance elements arranged in a matrix) are formed on the first substrate 100, and one set of the TFT arrays is transferred to the second substrate. In this embodiment, the separation layer 11 is formed only under the transferred TFT array.

Next, as shown in FIG. 1B, a gate electrode layer is formed on the first substrate 100 and patterned to form the gate electrode 21 and the auxiliary capacitance common wiring 22.
Next, as shown in FIG. 1C, the plasma insulating chemical vapor deposition (PECVD) method or the like is used to form the gate insulating film 23 and an amorphous silicon layer (hereinafter referred to as “a-Si: H layer” as an active layer of the TFT). ) 24 and an amorphous silicon layer (hereinafter referred to as an “n ⁺ a-Si: H layer”) 25 to be a source electrode and a drain electrode of the TFT are successively formed in this order. Note that the a-Si: H layer is an amorphous silicon layer to which no impurity is added. The n ⁺ a-Si: H layer is an amorphous silicon layer to which an impurity such as phosphorus is added. The a-Si: H layer and the n ⁺ a-Si: H layer usually contain several% to several tens% hydrogen atoms.

Next, as shown in FIGS. 1-4, the a-Si: H layer 24 and the n ⁺ a-Si: H layer 25 are patterned in an island shape.
Next, as shown in FIG. 1-5, the n ⁺ a-Si: H layer 25 corresponding to the gap portion between the source and drain of the TFT is removed by etching, and then the metal wiring 26 is formed only in the vicinity of the TFT. . The metal wiring 26 functions as a source electrode and a drain electrode of the TFT, and an auxiliary capacitance element is formed in a region where the metal wiring 26 and the auxiliary capacitance common wiring 22 overlap. Note that when two sets of TFT arrays 71 and 72 are formed on the first substrate 100 as in this embodiment, source bus lines should be formed only for the one set of TFT arrays. Is also possible. Since the gate bus line and the source bus line intersect each other, when transferring a plurality of times, two sets of source bus lines whose patterns are mutually exclusive cannot be transferred simultaneously. Further, in FIG. 1-5, when the n ⁺ a-Si: H layer 25 is removed by etching, a part of the a-Si: H layer 24 is also etched at the same time, but this is completely n ⁺ a. This is because over-etching is performed to completely separate the source electrode portion and the drain electrode portion of the Si: H layer 25, and the n ⁺ a-Si: H layer 25 is completely separated. If present, a portion of the a-Si: H layer 24 need not be etched.

Next, SiO ₂ or SiN _x is deposited as the interlayer insulating film 27. In the case where the separation process is performed by etching, an etching stopper layer 28 may be formed on the interlayer insulating film 27 as necessary. As the etching stopper layer 28, for example, a thin SiN _x film or the like can be used.

Thereafter, a SiO ₂ film 29 is deposited as the uppermost layer. In this example, tetraethyl orthosilicate (chemical formula is Si (OC ₂ H ₅ ) ₄ , in English notation Tetra Ethoxy Silane: TEOS) and a mixed gas of oxygen (O ₂ ) by PECVD method, A SiO ₂ film 29 was deposited. Finally, the surface of the uppermost SiO ₂ film 29 is flattened by chemical mechanical polishing (CMP) or the like, whereby the intermediate member 500 is obtained.

Next, as shown in FIGS. 1-6, a second substrate 200 for transferring the TFT array is prepared. Specifically, for alkaline earth-aluminoborosilicate glass (trade name: code 1737, manufactured by Corning), which is a high strain point glass, a region to which the TFT array is transferred on the surface to which the TFT array is transferred. Is left as the convex part 200a, and the surface of the other part is etched to form the concave part 200b. The depth at which the second substrate 200 is etched depends on the area and the flatness of the surface, but generally only needs to be several tens of nm or more.

Next, as shown in FIGS. 1-7, the upper surface 500s of the intermediate member 500 and the upper surface 200s of the convex part 200a of the 2nd board | substrate 200 are joined. Specifically, the upper surface 500s of the intermediate member 500 and the upper surface 200s of the second substrate 200 are immersed in an SC1 solution or the like containing hydrogen peroxide, or exposed to atmospheric pressure plasma after being immersed in the SC1 solution or the like. As a result, the upper surface 500s of the intermediate member 500 and the upper surface 200s of the second substrate 200 are activated and bonded together.

Next, as shown in FIGS. 1-8, a set of TFTs that are not transferred by a method such as applying shearing stress, tensile stress, or twisting stress to the separation layer 11 or impregnating an etching solution. The array 72 is separated and removed. As a result, as shown in FIGS. 1-9 and 1-10, two TFT array substrates are obtained in which the positional relationship between the gate electrode 21 and the a-Si: H layer 24, which is a semiconductor active layer, is turned upside down.

According to the present embodiment, as shown in FIGS. 1-6 and 1-7, the transfer process can be performed without using an adhesive by activating and bonding the substrate surface. A TFT array substrate having excellent bonding strength can be formed. In addition, since two TFT array substrates can be obtained from one TFT array substrate (intermediate member) on which two TFT arrays are formed, productivity can be improved and manufacturing cost can be reduced. Furthermore, since the process is completed by transferring a set of TFT arrays, there is an advantage that no further transfer-related processes are necessary. Since no adhesive is used, the flatness is extremely excellent. When a liquid crystal display device is formed, the uniformity of the cell gap is excellent.

In this example, Lucari earth-aluminoborosilicate glass (trade name: code 1737, manufactured by Corning) was used as the substrate 10 and the second substrate 200, but barium-borosilicate glass (trade name: code 7059, Corning) or alkali-free glass (trade name: AN100, manufactured by Asahi Glass) may be used. Further, as the substrate 10 and the second substrate 200, a glass substrate or a bare glass substrate in which a SiO ₂ film is deposited on the surface using TEOS may be used. In the case where it corresponds to a display device such as a flexible display, a flexible substrate such as a metal substrate such as plastic or stainless steel may be used for the second substrate 200.

In this embodiment, the arrangement of the two sets of TFT arrays 71 and 72 is in a translational symmetry relationship (for example, the arrangement pattern shown in FIG. 8), and the two sets of TFT arrays in a translational symmetry relationship are Although they are in an exclusive relationship, it is also possible to have a rotationally symmetric relationship and an exclusive relationship. In the present specification, “excluded from each other” means that they are transferred to different substrates. The arrangement of the two sets of TFT arrays 71 and 72 is not limited to these.

(Example 2)
A method for manufacturing a semiconductor device according to the second embodiment will be described below with reference to FIGS.
In this embodiment, the process of transferring the TFT array is performed twice. In the method of manufacturing a semiconductor device according to this embodiment, from the intermediate member 500 to the step of transferring the first set of TFT arrays, (1) the separation layer 11 is made of hydrogenated amorphous silicon and the substrate of the first substrate 100 Example 2 is the same as Example 1 except that it is provided on the entire surface and (2) the separation process is performed by laser ablation.

After performing the first transfer process using a method such as laser ablation, the upper surface 500 s of the intermediate member 500 and the upper surface 300 s of the third substrate 300 are activated, so that FIGS. As shown, the upper surface 500s of the intermediate member 500 and the upper surface 300s of the convex portion 300a of the third substrate 300 are joined. Thereafter, as shown in FIG. 2-3, the substrate 10 is separated and removed. When there is no other TFT array to be transferred onto the intermediate member 500, the upper surface 300s of the third substrate 300 may be a flat surface.

In this embodiment, the case where two sets of TFT arrays are transferred has been shown. However, when the separation process is performed by laser ablation as in this embodiment, two or more TFTs can be formed from one TFT array substrate (intermediate member) by selectively irradiating the separation layer with laser light. An array substrate can be obtained, and productivity can be further improved as compared with Example 1. Also in this example, as in Example 1, it is possible to perform a transfer step without using an adhesive by activating and bonding the substrate surfaces, and a TFT array having excellent heat resistance and bonding strength. A substrate can be formed.

(Example 3)
A method for manufacturing a semiconductor device according to the third embodiment will be described below with reference to FIGS.
First, as shown in FIG. 3A, the first substrate 100 is formed in the same manner as in the first embodiment. Subsequently, a SiO ₂ film (not shown) having a thickness of about 100 nm is formed on the entire top surface of the silicon oxide film 12 of the first substrate 100, and then silane (hereinafter referred to as “SiH ₄ ”) gas. By using the PECVD method, an a-Si: H layer having a thickness of about 50 nm to be an active layer of the TFT is deposited, and then dehydrogenation annealing is performed. Subsequently, the polycrystalline silicon film 30 is obtained by performing laser irradiation heating with an excimer laser and crystallizing the a-Si: H layer. Note that the heating of the a-Si: H layer is not limited to irradiation heating with an excimer laser, and may be irradiation heating with another laser or heating using a furnace, for example.

Next, as shown in FIG. 3B, the polycrystalline silicon film 30 is patterned into an island shape. Thereafter, as shown in FIG. 3C, a gate insulating film 23 having a film thickness of 30 to 100 nm is deposited by PECVD using SiH ₄ gas and nitrogen oxide (N ₂ O) gas. Next, as shown in FIG. 3-4, the gate electrode 21 and the auxiliary capacitance common wiring 22 are formed of a metal having heat resistance such as tungsten.

Subsequently, as shown in FIG. 3-5, after implanting impurity ions into the source and drain formation regions, activation annealing is performed to form the source and drain regions 34. The gate electrode material is polycrystalline silicon doped with impurities at a high concentration and tungsten silicide, but the material may be polycrystalline silicon alone, other refractory metal or silicide, and the necessary resistance and heat resistance can be obtained. Selected in consideration.

Next, as shown in FIG. 3-6, SiO ₂ or SiN _x is deposited as the interlayer insulating film 27. When separation is performed by etching as in this embodiment, a thin SiN _x film or the like is formed thereon as an etching stopper 28 as necessary, and a SiO ₂ film 29 is deposited on the uppermost layer. Here, a SiO ₂ film 29 was deposited by PECVD using TEOS. Finally, the intermediate member 500 is obtained by polishing and flattening the surface of the uppermost SiO ₂ film 29 by CMP or the like.

Next, as shown in FIGS. 3-7 and 3-8, the upper surface 500s of the intermediate member 500 and the upper surface 200s of the convex portion 200a of the second substrate 200 are joined. First, the second substrate 200 is prepared in which the region corresponding to the transfer is left as the convex portion 200a, and the surface of the other portion is etched to form the concave portion 200b. Next, the upper surface 500 s of the intermediate member 500 and the upper surface 200 s of the second substrate 200 are immersed in an SC1 solution or the like containing hydrogen peroxide, or after being immersed in an SC1 solution or the like and then exposed to atmospheric pressure plasma. Then, the upper surface 500 s of the intermediate member 500 and the upper surface 200 s of the second substrate 200 are activated and bonded to each other.

Next, as shown in FIG. 3-9, a set of TFT arrays 74 that are not transferred are separated and removed from the separation layer 11 together with the first substrate 100. As a result, as shown in FIGS. 3-10 and 3-11, two types of TFT array substrates are obtained in which the positional relationship between the gate electrode 21 and the a-Si: H layer 24, which is a semiconductor active layer, is turned upside down. .

By using the method of the present embodiment, it is possible to obtain two TFT array substrates from one TFT array substrate (intermediate member) as in the first embodiment, so that productivity can be improved. it can. Further, by activating and bonding the substrate surfaces, the transfer process can be performed without using an adhesive, and an array having excellent heat resistance and bonding strength can be formed. Furthermore, since the process is completed by transferring one TFT array as in the first embodiment, there is an advantage that no further transfer-related process is necessary.

Example 4
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to FIGS.
In the manufacturing method of the semiconductor device according to the present embodiment, (1) the separation layer 11 is made of hydrogenated amorphous silicon until the step of transferring the first set of TFT arrays from the intermediate member 500, (2) Similar to Example 3 except that the separation process is performed by laser ablation, and (3) the separation layer 11 is provided on the entire surface of the first substrate 100 and two or more TFT arrays can be selectively transferred. Therefore, it is omitted.

After performing the first transfer process using a method such as laser ablation, as shown in FIGS. 4-1 and 4-2, the upper surface 500s of the intermediate member 500 and the upper surface 300s of the convex portion 300a of the third substrate 300 are used. And join. First, at least the surface 500 s of the SiO ₂ film 29 formed on the TFT array 74 on the first substrate 100 and the upper surface 300 s of the convex portion 300 a of the third substrate 300 are activated and bonded. Thereafter, as shown in FIG. 4-3, the first substrate 100 is separated and removed from the third substrate 300 by a method such as applying shearing stress, tensile stress, or twisting stress, or impregnating an etching solution. .

By using the method of this embodiment, it is possible to obtain two or more TFT array substrates from one TFT array substrate (intermediate member) as in the first embodiment. , Productivity can be further improved. In addition, the transfer process can be performed without using an adhesive by activating and bonding the substrate surfaces, and a TFT array substrate having excellent heat resistance and bonding strength can be formed.

In the present embodiment, a method such as laser ablation is used to separate the TFT array 74 bonded to the upper surface 300s of the convex portion 300a of the third substrate 300 from the intermediate member 500. It is not limited to. For example, the separation layer 11 is formed using a material that dissolves with a different etchant for each TFT array to be transferred. By forming such a separation layer, it is possible to selectively separate three or more sets of TFT arrays even if separation by etching is performed.

(Example 5)
FIGS. 5-1 to 5-8 are schematic cross-sectional views illustrating the manufacturing flow of the semiconductor device according to the fifth embodiment.
First, using a single-crystal silicon substrate 400, a standard LSI manufacturing process, a bulk MOS (Metal Oxide Semiconductor) transistor gate, source / drain, LDD (Lightly Doped Drain), threshold control and short channel effect countermeasures For this purpose, an impurity ion implantation process such as Pocket implantation or HALO implantation is performed. Next, the gate electrode 21 is formed using a polycrystalline silicon film doped with impurities at a high concentration. At the same time, a peripheral drive circuit is formed. Accordingly, in this embodiment, the single crystal silicon substrate 400 is used to have a rotationally symmetric relationship with two sets of pixel arrays (for example, the arrangement shown in FIG. 9-1) that are in a rotationally symmetric and exclusive relationship with each other. A driver monolithic active matrix array including two sets of peripheral drive circuits (not shown) is formed. When the entire circuit is considered, the pixel arrays forming the two sets of peripheral drive circuits do not have to be rotationally symmetric with respect to the two sets of pixel arrays or the peripheral drive circuits that are in an exclusive relationship. , A portion may be translationally symmetric and is not particularly limited.

Next, an SiO ₂ film 38 is deposited and the surface is planarized by CMP or the like, and a metal film such as molybdenum (Mo) or tungsten (W) is selectively formed as an ion implantation mask. Specifically, after a metal film such as molybdenum (Mo) or tungsten (W) is formed, it is left on the upper layer of a set of driver monolithic active matrix arrays 76 transferred a second time by general photolithography. Next, the metal film is patterned. Using this as a mask 41, hydrogen ions and / or rare gas ions are implanted to a predetermined depth in a region where a pair of driver monolithic active matrix arrays 75 to be transferred for the first time are formed, thereby forming isolation regions 11. . Thereby, the intermediate member 600 is obtained.

Next, as shown in FIG. 5B, the second substrate 200 is prepared similarly to the first embodiment, and as shown in FIG. 5C, the upper surface 600s of the intermediate member 600 and the convex portion 200a of the second substrate 200. The upper surface 200s is joined. Specifically, the upper surface 600s of the intermediate member 600 and the upper surface 200s of the second substrate 200 are immersed in an SC1 solution or the like containing hydrogen peroxide, or exposed to atmospheric pressure plasma after being immersed in the SC1 solution or the like. Thus, the upper surface 600s of the intermediate member 600 and the upper surface 200s of the second substrate 200 are activated and bonded to each other by being brought into close contact with each other. Further, the bonding strength is increased by performing heat treatment.

Next, the separation layer 11 is heated and applied with a shearing stress, a tensile stress, a torsional stress, or a method of impregnating an etching solution, as shown in FIG. 5-4. Then, the driver monolithic active matrix array 76 that is not transferred is separated and removed together with the single crystal silicon substrate 400. Note that a set of driver monolithic active matrix arrays to be transferred may be separated only by heating, or in addition to heating, shear stress, tensile stress, or torsional stress may be applied.

Thereafter, as shown in FIG. 5-5, silicon film thickness adjustment, element isolation etching, polishing, and the like are performed, an interlayer insulating film 35 is deposited, contact holes are formed on the source and drain regions, and source wiring is formed. The drain wiring 42, the pixel electrode (not shown), and the like are formed.

Similarly to the first transfer step, as shown in FIG. 5-6, hydrogen ions and / or rare gas ions are applied to the remaining set of driver monolithic active matrix arrays 76 on the single crystal silicon substrate 400. The separation region 11 is formed by implanting to a predetermined depth.

Next, the third substrate 300 is prepared, and the upper surface 600s of the intermediate member 600 and the upper surface 300s of the convex portion 300a of the third substrate 300 are joined. Specifically, the upper surface 600s of the intermediate member 600 and the upper surface 300s of the third substrate 300 are immersed in an SC1 solution or the like containing hydrogen peroxide, or exposed to atmospheric pressure plasma after being immersed in the SC1 solution or the like. Thus, the upper surface 600s of the intermediate member 600 and the upper surface 300s of the third substrate 300 are activated and bonded to each other by being brought into close contact with each other. Furthermore, as shown in FIG. 5-7, the bonding strength is increased by performing a heat treatment, and the single crystal silicon substrate 400 is separated and removed by separation by the separation layer 11, and the same process as the first transfer is performed. Thus, another driver monolithic active matrix array substrate as shown in FIGS. 5-8 is obtained.

In this embodiment, the portions other than the portion where the driver monolithic active matrix array 76 of the third substrate 300 is transferred in the second transfer are etched and lowered. However, it is not necessary to form a convex portion or a concave portion by etching or the like for the substrate used for the final transfer. The intermediate member may be opaque, and a transmissive display panel can be formed by transferring the TFT array to a transparent substrate such as a glass substrate or a quartz substrate.

As described above, a driver monolithic active matrix array substrate formed of single crystal silicon TFTs on a low-cost glass substrate can be manufactured, and one driver monolithic active matrix array substrate (intermediate member) Since two driver monolithic active matrix array substrates can be manufactured, a semiconductor device having excellent productivity, cost, and performance can be realized. In particular, when the semiconductor device according to the present embodiment is applied as a projection panel, a beautiful display that does not cause display unevenness due to the grain boundary of polycrystalline silicon can be obtained even under high illumination light. In addition, by using the method of this example, it is possible to perform a transfer process without using an adhesive by activating and bonding the substrate surface in the same manner as in Examples 1-4. A TFT array suitable as a liquid crystal display panel having excellent bonding strength and flatness can be formed.

In this embodiment, the driver includes two sets of pixel arrays that are rotationally symmetric and exclusive with each other and two sets of peripheral drive circuits (for example, the arrangement shown in FIG. 9-2) that are rotationally symmetric. The case where the monolithic active matrix array is formed and the driver monolithic active matrix array is transferred one by one has been described. However, the pixel arrays formed using the single crystal silicon substrate 400 are in translational symmetry with each other. Also good.

(Example 6)
In Example 6, a method for forming a separation layer having a structure with a gap will be described below with reference to FIGS.
FIG. 6A is a schematic plan view illustrating the configuration of the separation layer. FIGS. 6-2 to 6-5 are schematic cross-sectional views illustrating the manufacturing flow of the separation layer. FIG. 6B shows a cross section taken along line A-B shown in FIG.

First, on a quartz substrate, high strain point glass, or a metal substrate such as stainless steel provided with an insulating film on the surface, hydrochloric acid and / or phosphate-soluble substances such as MoO ₂ , GeO, ZnO, Al, or amorphous silicon A soluble material layer 53 made of an alkali-soluble material such as polycrystalline silicon is deposited.

Next, after depositing a SiO ₂ film of approximately 0.3 μm on the soluble material layer 53 using the PECVD method, the SiO ₂ film is patterned using a photolithographic method, as shown in FIG. In this way, the lattice pattern 51 as fine as possible is formed. At this time, as shown in FIG. 6B, by etching so that the groove pattern 51 reaches the soluble material layer 53, a plurality of fine columnar SiO ₂ films 52 are formed. In this embodiment, the width of the groove pattern 51 is approximately 1 μm. Further, the pitch of the grooves is determined by the mechanical strength of the separation layer.

Next, as shown in FIG. 6C, an undercut 54 is formed by etching the soluble material layer 53 using an etchant. Next, as shown in FIG. 6-4, a SiO ₂ film 12 having a film thickness of about 0.5 to 1 μm is deposited by PECVD. Subsequently, the SiO ₂ film 12 is polished to form the final structure shown in FIG. This polishing step may be omitted if the flatness is not particularly problematic in the subsequent steps. Devices according to Examples 1 to 4 are formed on the separation layer. In the first and third embodiments in which two sets of TFT arrays and the like are formed on the first substrate 100 and one set is not separated from the first substrate 100, a separation layer is formed below the TFT array that is not separated. Shall not form.

By forming a separation layer having a partially spaced structure as in this embodiment, it is possible to facilitate separation of the TFT array and the like in the transfer process. In particular, the separation layer formed using alkali, hydrochloric acid and / or phosphoric acid soluble materials such as MoO ₃ , GeO, ZnO, Al, etc. as a material is composed of SiO ₂ as a main material even when etching is used for separation. Therefore, it can be said to be a more suitable material because it has less possibility of affecting the substrate and the formed semiconductor element.

(Example 7)
In Example 7, a method for forming a separation layer having a partially spaced structure on a substrate 10 according to an embodiment of the present invention will be described below with reference to FIGS.
FIGS. 7-1 to 7-4 are schematic cross-sectional views illustrating the manufacturing flow of the separation layer.
First, approximately 0.2 μm of SiN _x is deposited on the substrate 10 using PECVD. Next, using the photolithography method, the smallest possible lattice-like groove pattern 51 is formed in the same manner as in FIG. At this time, as shown in FIG. 7-1, a plurality of fine columnar SiN _x films 53 are formed by etching so that the groove pattern 51 reaches the glass substrate or the metal substrate. In the present embodiment, the width of the groove pattern 51 is approximately 1 μm. Further, the pitch of the grooves is determined by the mechanical strength of the separation layer.

Further, as shown in FIG. 7-2, when a glass substrate is used as the substrate 10, buffered hydrofluoric acid (buffered hydrofluoric acid: BHF) is used, and when a metal substrate is used as the substrate 10, the metal can be etched. Using an appropriate etchant, the substrate 10 is etched using the SiN _x film 53 as a mask to form an undercut 54. When a glass substrate is used as the substrate 10, the SiO ₂ film 12 is further formed on the SiN _x film 53 as shown in FIG. Therefore, in the separation by etching, there is a possibility that the SiO ₂ film 12 may be dissolved at the same time as the outermost surface of the substrate 10, and therefore the separation is performed by a shear stress. However, if a single layer of SiNx film is sandwiched on the device side, it can also be separated by etching.

Next, as shown in FIG. 7C, a SiO ₂ film having a film thickness of about 0.5 to 1 μm is deposited by PECVD. Then, it grind | polishes so that the whole may become flat, and the final structure shown to FIGS. 7-4 is formed. Devices according to Examples 1 to 4 are formed on the separation layer.

Since the separation layer produced in this example uses the substrate 10 as the soluble material layer, it is not necessary to provide a layer corresponding to the soluble material layer 53 in Example 6. Therefore, compared with the case of Example 6, it has the advantage that the number of processes can be reduced. Further, by forming a separation layer having a partially spaced structure as in this embodiment, it is possible to facilitate separation of the TFT array and the like in the transfer process.

(Example 8)
FIG. 8 is a schematic plan view when components of two sets of pixel arrays that are mutually exclusive are arranged on the first substrate 100 in a translationally symmetric relationship. Note that the source wirings 68a and 68b indicated by dotted lines in FIG. 8 are formed on the transferred substrate after the two sets of pixel arrays are transferred, and the source wirings are to be arranged. The positional relationship is shown.

By forming two sets of pixel arrays in the arrangement shown in FIG. 8, one set each including the TFT 58a or 58b, the auxiliary capacitance electrode 59a or 59b, the gate wiring 69a or 69b, and the auxiliary capacitance common wiring 70a or 70b. These pixel arrays can be transferred, and two pixel array substrates can be manufactured from one pixel array substrate. Further, the auxiliary capacitance element is formed in a region where the auxiliary capacitance electrode 59a or 59b and the auxiliary capacitance common wiring 70a or 70b overlap.

Example 9
FIG. 9A is a schematic plan view illustrating a configuration of a pixel array portion of two sets of driver monolithic active matrix arrays which are disposed on the first substrate and are mutually exclusive. Note that the source lines 68a and 68b indicated by dotted lines in FIG. 9-1 are formed on the transferred substrate after the two sets of pixel arrays are transferred, and the source lines are arranged. Shows the schedule location. FIG. 9-2 is a schematic plan view showing the arrangement relationship of two sets of driver monolithic active matrix arrays which are arranged on the first substrate and are mutually exclusive.
By forming two sets of pixel arrays arranged in a rotationally symmetrical manner as shown in FIG. 9A, as shown in FIG. 9B, the TFT 58a, the auxiliary capacitance electrode 59a, the gate wiring 69a and the auxiliary capacitance common wiring 70a. The peripheral drive circuit 60 corresponding to the pixel array including the pixel and the peripheral drive circuit 61 corresponding to the pixel array including the TFT 58b, the auxiliary capacitance electrode 59b, the gate wiring 69b, and the auxiliary capacitance common wiring 70b may be arranged at rotationally symmetric positions. it can. Further, the auxiliary capacitance element is formed in a region where the auxiliary capacitance electrode 59a or 59b and the auxiliary capacitance common wiring 70a or 70b overlap.

This makes it possible to form two sets of driver monolithic active matrix arrays in the same region. Further, by arranging them in this rotationally symmetrical relationship, as shown in FIG. 10, the peripheral drive circuit 60 and the pixel array corresponding to the peripheral drive circuit 60 and the peripheral drive circuit 61 and the pixels corresponding to the peripheral drive circuit 61 are arranged. Arrays can be arranged, and two sets of driver monolithic active matrix arrays can be arranged at high density on one mother glass. This arrangement of two driver monolithic active matrix arrays in a rotationally symmetric relationship can be used in the manufacture of a semiconductor device according to the fifth embodiment of the present invention. In the case of a TFT array or a pixel array that does not form a driver monolithic active matrix array, the arrangement of the pixel array in FIGS. 8 and 9-1 is applied in the manufacture of the semiconductor device according to the first, third, and fifth embodiments. can do. When the peripheral drive circuit and the pixel array are formed on one substrate, the TFT semiconductor active layer included in the peripheral drive circuit is formed of polycrystalline silicon, and the TFT semiconductor active layer included in the pixel array is formed of amorphous silicon. It is possible to preferably use a form in which both the peripheral drive circuit and the semiconductor active layer of the TFT included in the pixel array are formed of polycrystalline silicon. According to this, it is possible to improve the performance of the drive circuit.

(Example 10)
FIG. 11 shows an example when four sets of TFT arrays are formed on the first substrate 100.
The TFTs arranged as shown in FIG. 11 are transferred to the second substrate in order of the TFT 63 transferred the first time, the TFT 64 transferred the second time, the TFT 65 transferred the third time, and the TFT 66 transferred the fourth time. Do. Such an arrangement can be used in the manufacture of the semiconductor device according to the second, fourth, and fifth embodiments of the present invention. Here, an example of the first substrate 100 on which four sets of TFT arrays are formed is shown, but this is not a limitation, and the number of sets of TFT arrays may be three or five, Moreover, the number beyond it may be sufficient. If the number of TFT array groups is three or more, it is not possible to prepare a completely connected bus line wiring for each group. Therefore, it is necessary to separately form wirings connecting the whole after transfer. is there.

It is a cross-sectional schematic diagram which shows the structure of a 1st board | substrate (Example 1). FIG. 6 is a schematic cross-sectional view showing a step of forming a gate electrode and a gate wiring (Example 1). It is a cross-sectional schematic diagram which shows the process of forming the gate insulating film, the a-Si: H layer used as the active layer of TFT, and the n ^<+> a-Si: H layer used as the source electrode and drain electrode of TFT (Example) 1). (Example 1) which is a cross-sectional schematic diagram which shows the process of patterning an a-Si: H layer and an n ^<+> a-Si: H layer. Source - etching of the gap portion between the drain, the formation of metal wiring, formation of an etching stopper, the formation of the interlayer insulating film is a schematic sectional view showing a process of planarizing the formation and the surface of the outermost SiO ₂ film (Example 1). It is a cross-sectional schematic diagram which shows the joining process of a 1st board | substrate and a 2nd board | substrate (Example 1). It is a cross-sectional schematic diagram which shows the 1st board | substrate and the 2nd board | substrate after joining (Example 1). (Example 1) which is a cross-sectional schematic diagram which shows the process of isolate | separating the 1st board | substrate and the TT array which does not perform transcription | transfer from the state after joining of a 1st board | substrate and a 2nd board | substrate. In addition, the white arrow in a figure has shown the advancing direction of the intermediate member 500. FIG. (Example 1) which is a cross-sectional schematic diagram which shows the structure of the 2nd board | substrate after transferring 1 set of TFT arrays. FIG. 3 is a schematic cross-sectional view showing the configuration of the first substrate after transferring a set of TFT arrays (Example 1). (Example 2) which is a cross-sectional schematic diagram which shows the joining process of the 1st board | substrate after transferring 1 set of TFT arrays, and a 3rd board | substrate. (Example 2) which is a cross-sectional schematic diagram which shows the state after joining the 1st board | substrate after transferring 1 set of TFT arrays, and a 3rd board | substrate. (Example 2) which is a cross-sectional schematic diagram which shows the isolation | separation process of the TFT array which does not perform a 1st board | substrate and transcription | transfer from the state after joining a 1st board | substrate and a 3rd board | substrate. (Example 3) which is a cross-sectional schematic diagram which shows the structure of the 1st board | substrate after the process of forming a polycrystalline-silicon film. (Example 3) which is a cross-sectional schematic diagram which shows the structure of the 1st board | substrate after the patterning process of a polycrystalline-silicon film. (Example 3) which is a cross-sectional schematic diagram which shows the structure of the 1st board | substrate after a gate oxide film formation process. It is a cross-sectional schematic diagram which shows the structure of the 1st board | substrate after a gate electrode formation process (Example 3). (Example 3) which is a cross-sectional schematic diagram which shows the structure of the 1st board | substrate after the process of performing impurity ion implantation to a source-drain region and activation annealing. (Example 3) which is a cross-sectional schematic diagram which shows the structure of the 1st board | substrate after the formation process of an interlayer insulation film. It is a cross-sectional schematic diagram which shows the joining process of a 1st board | substrate and a 2nd board | substrate (Example 3). In addition, the white arrow in a figure has shown the advancing direction of the intermediate member 500. FIG. It is a cross-sectional schematic diagram which shows the 1st board | substrate and the 2nd board | substrate after joining (Example 3). (Example 3) which is a cross-sectional schematic diagram which shows the process of isolate | separating the 1st board | substrate and the TT array which does not perform transcription | transfer from the state after joining of a 1st board | substrate and a 2nd board | substrate. (Example 3) which is a cross-sectional schematic diagram which shows the structure of the 2nd board | substrate after transferring one set of TFT arrays. (Example 3) which is a cross-sectional schematic diagram which shows the structure of the 1st board | substrate after transferring one set of TFT arrays. (Example 4) which is a cross-sectional schematic diagram which shows the joining process of the 1st board | substrate after transferring 1 set of TFT arrays, and a 3rd board | substrate. (Example 4) which is a cross-sectional schematic diagram which shows the state after joining the 1st board | substrate after transferring 1 set of TFT arrays, and a 3rd board | substrate. (Example 4) which is a cross-sectional schematic diagram which shows the isolation | separation process of the TFT array which does not perform a 1st board | substrate and transcription | transfer from the state after joining a 1st board | substrate and a 3rd board | substrate. (Example 5) which is a cross-sectional schematic diagram which shows the cross section of the single crystal silicon substrate after the process of forming an isolation layer in the lower part of a TFT array. In addition, the arrow in a figure represents the direction of ion implantation. (Example 5) which is a cross-sectional schematic diagram which shows the joining process of the single crystal silicon substrate in which the TFT array was formed, and a 2nd board | substrate. (Example 5) which is a cross-sectional schematic diagram which shows the form after the joining process of the single crystal silicon substrate in which the TFT array was formed, and a 2nd board | substrate. (Example 5) It is a cross-sectional schematic diagram which shows the separation process of the single crystal silicon substrate which formed the TFT array from the state after joining of the single crystal silicon substrate and TFT substrate which formed the TFT array, and the TFT array which does not perform transfer. ). (Example 5) which is a cross-sectional schematic diagram which shows the 2nd board | substrate after forming the wiring etc. to the transferred TFT array. (Example 5) which is a cross-sectional schematic diagram which shows the joining process of the single crystal silicon substrate after transferring 1 set of TFT arrays, and a 3rd board | substrate. (Example 5) which is a cross-sectional schematic diagram which shows the isolation | separation process of the TFT array which does not perform a 1st board | substrate and transcription | transfer from the state after joining of a single crystal silicon substrate and a 3rd board | substrate. (Example 5) which is a cross-sectional schematic diagram which shows the 2nd board | substrate after forming the wiring etc. to the TFT array transcribe | transferred to the 2nd board | substrate. FIG. 10 is a schematic plan view showing a separation layer after forming a fine lattice-like groove pattern (Example 6). Sectional schematic diagram (Example 6) which shows the separation layer after forming a fine lattice-like groove pattern. Sectional schematic diagram which shows the separated layer after forming an undercut (Example 6). Cross-sectional view schematically showing a separation layer after the deposition of the SiO ₂ film (Example 6). Cross-sectional view schematically showing a separation layer after the surface planarization of the SiO ₂ film (Example 6). Cross-sectional schematic diagram (Example 7) which shows the separation layer after forming a fine lattice-like groove pattern. Sectional schematic diagram which shows the separated layer after forming an undercut (Example 7). Cross-sectional view schematically showing a separation layer after the deposition of the SiO ₂ film (Example 7). Cross-sectional view schematically showing a separation layer after flattening the surface of the SiO ₂ film (Example 7). (Example 8) which is a plane schematic diagram when two mutually exclusive TFT arrays are arrange | positioned by the translation symmetrical relationship. FIG. 10 is a schematic plan view when two mutually exclusive TFT arrays are arranged in a rotationally symmetric relationship (Example 9). (Example 9) which is a top schematic diagram which shows arrangement | positioning of the driver corresponding to each array when arrange | positioning two sets of TFT arrays by the rotationally symmetrical relationship. (Example 9) which is a top schematic diagram which shows the several driver monolithic active matrix array formed on one mother glass substrate. FIG. 10 is a schematic plan view showing an example when four sets of TFT arrays are formed on a first substrate (Example 10).

Explanation of symbols

10: Substrate 11: Separation layer, separation regions 12, 29, 38: Silicon oxide film (SiO ₂ film)
21: Gate electrodes 22, 70a, 70b: Auxiliary capacitance common wiring 23: Gate insulating film 24: a-Si: H layer 25: n ⁺ a-Si: H layer 26: Metal wiring 27, 35: Interlayer insulating film 28: Etching stopper 30: Polycrystalline silicon film 34: Source and drain region 37: LOCOS oxide film 41: Photoresist 42: Source wiring and drain wiring 51: Grid-like groove pattern 52: Fine columnar silicon oxide film 53: Soluble Material 54: Undercut 57: Fine columnar silicon nitride film 58a, 58b: TFT
59a, 59b: Auxiliary capacitance electrodes 60, 61: Peripheral drive circuit 62: Two pixel arrays 63, 75, 76: Driver monolithic active matrix array 64: Semiconductor element 65 transferred to the first time 65: Transferred to the second time Semiconductor element 66: Semiconductor element transferred at the third time 67: Semiconductor elements 68a and 68b transferred at the fourth time: Source wirings 69a and 69b: Gate wirings 71 to 74: TFT array 100: First substrate 200: Second substrate 200a: second substrate convex portion 200b: second substrate concave portion 200s: second substrate upper surface 300: third substrate 300a: third substrate convex portion 300b: third substrate concave portion 300s: third substrate upper surface 400 : Single crystal silicon substrate 500, 600: intermediate member 500s, 600s: upper surface of intermediate member

Claims (28)

A semiconductor device having a semiconductor element on a substrate,
The substrate has a convex portion on the surface on which the semiconductor element is disposed,
The semiconductor element is disposed on the upper surface of the convex portion of the substrate ,
The semiconductor device, wherein the semiconductor element is bonded to the upper surface of the convex portion of the substrate without an adhesive . The semiconductor device, the semiconductor device according to claim 1, characterized in that it comprises a pixel switching element. The semiconductor device according to claim 2 , wherein the semiconductor element includes a pixel switching element and an auxiliary capacitance element. 4. The semiconductor device according to claim 2 , wherein the pixel switching element is a thin film transistor. The semiconductor device, the semiconductor device according to any one of claims 1 to 4, characterized in that it comprises a pixel array. The semiconductor device, the semiconductor device according to any one of claims 1 to 5, characterized in that a peripheral driving circuit. The semiconductor device, the semiconductor device according to any one of claims 1 to 6, characterized in that it comprises a pixel array and a peripheral driving circuit. The semiconductor device, the semiconductor device according to any one of claims 1 to 7, characterized in that it comprises a single crystal silicon device. The pixel array includes a pixel switching element including amorphous silicon,
8. The semiconductor device according to claim 7 , wherein the peripheral driver circuit includes a thin film transistor including polycrystalline silicon. 8. The semiconductor device according to claim 7, wherein each of the pixel array and the peripheral drive circuit includes a thin film transistor including polycrystalline silicon. Display device characterized by being configured to include a semiconductor device according to any one of claims 1-10. It is a manufacturing method of the semiconductor device in any one of Claims 1-10 ,
The manufacturing method includes a step of transferring a semiconductor element or a component thereof to an upper surface of a convex portion of a substrate. The transfer step is a process of activating at least one of the upper surface of the intermediate member in which two or more sets of semiconductor elements or components thereof are arranged side by side, and the upper surface of the convex portion of the substrate;
A process of joining the upper surface of the intermediate member at least one of which is activated and the upper surface of the convex portion of the substrate;
13. A semiconductor device according to claim 12 , further comprising a process of separating a set of semiconductor elements or components thereof immediately below the upper surface of the intermediate member bonded to the upper surface of the convex portion of the substrate from the intermediate member. Manufacturing method. 14. The method for manufacturing a semiconductor device according to claim 13 , wherein the activation process is performed by an aqueous solution process containing hydrogen peroxide. 15. The method of manufacturing a semiconductor device according to claim 14 , wherein the activation process is performed by combining an aqueous plasma process including hydrogen peroxide with an atmospheric pressure plasma process. The method for manufacturing a semiconductor device according to claim 12 , wherein the transfer step performs a heat treatment. In the intermediate member, two or more sets of semiconductor elements or components thereof are arranged in parallel on an insulating substrate, and the semiconductor elements or components thereof are inserted from the intermediate member between the insulating substrate and the semiconductor elements or components thereof. Having a separation layer for separation,
The separation process is characterized in that a separation layer is used to separate a set of semiconductor elements or components thereof immediately below the upper surface of the intermediate member bonded to the upper surface of the convex portion of the substrate from the intermediate member. Item 17. A method for manufacturing a semiconductor device according to any one of Items 13 to 16 . The separation layer is composed of hydrogenated amorphous silicon,
18. The method of manufacturing a semiconductor device according to claim 17 , wherein the separation process liquefies the separation layer by laser ablation or generates a gas from the separation layer. The intermediate member includes two or more sets of semiconductor elements having active regions in the single crystal silicon substrate or components thereof arranged in parallel, and in the single crystal silicon substrate on the bottom side of the single crystal silicon substrate from the active region, It has a separation region for separating the semiconductor element or its component from the intermediate member,
The separation process is characterized in that the separation region is used to separate a set of semiconductor elements or components thereof immediately below the upper surface of the intermediate member bonded to the upper surface of the convex portion of the substrate from the intermediate member. Item 17. A method for manufacturing a semiconductor device according to any one of Items 13 to 16 . 20. The method of manufacturing a semiconductor device according to claim 19 , wherein the isolation region is formed by implanting hydrogen ions and / or rare gas ions into a single crystal silicon substrate. The separation layer or separation region has a structure with a gap,
20. The semiconductor device according to claim 17 , wherein in the separation process, a shear stress, a tensile stress, or a torsional stress is applied to the separation layer or the separation region, or the separation layer or the separation region is etched. Production method. The isolation layer or isolation region is composed of at least one selected from the group consisting of molybdenum oxide, germanium oxide, zinc oxide and aluminum, or silicon,
20. The method of manufacturing a semiconductor device according to claim 17 , wherein the separation process is performed by etching a separation layer or a separation region. The intermediate member includes two or more sets of pixel switching elements or components thereof arranged in parallel,
23. The method of manufacturing a semiconductor device according to claim 13 , wherein the two or more sets of pixel switching elements or components thereof are arranged in a rotational symmetry or a translational symmetry in a pixel region. . The intermediate member includes two or more sets of pixel switching elements or components thereof and two or more sets of auxiliary capacitance elements or components thereof, respectively.
The two or more sets of pixel switching elements or components thereof, and the two or more sets of auxiliary capacitance elements and auxiliary capacitance elements or components thereof are arranged in rotational symmetry, translational symmetry, or mirror symmetry in the pixel region, respectively. 24. A method of manufacturing a semiconductor device according to claim 23 . 25. The semiconductor device according to claim 23, wherein the pixel switching element or a component thereof is a thin film transistor or a component thereof. The intermediate member has two sets of peripheral drive circuits arranged side by side,
26. The method of manufacturing a semiconductor device according to claim 13 , wherein the two sets of peripheral drive circuits are arranged rotationally symmetrically. The intermediate member includes two sets of pixel switching elements or components thereof, two sets of auxiliary capacitance elements or components thereof, and two sets of peripheral drive circuits or components thereof, respectively.
The two sets of pixel switching elements or components thereof, and the two sets of auxiliary capacitance elements or components thereof are respectively arranged rotationally symmetrically within the pixel region,
27. The method of manufacturing a semiconductor device according to claim 13 , wherein the two sets of peripheral drive circuits or components thereof are arranged rotationally symmetrically. The intermediate member includes a pixel switching element including amorphous silicon or a first intermediate member in which two or more pixel arrays each including the component are arranged in parallel, and a thin film transistor including polycrystalline silicon or a component thereof. A second intermediate member in which two or more sets of peripheral drive circuits or components thereof are arranged side by side;
The method of manufacturing the semiconductor device includes a step of transferring a pixel array or a component thereof from the first intermediate member to the upper surface of the first convex portion of the substrate, and a peripheral drive circuit or a component thereof from the second intermediate member of the substrate. The method for manufacturing a semiconductor device according to claim 13, further comprising a step of transferring to the upper surface of the second convex portion.

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