JP5171997B2 - Decoding method and decoding apparatus - Google Patents

Description

  The present invention relates to a decoding method and a decoding apparatus for a low-density parity check convolutional code (LDPC-CC) or a convolutional code.

  In recent years, low-density parity-check (LDPC) codes have attracted attention as error-correcting codes that exhibit high error correction capability with a feasible circuit scale. Since the LDPC code has a high error correction capability and is easy to implement, it has been adopted in an error correction coding system such as an IEEE802.11n high-speed wireless LAN system or a digital broadcasting system.

  The LDPC code is an error correction code defined by a low-density parity check matrix H. The LDPC code is a block code having a block length equal to the number N of columns of the parity check matrix H.

  However, many of the current communication systems are characterized in that transmission information is collectively transmitted for each variable-length packet or frame, as in Ethernet (registered trademark). When an LDPC code that is a block code is applied to such a system, for example, a problem arises as to how a block of a fixed-length LDPC code corresponds to a variable-length Ethernet (registered trademark) frame. IEEE802.11n adjusts the length of the transmission information sequence and the block length of the LDPC code by applying padding processing and puncture processing to the transmission information sequence, but the coding rate changes depending on the padding and puncture. Or transmitting a redundant sequence cannot be avoided.

  For an LDPC code of such a block code (hereinafter referred to as LDPC-BC: Low-Density Parity-Check Block Code), encoding / decoding of an information sequence of an arbitrary length is possible. Possible LDPC-CC (Low-Density Parity-Check Convolutional Code) has been studied (for example, see Non-Patent Document 1 and Non-Patent Document 2).

LDPC-CC is a convolutional code defined by a low-density parity check matrix. For example, a parity check matrix H ^T [0, n] of an LDPC-CC with a coding rate R = 1/2 (= b / c). Is shown in FIG.

Here, elements h ₁ ^(m) (t) and h ₂ ^(m) (t) of H ^T [0, n] take 0 or 1. In addition, all elements other than h ₁ ^(m) (t) and h ₂ ^(m) (t) included in the parity check matrix H ^T [0, n] are 0. M represents the memory length in LDPC-CC, and n represents the length of the LDPC-CC codeword. As shown in FIG. 20, in the parity check matrix of LDPC-CC, 1 is set only in the diagonal term of the matrix and its neighboring elements, the lower left and upper right elements of the matrix are zero, and the parallelogram It is characterized by being a matrix of shape.

ここで、ｕ_ｎは送信情報系列，ｖ_１，ｎ，ｖ_２，ｎは送信符号語系列を表す。 Here, taking the example of coding rate R = 1/2 (= b / c), when h ₁ ⁽⁰⁾ (t) = 1, h ₂ ⁽⁰⁾ (t) = 1, LDPC-CC Is performed by executing the following equation according to the parity check matrix H ^T [0, n].

Here, _{u n} denotes the transmission information _{sequence, v 1, n, v 2} , n is a transmission codeword sequence.

  FIG. 21 shows an example of an LDPC-CC encoder that executes Equation (1).

  As shown in FIG. 21, the LDPC-CC encoder 10 includes shift registers 11-1 to 11-M, 14-1 to 14-M, weight multipliers 12-0 to 12-M, and 13-0 to 13-13. -M, a weight control unit 17, a mod2 adder 15, and a bit number counter 16.

The shift registers 11-0 to 11-M and the shift registers 14-1 to 14-M hold ν _1, ni, ν _2, ni (i = 0,..., M), respectively. It is a register, and at the timing when the next input is input, the held value is sent to the shift register on the right and the value sent from the shift register on the left is held.

The weight multipliers 12-0 to 12-M and 13-0 to 13-M set the values of h ₁ ^(m) and h ₂ ^(m) to 0 or 1 according to the control signal sent from the weight control unit 17. Switch to.

Based on the count number sent from the bit number counter 16 and the parity check matrix held in the weight control unit 17, the weight control unit 17 uses h ₁ ^(m) and h ₂ ^{(m) at} that timing. Are sent to the weight multipliers 12-0 to 12-M and 13-0 to 13-M. mod2 adder 15, weight multipliers 12-0 to 12-M, by performing mod2 addition process on the output of 13-0~13-M, and calculates the ν _{2, n-i.} Number bit counter 16 counts the number of bits of transmission information sequence u _n entered.

  By adopting such a configuration, LDPC-CC encoder 10 can perform LDPC-CC encoding according to a parity check matrix.

  The LDPC-CC encoder can be realized with a much simpler circuit than the circuit that performs multiplication of the generator matrix and the LDPC-BC encoder that performs operations based on the backward (forward) substitution method. . Further, since LDPC-CC is a convolutional code encoder, it is not necessary to encode a transmission information sequence by dividing it into fixed-length blocks, and an information sequence of an arbitrary length can be encoded.

  By the way, a sum-product algorithm can be applied to LDPC-CC decoding. Therefore, it is not necessary to use a decoding algorithm that performs maximum likelihood sequence estimation such as the BCJR algorithm or the Viterbi algorithm, so that the decoding process can be completed with a low processing delay. Furthermore, a pipeline decoding algorithm has been proposed that takes advantage of the parity check matrix shape in which 1 stands in the shape of a parallelogram (see Non-Patent Document 1, for example).

  When the decoding characteristics of LDPC-CC and LDPC-BC are compared with parameters that make the circuit scale of the decoder equivalent, it is shown that the decoding characteristics of LDPC-CC are superior.

  Incidentally, there is a desire to reduce the operation scale by reducing the number of iterations of iterative decoding in sum-product decoding. Conventionally, shuffled BP (Belief-Propagation) decoding described in Non-Patent Document 3 and Layered BP decoding described in Non-Patent Document 4 have been proposed as techniques for reducing the number of iterations compared to Sum-product decoding. ing.

A. J. Felstorom, and K. Sh. Zigangirov, “Time-Varying Periodic Convolutional Codes With Low-Density Parity-Check Matrix,” IEEE Transactions on Information Theory, Vol. 45, No. 6, pp2181-2191, September 1999. G. Richter, M. Kaupper, and K. Sh. Zigangirov, “Irregular low-density parity-Check convolutional codes based on protographs,” Proceeding of IEEE ISIT 2006, pp1633-1637. J. Zhang, and M. P. C. Fossorier, “Shuffled iterative decoding,” IEEE Trans. Commun., Vol.53, no.2, pp.209-213, Feb. 2005. D. Hocevar, “A reduced complexity decoder architecture via layered decoding of LDPC codes,” in Signal Processing Systems SIPS 2004. IEEE Workshop on, pp.107-112, Oct. 2004. B. Lu, G. Yue, and X. Wang, “Performance analysis and design optimization of LDPC-coded MIMO OFDM systems” IEEE Trans. Signal Processing., Vol.52, no.2, pp.348-361, Feb. 2004. B. M. Hochwald, and S. ten Brink, “Achieving near-capacity on a multiple-antenna channel” IEEE Trans. Commun., Vol.51, no.3, pp.389-399, March 2003. S. Baro, J. Hagenauer, and M. Wizke, “Iterative detection of MIMO transmission using a list-sequential (LISS) detector” Proceeding of IEEE ICC 2003, pp2653-2657. S. Lin, D. J. Jr., Costello, “Error control coding: Fundamentals and applications,” Prentice-Hall. R. D. Gallager, “Low-Density Parity-Check Codes,” Cambridge, MA: MIT Press, 1963. MPC Fossorier, M. Mihaljevic, and H. Imai, “Reduced complexity iterative decoding of low density parity check codes based on belief propagation,” IEEE Trans. Commun., Vol.47., No.5, pp.673-680, May 1999. J. Chen, A. Dholakia, E. Eleftheriou, MPC Fossorier, and X.-Yu Hu, “Reduced-complexity decoding of LDPC codes,” IEEE Trans. Commun., Vol.53., No.8, pp.1288 -1299, Aug. 2005.

  By the way, to further improve the communication speed, the number of iterations of iterative decoding is further reduced than the above-described shuffled BP decoding and layered BP decoding, thereby further reducing the operation scale and enabling higher-speed operation. A decoding device is required. Conventionally, in particular, little consideration has been given to methods for effectively reducing the number of iterations in LDPC-CC and improving processing delay.

  The present invention has been made in view of such points, and provides a decoding method and decoding apparatus for LDPC-CC or convolutional code that enables high-speed decoding operation.

According to one aspect of the decoding method of the present invention, in a parity check matrix, a protograph composed of a plurality of rows and a plurality of columns is regularly arranged, and the position where the protograph of the parity check matrix is arranged is excluded. The decoding method for decoding LDPC-CC (Low-Density Parity-Check Convolutional Code) defined by the parity check matrix is BP (Belief-Propagation), and uses the parity check matrix A calculation step for performing row processing calculation and column processing calculation, and a step of estimating a codeword using a calculation result in the calculation step, wherein in the calculation step, the protograph constituting the parity check matrix The columns of the parity check matrix are divided every number of columns × N (N: natural number), and the number of rows of the protograph × M (M: natural number) A plurality of groups which a plurality of blocks are allocated that are formed separated by the, by a plurality of computing system performs a parallel sequential operation at different times for each treatment period, and, in each processing period, Different groups are sequentially calculated, and in a predetermined processing period, at least one of the plurality of calculation systems is such that the sequential calculation is suspended.

According to one aspect of the decoding apparatus of the present invention, in the parity check matrix, a protograph composed of a plurality of rows and a plurality of columns is regularly arranged, and a position where the protograph of the parity check matrix is arranged is excluded. The matrix element is zero, and is a decoding device for decoding BP (Belief-Propagation) LDPC-CC (Low-Density Parity-Check Convolutional Code) defined by the parity check matrix, using the parity check matrix A plurality of row processing arithmetic units for performing row processing arithmetic, a plurality of column processing arithmetic units for performing column processing arithmetic using the parity check matrix, and arithmetic results in the row processing arithmetic unit and the column processing arithmetic unit. A plurality of row processing calculation units and a plurality of column processing calculation units, the number of columns of the protograph constituting the parity check matrix × N (N: Before every natural number) A plurality of groups in which columns of the parity check matrix are partitioned and a plurality of blocks formed by partitioning the parity check matrix for each number of rows of the protograph × M (M: natural number) are allocated The sequential calculation is performed in parallel by shifting the time for each processing period, and different groups are sequentially calculated in each processing period, and the plurality of row processing calculation units and the plurality of column processing calculation units Among them, at least one row processing calculation unit and at least one column processing calculation unit adopt a configuration in which sequential calculation is suspended in a predetermined processing period .

  ADVANTAGE OF THE INVENTION According to this invention, the decoding method, decoding apparatus, interleaving method, and transmission apparatus for LDPC-CC or a convolutional code which enable high-speed decoding operation are realizable.

FIG. 11 is a diagram illustrating an example of a parity check matrix of LDPC-CC in the first embodiment The figure which shows the calculation procedure with respect to the parity check matrix H in sum-product decoding (BP decoding). The figure which uses for description of the formation method of the protograph in Embodiment 1 The figure which uses for description of the BP decoding procedure in Embodiment 1 The figure which uses for description of the BP decoding procedure in Embodiment 1 Block diagram showing a configuration example of a transmitter that performs LDPC-CC encoding Block diagram showing an example of the configuration of a receiver that decodes LDPC-CC The block diagram which shows the structural example of the decoding part which performs sum-product decoding (BP decoding) FIG. 3 is a block diagram illustrating a configuration example of a decoding unit that performs BP decoding in the first embodiment FIG. 10 is a diagram for explaining grouping of row processing operations and column processing operations in the second embodiment. FIG. 9 is a block diagram illustrating a configuration example of a decoding unit that performs BP decoding in Embodiment 2. Timing chart for explaining the operation of the decoding unit in the second embodiment Timing chart for explaining the operation of the decoding unit of the second embodiment The figure which shows the frame structural example of the modulation signal transmitted Timing chart showing general signal processing timing on the receiving side The figure for demonstrating the block division | segmentation of the data symbol in Embodiment 3. Timing chart showing signal processing timing on the receiving side in the third embodiment The figure which shows an example of the parity check matrix of LDPC-CC in other embodiment The figure which uses for description of the formation method of the protograph in other embodiment The figure which shows the parity check matrix of LDPC-CC Diagram showing an example configuration of an LDPC-CC encoder

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
(1) Decoding algorithm (1-1) General decoding algorithm of LDPC-CC First, before describing the decoding method according to the present invention, a general decoding algorithm of LDPC-CC will be described.

  FIG. 1 shows an example of a parity check matrix H of LDPC-CC.

  The major flow of the sum-product decoding algorithm, which is a kind of BP (Belief-Propagation) decoding, on the receiving side is as follows.

なお、Ａ（ｍ）はパリティ検査行列Ｈのｍ行目において“１”である列インデックスの集合を意味し、Ｂ（ｎ）はパリティ検査行列Ｈのｎ行目において“１”である行インデックスの集合を意味する。 In the following description, a binary (M × N) matrix H = {H _mn } is used as a parity check matrix of an LDPC code to be decoded. Subsets A (m) and B (n) of the set [1, N] = {1, 2,..., N} are defined as follows:

A (m) means a set of column indexes that are “1” in the m-th row of the parity check matrix H, and B (n) is a row index that is “1” in the n-th row of the parity check matrix H. Means a set of

・ Step A ・ 1 (Initialization):
For all the sets (m, n) satisfying H _mn = 1, the log likelihood ratio β ⁽⁰⁾ _mn = λ _n is set. Further, the loop variable (number of iterations) l _sum = 1 is set, and the maximum number of loops is set to l _{sum, max} .

Step A.2 (line processing):
The log likelihood ratio α ⁽ⁱ⁾ _mn is updated using the following update formula for all pairs (m, n) satisfying H _mn = 1 in the order of m = 1, 2 _,. . Here, i represents the number of iterations. F is a Gallager function.

Step A.3 (column processing):
The log likelihood ratio β ⁽ⁱ⁾ _mn is updated using the following update formula for all pairs (m, n) satisfying H _mn = 1 in the order of n = 1, 2 _,. .

Step A · 4 (calculation of log likelihood ratio):
The log-likelihood ratio L ⁽ⁱ⁾ _n is obtained as follows for n∈ [1, N].

・ Step A ・ 5 (Counting the number of iterations):
If l _sum <l _{sum, max} , l _sum is incremented, and the process returns to step A · 2. When l _sum = l _{sum, max} , the codeword w is estimated as shown in the following equation, and the sum-product decoding is terminated.

  FIG. 2 shows a calculation procedure for the parity check matrix H in sum-product decoding. An arrow A1 in FIG. 2 indicates an arrow for imaging row processing, and an arrow A2 indicates an arrow for imaging column processing. Sum-product decoding is performed in the following order.

  First, row processing is performed at a position where “1” exists in the parity check matrix H as shown in FIG.

  Next, column processing is performed at a position where “1” exists in the parity check matrix H as shown in FIG. The above is the decoding operation of the first iteration.

  Next, after row processing is performed at a position where “1” exists in the parity check matrix H as shown in FIG. 2 <3>, “1” exists in the parity check matrix H as shown in FIG. 2 <4>. By performing column processing at the position, the decoding operation of the second iteration number is performed.

  Next, after row processing is performed at a position where “1” exists in the parity check matrix H as shown in FIG. 2 <5>, “1” exists in the parity check matrix H as shown in FIG. 2 <6>. By performing column processing at the position, the decoding operation of the second iteration number is performed.

  Thereafter, iterative decoding is repeated until a desired reception quality is obtained.

  Next, a procedure for generating an LDPC code will be briefly described.

The following relational expression is established between the parity check matrix H and the generator matrix G.

Also, the transmission sequence (encoded data) is n ₁ , n ₂ , n ₃ , n ₄ ,... As shown in FIG. 1, and the transmission sequence vector u = (n ₁ , n ₂ , n ₃ , n ₄ ,..., A transmission sequence vector u is an information sequence (data before encoding) vector i = (i ₁ , i ₂ ,...), A generator matrix G, and Is obtained as follows.

  On the encoding side, a transmission sequence is obtained by using the relational expression of Expression (10) and Expression (11). In the case of LDPC-CC, as shown in Non-Patent Document 1 and Non-Patent Document 2, encoding can be realized with a relatively simple configuration using a shift register and an exclusive OR circuit.

Incidentally, the log-likelihood ratio λ _n used in the sum-product decoding is equal to that of n ₁ , n ₂ , n ₃ , n ₄ ,. They will be arranged in order.

(1-2) Decoding method of the present embodiment As pointed out in Non-Patent Document 3 and Non-Patent Document 4, sum-product decoding is performed in order to obtain good reception quality. There is a drawback in that a large number of iterations must be set.

  Therefore, this embodiment proposes a decoding method suitable for LDPC-CC, which can obtain good reception quality with a small number of iterations. The decoding method of the present embodiment is a modification of sum-product decoding.

FIG. 3 shows an example of a parity check matrix H of LDPC-CC. When a transmission sequence (encoded data) is expressed as n _k , n _k−1 , n _k−2 , n _k−3 (k: even number), the following check expression is established from the parity check matrix H.

式（１２）及び式（１３）は３次の多項式である。 Here, the generator matrix G conforming to the parity check matrix H of FIG. 3 can be expressed by the following equation.

Expressions (12) and (13) are cubic polynomials.

  In the present embodiment, when the parity check matrix H check expression is expressed by a polynomial, the column of the parity check matrix H is divided every “order of the check expression + 1”. In the example of Expression (12), since the order of the check expression is third, the parity check matrix H is divided for every “3 + 1 = 4” columns. In general form, in this embodiment, the columns of the parity check matrix H are divided every “(order of check expression + 1) × N”. Here, N is a natural number.

  Also, the parity check matrix H in the LDPC-CC parity check matrix H + 1 and the jth row check equation are shifted by n bits. That is, the parity check matrix H parity check equation of LDPC-CC is established each time n bits are shifted in the column direction of the parity check matrix H. Therefore, in the present embodiment, the rows of the parity check matrix H are divided every “(order of the check expression + 1) × N / n”. In the example of FIG. 3, since the order of the check equation is 3, and n = 2, the row of the parity check matrix H is divided for each “(3 + 1) × 1/2 = 2 (where N = 1)” row.

  A dotted line in FIG. 3 illustrates a state in which the columns and rows of the parity check matrix are divided by the above-described method. As can be seen from FIG. 3, the protograph obtained by dividing the columns and rows of the parity check matrix H by the method described above (the portion surrounded by the dotted line in the figure) belongs to one of the three types of patterns. It becomes. That is, the parity check matrix H is configured by collecting a protograph of a pattern indicated by a reference symbol P1, a protograph of a pattern indicated by a reference symbol P2, or a protograph of a pattern indicated by a reference symbol P3.

  Next, a BP (Belief-Propagation) decoding procedure according to the present embodiment will be described with reference to FIG. In FIG. 4, <1> to <18> indicate the order of processing.

  Process <1>: Protograph composed of 4 columns from 1 column and 4 rows from 1 row (protograph formed by column region C1 and row region R1, and formed by column region C1 and row region R2) Line processing is performed at a position where “1” of the generated protograph exists.

  Process <2>: Protograph composed of 4 columns from 1 column and 4 rows from 1 row (protograph formed by column region C1 and row region R1, and formed by column region C1 and row region R2) Column processing is performed at a position where “1” of the generated protograph) exists.

  Process <3>: Protograph composed of 8 columns from 3 columns and 4 rows from 3 rows (protograph formed by column region C1 and row region R2, and formed by column region C2 and row region R2) Line processing is performed at a position where “1” of the generated protograph exists. In addition, row processing is performed at a position where “1” of the protograph (protograph formed by the column region C2 and the row region R3) including 5 to 8 columns and 5 to 6 rows exists.

  Process <4>: Protograph composed of 4 columns from 1 column and 4 rows from 1 row (protograph formed by column region C1 and row region R1, and formed by column region C1 and row region R2) Column processing is performed at a position where “1” of the generated protograph) exists. In addition, a protograph composed of 5 to 8 columns and 3 to 6 rows (a protograph formed by the column region C2 and the row region R2, and a column region C2 and the row region R3) Column processing is performed at a position where “1” of the protograph exists.

  Process <5>: Protograph composed of 5 to 12 columns and 5 to 6 rows (protograph formed by column region C2 and row region R3, and formed by column region C3 and row region R3) Line processing is performed at a position where “1” of the generated protograph exists. In addition, row processing is performed at a position where “1” of the protograph (protograph formed by the column region C3 and the row region R4) including 9 to 12 columns and 7 to 8 rows exists.

  Process <6>: Protograph composed of 5 columns to 8 columns and 3 rows to 6 rows (protograph formed by column region C2 and row region R2, and formed by column region C2 and row region R3) Column processing is performed at a position where “1” of the generated protograph) exists. In addition, a protograph composed of 9 to 12 columns and 5 to 8 rows (formed by a column region C3 and a row region R3, and formed by a column region C3 and a row region R4) Column processing is performed at a position where “1” of the protograph exists.

  Similarly, in the processing <7>, processing <8>,..., Row processing or column processing is performed. Here, the row processing is processing corresponding to Step A · 2 described above. If β has already been updated, the updated value is used. Similarly, the column processing is processing corresponding to Step A · 3 described above. If α has already been updated, the updated value is used.

  By using the algorithm as described above, it is possible to obtain an effect that the number of iterations for obtaining good reception quality can be reduced as compared with sum-product decoding. Even when compared with Shuffled BP decoding described in Non-Patent Document 3, it is possible to obtain an effect that the number of iterations for obtaining good reception quality can be reduced.

  Next, a BP decoding method different from the BP decoding method described in FIG. 4 will be described with reference to FIG. The BP decoding method described in FIG. 5 is also based on the assumption that the parity check matrix H (FIG. 3) partitioned as described above is used.

  Process <1>: Protograph composed of 4 columns from 1 column and 4 rows from 1 row (protograph formed by column region C1 and row region R1, and formed by column region C1 and row region R2) Line processing is performed at a position where “1” of the generated protograph exists.

  Process <2>: Protograph composed of 4 columns from 1 column and 4 rows from 1 row (protograph formed by column region C1 and row region R1, and formed by column region C1 and row region R2) Column processing is performed at a position where “1” of the generated protograph) exists.

  Process <3>: Row processing is performed at a position where “1” exists in a protograph (protograph formed by the column region C1 and the row region R1) composed of four columns from one column and two rows from one row. Apply. In addition, a protograph composed of 1 to 8 columns and 3 to 4 rows (a protograph formed by the column region C1 and the row region R2, and a column region C2 and the row region R2). Line processing is performed at a position where “1” of the protograph exists. In addition, row processing is performed at a position where “1” of the protograph (protograph formed by the column region C2 and the row region R3) including 5 to 8 columns and 5 to 6 rows exists.

  Process <4>: Protograph composed of 4 columns from 1 column and 4 rows from 1 row (protograph formed by column region C1 and row region R1, and formed by column region C1 and row region R2) Column processing is performed at a position where “1” of the generated protograph) exists. In addition, a protograph composed of 5 to 8 columns and 3 to 6 rows (a protograph formed by the column region C2 and the row region R2, and a column region C2 and the row region R3) Column processing is performed at a position where “1” of the protograph exists.

  Process <5>: Protograph composed of 8 columns from 3 columns and 4 rows from 3 rows (protograph formed by column region C1 and row region R2, and formed by column region C2 and row region R2) Line processing is performed at a position where “1” of the generated protograph exists. In addition, a protograph composed of 5 to 12 columns and 5 to 6 rows (a protograph formed by the column region C2 and the row region R3, and a column region C3 and the row region R3). Line processing is performed at a position where “1” of the protograph exists.

  Process <6>: Protograph composed of 4 columns from 1 column and 4 rows from 1 row (protograph formed by column region C1 and row region R1, and formed by column region C1 and row region R2) Column processing is performed at a position where “1” of the generated protograph) exists. In addition, a protograph composed of 5 to 8 columns and 3 to 6 rows (a protograph formed by the column region C2 and the row region R2, and a column region C2 and the row region R3) Column processing is performed at a position where “1” of the protograph exists. In addition, a protograph composed of 9 to 12 columns and 5 to 8 rows (a protograph formed by the column region C3 and the row region R3, and a column region C3 and the row region R4). Column processing is performed at a position where “1” of the protograph exists.

  Similarly, in the processing <7>, processing <8>,..., Row processing or column processing is performed. Here, the row processing is processing corresponding to Step A · 2 described above. If β has already been updated, the updated value is used. Similarly, the column processing is processing corresponding to Step A · 3 described above. If α has already been updated, the updated value is used.

  By using the algorithm as described above, it is possible to obtain the effect that the number of iterations for obtaining good reception quality can be reduced as compared with the sum-product decoding, similarly to the algorithm of FIG. Even when compared with Shuffled BP decoding described in Non-Patent Document 3, it is possible to obtain an effect that the number of iterations for obtaining good reception quality can be reduced.

(2) Configuration FIG. 6 shows a configuration example of the transmission apparatus according to the present embodiment. Encoding section 102 performs LDPC-CC encoding on transmission digital signal 101 and outputs encoded data 103 obtained thereby to interleaving section 104.

  Interleaving section 104 receives encoded data 103 and frame configuration signal 112 as input, interleaves encoded data 103 based on the frame configuration indicated by frame configuration signal 112, and obtains interleaved data 105 obtained thereby as modulation section 106. Output to.

  Modulation section 106 receives interleaved data 105, control information 114, and frame configuration signal 112, and modulates interleaved data 105 and control information 114 based on the modulation scheme and frame configuration indicated by frame configuration signal 112. At the same time, a transmission frame is formed, and the modulated signal 107 obtained thereby is output to the radio section 108. Radio section 108 performs predetermined radio processing such as frequency conversion and amplification on modulated signal 107 and supplies transmission signal 109 obtained thereby to antenna 110.

  The frame configuration signal generation unit 111 outputs a frame configuration signal 112 including frame configuration information. The control information generation unit 113 receives the frame configuration signal 112 as input, and includes control information including information for the communication partner to acquire frequency synchronization and time synchronization, information for notifying the communication partner of the modulation scheme of the modulation signal, and the like. 114 is generated and output.

  FIG. 7 shows a configuration example of the receiving apparatus of this embodiment.

  Radio section 203 performs predetermined radio processing such as amplification and frequency conversion on reception signal 202 received by reception antenna 201, and outputs modulated signal 204 obtained thereby to quadrature demodulation section 205. The orthogonal demodulation unit 205 performs orthogonal demodulation on the modulated signal 204 and outputs the baseband signal 206 obtained thereby to the channel fluctuation estimation unit 207, the control information detection unit 209, and the log likelihood ratio calculation unit 211.

  Channel fluctuation estimation section 207 detects, for example, a preamble from baseband signal 206, estimates channel fluctuation based on this preamble, and outputs channel fluctuation estimation signal 208 to log likelihood ratio calculation section 211. The control information detector 209 detects a preamble from the baseband signal 206, acquires time synchronization / frequency synchronization of the baseband signal 206 based on the preamble, and removes transmission data from the acquired baseband signal 206. Information is extracted and this control information is output as a control signal 210.

  The log-likelihood ratio calculation unit 211 receives the baseband signal 206, the channel fluctuation estimation signal 208, and the control signal 210 as input, for example, as shown in Non-Patent Document 5, Non-Patent Document 6, and Non-Patent Document 7. Then, a log likelihood ratio for each bit is obtained from the channel fluctuation estimation signal 208 and the baseband signal 206, and a log likelihood ratio signal 212 is output. In addition, a timing signal 217 indicating a data section (for example, a block size) is output.

  The deinterleaver 213 receives the log-likelihood ratio signal 212 as input, returns the sequence of the log-likelihood ratio signal 212 to the order before the rearrangement in the interleaving unit 104 (FIG. 6), and obtains the logarithm after deinterleaving obtained thereby. The likelihood ratio signal 214 is output to the decoding unit 215.

  Decoding section 215 receives log-likelihood ratio signal 214 after deinterleaving and timing signal 217 as input, and decodes log-likelihood ratio signal 214 after deinterleaving to obtain received data 216.

  Next, the configuration of the decoding unit 215 will be described in detail. First, before describing the configuration of the decoding unit according to the present embodiment, a general configuration for performing sum-product decoding will be described with reference to FIG. 8, and then with reference to FIG. 9, the configuration of the present embodiment will be described. A configuration example for realizing BP decoding will be described.

  FIG. 8 illustrates a configuration example of the decoding unit 215 in FIG. 7 when sum-product decoding is performed.

  Log likelihood ratio storage section 303 receives log likelihood ratio signal 301 (corresponding to log likelihood ratio signal 214 in FIG. 7) and timing signal 302 (corresponding to timing signal 217 in FIG. 7) as inputs. Based on this, the log likelihood ratio of the data section is stored. The stored log likelihood ratio is appropriately output as necessary.

  The row processing operation unit 305 receives the log-likelihood ratio signal 304 and the column-processed signal 312 as input, and performs the above-described Step A · 2 (row processing) operation at a position where “1” exists in the parity check matrix H. Do. In practice, since the decoding unit 215 performs iterative decoding, the row processing operation unit 305 performs row processing using the log likelihood ratio signal 304 at the time of the first decoding (corresponding to the above-described processing of Step A · 1). In the second decoding, row processing is performed using the signal 312 after column processing.

  The post-row processing signal 306 is stored in the post-row processing data storage unit 307. The post-row processing data storage unit 307 stores all post-row processing values (signals).

  The column processing operation unit 309 receives the signal 308 and the control signal 314 after row processing as input, confirms from the control signal 314 that it is not the last iterative operation, and at the position where “1” exists in the parity check matrix H, Perform Step A • 3 (column processing).

  The post-column processing signal 310 is stored in the post-column processing data storage unit 311. The post-column processing data storage unit 311 stores all post-column processing values (signals).

  The control unit 313 counts the number of iterations based on the timing signal 302 and outputs the number of iterations as a control signal 314.

  The log likelihood ratio calculation unit 315 receives the row-processed signal 308 and the control signal 314 as input, and determines that the parity check matrix H is “1” when it is determined based on the control signal 314 that the calculation is the last iteration. The log likelihood ratio signal 316 is obtained by performing Step A · 4 calculation (log likelihood ratio calculation) on the existing position using the signal 308 after row processing. Log likelihood ratio signal 316 is output to determination section 317.

  The determination unit 317 estimates a code word by executing, for example, Equation (9) using the log likelihood ratio signal 317, and outputs an estimated bit 318 (corresponding to the reception data 216 in FIG. 7).

  Next, a configuration example for realizing BP decoding according to the present embodiment will be described with reference to FIG.

  FIG. 9 shows a configuration example of the decoding unit 215 of FIG. 7 for realizing the BP decoding of the present embodiment. That is, the decoding unit 215 in FIG. 9 is a configuration example for realizing the BP decoding described with reference to FIGS. 4 and 5.

  Log likelihood ratio storage section 403 receives log likelihood ratio signal 401 (corresponding to log likelihood ratio signal 214 in FIG. 7) and timing signal 402 (corresponding to timing signal 217 in FIG. 7) as inputs. Based on this, the log likelihood ratio of the data section is stored. The stored log likelihood ratio is appropriately output as necessary.

  The row processing calculation unit 405 # 1 is a calculation unit for performing the row processing of the process <1> in FIG. 4 or 5 and receives the log likelihood ratio signal 404 and the signal 413 after column processing. The row processing calculation unit 405 # 1 performs the row processing of the process <1> of FIG. 4 or 5 using the log likelihood ratio signal 404 at the time of the first decoding. At the time of the second decoding, the row process of the process <1> in FIG. 4 or 5 is performed using the signal 413 after the column process.

  The post-row processing signal 406 # 1 obtained by the row processing operation unit 405 # 1 is stored in the post-row processing data storage unit 407. The post-row processing data storage unit 407 updates only the value updated by the post-row processing signal 406 # 1 in the stored post-row processing data.

  The column processing calculation unit 410 # 1 is a calculation unit for performing the column processing of the process <2> in FIG. 4 or FIG. The column processing calculation unit 410 # 1 obtains the signal 411 # 1 after the column processing by performing the column processing of the process <2> of FIG. 4 or FIG.

  The post-column processing signal 411 # 1 obtained by the column processing calculation unit 410 # 1 is stored in the post-column processing data storage unit 412. The post-column processing data storage unit 412 updates only the value updated by the post-column processing signal 411 # 1 in the stored post-column processing data.

  The row processing calculation unit 405 # 2 is a calculation unit for performing the row processing of the process <3> of FIG. 4 or FIG. 5, and receives the log likelihood ratio signal 404 and the signal 413 after column processing. The row processing operation unit 405 # 2 performs the row processing of the process <3> of FIG. 4 or 5 using the log likelihood ratio signal 404 at the time of the first decoding. At the time of the second decoding, the row process of the process <3> in FIG. 4 or 5 is performed using the signal 413 after the column process.

  The post-row processing signal 406 # 2 obtained by the row processing operation unit 405 # 2 is stored in the post-row processing data storage unit 407. The post-row processing data storage unit 407 updates only the value updated by the post-row processing signal 406 # 2 in the stored post-row processing data.

  The column processing calculation unit 410 # 2 is a calculation unit for performing the column processing of the process <4> of FIG. 4 or FIG. The column processing calculation unit 410 # 2 obtains a signal 411 # 2 after the column processing by performing the column processing of the process <4> of FIG. 4 or FIG.

  The post-column processing signal 411 # 2 obtained by the column processing calculation unit 410 # 2 is stored in the post-column processing data storage unit 412. The post-column processing data storage unit 412 updates only the value updated by the post-column processing signal 411 # 2 in the post-column processing data.

  The same calculation is performed in the row processing calculation unit after the row processing calculation unit 405 # 3 and the column processing calculation unit after the column processing calculation unit 410 # 3. Thereby, the processing after the procedure <5> of FIG. 4 or FIG. 5 is performed, and the data after the row processing and the data after the column processing are sequentially updated.

  The control unit 414 counts the number of iterations based on the timing signal 402 and outputs the number of iterations as a control signal 415.

  The log likelihood ratio calculation unit 416 receives the row-processed signal 409 and the control signal 415 as input, obtains a log likelihood ratio in the final iteration, and outputs it as a log likelihood ratio signal 417.

  The determination unit 418 estimates the codeword by executing Equation (9) using the log likelihood ratio signal 417, and outputs an estimated bit 419 (corresponding to the reception data 216 in FIG. 7).

  As described above, the BP decoding described with reference to FIGS. 4 and 5 can be performed by using the configuration shown in FIG.

  Incidentally, when the BP decoding described in FIG. 4 is realized, the row processing calculation units 405 # 1, 405 # 2,... And the column processing calculation units 410 # 1, 410 # 2,. The protograph is processed as shown in FIG. On the other hand, when the BP decoding described in FIG. 5 is realized, the row processing calculation units 405 # 1, 405 # 2,... And the column processing calculation units 410 # 1, 410 # 2,. The protograph is processed as shown in FIG. If the configuration as shown in FIG. 9 is used, the BP decoding described with reference to FIGS. 4 and 5 can be performed by the same basic operation other than that.

  As described above, according to the present embodiment, the order of the parity check matrix H check equation is D, and the relationship between the parity check matrix H j + 1-th row check equation and the j-th row check equation is When there is a relationship shifted by n bits, the columns of the parity check matrix H are divided every “(D + 1) × N (N: natural number)” and the parity check matrix H is divided every “(D + 1) × N / n”. The protograph formed by separating the rows is used as a processing unit of row processing calculation and column processing calculation.

  As a result, high-speed BP decoding can be performed while taking over the update value (that is, probability propagation) between the row processing operation and the column processing operation satisfactorily. In practice, the parity check matrix H is divided into a total of three types of protographs P1, P2 of two patterns including "1" and "0" and a protograph P3 consisting of only "0". The division into P2 and P3 is an important factor in realizing good probability propagation.

  In the present embodiment, the case where the present invention is applied to LDPC-CC has been described. However, the present invention is not limited to this, and may be applied to, for example, a convolutional code as shown in Non-Patent Document 8. it can. That is, the BP decoding method of the present embodiment can also be applied to the case where a parity check matrix H for a convolutional code as shown in Non-Patent Document 8 is created and BP decoding is performed. Also in this case, the same effect as the above-described embodiment can be obtained.

  The present invention can be widely applied to various BP decoding. That is, the BP decoding of the present invention includes min-sum decoding, offset BP decoding, normalized BP decoding, and the like that are approximate to BP decoding, as described in Non-Patent Documents 9 to 11, for example. The same applies to the embodiments described below.

(Embodiment 2)
In the first embodiment, the method and configuration have been described in which the computation scale is small and good reception quality can be obtained in the LDPC-CC BP decoding.

  In the present embodiment, there is provided a method and configuration capable of performing BP decoding at a higher speed than in the first embodiment by improving the first embodiment while having the basic principle and the basic configuration in the first embodiment. Present.

  In the first embodiment, the processing described with reference to FIGS. 4 and 5 and the configuration in FIG. 9 perform message exchange sequentially. On the other hand, in the present embodiment, as shown in FIG. 10, the processing <1>, <2>,..., Which is the row processing and the column processing in FIGS. By performing processing in units of groups, processing delay due to sequential processing can be reduced and high-speed BP decoding can be performed.

  In FIG. 10, processes <1>, <2>,... Are the row processing and column processing operations of the processes <1>, <2>,. It corresponds to. In the example of FIG. 10, one process group G1 is configured by processes <1>, <2>, <3>, <4>, <5>, <6>, and processes <7>, <8>, <6 9>, <10>, <11>, <12> constitute one processing group G2, and one processing group G2, <14>, <15>, <16>, <17>, <18>. One processing group G3 was configured, and one processing group G4 was configured by the processing <19>, <20>, <21>, <22>, <23>, <24>. That is, all the processes <1>, <2>,... Are divided into six processes as one group.

  FIG. 11 shows a configuration example of the decoding unit of the present embodiment. The decoding unit 500 in FIG. 11 is used as, for example, the decoding unit 215 in FIG.

  Log-likelihood ratio storage unit # 1 (503 # 1) receives log-likelihood ratio signal 501 (corresponding to log-likelihood ratio signal 214 in FIG. 7) as input, and log-likelihood belonging to the processing of group G1 in FIG. The ratio is stored, and the stored log likelihood ratio is output as a signal 504 # 1.

  Similarly, log-likelihood ratio storage unit #k (503 # k) receives log-likelihood ratio signal 501 (corresponding to log-likelihood ratio signal 212 in FIG. 7) as an input, and performs group Gk (1 <k) in FIG. The log likelihood ratio belonging to the process <Z) is stored, and the stored log likelihood ratio is output as a signal 504 # k. Also, the log likelihood ratio storage unit #Z (503 # Z) receives the log likelihood ratio signal 501 (corresponding to the log likelihood ratio signal 212 in FIG. 2) as an input, and the logarithms belonging to the processing of the group GZ in FIG. The likelihood ratio is stored, and the stored log likelihood ratio is output as a signal 504 # Z.

  The connection switching unit 505 receives the log-likelihood ratio signals 504 # 1 to 504 # Z and the control signal 527 belonging to the processing of each group G1 to GZ, switches the input / output connection based on the control signal 527, and Log likelihood ratio signals 506 # 1 to 506 # Z are output to the row / column processing calculation units # 1 to #Z (507 # 1 to 507 # Z). The operation of the connection switching unit 505 will be described in detail later.

  The row / column processing calculation unit # 1 (507 # 1) includes the log likelihood ratio signal 506 # 1 from the connection switching unit 505, the data # 1 (515 # 1) after the row processing from the connection switching unit 514, and the connection. By using the column-processed data # 1 (521 # 1) from the switching unit 520 as an input and performing the same row processing / column processing calculation as described with reference to FIG. Data 508 # 1 after processing and data 509 # 1 after column processing are obtained.

  The row / column processing calculation unit #k (507 # k) includes a log-likelihood ratio signal 506 # k from the connection switching unit 505, data #k (515 # k) after the row processing from the connection switching unit 514, and the connection. By using the column processed data #k (521 # k) from the switching unit 520 as an input and performing the same row processing / column processing calculation as described with reference to FIG. 9 of the first embodiment, Data 508 # k after processing and data 509 # k after column processing are obtained.

  The row / column processing calculation unit #Z (507 # Z) includes the log likelihood ratio signal 506 # Z from the connection switching unit 505, the data #Z (515 # Z) after the row processing from the connection switching unit 514, and the connection. By inputting the post-column processing data #Z (521 # Z) from the switching unit 520 and performing the same row processing / column processing calculation as described with reference to FIG. 9 of the first embodiment, Data 508 # Z after processing and data 509 # Z after column processing are obtained.

  The processing contents of the row / column processing operation units # 1 to #Z (507 # 1 to 507 # Z) will be described in detail later.

  The connection switching unit 510 receives the row-processed data 508 # 1 to 508 # Z and the control signal 527, switches the input / output connection based on the control signal 527, and performs the subsequent row-processed data storage unit # 1. The data 511 # 1 to 511 # Z after row processing are output to .about. # Z (512 # 1 to 512 # Z). The operation of the connection switching unit 510 will be described in detail later.

  The post-row processing data storage unit # 1 (512 # 1) updates only the value updated in the post-row processing data 511 # 1 among the stored post-row processing data. The post-row processing data storage unit # 1 (512 # 1) outputs row data 513 # 1 for performing column processing.

Similarly, the post-row processing data storage unit #Z (512 # Z) updates only the value updated with the post-row processing data 511 # Z among the stored post-row processing data. Further, the post-row processing data storage unit #Z (512 # Z) outputs row data 513 # Z for performing column processing.

  The connection switching unit 514 receives the row data 513 # 1 to 513 # Z and the control signal 527 as inputs, switches the input / output connection based on the control signal 527, and performs row / column processing calculation units # 1 to #Z (507). The row data 515 # 1 to 515 # Z after connection switching is output to # 1 to 507 # Z). The operation of the connection switching unit 514 will be described in detail later.

  The connection switching unit 516 receives the post-column processing data 509 # 1 to 509 # Z and the control signal 527, switches the input / output connection based on the control signal 527, and performs the post-column processing data storage unit # 1. The data 517 # 1 to 517 # Z after column processing are output to .about. # Z (518 # 1 to 518 # Z). The operation of the connection switching unit 516 will be described in detail later.

  The post-column processing data storage unit # 1 (518 # 1) updates only the value updated in the post-column processing data 517 # 1 among the stored post-column processing data. Further, the post-column processing data storage unit # 1 (518 # 1) outputs column data 519 # 1 for performing row processing. Similarly, the post-column processing data storage unit #Z (518 # Z) updates only the value updated with the post-column processing data 517 # Z among the stored post-column processing data. The post-column processing data storage unit #Z (518 # Z) outputs column data 519 # Z for performing row processing.

  The connection switching unit 520 receives the column data 519 # 1 to 519 # Z and the control signal 527, switches the input / output connection based on the control signal 527, and performs the row / column processing calculation units # 1 to #Z (507). Column data 521 # 1 to 521 # Z after connection switching is output to # 1 to 507 # Z). The operation of the connection switching unit 520 will be described in detail later.

  The control unit 526 receives the timing signal 502, generates a control signal 527 based on the timing signal 502, and outputs it.

  The log likelihood ratio calculation unit 522 receives the row data 513 # 1 to the row data 513 # Z and the control signal 527, and determines that the log likelihood ratio is the final iteration based on the control signal 527. Is calculated, and a log likelihood ratio signal 523 is output.

  The determination unit 524 receives the log-likelihood ratio signal 523, estimates the codeword by executing, for example, the equation (9) using the log-likelihood ratio signal 523, and outputs the estimated bit 525 obtained thereby. .

  The basic operation of the decoding unit 500 has been described above. Next, the relationship between the configuration of the decoding unit 500 in FIG. 11 and the row / column processing schedule in FIG. 10 will be described in detail with reference to FIGS. Here, the number of groups will be described as Z.

  The post-row processing data storage unit # 1 (512 # 1) stores the post-row processing data of the group G1 (FIG. 10). Similarly, the post-row processing data storage unit #Z (512 # Z) stores the post-row processing data of the group GZ.

  The post-column processing data storage unit # 1 (518 # 1) stores the post-column processing data of the group G1. Similarly, post-column processing data storage unit #Z (518 # Z) stores post-column processing data of group GZ.

  12 and 13 show processing timings on the time axis of the row / column processing calculation units # 1 to #Z (507 # 1 to 507 # Z). 12 and 13, the “L (Low)” section indicates that no row / column processing operation is performed, and the “H (High)” section performs a row / column processing operation. Indicates that

  As shown in FIG. 12, the row / column processing calculation unit # 1 performs the row / column processing of the group G1 (FIG. 10) in the “H” section 601 # 1. In this “H” section 601 # 1, the other row / column processing operation units # 2 to #Z have not yet started the iterative decoding operation.

  The row / column processing calculation unit # 1 performs the row / column processing of the group G2 in the “H” section 602 # 1. In the “H” section 601 # 2, which is the same section as the “H” section 602 # 1, the row / column processing calculation unit # 2 performs the row / column processing of the group G1. The processing operation units # 3 to #Z have not yet started the iterative decoding operation.

  The row / column processing calculation unit # 1 performs the row / column processing of the group G3 in the “H” section 603 # 1. In the “H” section 602 # 2, which is the same section as the “H” section 603 # 1, the row / column processing calculation unit # 2 performs the row / column processing of the group G2. In the “H” section 601 # 3, which is the same section as the “H” section 603 # 1, the row / column processing calculation unit # 3 performs the row / column processing of the group G1. In this section, the other row / column processing operation units # 4 to #Z have not yet started the iterative decoding operation.

  As described above, the row / column processing calculation units # 1 to #Z sequentially start iterative decoding. In addition, groups subjected to row / column processing by the row / column processing calculation units # 1 to #Z are moved one by one between the row / column processing calculation units # 1 to #Z as time passes. In order to realize this operation, the connection switching units 505, 510, 514, 516, and 520 in FIG. 11 switch the connection between input and output.

  In the processing timing on the time axis in FIG. 13, the section (N−1) # 1 indicates that the row / column processing calculation unit # 1 performs the (N−1) th decoding. Similarly, the section (N−1) # 2 indicates that the row / column processing calculation unit # 2 performs the (N−1) th decoding. Thus, (N−1) #k indicates that the row / column processing operation unit #k is performing the (N−1) th decoding.

  The section N # 1 indicates that the row / column processing calculation unit # 1 is performing the Nth decoding. Similarly, a section N # 2 indicates that the row / column processing calculation unit # 2 is performing the Nth decoding. Thus, the section N # k indicates that the row / column processing calculation unit #k is performing the Nth decoding.

  Within each iterative decoding section, as described with reference to FIG. 12, the groups subjected to the row / column processing by the row / column processing operation units # 1 to #Z are subjected to row / column processing over time. It is moved one by one between the calculation units # 1 to #Z (see the right half of FIG. 13).

  By performing such processing, the decoding unit 500 of the present embodiment, when all the row / column processing operation units # 1 to #Z complete the Nth decoding process, the decoding unit 215 of the first embodiment. This is equivalent to performing Z times of N times of decoding processing (FIG. 9), that is, performing Z × N times of decoding processing. Therefore, if the configuration of decoding section 500 of this embodiment is adopted, the number of iterative decoding necessary to obtain good reception quality can be reduced, so that it is compared with decoding section 215 of Embodiment 1. Thus, the processing delay can be shortened, and high-speed BP decoding can be performed. That is, in the decoding unit 500, since the decoding process of Z times that of the decoding unit 215 is performed by parallel processing in one iterative decoding, the number of iterative decoding required to obtain reception quality equivalent to that of the decoding unit 215 is approximately 1 Therefore, the reception quality equivalent to that of the decoding unit 215 can be obtained in a short time.

  As described above, according to the present embodiment, row processing and column processing are divided into a plurality of groups G1 to GZ, and row processing and column processing of each group G1 to GZ are performed for each row / column processing operation. Are sequentially executed by the units # 1 to #Z (507 # 1 to 507 # Z), and the time is shifted by the plurality of row / column processing calculation units # 1 to #Z (507 # 1 to 507 # Z). By executing in parallel, BP decoding can be performed at a higher speed than in the first embodiment.

  Note that the grouping method for row processing and column processing is not limited to that shown in FIG.

  Further, although cases have been described with the present embodiment where the present invention is applied to LDPC-CC, the present invention is not limited thereto, and may be applied to, for example, a convolutional code as shown in Non-Patent Document 8. it can. That is, the BP decoding method of the present embodiment can also be applied to the case where a parity check matrix H for a convolutional code as shown in Non-Patent Document 8 is created and BP decoding is performed. Also in this case, the same effect as the embodiment can be obtained.

(Embodiment 3)
In the present embodiment, an interleaving method on the transmission side suitable for performing the decoding described in Embodiment 2 on the reception side is presented. In the present embodiment, as an example, a configuration in the case where the transmission apparatus performs interleaving after encoding as illustrated in FIG. 6 will be described.

  FIG. 14 shows an example of a frame configuration (one frame) on the time axis of the modulation signal transmitted by the transmission apparatus 100 of FIG. In FIG. 14, the modulated signal is composed of a preamble 801 and a data symbol 802. Preamble 801 includes pilot symbols for the receiver to estimate channel fluctuations, symbols for estimating frequency offset, symbols for transmitting control information other than data, and the like.

  Data symbols (symbols for transmitting data) 802 have been subjected to LDPC-CC encoding based on the parity check matrix H of FIG. In the present embodiment, it is assumed that one frame of data symbol 802 includes 3600 symbols and is BPSK modulated.

  FIG. 15 shows signal processing timing on the receiving side when the data symbol 802 in FIG. 14 is randomly interleaved in units of one frame (3600 symbols) in the interleaving unit 104 in FIG. 6, for example.

  FIG. 15A shows the reception status of the data symbol 802 in the receiving apparatus. In the “H” period, the receiving apparatus receives data symbols 802, and in the “L” period, the receiving apparatus does not receive data symbols 802.

  FIG. 15B shows the deinterleaving processing status in the receiving apparatus. In the “H” section, the receiving apparatus is in a state of performing deinterleaving, and in the “L” section, the receiving apparatus is in a state of not performing deinterleaving.

  As can be seen from FIGS. 15 (a) and 15 (b), when random interleaving is performed on the data symbol 802 of FIG. 14 in units of one frame (3600 symbols), the receiving apparatus has received all 3600 symbols. Unless you do this, you cannot deinterleave.

  FIG. 15C shows the processing status of the decoding unit (see FIGS. 9 and 11) in the receiving apparatus. In the “H” period, the decoding unit is performing a decoding operation, and in the “L” period, the decoding unit is not performing a decoding operation.

  As described above, when random interleaving is performed in units of one frame (3600 symbols), the deinterleaving operation can be started only after reception of all the data symbols of one frame is completed. Further, the decoding operation (for example, FIGS. 12 and 13) can be started only after the deinterleaving is completed (FIG. 15B).

  This causes a processing delay. Therefore, in the present embodiment, the interleaving method that takes advantage of the characteristics described in the second embodiment, such as dividing the row / column processing into groups, and processing the divided group row / column processing sequentially and in parallel, is performed. suggest.

  In the LDPC-CC encoding process described in the first embodiment, the order of the parity check matrix H is D, and the parity check matrix H has the j + 1-th row check equation, the j-th row check equation, , The column of the parity check matrix H is divided every “(D + 1) × N (N: natural number)” and the parity is divided every “(D + 1) × N / n”. A protograph formed by dividing the rows of the check matrix H is used as a processing unit for row processing operations and column processing operations.

  Therefore, if the interleaving block size is set to “(D + 1) × N (N: natural number) × M (M: natural number)” bits and interleaving is performed in units of this block size, the interleaving block size is as shown in FIG. Thus, since it is an integral multiple of the block size divided into groups, all received bits can be deinterleaved without causing a waiting time as described with reference to FIG. As a result, the processing delay in the receiving apparatus can be reduced.

  For example, when the parity check matrix is divided as shown in FIG. 10, (order + 1) = 4 and N = 1. In the present embodiment, in consideration of this, as shown in FIG. 16, a data symbol 802 of 3600 symbols is divided into 6 to constitute one block with 600 symbols. Accordingly, in FIG. 16, the data symbol 802 includes block # 1 (901 # 1), block # 2 (901 # 2), block # 3 (901 # 3), block # 4 (901 # 4), block # 5 (901 # 5) and block # 6 (901 # 6).

In this embodiment, interleaving is performed only within the block. For example, assuming that BPSK modulation is used, the interleaving unit 104 (FIG. 6) performs interleaving with 600 bits constituting block # 1 (901 # 1). Similarly, interleaving is performed with 600 bits constituting block # 2 (901 # 2). That is, interleaving is performed with 600 bits constituting block #k (901 # k) (k = 1, 2,..., 6).
By doing so, the condition “the block size is“ (order + 1) × N (N: natural number) × M (N: natural number) ”as the block size for interleaving” as described above ”is satisfied. Interleave processing can be realized. This is because (order + 1) × 1 = (3 + 1) × 1 = 4 and 600/4 = 150 (natural number).

  In this way, the receiving apparatus can perform deinterleaving immediately after reception of one block is completed, and in the case of the decoder of FIG. 11, the row / column processing operation is performed immediately after deinterleaving is completed. Can start. As a result, as shown in FIG. 15, it is possible to shorten the operation delay compared to the method of waiting for deinterleaving until reception of one frame is completed and waiting for decoding until deinterleaving for one frame is completed. it can.

  Next, the processing timing of the decoding unit 500 of FIG. 11 when the data symbol section is divided into blocks as shown in FIG. 16 and interleaving is performed only within the blocks will be described using FIG.

  FIG. 17A shows the reception status of the data symbol 802 in the receiving apparatus. In the “H” period, the receiving apparatus receives data symbols 802, and in the “L” period, the receiving apparatus does not receive data symbols 802.

  FIG. 17B shows that data in block # 1 (901 # 1) is deinterleaved after reception of block # 1 (901 # 1) in FIG. 16 is completed. That is, in the “H” section, the data of block # 1 (901 # 1) is deinterleaved.

  FIG. 17C shows the operation timing of the row / column processing calculation unit # 1 (507 # 1) of FIG. In the “H” section, the row / column processing calculation unit # 1 (507 # 1) performs row / column processing calculation. Incidentally, immediately after the start of the operation, the process <1> shown in FIG. 4 or 5 is performed. FIG. 17D shows the operation timing of the row / column processing calculation unit # 2 (507 # 2) of FIG.

  As can be seen from FIGS. 17A, 17B, and 17C, immediately after the reception of block # 1 (901 # 1) is completed, the deinterleaver 213 (FIG. 7) performs block # 1 (901 #). All the data of 1) can be deinterleaved, and immediately after the completion of the deinterleaving process, the row / column processing calculation unit # 1 (507 # 1) can perform the row / column processing calculation.

  Then, as shown in FIG. 17 (d), the row / column processing operation unit # 2 (507 # 2) has started after the row / column processing operation unit # 1 (507 # 1) starts the row / column processing operation. A certain time interval (in FIG. 12, this corresponds to the time interval from when the row / column processing operation unit # 1 starts processing of the group G1 to when the row / column processing operation unit # 2 starts processing of the group G1. ) To start the row / column processing operation. The row / column processing operation units # 2 to #Z also sequentially start row / column operations at regular time intervals.

  FIG. 17E shows that the data of block # 2 (901 # 2) is deinterleaved after the reception of block # 2 (901 # 2) of FIG. 16 is completed. That is, in the “H” section, the data of block # 2 (901 # 2) is deinterleaved.

  As can be seen from FIGS. 17A and 17E, immediately after the reception of the block # 2 (901 # 2) is completed, all the data of the block # 2 (901 # 2) is transferred by the deinterleaver 213 (FIG. 7). Can be de-interleaved.

  Of course, before the deinterleaving of the data of block # 2 (901 # 2) is completed, the row / column processing operation unit #k (k = 1, 2,..., Z) of FIG. Data that can be subjected to row / column processing is limited to data of block # 1 (901 # 1).

  As described above, according to the present embodiment, in a transmission apparatus that performs LDPC-CC encoding, a data symbol section in one frame is divided into two or more blocks, and one block of data is converted to “( The order +1) × N (N: natural number) × M (M: natural number) ”bits are configured to be interleaved in the block, so that the delay in calculation by the decoding process on the receiving side can be shortened. . This is particularly effective when performing BP decoding as described in the first and second embodiments on the receiving side.

  In this embodiment, LDPC-CC has been described as an example. For example, a parity check matrix H is created for the convolutional code shown in Non-Patent Document 8 and BP decoding is performed in the same manner. can do.

  In the present embodiment, the case where the transmission method and transmission apparatus of the present invention are applied to a system that performs LDPC-CC coding and LDPC-CC BP decoding has been described. However, the transmission method and transmission of the present invention are described. The apparatus is not limited to this, and can be applied to a convolutional code as shown in Non-Patent Document 8, for example. That is, the transmission method and transmission apparatus of the present embodiment can also be applied to the case where a parity check matrix H for a convolutional code as shown in Non-Patent Document 8 is created and BP decoding is performed. Also in this case, the same effect as the above-described embodiment can be obtained.

  In this embodiment, the case of performing BPSK has been described as an example. However, the present invention is not limited to this, and the present invention can be similarly performed even when other modulation schemes such as QPSK, 16QAM, and 64QAM are used. .

(Other embodiments)
Here, an implementation method for LDPC-CC using a parity check matrix different from the LDPC-CC parity check matrix described above will be described. Here, in particular, as shown in Non-Patent Document 2, an implementation method for LDPC-CC using a parity check matrix in which “1” exists at a protograph and a specific position will be described in detail.

  FIG. 18 shows an example of a parity check matrix H of LDPC-CC. A matrix Hnp surrounded by a dotted line in FIG. 18 is called a protograph. The parity check matrix H is configured based on the protograph Hnp. That is, the protograph Hnp is a transposed parity check matrix for configuring the LDPC-CC. In addition, in the parity check matrix H, “1” is arranged according to a specific rule separately from the protograph Hnp (“1” surrounded by circles in FIG. 18). As shown in FIG. 18, a transmission sequence (encoded data) is represented as nk (k: natural number).

  In the present embodiment, the parity check matrix H is divided as shown in FIG. The division rules are as follows.

  1) Since the number of columns of the protograph Hnp is 4, the columns of the parity check matrix H are divided into four columns. In FIG. 19, as an example, it is divided for each “number of protograph columns”, but may be divided for each “(number of protograph columns) × N (N: natural number)”.

  2) Since the number of rows of the protograph Hnp is 3, the rows of the parity check matrix H are divided every third. In FIG. 19, as an example, it is divided for each “number of protograph lines”, but may be divided for each “(number of protograph lines) × M (M: natural number)”.

  The parity check matrix H is partitioned according to the above rules 1) and 2). Then, if BP decoding is performed in accordance with the processing procedure shown in FIG. 4 or FIG. 5 by using the protograph formed in this way as a processing unit for row processing operation and column processing operation, Embodiment 1 will be described. In addition, the same effect as described in the second embodiment can be obtained. That is, as shown in FIG. 18, the parity check matrix H is also set as in rules 1) and 7) for an LDPC-CC using a parity check matrix in which “1” exists at a protograph and a specific position. By dividing, the BP decoding described in the first embodiment and the second embodiment can be performed, and the same effect can be obtained.

  Further, when LDPC-CC of a parity check matrix having “1” is used at the protograph Hnp and a specific position as shown in FIG. 18, the calculation by the decoding process on the receiving side is performed as in the third embodiment. In order to shorten the delay, the following interleaving process may be performed on the transmission side. That is, a data symbol section in one frame is divided into two or more blocks, and one block of data is composed of the number of columns of the protograph Hnp constituting the parity check matrix H × N (N: natural number) bits, Interleaving may be performed within the block.

  The present invention is not limited to the embodiment described above, and can be implemented with various modifications. For example, although cases have been described with the above embodiment where the present invention is mainly implemented by hardware, the present invention can also be implemented by software. For example, a program for executing the method of the present invention may be stored in advance in a ROM (Read Only Memory), and the program may be operated by a CPU (Central Processor Unit).

  In the above embodiment, the case where the present invention is applied mainly to a transmission device and a reception device (FIGS. 6 and 7) that perform single carrier transmission has been described as an example, but the present invention is not limited thereto, The present invention can also be applied to a multi-carrier transmission system such as OFDM or a transmission system using a spread spectrum communication system.

  The present invention can be widely applied to a radio system using LDPC-CC or a convolutional code.

DESCRIPTION OF SYMBOLS 100 Transmission apparatus 102 Encoding part 104 Interleaving part 200 Receiving apparatus 213 Deinterleaver 215,500 Decoding part 405 # 1,405 # 2,405 # 3 Row process calculating part 407,512 # 1-512 # Z Data storage after row process Unit 410 # 1, 410 # 2, 410 # 3 column processing operation unit 412, 518 # 1 to 518 # Z post-column processing data storage unit 416, 522 log likelihood ratio operation unit 418, 524 determination unit 505, 510, 514 , 516, 520 Connection switching unit 507 # 1-507 # Z Row / column processing operation unit

Claims (6)

In the parity check matrix, a protograph composed of a plurality of rows and a plurality of columns is regularly arranged, and the elements of the matrix excluding the position where the protograph of the parity check matrix is arranged are zero, and the parity check A decoding method for BP (Belief-Propagation) decoding of LDPC-CC (Low-Density Parity-Check Convolutional Code) defined by a matrix,
An operation step of performing a row processing operation and a column processing operation using the parity check matrix;
Estimating a codeword using a calculation result in the calculation step;
Including
In the calculation step,
The columns of the parity check matrix are divided every number of columns of the protograph constituting the parity check matrix × N (N: natural number) and the number of rows of the protograph × M (M: natural number) A plurality of groups in which a plurality of blocks formed by dividing rows of a parity check matrix are allocated, and a plurality of arithmetic systems perform sequential operations in parallel at different processing periods, and In each processing period, different groups are calculated sequentially,
In a predetermined processing period, at least one arithmetic system of the plurality of arithmetic systems is paused for sequential calculation.
Decryption method. The calculation step includes:
After the completion of the sequential calculation in each processing period, the next sequential calculation is started after the pause period has elapsed.
The decoding method according to claim 1. The calculation step includes:
At the first processing time,
A first calculation system among the plurality of calculation systems sequentially calculates the first group,
The second arithmetic system among the plurality of arithmetic systems pauses the sequential arithmetic operation,
At the second processing time,
The first calculation system sequentially calculates a second group of the plurality of groups,
The second calculation system sequentially calculates the first group.
The decoding method according to claim 1. In the parity check matrix, a protograph composed of a plurality of rows and a plurality of columns is regularly arranged, and the elements of the matrix excluding the position where the protograph of the parity check matrix is arranged are zero, and the parity check A decoding device for decoding BP (Belief-Propagation) LDPC-CC (Low-Density Parity-Check Convolutional Code) defined by a matrix,
A plurality of row processing operation units for performing row processing operations using the parity check matrix;
A plurality of column processing calculation units that perform column processing calculation using the parity check matrix;
A determination unit that estimates codewords using calculation results in the row processing calculation unit and the column processing calculation unit;
Have
The plurality of row processing calculation units and the plurality of column processing calculation units are:
The columns of the parity check matrix are divided every number of columns of the protograph constituting the parity check matrix × N (N: natural number) and the number of rows of the protograph × M (M: natural number) A plurality of groups in which a plurality of blocks formed by dividing rows of a parity check matrix are allocated to perform sequential operations in parallel at different processing periods, and are different in each processing period. Sequentially calculate groups,
Among the plurality of row processing calculation units and the plurality of column processing calculation units, at least one row processing calculation unit and at least one column processing calculation unit are suspended in sequential calculation during a predetermined processing period.
Decoding device. The plurality of row processing calculation units and the plurality of column processing calculation units are:
After the completion of the sequential calculation in each processing period, the next sequential calculation is started after the pause period has elapsed.
The decoding device according to claim 4. The plurality of row processing calculation units and the plurality of column processing calculation units are:
A first row processing calculation unit, a first column processing calculation unit, a second row processing calculation unit, a second column processing calculation unit,
Including
In the first processing period,
The first row processing calculation unit and the first column processing calculation unit sequentially calculate the first group,
The second row processing calculation unit and the second column processing calculation unit pause sequential calculation,
In the second processing period,
The first row processing calculation unit and the first column processing calculation unit sequentially calculate a second group of the plurality of groups,
The second row processing calculation unit and the second column processing calculation unit sequentially calculate the first group.
The decoding device according to claim 4.

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