KR20180122911A - Apparatus and method for channel encoding/decoding in communication or broadcasting system - Google Patents

Abstract

The present disclosure relates to a 5G or a pre-5G communication system for supporting a higher data transfer rate than a 4G communication system such as LTE. The present invention provides a method and a device for low density parity check (LDPC) encoding/decoding capable of supporting various input lengths and coding rates. The method for channel encoding in a communication or a broadcasting system comprises the following processes of: checking an input bit size; determining a size (Z) of a block; determining an LDPC progression to perform LDPC encoding; and performing the LDPC encoding based on the LDPC progression and the block size.

Description

TECHNICAL FIELD [0001] The present invention relates to a method and apparatus for channel encoding / decoding in a communication or broadcasting system,

The present invention relates to a channel coding / decoding method and apparatus in a communication or broadcasting system.

Efforts are underway to develop an improved 5G or pre-5G communication system to meet the growing demand for wireless data traffic after commercialization of the 4G communication system. For this reason, a 5G communication system or a pre-5G communication system is called a system after a 4G network (Beyond 4G network) communication system or after a LTE system (Post LTE).

To achieve a high data rate, 5G communication systems are being considered for implementation in very high frequency (mmWave) bands (e.g., 60 gigahertz (60GHz) bands). In order to mitigate the path loss of the radio wave in the very high frequency band and to increase the propagation distance of the radio wave, in the 5G communication system, beamforming, massive MIMO, full-dimension MIMO (FD-MIMO ), Array antennas, analog beam-forming, and large scale antenna technologies are being discussed.

In order to improve the network of the system, the 5G communication system has developed an advanced small cell, an advanced small cell, a cloud radio access network (cloud RAN), an ultra-dense network, (D2D), a wireless backhaul, a moving network, cooperative communication, Coordinated Multi-Points (CoMP), and interference cancellation Have been developed.

In addition, in the 5G system, the Advanced Coding Modulation (ACM) scheme, Hybrid FSK and QAM Modulation (FQAM) and Sliding Window Superposition Coding (SWSC), the advanced connection technology, Filter Bank Multi Carrier (FBMC) (non-orthogonal multiple access), and SCMA (sparse code multiple access).

In a communication or broadcasting system, the link performance may be significantly degraded by various noise, fading phenomena and inter-symbol interference (ISI) of the channel. Therefore, in order to implement high-speed digital communication or broadcasting systems requiring high data throughput and reliability, such as next generation mobile communication, digital broadcasting, and portable Internet, it is required to develop a technique for overcoming noise, fading and intersymbol interference. As a part of research for overcoming noise and the like, recently, error-correcting code has been actively studied as a method for improving the reliability of communication by efficiently restoring information distortion.

The present invention provides an LDPC encoding / decoding method and apparatus capable of supporting various input lengths and coding rates.

The present invention provides a LDPC code design method and a coding / decoding method and apparatus having a short information word length of about 100 bits and suitable for a code rate.

The present invention proposes a method of simultaneously designing a lifting method and a trapping set characteristic in designing an LDPC code capable of supporting various lengths and coding rates.

The present invention proposes a method of designing a dedicated LDPC code suitable for a case where the number of information bits is small and the code rate is fixed.

The present invention can support LDPC codes for variable length and variable rate.

1 is a schematic diagram of a systematic LDPC codeword.
2 is a diagram illustrating a graph representation method of an LDPC code.
3A and 3B are diagrams for explaining the cycle characteristics of a QC-LDPC code.
4 is a block diagram of a transmission apparatus according to an embodiment of the present invention.
5 is a block diagram of a receiving apparatus according to an embodiment of the present invention.
6A and 6B are message structure diagrams illustrating message passing operations at arbitrary check nodes and variable nodes for LDPC decoding.
FIG. 7 is a block diagram illustrating a detailed configuration of an LDPC encoder according to an embodiment of the present invention. Referring to FIG.
8 is a block diagram illustrating a configuration of a decoding apparatus according to an embodiment of the present invention.
9 is a block diagram of an LDPC decoding unit according to another embodiment of the present invention.
10 is a block diagram of a transmission block according to another embodiment of the present invention.
11, 11A and 11B are views illustrating an example of an LDPC code exponent matrix according to an embodiment of the present invention.
12, 12A and 12B are diagrams illustrating another example of an LDPC code exponent matrix according to an embodiment of the present invention.
13, 13A and 13B are diagrams illustrating another example of an LDPC code exponent matrix according to an embodiment of the present invention.
14, 14A and 14B are diagrams illustrating another example of an LDPC code exponent matrix according to an embodiment of the present invention.
15, 15A and 15B are diagrams illustrating another example of an LDPC code exponent matrix according to an embodiment of the present invention.
16, 16A and 16B are diagrams illustrating another example of a basic matrix of an LDPC code according to an embodiment of the present invention.
17, 17A and 17B are diagrams illustrating another example of an LDPC code exponent matrix according to an embodiment of the present invention.
18, 18A and 18B are diagrams illustrating another example of an LDPC code exponent matrix according to an embodiment of the present invention.
19, 19A and 19B are diagrams illustrating another example of an LDPC code exponent matrix according to an embodiment of the present invention.
20, 20A and 20B are diagrams illustrating another example of an LDPC code exponent matrix according to an embodiment of the present invention.
21, 21A and 21B are diagrams illustrating another example of an LDPC code exponent matrix according to an embodiment of the present invention.
22, 22A and 22B are diagrams illustrating another example of an LDPC code exponent matrix according to an embodiment of the present invention.
23, 23A and 23B are diagrams illustrating another example of an LDPC code exponent matrix according to an embodiment of the present invention.
24, 24A and 24B are diagrams illustrating another example of an LDPC code exponent matrix according to an embodiment of the present invention.
25, 25a, 25b, 25c, 25d, 25e, 25f, 25g, 25h and 25i are other examples of the LDPC code basic matrix according to the embodiment of the present invention.
26, 26a, 26b, 26c, 26d, 26e, 26f, 26g, 26h and 26i are other examples of the LDPC code exponent matrix according to the embodiment of the present invention.
FIG. 27 is another example of an LDPC code exponent matrix according to an embodiment of the present invention.
28 is another example of an LDPC code exponent matrix according to an embodiment of the present invention.
29 is another example of an LDPC code exponent matrix according to an embodiment of the present invention.
30 is another example of an LDPC code exponent matrix according to an embodiment of the present invention.
31 is another example of an LDPC code exponent matrix according to an embodiment of the present invention.
32 is another example of an LDPC code exponent matrix according to an embodiment of the present invention.
33 is another example of an LDPC code exponent matrix according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions of the present invention, and these may be changed according to the intention of the user, the operator, or the like. Therefore, the definition should be based on the contents throughout this specification.

It is to be understood that the subject matter of the present invention is also applicable to other systems having similar technical backgrounds, with a slight variation not exceeding the scope of the present invention, and it can be done by a person skilled in the art It will be possible.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The Low Density Parity Check (LDPC) code, first introduced by Gallager in the 1960s, has long been forgotten due to the complexity of the technology at the time. However, since turbo codes proposed by Berrou, Glavieux, and Thitimajshima in 1993 showed a performance close to the channel capacity of Shannon, many interpretations on the performance and characteristics of turbo codes were made, iterative decoding, and graph-based channel coding. When the LDPC code is re-studied in the late 1990s, iterative decoding based on a sum-product algorithm is applied on a Tanner graph corresponding to the LDPC code to perform decoding, It has also been found that it has performance close to the capacity of the channel.

An LDPC code can be expressed using a bipartite graph, which is generally defined as a parity-check matrix and is collectively referred to as a tanner graph.

1 is a diagram illustrating a systematic LDPC codeword structure.

(102)를 LDPC 부호화하면, 부호어

(100)가 생성된다. 즉, 정보어 및 부호어는 다수의 비트로 구성되어 있는 비트열이며, 정보어 비트 및 부호어 비트는 정보어 및 부호어를 구성하는 각각의 비트를 의미한다. 통상적으로 부호어가

와 같이 정보어를 포함하고 있을 경우 시스테메틱(systemetic) 부호라 한다. 여기에서,

는 패리티 비트(104)이고, 패리티 비트의 개수 N_parity는 N_parity=N_ldpc - K_ldpc 로 나타낼 수 있다. _Referring to FIG. 1, an LDPC code receives an information word 102 composed of K _ldpc bits or symbols and performs LDPC coding to generate a codeword 100 consisting of N _ldpc bits or symbols do. For convenience of explanation, it is assumed that a codeword 100 composed of N _ldpc bits is generated by receiving an information word 102 including K _ldpc bits. That is, K _ldpc input bits

(102) is LDPC-coded, a codeword

(100) is generated. That is, the information word and the codeword are bit strings composed of a plurality of bits, and the information word bit and the codeword bit are each bit constituting the information word and the codeword. Typically,

, It is called a systematic code. From here,

Is the parity bit 104 and the number N _parity of the parity bits is N _parity = N _ldpc - K _ldpc .

The LDPC code is a type of linear block code and includes a process of determining a codeword satisfying the following Equation (1).

[Equation 1]

이다. From here,

to be.

In Equation (1), H denotes a parity check matrix, C denotes a codeword, c _i denotes an i-th bit of a codeword, and N _ldpc denotes an LDPC codeword length. Here, h _i denotes an i-th column of the parity check matrix H.

The parity check matrix H is composed of N _ldpc columns equal to the number of bits of the LDPC codeword. Equation 1 means that the sum of the product of the i-th column h _i of the parity check matrix and the i-th codeword bit c _i is '0', so that the i-th column h _i is the i-th codeword bit c _i . < / RTI >

A graphical representation method of an LDPC code will be described with reference to FIG.

FIG. 2 illustrates an example of a parity check matrix H ₁ of an LDPC code including four rows and eight columns, and a diagram thereof as a Tanner graph. Referring to FIG. 2, a parity check matrix H ₁ generates a codeword having a length of 8 because there are eight columns. A code generated through H ₁ means an LDPC code. Bit.

Referring to FIG. 2, a tanner graph of an LDPC code for encoding and decoding based on a parity check matrix H ₁ includes eight variable nodes, that is, x ₁ 202, x ₂ 204, x ₃ 206, x ₄ 208, x ₅ 210, x ₆ 212, x ₇ 214 and x ₈ 216 and four check nodes 218, 220, 222, 224, . Here, the i-th column and the j-th row of the parity check matrix H ₁ of the LDPC code correspond to the variable nodes x _i and j-th check nodes, respectively. The value of 1, that is, a value other than 0 at the intersection of the j-th column and the j-th row of the parity check matrix H ₁ of the LDPC code means that the variable node x _i and the jth check This means that there is an edge connecting the node.

In the Tanner graph of the LDPC code, the degree of the variable node and the check node means the number of segments connected to each node. This means that in the parity check matrix of the LDPC code, 0 Is equal to the number of non-elemental entries. For example, in FIG. 2, variable nodes x ₁ 202, x ₂ 204, x ₃ 206, x ₄ 208, x ₅ 210, x ₆ 212, x ₇ 214 ), the order of the x ₈ (216) are each in sequence 4, 3, 3, 3, 2, 2, 2, and 2, the degree of the check nodes (218, 220, 222, 224) is 6, as each sequence , 5, 5, 5. In addition, the number of non-zero elements in each column of the parity check matrix H ₁ of FIG. 2 corresponding to the variable node of FIG. 2 corresponds to the order 4, 3, 3, 3, 2, 2, And the number of non-zero elements in each row of the parity check matrix H ₁ of FIG. 2 corresponding to the check nodes of FIG. 2 coincides in order with the above-mentioned orders 6, 5, 5 and 5 .

The LDPC code can be decoded using an iterative decoding algorithm based on a sum-product algorithm on the bipartite graph shown in FIG. Here, the summing algorithm is a kind of message passing algorithm, and the message passing algorithm is a method of exchanging messages through an edge on a half-graph and calculating an output message from messages input to a variable node or a check node It shows the algorithm to update.

Here, the value of the i-th encoding bit can be determined based on the message of the i-th variable node. The value of the i-th encoded bit can be either a hard decision or a soft decision. Therefore, the performance of the i-th bit c _i of the LDPC codeword corresponds to the performance of the i-th variable node of the tanner graph, which can be determined according to the position and number of 1s in the i-th column of the parity check matrix. In other words, the performance of the N _ldpc codeword bits of the codeword can be influenced by the position and the number of 1s of the parity check matrix, which indicates that the performance of the LDPC code is greatly affected by the parity check matrix do. Therefore, a method for designing a good parity check matrix is needed to design an LDPC code having excellent performance.

A parity check matrix used in a communication and broadcasting system is typically a quasi-cyclic LDPC code (or QC-LDPC code) using a parity check matrix, .

The QC-LDPC code is characterized by having a parity check matrix composed of a 0-matrix or a circulant permutation matrix having a small square matrix. In this case, the permutation matrix means a matrix in which all elements of the square matrix are 0 or 1, and each row or column contains only one 1. Also, the circular permutation matrix means a matrix obtained by cyclically shifting each element of the identity matrix to the right.

Hereinafter, the QC-LDPC code will be described in detail.

크기의 순환 순열 행렬

을 정의한다. 여기서

는 행렬 상기 행렬 P에서의 i번째 행(row), j번째 열(column)의 원소(entry)를 의미한다.(0 ≤i, j < L) First, as shown in Equation (2)

A circular permutation matrix of size

. here

(0? I, j < L) denotes an element of an i-th row and a j-th column in the matrix P,

&Quot; (2) &quot;

(0 ≤ i < L)는

크기의 항등 행렬(identity matrix)의 각 원소들을 i 번 만큼 오른쪽 방향으로 순환 이동(circular shift) 시킨 형태의 순환 순열 행렬임을 알 수 있다. For the permutation matrix P defined above,

(0 < i &lt; L)

It is a circular permutation matrix in which each element of the size identity matrix is circularly shifted to the right by i times.

The parity check matrix H of the simplest QC-LDPC code can be expressed by the following equation (3).

&Quot; (3) &quot;

을

크기의 0-행렬이라 정의할 경우, 상기 수학식 3에서 순환 순열 행렬 또는 0-행렬의 각 지수

는 {-1, 0, 1, 2, ..., L-1} 값 중에 하나를 가지게 된다. 또한 상기 수학식 3의 패리티 검사 행렬 H는 열 블록(column block)이 n개, 행 블록이 m개이므로,

크기를 가지게 됨을 알 수 있다. if

of

Matrix is defined as a 0-matrix having a size of 0,

Has one of {-1, 0, 1, 2, ..., L-1}. Since the parity check matrix H of Equation (3) has n column blocks and m row blocks,

It is understood that it has a size.

If the parity check matrix of Equation (3) has a full rank, it is obvious that the size of the information bits of the QC-LDPC code corresponding to the parity check matrix is (n-m) L. For convenience, (n-m) column blocks corresponding to information bits are called information word column blocks, and m column blocks corresponding to the remaining parity bits are called parity column blocks.

크기의 이진(binary) 행렬을 패리티 검사 행렬 H의 모행렬(mother matrix) 또는 기본 행렬(base matrix) M(H)라 하고, 각 순환 순열 행렬 또는 0-행렬의 지수를 선택하여 수학식 4와 같이 얻은

크기의 정수 행렬을 패리티 검사 행렬 H의 지수 행렬 E(H)라 한다. Normally, in the parity check matrix of Equation (3), each of the cyclic permutation matrix and the 0-matrix is replaced with 1 and 0,

A binary matrix of a size M is defined as a mother matrix or a base matrix M (H) of a parity check matrix H and the exponents of the respective cyclic permutation matrixes or 0-matrices are selected, Gained with

The integer matrix of size is called the exponent matrix E (H) of the parity check matrix H.

&Quot; (4) &quot;

As a result, one integer included in the exponent matrix corresponds to a cyclic permutation matrix in the parity check matrix, so that the exponential matrix may be expressed as a series of integers for the sake of convenience. (The sequence may be called an LDPC sequence or an LDPC code sequence to distinguish it from another sequence). In general, the parity check matrix can be expressed not only as an exponent matrix but also as a sequence having the same characteristics as logarithmically. In the present invention, the parity check matrix is represented by an exponent matrix or a sequence which indicates a position of 1 in the parity check matrix. However, the sequence notation method for distinguishing the positions of 1 or 0 included in the parity check matrix And thus can be represented in various forms of the series which exhibit the same effect algebraically, without being limited to the method described in this specification.

In addition, a transmission / reception apparatus on a device may directly generate a parity check matrix to perform LDPC encoding and decoding. However, according to characteristics of an implementation, an LDPC coding and decoding using an exponent matrix or a sequence having an algebraic effect on the parity check matrix, . Therefore, although the encoding and decoding using the parity check matrix are described for convenience in the present invention, it is considered that the present invention can be implemented by various methods that can achieve the same effect as the parity check matrix on an actual device.

For reference, algebraically the same effect means that two or more expressions that are different can be described logically or mathematically as being perfectly identical to each other or convertible.

의 합으로 포함되어 있을 때, 그 지수 행렬은 수학식 6과 같이 나타낼 수 있다. 상기 수학식 6을 살펴보면, 상기 복수 개의 순환 순열 행렬 합이 포함된 행 블록 및 열 블록에 대응되는 i 번째 행 및 j 번째 열에 2 개의 정수가 대응되는 행렬임을 알 수 있다. In the present invention, only one cyclic permutation matrix corresponding to one block is described. However, the present invention can be applied to a case where a plurality of cyclic permutation matrixes are included in one block. For example, as shown in the following Equation 5, two cyclic permutation matrices at the positions of one i-th row block and j-th column block

, The exponent matrix can be expressed by Equation (6). &Quot; (6) &quot; Referring to Equation (6), it can be seen that two integers correspond to the i-th row and the j-th column corresponding to the row block and column block including the sum of the plurality of cyclic permutation matrixes.

&Quot; (5) &quot;

&Quot; (6) &quot;

크기의 행렬을 순환 행렬(circulant matrix 또는 circulant)이라 한다.In the QC-LDPC code, a plurality of cyclic permutation matrices may correspond to one row block and a column block in the parity check matrix, but in the present invention, one circular permutation matrix corresponds to one block for convenience. Only the case will be described, but the gist of the invention is not limited thereto. For reference, when a plurality of circular permutation matrixes are overlapped in one row block and column block

The size matrix is called a circulant matrix or circulant.

The parity check matrix and the base matrix for the parity check matrix and the exponent matrix of Equations (5) and (6) are defined as 1 and 0 for each of the circulant permutation matrix and the 0-matrix, respectively, Means a binary matrix obtained by replacing a sum of a plurality of cyclic permutation matrices included in one block (i.e., a circulating matrix) with 1 simply.

Since the performance of an LDPC code is determined according to a parity check matrix, it is necessary to design a parity check matrix for an LDPC code having a good performance. Also, there is a need for an LDPC coding or decoding method capable of supporting various input lengths and coding rates.

Lifting is used not only for efficient design of QC-LDPC codes but also for generating parity check matrices of various lengths from a given exponent matrix or generating LDPC codewords. That is, the lifting may be applied to efficiently design a very large parity check matrix by setting a L-value that determines the size of a circular permutation matrix or a 0-matrix from a given small mother matrix according to a specific rule, The LDPC codeword is generated by generating a parity check matrix of various lengths by applying an appropriate L value to the sequence.

The existing lifting method and the characteristics of the QC-LDPC code designed through lifting are briefly described with reference to the following reference [Myung2006].

Reference [Myung2006]

S. Myung, K. Yang, and Y. Kim, "Lifting Methods for Quasi-Cyclic LDPC Codes," IEEE Communications Letters. vol. 10, pp. 489-491, June 2006.

는

크기의 지수 행렬

을 가지며 각 지수

들은 {-1, 0, 1, 2, ..., L_k - 1} 값 중에 하나로 선택된다. First, S QC-LDPC codes to be designed through a lifting method are C ₁ , ..., C _S when an LDPC code C ₀ is given, and a row block and a column block of a parity check matrix of each QC- The value corresponding to the size of L is called L _k . Here, C ₀ corresponds to the smallest LDPC code having a matrix of C ₁ , ..., C _S as a parity check matrix, and the L ₀ value corresponding to the size of the row block and the column block is 1. For convenience, the parity check matrix of each code _Ck

The

Exponent matrix of size

And each index

Are selected as one of {-1, 0, 1, 2, ..., L _k - 1}.

만 저장하고 있으면 리프팅 방식에 따라 다음 수학식 7을 이용하여 상기 QC-LDPC 부호 C₀, C₁, ..., C_S를 모두 나타낼 수 있다.The existing lifting method consists of the steps of C ₀ → C ₁ → ... → C _S and L _{k +1} = q _{k + 1} L _k (q _{k +1} is a positive integer, k = 0, 1, ..., S-1). In addition, the parity check matrix of the C _S by the properties of the lifting process,

The QC-LDPC codes C ₀ , C ₁ , ..., C _S can be represented by the following Equation (7) according to the lifting method.

&Quot; (7) &quot;

or

&Quot; (8) &quot;

Thus large QC-LDPC code C _1, than from C ₀ ..., C _S, such as how to design as well as a large sign small code using an appropriate method as shown in Equation 7 or Equation 8 from C _k C _i (i = k-1, k-2, ..., 1, 0) is called lifting.

In the lifting scheme of Equation (7) or (8), the L _k corresponding to the size of the row block or the column block in the parity check matrix of each QC-LDPC code C _{k has} a multiple relation with each other, Lt; / RTI &gt; The existing lifting method can easily design the QC-LDPC code that improves the error floor characteristics by improving the algebraic or graph characteristics of each parity check matrix designed through lifting.

만을 가질 수 있다. 즉, 리프팅을 10 단계 적용할 경우(S=10) 패리티 검사 행렬의 크기는 총 10 가지를 생성할 수 있으며, 이는 곧 10 가지 종류의 길이를 가지는 QC-LDPC 부호를 지원할 수 있음을 의미한다. However, since each L _k value is in a multiple relation with each other, the length of each code is severely limited. For example, assuming that a minimum lifting scheme such as L _{k +1} = 2 × L _k is applied to each L _k value, in this case, the size of the parity check matrix of each QC-LDPC code is

. That is, when lifting is applied in 10 steps (S = 10), the size of the parity check matrix can generate 10 kinds, which means that QC-LDPC codes having 10 kinds of lengths can be supported.

For this reason, existing lifting schemes are somewhat disadvantageous in designing QC-LDPC codes that support various lengths. However, in a commonly used communication system, a very high level of length compatibility is required in consideration of various types of data transmission. For this reason, there is a problem that the LDPC coding technique based on the existing lifting method is difficult to apply in a communication system.

In order to solve such a problem, the present invention uses the following lifting method.

라 하고, L 값에 따라 변환된 지수 행렬을

이라 할 때 일반적으로 다음과 수학식 9와 같은 변환식을 적용할 수 있다. In general, lifting may be considered to use the exponent matrix of FIG. 4 for LDPC encoding and decoding by varying the values of the elements for various L values. For example, the exponent matrix of FIG.

, And the exponent matrix transformed according to the L value

The following equation (9) can be generally applied.

&Quot; (9) &quot;

는 다양한 형태로 정의할 수 있는데 예를 들면 다음 수학식 10과 같은 정의들을 사용할 수도 있다. In Equation (9)

Can be defined in various forms. For example, the following definitions may be used.

&Quot; (10) &quot;

In Equation (10), mod (a, b) denotes a modulo-b operation for a, and D denotes a constant that is a positive integer defined in advance.

4 is a block diagram of a transmission apparatus according to an embodiment of the present invention.

4, the transmitting apparatus 400 includes a segmenting unit 410, a zero padding unit 420, an LDPC coding unit 430, a rate matching unit 440 ), A modulation unit 450, and the like. The rate matching unit 440 may include an interleaver 441 and a puncturing / repetition / zero elimination unit 442.

Here, the components shown in Fig. 4 are components for performing encoding and modulation on variable length input bits, which is only an example, and in some cases, some of the components shown in Fig. 4 are omitted or changed And other components may be added.

Meanwhile, the transmitting apparatus 400 may transmit the required parameters (e.g., input bit length, modulation and code rate, parameters for zero padding (or shortening), code rate / codeword length of LDPC code, interleaving A parameter and modulation scheme for repetition and puncturing, and the like), encoding based on the determined parameter, and transmitting the encoded parameter to the receiving apparatus 500.

In the case that the number of input bits is variable, if the number of input bits is larger than a predetermined value, it can be segmented to have a length equal to or shorter than a predetermined value. Also, each of the segmented blocks may correspond to one LDPC coded block. However, if the number of input bits is less than or equal to a preset value, no segmentation occurs. The input bits may correspond to one LDPC coded block.

On the other hand, the transmission apparatus 400 may store various parameters used for coding, interleaving, and modulation. Here, the parameters used for coding may be information on the code rate of the LDPC code, the codeword length, and the parity check matrix. A parameter used for interleaving may be information on an interleaving rule, and a parameter used for modulation may be information on a modulation scheme. Further, the information on the puncturing can be a puncturing length. In addition, the information about repetition can be the repetition length. The information on the parity check matrix may store the exponent value of the circulant matrix when the parity matrix proposed in the present invention is used.

In this case, each component constituting the transmitting apparatus 400 can be operated using these parameters.

Although not shown, the transmitting apparatus 400 may further include a controller (not shown) for controlling the operation of the transmitting apparatus 400 according to circumstances.

5 is a block diagram of a receiving apparatus according to an embodiment of the present invention.

5, the receiving apparatus 500 includes a demodulator 510, a rate dematching unit 520, an LDPC decoding unit 530, a zero elimination unit 540, and a demodulation unit 530 to process variable length information. A demagnetization unit 550, and the like. The rate dematching unit 520 may include a log likelihood ratio (LLR) insertion unit 522, an LLR combiner 523, a deinterleaver 524, and the like.

Here, the components shown in Fig. 5 are components that perform the functions corresponding to the components shown in Fig. 5, which are merely examples, and in some cases, some of them may be omitted or changed, More may be added.

The parity check matrix in the present invention may be read using a memory, or may be given in advance in a transmitting apparatus or a receiving apparatus, or may be directly generated in a transmitting apparatus or a receiving apparatus. Also, the transmitting apparatus may store or generate a sequence or exponent matrix corresponding to the parity check matrix and apply it to the encoding. Likewise, the receiving apparatus may also store or generate a sequence or exponent matrix corresponding to the parity check matrix and apply the same to decoding.

Hereinafter, the receiver operation will be described in detail with reference to FIG.

The demodulation unit 510 demodulates a signal received from the transmission apparatus 400.

The demodulation unit 510 demodulates a signal received from the transmission apparatus 400 and transmits the bits transmitted from the transmission apparatus 400 to the demodulation unit 450. [ Lt; / RTI &gt;

To this end, the receiving apparatus 500 may store information on a modulation scheme modulated according to a mode in the transmitting apparatus 400. Accordingly, the demodulator 510 may demodulate the signal received from the transmitting apparatus 400 according to the mode, and generate values corresponding to the LDPC codeword bits.

Meanwhile, the value corresponding to the bits transmitted from the transmitting apparatus 400 may be a log likelihood ratio (LLR) value.

Specifically, the LLR value can be represented by a value obtained by taking a log as a ratio of the probability that the bits transmitted from the transmitting apparatus 400 are zero and the probability of one day. Alternatively, the LLR value may be a bit value itself, and the LLR value may be a representative value determined according to an interval in which the probability that the bit transmitted from the transmitting apparatus 400 is 0 or 1 belongs.

The demodulation unit 510 performs multiplexing (not shown) on the LLR value. Specifically, an operation corresponding to a bit demux (not shown) can be performed with a component corresponding to a bit demux (not shown) of the transmission apparatus 400.

To this end, the receiving apparatus 500 may be storing information on parameters that the transmitting apparatus 400 has used for demultiplexing and block interleaving. Accordingly, the MUX (not shown) performs the demultiplexing and the block interleaving operations performed in the bit demux (not shown) with respect to the LLR value corresponding to the cell word, and returns the LLR value corresponding to the cell word in the bit unit Lt; / RTI &gt;

The rate dematching unit 520 may insert an LLR value into the LLR value output from the demodulation unit 510. [ In this case, the rate dematching unit 520 may insert predetermined LLR values between the LLR values output from the demodulation unit 510.

Specifically, the rate dematching unit 520 corresponds to the rate matching unit 440 of the transmission apparatus 400 and includes an interleaver 441, a zero elimination and puncturing / repetition / zero elimination unit 442 ) Can be performed.

First, the rate dematching unit 520 deinterleaves the interleaver 441 to correspond to the interleaver 441 of the transmitter. The output values of the deinterleaver 524 may insert LLR values corresponding to zero bits at positions where the zero bits are padded in the LDPC codeword in the LLR inserter 522. [ In this case, the LLR value corresponding to the padded zero bits, that is, the shortened zero bits, may be ∞ or -∞. However, ∞ or -∞ is a theoretical value, which may be substantially the maximum or minimum value of the LLR value used in the receiving apparatus 500.

For this purpose, the receiving apparatus 500 may be storing information on parameters that the transmitting apparatus 400 has used to padd the zero bits. Accordingly, the rate dematching unit 520 can determine the position where the zero bits are padded in the LDPC code word, and insert the LLR value corresponding to the shortened zero bits at the corresponding position.

The LLR insertion unit 522 of the rate dematching unit 520 may insert an LLR value corresponding to the punctured bits at the positions of the punctured bits in the LDPC codeword. In this case, the LLR value corresponding to the punctured bits may be zero.

To this end, the receiving apparatus 500 may store information on parameters used for puncturing in the transmitting apparatus 400. Accordingly, the LLR insertion unit 522 can insert an LLR value corresponding to the position where the LDPC parity bits are punctured.

The LLR combiner 523 can combine or sum up the LLR values output from the LLR insertion unit 522 and the demodulation unit 510. Specifically, the LLR combiner 523 is a component corresponding to the puncturing / repetition / zero elimination unit 442 of the transmitting apparatus 400, and performs an operation corresponding to the repetition unit 442 . First, the LLR combiner 523 may combine the LLR value corresponding to the repeated bits with another LLR value. Here, another LLR value may be an LLR value for the bits based on generation of repeated bits in the transmitting apparatus 400, that is, the LDPC parity bits selected for repetition.

That is, as described above, the transmitting apparatus 400 selects the bits from the LDPC parity bits, and repeats them between the LDPC information bits and LDPC parity bits to transmit to the receiving apparatus 500.

Accordingly, the LLR value for the LDPC parity bits is the LLR value for the repaired LDPC parity bits and the LLR value for the unreputed LDPC parity bits, i.e., the LDPC parity bits generated by the encoding Lt; / RTI &gt; Thus, the LLR combiner 523 can combine the LLR values with the same LDPC parity bits.

To this end, the receiving apparatus 500 may store information on parameters used for repetition in the transmitting apparatus 400. [ Accordingly, the LLR combiner 523 can determine the LLR value for the repaired LDPC parity bits and combine it with the LLR value for the LDPC parity bits on which the repetition is based.

In addition, the LLR combiner 523 may combine the LLR values corresponding to retransmission or IR (Increment Redundancy) bits with other LLR values. Here, the different LLR values may be the LLR values for the bits that were selected for generating the LDPC codeword bits based on retransmission or IR generated bits in the transmitting device 400.

That is, as described above, the transmitting apparatus 400 may transmit some or all of the codeword bits to the receiving apparatus 500 when a NACK occurs for HARQ.

Accordingly, the LLR combiner 523 may combine the LLR values for the bits received via retransmission or IR with the LLR values for the LDPC codeword bits received over the previous frame.

To this end, the receiving apparatus 500 may store information on parameters used for retransmission or IR bits generation in the transmitting apparatus 400. Accordingly, the LLR combiner 523 can determine the LLR value for the number of retransmission or IR bits and combine it with the LLR value for the LDPC parity bits based on the generation of the retransmission bits.

The deinterleaver 524 may deinterleave the LLR value output from the LLR combiner 523. [

Specifically, the deinterleaver unit 524 is a component corresponding to the interleaver 441 of the transmission apparatus 400, and can perform an operation corresponding to the interleaver 441. [

To this end, the receiving apparatus 500 may store information on parameters used by the transmitting apparatus 400 for interleaving. Accordingly, the deinterleaver 524 reverses the interleaving operation performed in the interleaver 441 with respect to the LLR value corresponding to the LDPC codeword bits, and deinterleaves the LLR value corresponding to the LDPC codeword bits .

The LDPC decoding unit 530 may perform LDPC decoding based on the LLR value output from the rate dematching unit 520. [

Specifically, the LDPC decoding unit 530 is a component corresponding to the LDPC encoding unit 430 of the transmission apparatus 400, and can perform an operation corresponding to the LDPC encoding unit 430.

To this end, the receiving apparatus 500 may store information on parameters used for performing LDPC coding according to a mode in the transmitting apparatus 400. Accordingly, the LDPC decoding unit 530 can perform LDPC decoding based on the LLR value output from the rate dematching unit 520 according to the mode.

For example, the LDPC decoding unit 530 performs LDPC decoding based on the LLR value output from the rate dematching unit 520 on the basis of the iterative decoding scheme based on the summing algorithm, and outputs the error- Bits. &Lt; / RTI &gt;

The zero elimination unit 540 may remove the zero bits from the bits output from the LDPC decoding unit 530.

Specifically, the zero elimination unit 540 is a component corresponding to the zero padding unit 420 of the transmission apparatus 400 and may perform an operation corresponding to the zero padding unit 420. [

To this end, the receiving apparatus 500 may store information on parameters used for padding the zeroth bits in the transmitting apparatus 400. Accordingly, the zero elimination unit 540 can remove the zero bits padded by the zero padding unit 420 from the bits output from the LDPC decoding unit 530. [

The demagnetization unit 550 is a component corresponding to the segmentation unit 410 of the transmission apparatus 400 and can perform an operation corresponding to the segmentation unit 410. [

To this end, the receiving apparatus 500 may store information on parameters used by the transmitting apparatus 400 for segmentation. Accordingly, the demagnetization unit 550 may combine the bits output from the zero elimination unit 540, that is, the segments for the variable length input bits, to recover the bits before segmentation.

On the other hand, the LDPC code can be decoded by using an iterative decoding algorithm based on the sum algorithm on the half graph shown in FIG. 2, and the summing algorithm is a type of message passing algorithm.

Hereinafter, a message passing operation generally used in LDPC decoding will be described with reference to FIGS. 6A and 6B.

6A and 6B show message passing operations at any check node and variable node for LDPC decoding.

6A shows a plurality of variable nodes 610, 620, 630, and 640 connected to the check node m 600 and the check node m 600. In the illustrated example, Tn ', m represents a message passed from the variable node n' 610 to the check node m 600, and En and m are passed from the check node m 600 to the variable node n 630 . Define a set of all variable nodes connected to the check node m 600 as N (m), and define a set N (m) excluding N (m) as variable N (m) .

In this case, a message update rule based on the sum-of-product algorithm can be expressed by Equation (11).

&Quot; (11) &quot;

는 하기의 수학식 12와 같이 나타낼 수 있다. Here, Sign (E _{n, m} ) represents the sign of the message E _{n, m} , and | E _{n, m} | represents the magnitude of the message E _{n, m} . Meanwhile,

Can be expressed by the following equation (12).

&Quot; (12) &quot;

6B shows a plurality of check nodes 660, 670, 680 and 690 connected to the variable node x 650 and the variable node x 650. In the illustrated example, E _{y ', x} represents a message passed from the check node y' 660 to the variable node x 650, and T _{y, x} represents the variable node y 680 in the variable node x 650, Message. &Lt; / RTI &gt; Define a set of all variable nodes connected to the variable node x 650 as M (x) and define a set excluding M (x) as the check node y (680) as M (x) . In this case, the message update rule based on the sum-of-products algorithm can be expressed by Equation (13).

&Quot; (13) &quot;

Here, E _x denotes the initial message value of the variable node x.

When the bit value of the node x is determined, it can be expressed by the following equation (14).

&Quot; (14) &quot;

In this case, the encoding bit corresponding to the node x can be determined according to the P _x value.

6A and 6B is a general decoding method, a detailed description will be omitted. However, in addition to the method described in FIGS. 6A and 6B, other methods may be applied to determine the value of the passed message at the variable node and the check node, and a detailed description thereof can be found in Frank R. Kschischang, Brendan J. Frey, and Hans-Andrea Loeliger, "Factor Graphs and the Sum-Product Algorithm," IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 47, NO. 2, FEBRUARY 2001, pp 498-519).

FIG. 7 is a block diagram illustrating a detailed configuration of an LDPC encoder according to an embodiment of the present invention. Referring to FIG.

)을 구성할 수 있다. LDPC 부호화부(700)는 K_ldpc 개의 LDPC 정보어 비트들을 시스테매틱하게 LDPC 부호화하여, N_ldpc 개의 비트들로 구성된 LDPC 코드워드

=(c₀,c₁,..., c_Nldpc-1)=(i₀,i₁,..., i_Kldpc-1,p₀,p₁,...,p_{Nldpc-Kldpc-1})를 생성할 수 있다. The K _ldpc bits correspond to K _ldpc LDPC information bits I = (i ₀ , i ₁ , ...,

). The LDPC encoding unit 700 systematically LDPC-codes the K _ldpc LDPC information bits to generate LDPC codewords having N _ldpc bits

_{= (c 0, c 1,} ..., c Nldpc-1) = (i 0, i 1, ..., i Kldpc-1, p 0, p 1, ..., p Nldpc-Kldpc-1 Can be generated.

And determining a codeword so that a product of the LDPC codeword and the parity check matrix becomes a zero vector, as described in Equation (1).

Referring to FIG. 7, the encoding apparatus 700 includes an LDPC encoding unit 710. The LDPC encoding unit 710 may generate LDPC codewords by performing LDPC encoding on input bits based on a parity check matrix or a corresponding exponent matrix or sequence. In this case, the LDPC encoding unit 710 can perform LDPC encoding using different parity check matrices defined according to the code rate (i.e., the code rate of the LDPC code).

The encoding apparatus 700 may further include a memory (not shown) for storing information on a code rate, a codeword length, and a parity check matrix of the LDPC code. The LDPC encoding unit 710 may include such information To perform LDPC encoding. The information on the parity check matrix may store information on the exponent value of the circulant matrix when the parity matrix proposed in the present invention is used.

8 is a block diagram illustrating a configuration of a decoding apparatus according to an embodiment of the present invention.

Referring to FIG. 8, the decoding apparatus 800 may include an LDPC decoding unit 810.

The LDPC decoding unit 810 performs LDPC decoding on the LDPC codeword based on the parity check matrix or a corresponding exponent matrix or sequence.

For example, the LDPC decoding unit 810 may perform LDPC decoding to generate information word bits by passing an LLR (Log Likelihood Ratio) value corresponding to LDPC codeword bits through an iterative decoding algorithm.

Here, the LLR value is a channel value corresponding to the LDPC codeword bits, and can be expressed in various ways.

For example, the LLR value can be expressed as a value obtained by taking a log as a ratio of the probability that the bit transmitted through the channel on the transmitting side is 0 and the probability of 1 day. The LLR value may be the bit value itself determined according to the hard decision, and may be a representative value determined according to the interval in which the probability that the bit transmitted from the transmitting side is 0 or 1 belongs.

In this case, the transmitting side can generate the LDPC codeword using the LDPC coding unit 710 as shown in FIG.

In this case, the LDPC decoding unit 810 can perform LDPC decoding using a parity check matrix defined differently according to the coding rate (i.e., the coding rate of the LDPC code).

FIG. 9 shows a structure of an LDPC decoding unit according to another embodiment of the present invention.

As described above, the LDPC decoding unit 810 can perform LDPC decoding using an iterative decoding algorithm. In this case, the LDPC decoding unit 810 can be configured as shown in FIG. However, in the case of the iterative decoding algorithm, the detailed configuration shown in FIG. 9 is only an example in that it is already known.

9, the decoding apparatus 900 includes an input processor 901, a memory 902, a variable node operator 904, a controller 906, a check node operator 908, and an output processor 910 .

The input processor 901 stores the input value. Specifically, the input processor 901 may store an LLR value of a reception signal received via a wireless channel.

The controller 904 calculates the number of values input to the variable node calculator 904 based on the parity check matrix corresponding to the size of the block of the received signal (i.e., the length of the codeword) The address value in the memory 902, the number of values input to the check node operator 908, and the address value in the memory 902, and the like.

The memory 902 stores input data and output data of the variable node operator 904 and the check node operator 908.

The variable node operator 904 receives the data from the memory 902 according to the address information of the input data and the number information of the input data received from the controller 906 and performs variable node operation. Thereafter, the variable node operator 904 stores the variable node operation results in the memory 902 based on the address information of the output data input from the controller 906 and the number information of the output data. The variable node operator 904 inputs the result of the variable node operation to the output processor 910 based on the data input from the input processor 901 and the memory 902. Here, the variable node operation has been described above with reference to FIG.

The check node calculator 908 receives data from the memory 902 based on the address information of the input data and the number information of the input data received from the controller 906 and performs check node calculation. Then, the check node operator 908 stores the variable node operation results in the memory 902 based on the address information of the output data input from the controller 906 and the number information of the output data. Here, the check node operation has been described above with reference to FIG.

The output processor 910 outputs a hard decision result based on the data received from the variable node operator 904 after determining whether the information bits of the codeword on the transmission side are 0 or 1, 910 are finally decoded values. In this case, it is possible to make a hard decision based on the sum of all message values (initial message value and all message values input from the check node) input to one variable node in FIG.

The decoding apparatus 900 may further include a memory (not shown) for storing the code rate, the codeword length, and the parity check matrix information of the LDPC code. The LDPC decoding unit 810 decodes the information To perform LDPC encoding. However, this is only an example, and the information may be provided from the transmitting side.

10 is a block diagram of a transmission block according to another embodiment of the present invention.

Referring to FIG. 10, it is possible to add < Null > bits so that the segmented lengths are the same.

The < Null > bits may be added to match the information length of the LDPC code.

In the foregoing, a method of applying various block sizes based on a QC-LDPC code has been described in a communication and broadcasting system supporting LDPC codes of various lengths. Next, we propose a method to improve the coding performance in the proposed method.

In general, if a sequence is suitably transformed from a single LDPC exponent matrix or a sequence, such as the lifting method described in Equations (9) and (10), to a very different block size L, There are many benefits because it only needs to be implemented for. However, it is very difficult to design an LDPC code with good performance for all block sizes as the number of types of block sizes to be supported increases.

에 기반한 리프팅을 가정하여 설명을 진행하지만 반드시 이에 국한할 필요는 없다. In order to solve such a problem, an efficient design method of the QC LDPC code is described as follows. The present invention proposes a method of designing a parity check matrix having excellent performance considering the lifting method of Equations (9) and (10) and the parity check matrix of the LDPC code or the trapping set characteristic of the Tanner graph. In the present invention,

Based lifting, but need not be limited to this.

* Design Method of Variable Length QC LDPC Code

Step 1) In determining the noise threshold for decode success of the channel code, a convergence criterion for iteration number and density evolution is changed, and a density evolution analysis is performed, Obtain the weight distribution of the matrix.

Step 2) If the weight distribution obtained in Step 1) can be improved through the Hill Climbing method, the improved weight distribution is set as the weight distribution of the final basic matrix.

Step 3) Obtain one basic matrix based on the weight distribution obtained in Step 2). At this time, the method of obtaining the basic matrix may be designed through various known methods.

의 범위를 만족하는 L 값에 대해 모두 동일한 지수 행렬을 사용하여 부호화 및 복호화를 수행함을 가정한다. Step 3) The lifting is expressed by Equation 10 . In other words,

It is assumed that encoding and decoding are performed using the same exponent matrix for all the L values satisfying the range of &quot; L &quot;.

의 범위를 만족하는 L 값에 따라 지수 행렬을 결정함에 있어 먼저 거스(girth, Tanner 그래프 상의 사이클 길이 중 가장 작은 값)를 최대화한 다음, 사전에 결정된 트랩핑 집합 제거 순서에 따라 트랩핑 집합이 순서대로 최대한 제거되는 지수 행렬을 결정한다. 여기서 상기 결정된 트랩핑 집합 제거 순서는 다음과 같다. Step 4)

In order to determine the exponent matrix according to the L value satisfying the range of L, the Gaussian (the smallest value of the cycle length on the Tanner graph) is first maximized, and then the trapping set is sorted in order And determines the exponent matrix to be removed as much as possible. Here, the determined trapping set removal order is as follows.

1 rank: (4,0) trapping set

2 ranks: (3,1) trapping set

3 ranks: (2,2) trapping set

4 ranks: (3,2) trapping set

5 ranks: (4,1) trapping set

6 ranks: (4,2) trapping set

Step 5) The above steps 1) to 4) are repeated a predetermined number of times, and the code having the best performance with the best performance according to the L value is finally selected through computational experiments on the obtained codes. The average performance can be defined in various ways. For example, the minimum signal-to-noise ratio (SNR) required to achieve the required block error rate (BLER) The code having the smallest average SNR can be finally selected.

It is obvious that the method of designing the variable length QC LDPC code is only an embodiment and can be changed according to the requirements of the channel code. For example, Step 3) can be changed by considering the lifting method when the lifting method to be applied in the system is different. In step 4), the removal order of the trapping set may be changed according to the characteristics of the channel code required in the system. In addition, although the variable length QC LDPC code design method is described for a variable length, even if the length is fixed to one, the lifting process can be applied only in steps 3) and 4).

For example, when the number of information bits is set to a small number, and the code rate is low, codes can be designed assuming that a part of codeword bits obtained after channel coding are repetitively transmitted considering complexity and performance. In this case, in step 1) of the method of designing the variable-length QC LDPC code, a noise threshold is determined by increasing a part of the initial value for density evolution analysis by the number of repetitive transmissions. If the coding rate or length is also fixed, the lifting procedure can be excluded in Step 3) and Step 4).

For reference, details of the well-known density evolution analysis method and the characteristics of the trapping set are out of the scope of the present invention and are replaced by the following reference references [RSU2001] and Reference [KaBa2012] respectively:

Reference [RSU2001]:

T. J. Richardson, M. A. Shokrollahi, and R. L. Urbanke, "Design of capacity-approaching irregular low-density parity-check codes," IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 619-637, Feb. 2001.

Reference [KaBa2012]:

M. Karimi and A. H. Banihashemi, &quot; Efficient algorithm for finding trapping sets of LDPC codes, &quot; IEEE Trans. Inf. Theory, vol. 58, no. 11, pp. 6942-6958, Nov. 2012.

FIGS. 11 to 15 show embodiments of the exponent matrix or the LDPC sequence of the parity check matrix designed through the design method of the present invention.

11A to 11B are enlarged views of the parity check matrix of FIG. 11 by dividing the parity check matrix. 11 corresponds to a matrix corresponding to the reference numerals shown in the respective parts. 11A to 11B may be combined to form one parity check matrix of the form shown in FIG. This also applies to FIGS. 12 to 15. In the exponent matrix of FIGS. 11 to 15, each empty block corresponds to a zero matrix of LxL size.

The feature of the exponent matrix shown in FIG. 11 is that the partial matrix consisting of 7 rows from the top and 17 columns from the front has a degree of 2 or more. Another feature of the exponent matrix shown in FIG. 11 is that all the columns from the 18th column to the 52nd column have a degree of 1. That is, the exponent matrix of 35x52 size composed of the eighth row to the 42nd row of the exponent matrices corresponds to a large number of single parity-check codes. As a result, the exponent matrix shown in FIG. 11 includes an LDPC code having a parity check matrix consisting of 7 row blocks and 17 column blocks with a degree of 2 or more, a plurality of single check codes consisting of 35 row blocks and 52 column blocks, And correspond to concatenation parity check matrices.

The parity check matrix using the concatenation with a single parity check code is advantageous in that the IR (Incremental Redundancy) technique is applied because it is easy to expand. Since the IR scheme is an important technology for supporting HARQ (Hybrid Automatic Repeat reQuest), an efficient IR scheme with high performance increases the efficiency of the HARQ system. The LDPC codes based on the parity check matrices can be efficiently and efficiently implemented by generating and transmitting new parity using a portion extended by a single parity check code.

In the exponent matrix of FIG. 11, the first 10 columns correspond to the information bits. Therefore, the information bits can be determined to have the same size as 10 L according to the size L of the circulating permutation matrix or the circulation matrix in the parity check matrix. Generally, information bit lengths other than 10L can be supported by a method such as shortening. Also, since the codeword bit length is 52 in the exponent matrix of FIG. 11, the codeword bit length can be supported as 52 L according to the L value. In general, if the code rate is not 52L or the code rate is not 10/52, it can be supported by shortening a part of the information bits, puncturing a part of the code bits, or applying both methods.

11 is designed in consideration of the following L value, but it is not necessarily limited thereto.

L = {4,5,6,7} {8,9,10,11,12,13,14,15} {16,18,20,22,24,26,28,30} {32, 36, 128, 144, 160, 176, 192, 208, 224, 240} {256, 40, 44, 48, 52, 56, 60} {64, 72, 80, 88, 96,

The exponent matrix shown in FIGS. 12 to 15 is an exponent matrix for a case where L = 16 and the sign bit number is fixed at 880.

In FIG. 12, the former six columns are used. In FIG. 13, the former five columns are used. In FIG. 14, the former four columns are used. In the exponent matrix, And a column corresponds to an information bit. Therefore, the information bits may be determined as 96, 80, 64, 48, etc. according to the size L = 16 of the cyclic permutation matrix or circulant matrix in the parity check matrix. In general, the information bit length other than the 96, 80, 64, and 48 values can be supported by a method such as shortening. In general, if the number of code bits is not 880, it is possible to shorten a part of the information bits, puncture a part of the code bits, or apply both methods.

As another embodiment of the present invention, there is proposed a method of applying a plurality of exponential matrices or LDPC sequences on a predetermined basic matrix. That is, there is one basic matrix, and an exponent matrix or a sequence of LDPC codes is obtained on the basic matrix, and lifting is applied according to the block size included in each block size group from the exponent matrix or sequence, And decryption. In other words, base matrices of a parity check matrix corresponding to exponent matrices or sequences of a plurality of different LDPC codes are the same. In this scheme, the elements or numbers constituting the exponent matrix or the LDPC sequence of the LDPC code may have different values, but the positions of the elements or numbers have exactly the same characteristics. As described above, the exponent matrix or the LDPC sequence is an index of the cyclic permutation matrix, that is, a kind of circular permutation value for the bits. By setting the positions of the elements or the numbers to be equal to each other, Is easy to grasp.

First, the block size (Z) to be supported is divided into a plurality of block size groups (or sets) as shown in the following Equation (15). Note that the block size Z is a value corresponding to the size ZxZ of the circular permutation matrix or the circular matrix in the parity check matrix of the LDPC code.

&Quot; (15) &quot;

Z1 = {12, 24, 48, 96, 192}

Z2 = {11, 22, 44, 88, 176}

Z3 = {10, 20, 40, 80, 160}

Z4 = {9, 18, 36, 72, 144}

Z5 = {8, 16, 32, 64, 128, 256}

Z6 = {15, 30, 60, 120, 240}

Z7 = {14, 28, 56, 112, 224}

Z8 = {13, 26, 52, 104, 208}

라 하고, 상기 p번째 그룹에 포함된 Z 값에 대응되는 지수 행렬을

라 할 때,

를 이용하여 수학식 9와 같은 수열의 변환 방법을 적용한다고 하자. 즉, 예를 들어 블록 크기 Z가 Z = 28와 같이 결정된 경우에는 Z = 28이 포함되어 있는 7번째 블록 크기 그룹에 대응되는 지수 행렬

에 대해서 Z = 28에 대한 지수 행렬

의 각 원소

를 다음 수학식 16과 같이 얻을 수 있다. The features of the block size groups in Equation (15) are not only different in granularity but also have the same ratio of neighboring block sizes. That is, the block sizes included in one group are in a divisor or multiple relation. The exponential matrices corresponding to p (p = 1, 2, ..., 8)

, And an exponent matrix corresponding to the Z value included in the p-th group

In other words,

And the transformation method of the sequence as shown in Equation (9) is applied. That is, for example, when the block size Z is determined as Z = 28, the exponent matrix corresponding to the 7th block size group including Z = 28

The exponent matrix for Z = 28 for

Of each element

Can be obtained by the following equation (16).

&Quot; (16) &quot;

The conversion of Equation (16) can be simply expressed as Equation (17).

&Quot; (17) &quot;

The basic matrix and the exponent matrix (or LDPC sequence) of the LDPC code designed in consideration of the above equations (15) to (17) are shown in FIG. 16 to FIG. In the above description, the lifting or exponentiation matrix transformation method in Equation (9) or (16) to (17) is applied to the entire exponent matrix corresponding to the parity check matrix, but the partial matrix . For example, a sub-matrix corresponding to a parity bit of a parity check matrix usually has a special structure for efficient encoding. In this case, the encoding method or the complexity may change due to lifting. Therefore, in order to maintain the same encoding method or the complexity, a lifting method in which lifting is not applied to a partial matrix corresponding to a parity in a parity check matrix in a parity check matrix or an exponent matrix is applied to a partial matrix corresponding to an information bit, Other lifting can be applied. In other words, the lifting scheme applied to the sequence corresponding to the information bits in the exponent matrix and the lifting scheme applied to the sequence corresponding to the parity bits can be set differently. In some cases, a part of the sequence corresponding to the parity bit or In all, no lifting is applied and fixed values can be used without transforming the sequence.

An example of a basic matrix or an exponent matrix corresponding to a parity check matrix of an LDPC code designed using the QC LDPC code design method proposed by the present invention based on Equations (15) to (17) Respectively. (Note that empty blocks in the basic matrix and exponent matrix of FIGS. 16 to 24 represent portions corresponding to the zero matrix of ZxZ size.) In some cases, empty blocks in the basic matrix of FIG. Empty blocks in the exponent matrix of Figs. 17 to 24 can also be expressed by a specified value such as -1). Exponential matrices of the LDPC codes shown in Figs. 17 to 24 have the same basic matrix.

16 to 24 are diagrams showing a basic matrix or a LDPC exponent matrix of 42x52 size. Also, in each exponent matrix, the partial matrix consisting of the above five rows and the first 15 columns does not have a column of degree 1. That is, the parity check matrix that can be generated by applying lifting from the partial matrix means that there is no column or column block with degree 1.

16A and 16B are enlarged views of the exponent matrix of FIG. 16 corresponds to the matrix of the drawing corresponding to the reference numerals shown in the respective parts. Therefore, one basic matrix can be constructed by combining Figs. 16A to 16B.

17A to 17B are enlarged views of the exponent matrix shown in FIG. 17 by dividing the exponent matrix. 17 corresponds to the matrix of the drawing corresponding to the reference numerals shown in the respective parts. Therefore, one exponent matrix or an LDPC sequence can be constructed by combining Figs. 17A to 17B. Similarly, FIGS. 18 to 24 are enlarged views of respective exponent matrices.

The other features of the exponent matrix shown in FIG. 16 to FIG. 24 are that all of the 16th column to the 52nd column have a degree of 1. That is, a basic matrix or exponent matrix of 37x52 size composed of the 6th to 42nd rows of the exponent matrices corresponds to a single parity-check code.

The exponential matrices shown in FIG. 17 to FIG. 24 correspond to the LDPC codes designed in consideration of the block size group defined in Equation (15), respectively. However, it is not necessary to support all block sizes included in the block size group according to the requirements of the system. As a result, the exponential matrices shown in FIGS. 17 to 24 can not only support the block sizes corresponding to the block size group (set) defined in Equation (15) but also have a block size corresponding to a subset of each group .

In addition, the basic matrix and exponential matrix shown in FIGS. 16 to 24 may be used as they are, or only a part of them may be used. For example, a new exponent matrix is generated by concatenating a 7x17 size sub-matrix composed of 7 rows and 17 columns from the basic matrix and exponent matrices shown in FIGS. 16 to 24 and another exponent matrix of 35x52 size So that LDPC encoding and decoding can be applied.

Likewise, in the basic matrix and exponent matrix shown in Figs. 16 to 24, a 35x52 size sub-matrix composed of the 8th row to the last row and the 1st row to the 52nd row is concatenated with another sub-matrix of 7x17 size, Matrix can be generated to perform LDPC encoding and decoding.

Generally, a partial matrix formed by appropriately selecting rows and columns in the basic matrix of FIG. 16 may be applied as a new basic matrix to perform LDPC encoding and decoding. Likewise, LDPC coding and decoding may be performed by applying a partial matrix formed by selecting row blocks and column blocks appropriately in the exponent matrix of Figs. 17 to 24 as a new exponent matrix.

Generally, LDPC codes can be controlled by applying puncturing of codeword bits according to the coding rate. When the LDPC code based on the basic matrix or the exponent matrix shown in FIG. 16 to FIG. 24 is punctured with a parity bit corresponding to a column of degree 1, the LDPC decoder can perform decoding without using the corresponding part in the parity check matrix The decoding complexity is reduced. However, when coding performance is considered, there is a method of improving the performance of the LDPC code by adjusting the puncturing order of the parity bits or the transmission order of the generated LDPC codeword.

For example, if the information bits corresponding to the first two columns out of the basic matrix or exponent matrix corresponding to FIG. 16 to FIG. 24 are punctured and all the parity bits having the degree 1 corresponding to the 18th column to the 52nd column are punctured The LDPC codeword with a coding rate of 10/15 can be transmitted. Generally, performance may be further improved by appropriately applying rate matching after generating an LDPC codeword using the basic matrix and exponent matrix corresponding to FIGS. 16 to 24 above. Of course, considering the rate matching, the order of the columns in the basic matrix or the exponent matrix may be appropriately rearranged and applied to LDPC coding and decoding.

Generally, the LDPC coding process first determines a size of an input bit (or a code block) to which LDPC coding is to be applied, determines a block size (Z) to which the LDPC coding is applied according to the size, Determines an LDPC exponent matrix or a sequence, and then performs LDPC encoding based on the block size (Z) and the determined exponent matrix or LDPC sequence. At this time, the LDPC exponent matrix or the sequence may be applied to the LDPC encoding without conversion, and the LDPC exponent matrix or the sequence may be appropriately converted according to the block size Z to perform LDPC encoding.

Similarly, the LDPC decoding process determines an input bit (or a code block) size for the transmitted LDPC codeword, then determines a block size (Z) to which LDPC decoding is applied according to the size, And then performs LDPC decoding based on the block size (Z) and the determined exponent matrix or LDPC sequence. At this time, the LDPC exponent matrix or sequence may be applied to the LDPC decoding without conversion, and if necessary, the LDPC exponent matrix or the sequence may be appropriately converted according to the block size Z to perform LDPC decoding.

The basic matrix shown in FIG. 16 can be expressed in various forms. For example, the basic matrix shown in FIG. 16 may be expressed using a sequence such as the following equations (18) to (21).

Equation (18) shows the position of the element 1 in each sub-matrix of 42x52 size in the basic matrix of FIG. For example, in Equation (18), the second value 6 of the second sequence means that element 1 exists in the sixth column of the second matrix in the basic matrix. (In the above example, the order of the elements in the sequence and the matrix is regarded as starting from 0.)

The expression (19) represents the position of the element 1 in each column in the 42x52 size submatrix in the basic matrix of FIG. For example, the third value 10 of the third sequence in Equation (18) means that there is an element 1 in the tenth row of the third column in the basic matrix. (In the above example, the order of the elements in the sequence and the matrix is regarded as starting from 0.)

&Quot; (18) &quot;

0 2 3 4 5 6 7 9 10 11

0 1 8 11 12

0 1 6 8 9 10 12 13

0 2 3 4 5 7 8 9 13 14

0 2 3 4 5 6 7 10 14

0 1 10 15

0 1 6 9 10 16

1 3 4 9 17

0 1 2 8 10 18

0 5 6 19

0 1 7 12 20

1 2 6 21

0 4 7 10 22

0 1 3 23

0 5 8 10 24

0 4 12 25

1 2 8 26

0 1 9 14 27

0 3 12 28

1 8 14 29

1 5 12 30

0 6 9 31

1 4 14 32

0 13 33

1 12 14 34

0 5 8 35

4 14 36

1 2 12 37

0 3 38

1 7 13 39

8 10 12 40

1 3 7 41

6 10 12 42

1 5 43

2 9 12 44

1 13 45

2 4 12 46

1 6 7 8 47

0 4 48

12 13 14 49

1 10 50

3 8 12 51

&Quot; (19) &quot;

0 3 4 7 13 18 28 31 41

0 3 4 7 12 15 22 26 36 38

0 3 4 9 14 20 25 33

0 2 4 6 9 11 21 32 37

0 3 4 10 12 29 31 37

1 2 3 8 14 16 19 25 30 37 41

0 2 3 6 7 17 21 34

0 2 4 5 6 8 12 14 30 32 40

0 1

1 2 10 15 18 20 24 27 30 32 34 36 39 41

2 3 23 29 35 39

3 4 17 19 22 24 26 39

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

When there is a specific rule in the basic matrix of FIG. 16 and the position of the column of degree 1, information on the position can be omitted as shown in the following Equation 20 and Equation 21, respectively. Of course, it is assumed that the transmitting device and the receiving device know the specific rule.

If the basic matrix or a part of the exponent matrix has a certain rule, the basic matrix or the exponent matrix may be expressed more simply. For example, in a case where a diagonal from the 15th column block to the last column block is diagonal like the basic matrix or exponent matrix shown in FIGS. 16 to 24, the positions of the elements and their exponent values are omitted, .

As an example, the following equations (20) and (21) are examples in which the positions of the elements 1 from the 15th column block to the last column block in the equations (18) and (19) are omitted.

&Quot; (20) &quot;

0 2 3 4 5 6 7 9 10 11

0 1 8 11 12

0 1 6 8 9 10 12 13

0 2 3 4 5 7 8 9 13 14

0 2 3 4 5 6 7 10 14

0 1 10

0 1 6 9 10

1 3 4 9

0 1 2 8 10

0 5 6

0 1 7 12

1 2 6

0 4 7 10

0 1 3

0 5 8 10

0 4 12

1 2 8

0 1 9 14

0 3 12

1 8 14

1 5 12

0 6 9

1 4 14

0 13

1 12 14

0 5 8

4 14

1 2 12

0 3

1 7 13

8 10 12

1 3 7

6 10 12

1 5

2 9 12

1 13

2 4 12

1 6 7 8

0 4

12 13 14

1 10

3 8 12

&Quot; (21) &quot;

0 3 4 7 13 18 28 31 41

0 3 4 7 12 15 22 26 36 38

0 3 4 9 14 20 25 33

0 2 4 6 9 11 21 32 37

0 3 4 10 12 29 31 37

1 2 3 8 14 16 19 25 30 37 41

0 2 3 6 7 17 21 34

0 2 4 5 6 8 12 14 30 32 40

0 1

1 2 10 15 18 20 24 27 30 32 34 36 39 41

2 3 23 29 35 39

3 4 17 19 22 24 26 39

The expression (21) represents each element value in each exponent matrix in the exponent matrix of 42x52 size in the exponent matrix of FIG. For example, the second value 56 of the second sequence in Equation (22) means that the value of the second element of the second row in the exponent matrix is 56, which means that parity The index of the cyclic permutation matrix corresponding to the second row block and the sixth column block in the check matrix is 56.

The exponent matrix may be expressed more simply when a certain rule is applied to a part of the exponent matrix. For example, in a case where a diagonal from the 15th column to the last column block is diagonal like the exponent matrix shown in FIGS. 17 to 24, it is assumed that the exponent values are omitted and the corresponding rule is known.

For example, the following equation (23) is an example in which the exponent 0 value is omitted from the 15th column block to the last column block.

&Quot; (22) &quot;

157 77 187 94 180 112 163 155 1 0

10 24 17 0 0

24 104 56 88 46 0 0 0

69 11 14 92 53 88 66 26 0 0

18 102 173 45 112 168 45 1 0

157 101 135 0

188 91 185 98 175 0

79 24 86 107 0

150 36 129 107 106 0

110 76 189 0

147 16 151 186 0

24 64 100 0

74 185 67 89 0

88 58 181 0

29 47 63 34 0

189 172 85 0

73 21 145 0

125 112 120 37 0

3 10 98 0

9 154 58 0

136 84 5 0

118 89 147 0

98 100 161 0

37 143 0

131 138 157 0

118 41 87 0

188 146 0

190 15 12 0

112 180 0

41 191 76 0

139 33 132 0

110 8 127 0

102 4 69 0

150 92 0

82 146 14 0

51 41 0

154 83 48 0

61 2 165 81 0

151 132 0

63 152 86 0

0 151 0

79 144 33 0

&Quot; (22) &quot;

157 77 187 94 180 112 163 155 1 0

10 24 17 0 0

24 104 56 88 46 0 0 0

69 11 14 92 53 88 66 26 0 0

18 102 173 45 112 168 45 1 0

157 101 135

188 91 185 98 175

79 24 86 107

150 36 129 107 106

110 76 189

147 16 151 186

24 64 100

74 185 67 89

88 58 181

29 47 63 34

189 172 85

73 21 145

125 112 120 37

3 10 98

9 154 58

136 84 5

118 89 147

98 100 161

37 143

131 138 157

118 41 87

188 146

190 15 12

112 180

41 191 76

139 33 132

110 8 127

102 4 69

150 92

82 146 14

51 41

154 83 48

61 2 165 81

151 132

63 152 86

0 151

79 144 33

In this way, the basic matrix and the exponent matrix can be expressed in various ways. If the permutation of a column or a row is applied, the positions of the numbers in the sequence or sequence may be appropriately changed in the equations (18) to The same can be expressed.

An example of designing the basic matrix and the exponent matrix through the design method proposed by the present invention will be described with reference to FIG. 25 to FIG. The basic matrix and the exponent matrix shown in FIGS. 25 to 33 are the basic matrix generated on condition that a 22x32 sub-matrix consisting of 22 rows from the top and 32 columns from the top in each basic matrix and exponent matrix is already fixed, and Exponent matrix. That is, the basic matrix of FIG. 25 is an example of a basic matrix designed by extending FIGS. 25A to 25F by designing FIGS. 25G to 25I by applying the design method proposed by the present invention. 26 to 33 are also examples of exponential matrices designed in a manner similar to that of FIG. In this way, even when a basic matrix or a part of the exponent matrix is fixed in advance by a specific matrix or sequence, it can be understood that the basic matrix or exponent matrix can be designed by the method proposed by the present invention.

The basic matrix or exponent matrix of FIGS. 25 to 33 has a size of 42x52, and the empty blocks of the exponent matrix typically correspond to a zero matrix of ZxZ size, and can be expressed by a specific value such as -1.

Basically, each basic matrix and exponent matrices are designed in consideration of the conditions and methods as shown in Equations (15) to (17) above, but need not be limited thereto. For example, it may support a block size (Z) value included in a block size group of Equation (15), but may be applicable to a block size group as shown in Equation (23) A block size value included in the set may be used, or a suitable value may be added to the block size group (set) of Equation (15) or (23).

&Quot; (23) &quot;

Z1 '= {3, 6, 12, 24, 48, 96, 192, 384}

Z2 '= {11, 22, 44, 88, 176, 352}

Z3 '= {5, 10, 20, 40, 80, 160, 320}

Z4 '= {9, 18, 36, 72, 144, 288}

Z5 '= {2, 4, 8, 16, 32, 64, 128, 256}

Z6 '= {15, 30, 60, 120, 240}

Z7 '= {7, 14, 28, 56, 112, 224}

Z8 '= {13, 26, 52, 104, 208}

An exemplary exponent matrix corresponding to a parity check matrix of a QC LDPC code designed based on Equations (15) to (17) or (23) is shown in FIG. 26 to FIG. The exponent matrices of the LDPC codes shown in FIGS. 26 to 33 have the same basic matrix, and the basic matrix is characterized in FIG.

25A to 25I are enlarged views of the basic matrix of the basic matrix shown in Fig. 25 corresponds to the matrix of the drawing corresponding to the reference numerals shown in the respective parts. Therefore, one basic matrix can be constructed by combining Figs. 25A to 25I.

Figs. 26A to 26I are enlarged views of the exponent matrix of Fig. 26 corresponds to the matrix of the figure corresponding to the reference numerals shown in the respective parts. 26A to 26I may be combined to form one exponent matrix. Figs. 27 to 33 show only the portions A, D and G in Fig. The portions B, C, E, F, H and I of Figs. 27 to 33 are the same as the portions B, C, E, F, H and I of Fig. 26b, 26c, 26e, 26f, 26h and 26i. The exponent matrix can be constructed by combining Figures 26A, 26B, 26C, 26E, 26F, 26H and 26i with Figures 27 to 33 as A, D and G portions.

The basic matrix and the exponent matrix shown in FIGS. 25 to 33 are basic matrixes and exponential matrices generated based on a 22x32 partial matrix consisting of 22 rows from the top and 32 columns from the top in each basic matrix and exponent matrix. That is, even when a basic matrix or a part of the exponent matrix is fixed in advance by a specific matrix or sequence, the basic matrix or exponent matrix can be designed by the method proposed by the present invention.

The basic matrix and the exponent matrix shown in FIGS. 25 to 33 can be expressed in various forms. For example, the basic matrix and the exponent matrix shown in FIGS. Equation 24 shows the position of the element 1 in each row in the basic matrix of FIG.

&Quot; (24) &quot;

0 1 2 3 6 9 10 11

0 3 4 5 6 7 8 9 11 12

0 1 3 4 8 10 12 13

1 2 4 5 6 7 8 9 10 13

0 1 11 14

0 1 5 7 11 15

0 5 7 9 11 16

1 5 7 11 13 17

0 1 12 18

1 8 10 11 19

0 1 6 7 20

0 7 9 13 21

1 3 11 22

0 1 8 13 23

1 6 11 13 24

0 10 11 25

1 9 11 12 26

1 5 11 12 27

0 6 7 28

0 1 10 29

1 4 11 30

0 8 13 31

1 2 32

0 3 5 33

1 2 9 34

0 5 35

2 7 12 13 36

0 6 37

1 2 5 38

0 4 39

2 5 7 9 40

1 13 41

2 5 7 8 42

1 12 43

0 3 44

2 5 7 45

1 10 46

2 5 7 47

0 8 12 48

2 5 7 49

0 4 50

2 12 13 51

Equation (25) represents the position of the element 1 in each element in the basic matrix of FIG.

&Quot; (25) &quot;

0 1 2 4 5 6 8 10 11 13 15 18 19 21 23 25 27 29 34 38 40

0 2 3 4 5 7 8 9 10 12 13 14 16 17 19 20 22 24 28 31 33 36

0 3 22 24 26 28 30 32 35 37 39 41

0 1 2 12 23 34

1 2 3 20 29 40

1 3 5 6 7 17 23 25 28 30 32 35 37 39

0 1 3 10 14 18 27

1 3 5 6 7 10 11 18 26 30 32 35 37 39

1 2 3 9 13 21 32 38

0 1 3 6 11 16 24 30

0 2 3 9 15 19 36

0 1 4 5 6 7 9 12 14 15 16 17 20

1 2 8 16 17 26 33 38 41

2 3 7 11 13 14 21 26 31 41

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

If a certain rule can be found for a part of the basic matrix, the basic matrix may be expressed more simply. For example, in a case where a diagonal from the 15th column to the last column as in the basic matrix of FIG. 25 has a diagonal structure, it is possible to omit the position of the element and its element values when it is assumed that the rule is known by the transceiver .

For reference, a part of an information bit is shortened appropriately for an LDPC code that can be generated based on the basic matrix or the exponent matrix shown in FIG. 25 to FIG. 33, and a part of a codeword bit is punctured, Length LDPC coding and decoding. For example, if a shortening is applied to a part of information bits in the basic matrix and exponent matrix shown in FIGS. 25 to 33, the information bits corresponding to the first two columns are always punctured, and if a part of parity is punctured, (Or code block length) and various code rates.

In addition, when the variable information length or the variable code rate is supported using the shortening or zero padding of the LDPC code, the performance of the code can be improved according to the shortening procedure or the shortening method. If the shortening sequence is already set, the coding performance can be improved by rearranging some or all of the given basic matrices accordingly. It is also possible to improve the performance by appropriately determining the size of the block to be applied to the specific information word length (or code block length) or the size of the column block to which the shortening is to be applied.

For example, in FIG. 25 to FIG. 33, ten columns from the beginning correspond to information word bits (or code blocks). When the number of columns required for LDPC coding is Kb, appropriate rules By determining Kb and block size (Z) values, better performance can be obtained.

if (CBS > 640)

Kb = 10;

elseif (CBS> = 576)

Kb = 9;

elseif (CBS> = 200)

Kb = 8;

else

if (CBS is member of [48,96,176,184,192])

Kb = 7;

else

Kb = 6;

end

end

CBS stands for information bit length or code block length. The block size (Z) value can be determined as a minimum value satisfying Z x Kb> = CBS when the K b value is determined as above. For example, Kb and the block size are determined as shown in the following Equation (26).

&Quot; (26) &quot;

CBS = 40 => Kb = 6 => Z = 7

CBS = 48 => Kb = 7 => Z = 7

CBS = 56 => Kb = 6 => Z = 10

CBS = 64 => Kb = 6 => Z = 11

CBS = 72 => Kb = 6 => Z = 12

CBS = 80 => Kb = 6 => Z = 14

CBS = 200 => Kb = 8 => Z = 26

CBS = 640 => Kb = 9 => Z = 72

CBS = 1024 => Kb = 10 => Z = 104

Depending on the system, the basic matrix or exponential matrix shown in FIG. 25 to FIG. 33 may be used as it is, or only a part thereof may be used. For example, a 22x32 LDPC basic matrix different from the partial matrix except a 22x32 submatrix composed of the basic matrix or the upper 22 rows of the respective exponent matrices and the 32 columns from the preceding ones is excluded. Or may be used in an LDPC encoding and decoding method and apparatus based on a new base matrix or exponent matrix in conjunction with an exponent matrix. For example, a new base matrix may be generated by concatenating with the other base matrices using the following 20 sequences as shown in Equation (27) in Equation (24).

&Quot; (27) &quot;

1 2 32

0 3 5 33

1 2 9 34

0 5 35

2 7 12 13 36

0 6 37

1 2 5 38

0 4 39

2 5 7 9 40

1 13 41

2 5 7 8 42

1 12 43

0 3 44

2 5 7 45

1 10 46

2 5 7 47

0 8 12 48

2 5 7 49

0 4 50

2 12 13 51

As another example, it is possible to generate a new basic matrix by concatenating the above 32 sequences and 10 different LDPC basic matrices or LDPC sequences, as shown in the following Equation (28), and the LDPC coding and decoding based on the basic matrix Methods and apparatuses. Note that, as shown in Equation 28, the partial matrix of the basic matrix defined by selecting the 32 upper sequences in Equation 24 is the same as the partial matrix of the basic matrix defined by selecting the upper 32 rows in FIG.

When a new basic matrix is defined using a sequence corresponding to a sub-matrix (or a part of a sequence) of the LDPC basic matrix (or sequence) corresponding to FIG. 25 or (24) It is possible to generate a new exponent matrix by using only the part corresponding to the partial matrix (or a part of the sequence) in the LDPC exponent matrix corresponding to FIG. 26 to FIG.

&Quot; (28) &quot;

0 1 2 3 6 9 10 11

0 3 4 5 6 7 8 9 11 12

0 1 3 4 8 10 12 13

1 2 4 5 6 7 8 9 10 13

0 1 11 14

0 1 5 7 11 15

0 5 7 9 11 16

1 5 7 11 13 17

0 1 12 18

1 8 10 11 19

0 1 6 7 20

0 7 9 13 21

1 3 11 22

0 1 8 13 23

1 6 11 13 24

0 10 11 25

1 9 11 12 26

1 5 11 12 27

0 6 7 28

0 1 10 29

1 4 11 30

0 8 13 31

1 2 32

0 3 5 33

1 2 9 34

0 5 35

2 7 12 13 36

0 6 37

1 2 5 38

0 4 39

2 5 7 9 40

1 13 41

In general, a partial matrix formed by appropriately selecting rows and columns from the basic matrix and the exponent matrix of FIGS. 25 to 33 may be applied to a new basic matrix and exponent matrix, and used in an LDPC encoding and decoding method and apparatus.

While the present invention has been described in terms of preferred embodiments, various changes and modifications may be suggested to those skilled in the art. Such variations and modifications are intended to be included within the scope of the appended claims.

Claims (1)

A channel coding method in a communication or broadcasting system,
Determining an input bit size;
Determining a size (Z) of a block;
Determining an LDPC sequence to perform LDPC encoding;
LDPC coding based on the LDPC sequence and the block size;
Wherein the channel coding method comprises the steps of:

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