JP5171595B2 - Circuit input and circuit state evaluation method and evaluation apparatus - Google Patents

Description

  The present invention relates to a circuit input and circuit state evaluation method and an evaluation apparatus for a circuit having a semiconductor element.

  Conventionally, when an analog operation analysis of an electric circuit or an electronic circuit having a semiconductor element is performed, a circuit simulator such as a SPICE (Simulation Program with Integrated Circuit Emphasis) is used. In this case, the circuit state is evaluated with reference to waveform data or numerical data obtained from the simulation.

However, skill is required to evaluate a circuit state only from waveform data or numerical data. Thus, various methods for visualizing simulation results have been introduced to facilitate evaluation (see, for example, Non-Patent Documents 1 and 2). According to these methods, for example, a cutoff region, a linear region, and a saturation region, which are known as DC characteristics of a MOS (Metal Oxide Semiconductor) transistor, can be visualized. As a result, it is possible to analyze the presence / absence of a failure from the presence / absence of a difference between the operation region of a normal circuit including a MOS transistor without a failure and the operation region at the time of the failure.
Y. Miura, “Analysis of Analog and Mixed-Signal Circuits by an Operation-Region Model,” IEICE Trans. INF. & SYST. , Vol. E85-D, No. 10, pp. 1551-1557 October 2002. Yukiya Miura and Daisuke Kato, “Analysis and Testing of Analog and Mixed-Circuits by an Operation-Region Model: A Case Study. 18th IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 279-286, November 2003.

  However, even with the conventional evaluation method and evaluation apparatus, quantitative evaluation may be difficult depending on the waveform pattern of the circuit input signal. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a circuit input and circuit state evaluation method and an evaluation apparatus that can quantitatively and in detail evaluate the relationship between the circuit input and the circuit state. And

The present invention employs the following means in order to solve the above problems.
The circuit input and circuit state evaluation method according to the present invention calculates an operation state of the semiconductor element based on an input step of applying an input signal to an input terminal of a circuit having the semiconductor element and an output signal from the semiconductor element. A calculation step, a display step for continuously displaying the operation state calculated according to a change amount or an application time of the input signal, and at least a part of the operation state from the operation state for a detailed evaluation. A selection step of selecting according to an algorithm; and a generation step of generating a new input signal for changing the selected operation state.

  The circuit input and circuit state evaluation method according to the present invention is the circuit input and circuit state evaluation method, wherein the target semiconductor element is a field effect transistor, and the operation state is a blocking region of the field effect transistor. , One of a linear region and an operation region consisting of a saturation region.

  The circuit input and circuit state evaluation method according to the present invention is the circuit input and circuit state evaluation method, wherein a DC voltage or a DC current is applied in advance as an input signal to predict an operation state of the semiconductor element. A DC step is provided.

In addition, the circuit input and circuit state evaluation apparatus according to the present invention provides an input unit that applies an input signal to an input terminal of a circuit having a semiconductor element, and an operation state of the semiconductor element based on an output signal from the semiconductor element A calculation unit for calculating, a display unit for continuously displaying the operation state calculated according to the change amount or application time of the input signal, and at least a part of the operation state from the operation state for detailed evaluation. A selection unit that selects according to a certain algorithm, and a generation unit that generates a new input signal that changes the selected operation state are provided.

  The circuit input and circuit state evaluation program according to the present invention includes a computer, an input unit that applies an input signal to an input terminal of a circuit having a semiconductor element, and an output signal from the semiconductor element. The calculation means for calculating the operation state, the display means for continuously displaying the operation state calculated according to the amount of change or the application time of the input signal, and the operation state displayed continuously are selected. It is made to function as a production | generation means which produces | generates the new input signal which changes at least one part operating state.

  According to the present invention, the relationship between circuit input and circuit state can be evaluated quantitatively and in detail.

A first embodiment according to the present invention will be described with reference to FIGS.
As shown in FIG. 1, the circuit input and circuit state evaluation apparatus 1 according to the present embodiment is used, for example, for circuit state evaluation of a transistor circuit 2 having PMOS transistors M11 and M21 and NMOS transistors M12 and M22.

The circuit input and circuit state evaluation apparatus 1 includes an input unit 11 that applies an input voltage (input signal) as a circuit input to an input terminal 10 of a transistor circuit 2, and output voltages from the MOS transistors M11, M12, M21, and M22. Based on the (output signal), the calculation unit 12 that calculates these operation states, the display unit 13 that continuously displays the operation states calculated according to the change amount or application time of the input voltage, and for detailed evaluation The selecting unit 14 that selects at least a part of the operating states from the operating states displayed in accordance with the predetermined algorithm, and the generating unit 15 that generates a new input signal that changes the selected operating state.

  In the transistor circuit 2, the source of the PMOS transistor M <b> 11 is connected to the power supply terminal (VDD), and the gate is connected to the input terminal 10. The source of the NMOS transistor M12 is connected to the ground (GND), and the drain is connected to the drain of the PMOS transistor M11 to constitute the node 20. The source of the PMOS transistor M21 is connected to the power supply terminal (VDD). The source of the NMOS transistor M22 is connected to the ground (GND), and the drain is connected to the drain of the PMOS transistor M21 to constitute a node 25. The drains of the PMOS transistor M11 and NMOS transistor M12 are connected to the gates of the PMOS transistor M21 and NMOS transistor M22.

  Here, in the case of a MOS transistor, the operation state of the transistor is determined from the magnitude relationship among the gate-source voltage (Vgs), the drain-source voltage (Vds), and the threshold voltage (Vt) shown in Table 1. , The cut-off region (C), the linear region (L), or the saturation region (S).

In the case of the transistor circuit 2 according to this embodiment, the NMOS transistor M11 and the PMOS transistor M12, and the NMOS transistor M21 and the PMOS transistor M22 each constitute a CMOS NOT gate. FIG. 2 shows the DC characteristics of the CMOS NOT gate in this case.

  When the transistor is normal, for example, in the region A of FIG. 2, the PMOS transistor is a linear region (L) and the NMOS transistor is a blocking region (C). That is, the PMOS transistor is turned on and the NMOS transistor is turned off. On the contrary, in the E region, the PMOS transistor is a cut-off region (C), and the NMOS transistor is a linear region (L). That is, the PMOS transistor is turned off and the NMOS transistor is turned on.

  On the other hand, the state of the BD area | region of FIG. 2 may also exist. In the B region, the PMOS transistor is a linear region (L), and the NMOS transistor is a saturation region (S). In the C region, all become saturated regions (S). In the D region, the PMOS transistor is a saturation region (S), and the NMOS transistor is a linear region (L). The circuit input and circuit state evaluation method according to this embodiment uses the above-described characteristics of the MOS transistor.

  As shown in FIG. 3, the circuit input and circuit state evaluation method includes an input step (S01) for applying an input voltage to the input terminal 10 of the transistor circuit 2, and outputs from the MOS transistors M11, M12, M21, and M22. A calculation step (S02) for calculating the operating state of each of the MOS transistors M11, M12, M21, and M22 based on the voltage (output signal), and the operating state calculated according to the amount of change or the application time of the input voltage are continuously displayed. A display step (S03) for displaying, a selection step (S04) for selecting at least a part of operation states from the operation states displayed for detailed evaluation according to a certain algorithm, and a new operation for changing the selected operation state Generating step (S05) for generating a simple input signal.

  First, in the input step (S01), as shown in the upper part of FIG. 4, an input voltage that linearly increases with time from 0 to the power supply voltage is applied to the input terminal 10. At this time, the output voltages from the MOS transistors M11, M12, M21, and M22 also change with time.

  In the next calculation step (S02), the operation region corresponding to the input voltage is calculated based on the relationship shown in Table 1 from the magnitude relationship of Vgs, Vds, and Vt in each of the MOS transistors M11, M12, M21, and M22.

  In the display step (S03), as shown in the right stage of FIG. 5, the calculated operation region is continuously displayed in time series.

  Here, the process proceeds to the selection step (S04), and the P region in the right stage of FIG. 5 in which both the MOS transistors M11 and M12 are in the saturation region (S) is selected as a region requiring detailed evaluation by a certain algorithm. The Thereafter, the process proceeds to the generation step (S05).

  In the generation step (S05), in order to actually widen the display range of the P region, an input voltage pattern changed as shown in the lower part of FIG. 4 is generated. Then, by repeating the above steps (S01) to (S03) with respect to this input voltage, a Q region obtained by enlarging the P region is obtained as shown on the left side of FIG.

  When it is necessary to further expand the Q region and evaluate the details, another input voltage is generated in the selection step (S04) and the generation step (S05).

  Thus, by generating and applying the input voltage shown in the lower part of FIG. 6 to the input voltage shown in the upper part of FIG. 6, the operation region display of each MOS transistor M11, M12, M21, M22 is also shown in FIG. As shown, the right Q region is enlarged and changed to the left R region. In this state, the circuit state is evaluated. On the other hand, if there is no need for detailed evaluation based on a certain algorithm, the process ends after the selection step (S04).

  According to this circuit input and circuit state evaluation method and apparatus, the operating state of each of the MOS transistors M11, M12, M21, and M22 is continuously displayed according to the amount of change or application time of the input voltage. Is easier to understand visually. Then, by applying a new input voltage, it is possible to change at least a part of operation states selected for detailed evaluation, and to easily compare before and after the change. Therefore, the relationship between the circuit input and the circuit state can be evaluated quantitatively and in detail.

  In particular, in the case of a MOS transistor, a cutoff region (C) and a linear region (L) are obtained from the relationship between the gate-source voltage Vds, the drain-source voltage Vgs, and the threshold voltage Vt as shown in Table 1. ), The saturation region (S) can be calculated, and the circuit state can be evaluated in the cutoff region (C), the linear region (L), and the saturation region (S).

Next, a second embodiment of the present invention will be described with reference to FIGS.
The circuit input and circuit state evaluation apparatus according to the present embodiment is the same as the apparatus 1 according to the first embodiment.

On the other hand, the difference between the circuit input and circuit state evaluation method according to this embodiment and the first embodiment is that the circuit input and circuit state evaluation method according to this embodiment uses a DC voltage or a DC current as an input signal in advance. A DC step (ST1) for applying and predicting the operating state of the semiconductor element is further provided.

  The circuit evaluated in this embodiment is, for example, a Schmitt trigger circuit 30 shown in FIG. The Schmitt trigger circuit 30 includes PMOS transistors M31, M33, M35, and NMOS transistors M32, M34, M36.

The source of the PMOS transistor M31 is connected to the power supply terminal (VDD), and the gate is connected to the input terminal 40. The source of the NMOS transistor M32 is connected to the ground (GND), and the drain is connected to the drain of the PMOS transistor M31 to form a node 50. The gate of the PMOS transistor M33 is connected to the output node 60, and the source is connected to the power supply terminal (VDD). The gate of the NMOS transistor M34 is connected to the output node 60, and the source is connected to the ground (GND). The drain of the PMOS transistor M33 and the drain of the NMOS transistor M34 are connected to the gates of the PMOS transistor M35 and the NMOS transistor M36. The source of the PMOS transistor M35 is connected to the power supply terminal (VDD), and the drain is connected to the gate of the PMOS transistor M33 via the output node 60. The source of the NMOS transistor M36 is connected to the ground (GND), the drain is connected to the drain of the PMOS transistor M35, and further serves as an output node 60.

  In this circuit input and circuit state evaluation method, as shown in FIG. 9, a DC step is performed in which a DC voltage is applied in advance as an input voltage to predict the operation state of each of the MOS transistors M31, M32, M33, M34, M35, and M36. (ST1) and, similarly to the first embodiment, an input step (S01) for applying an input voltage to the input terminal 40 of the transistor circuit 30, and from each of the MOS transistors M31, M32, M33, M34, M35, M36 A calculation step (S02) for calculating an operation state based on the output voltage (output signal), a display step (S03) for continuously displaying the operation state calculated according to the change amount or the application time of the input voltage, A selection step (S) of selecting at least a part of the operation states displayed for the detailed evaluation according to a certain algorithm And 4), and a generating step of generating a new input signal for changing the selected operating state (S05), the. In the DC step (ST1), a DC current may be input instead of a DC voltage depending on the transistor circuit.

  In the DC step (ST1), the input voltage linearly increasing from 0 to the power supply voltage as shown in FIG. 10A is applied to the input terminal 40 in the input step (S01) similar to the first embodiment. To do. Then, the same calculation step (S02) and display step (S03) as those in the first embodiment are performed, and as shown in FIG. 10 (b), each of the MOS transistors M31, M32, M33, M34, M35, M36. The operation area obtained from the output voltage of the current is displayed.

Similarly, an input voltage that linearly increases from the power supply voltage to 0 is applied to the input terminal 40 as shown in FIG. Similarly, the calculation step (S02) and the display step (S03) are carried out, and as shown in FIG. 11 (b), obtained from the output voltages of the MOS transistors M31, M32, M33, M34, M35, and M36. Display the active area. Thus, the relationship between the input voltage in the input step (S01) and the output voltages of the MOS transistors M31, M32, M33, M34, M35, and M36 at this time is grasped in advance.

  Thereafter, the input step (S01), the calculation step (S02), the display step (S03), the selection step (S04), and the generation step (S05) are performed as in the first embodiment. In this way, by changing the input voltage as shown from the upper stage to the lower stage of FIG. 12, the details of the circuit state are evaluated in the T1 and T2 regions, which are enlarged S1 and S2 regions, as shown in FIG.

  According to this circuit input and circuit state evaluation method and apparatus, not only the same effects as in the first embodiment but also what output voltage can be obtained by what input voltage to the MOS transistor is grasped in advance. I can keep it. Therefore, evaluation can be performed efficiently.

The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.
For example, the transistor is not limited to the MOS type but may be a bipolar type. In addition to the transistor, other semiconductor elements such as a diode and a resistor may be used. Further, the input signal and the output signal are not limited to voltage but may be current, and the circuit may be either a digital circuit or an analog circuit.

  It is also possible to record a program for realizing a circuit input and circuit state evaluation method and apparatus on a computer-readable recording medium and execute the program recorded on the recording medium.

1 is a block diagram of a circuit input and circuit state evaluation apparatus and an evaluation target circuit according to a first embodiment of the present invention. It is explanatory drawing which shows the operation area | region of the MOS transistor in the circuit input and circuit state evaluation method and apparatus concerning the 1st Embodiment of this invention. It is a flowchart which shows the circuit input and circuit state evaluation method which concern on the 1st Embodiment of this invention. 5 is a graph showing respective input voltages initially and newly generated in the circuit input and circuit state evaluation method and apparatus according to the first embodiment of the present invention. It is a graph which shows the result of having calculated the operation area from the output voltage of the MOS transistor in the circuit input and circuit state evaluation method and device concerning a 1st embodiment of the present invention. 5 is a graph showing respective input voltages initially and newly generated in the circuit input and circuit state evaluation method and apparatus according to the first embodiment of the present invention. It is a graph which shows the result of having calculated the operation area from the output voltage of the MOS transistor in the circuit input and circuit state evaluation method and device concerning a 1st embodiment of the present invention. It is a block diagram of an evaluation object circuit in a circuit input and circuit state evaluation method and device concerning a 2nd embodiment of the present invention. It is a flowchart which shows the circuit input and circuit state evaluation method which concern on the 2nd Embodiment of this invention. In the circuit input and circuit state evaluation method and apparatus concerning a 2nd embodiment of the present invention, it is a graph which shows each input voltage after the beginning and newly generated. It is a graph which shows the result of having calculated the operation area from the output voltage of the MOS transistor in the circuit input and circuit state evaluation method and device concerning a 2nd embodiment of the present invention. In the circuit input and circuit state evaluation method and apparatus concerning a 2nd embodiment of the present invention, it is a graph which shows each input voltage after the beginning and newly generated. It is a graph which shows the result of having calculated the operation area from the output voltage of the MOS transistor in the circuit input and circuit state evaluation method and device concerning a 2nd embodiment of the present invention.

Explanation of symbols

1 Circuit input and circuit state evaluation device 2, 30 Transistor circuit (circuit)
DESCRIPTION OF SYMBOLS 11 Input part 12 Calculation part 13 Display part 14 Selection part 15 Generation | occurrence | production part M11, M12, M21, M22, M31, M32, M33, M34, M35, M36 MOS transistor (semiconductor element)

Claims (5)

An input step of applying an input signal to an input terminal of a circuit having a semiconductor element;
A calculation step of calculating an operating state of the semiconductor element based on an output signal from the semiconductor element;
A display step for continuously displaying the operation state calculated in accordance with a change amount or an application time of the input signal;
For detailed evaluation, a selection step of selecting an operation state of a predetermined region among the operation states displayed in the display step ;
Generating an input signal having a voltage increase or decrease less than the voltage increase or decrease per time in the input step so as to change the selected operating state;
A circuit input and circuit state evaluation method comprising: The semiconductor element is a field effect transistor;
2. The circuit input and circuit state evaluation method according to claim 1, wherein the operation state is one of an operation region including a cutoff region, a linear region, and a saturation region of the field effect transistor.   3. The circuit input and circuit state evaluation method according to claim 1, further comprising a DC step of predicting an operation state of the semiconductor element by previously applying a DC voltage or a DC current as an input signal. An input unit for applying an input signal to an input terminal of a circuit having a semiconductor element;
A calculation unit for calculating an operation state of the semiconductor element based on an output signal from the semiconductor element;
A display unit that continuously displays the operation state calculated according to the change amount or application time of the input signal;
A selection unit for selecting an operation state of a predetermined region among the operation states displayed in the display step for detailed evaluation;
Generation of generating an input signal having a voltage increase / decrease amount smaller than the voltage increase / decrease amount per time of the input signal first input at the input unit so as to change the selected operation state And
A circuit input and circuit state evaluation apparatus comprising: Computer
Input means for applying an input signal to an input terminal of a circuit having a semiconductor element;
Calculation means for calculating an operating state of the semiconductor element based on an output signal from the semiconductor element;
Display means for continuously displaying the operation state calculated according to the amount of change or application time of the input signal;
A selection means for selecting an operation state of a predetermined region among the operation states displayed in the display step for detailed evaluation;
In order to change at least a part of the operation states selected from the continuously displayed operation states, the voltage is more than the voltage increase / decrease amount per time in the input signal first input by the input means. Generating means for generating a new input signal with a small increase or decrease ; and
Circuit input and circuit state evaluation program, characterized in that

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