JP5169749B2 - Signal converter - Google Patents

Description

  The present invention relates to a signal converter for converting an analog signal into a digital signal.

  The signal converter converts the input analog signal into a digital signal according to the sampling clock. In order to accurately sample the input signal, it is necessary to sample at a sampling frequency that is at least twice the maximum frequency component included in the analog signal according to the sampling theorem. The higher the sampling frequency, the greater the power consumption of the signal conversion device.

  Depending on the nature of the input analog signal, a high-frequency signal component is unnecessary. Therefore, a filter circuit is used to cut unnecessary high frequency components. By cutting unnecessary high frequency components using a filter circuit, the sampling frequency can be lowered.

  However, there are manufacturing variations in filter circuits. For this reason, aliasing noise occurs when the sampling frequency is too low based on the design value of the filter circuit.

The following patent documents disclose a technique for sampling an input signal after it is processed by a filter circuit.
JP 2004-96141 A JP 2006-319571 A

  An object of an embodiment of the present invention is to provide a signal converter that optimizes a sampling frequency while suppressing generation of aliasing noise even if there is a manufacturing variation in a filter circuit.

  In order to solve the above-described problem, a signal conversion device including a filter circuit that filters an input signal and an analog-digital conversion unit that samples an output signal from the filter circuit with a sampling clock and converts the sampled signal into a digital signal. A filter characteristic measuring circuit for measuring a frequency characteristic of the circuit, and a sampling clock generating unit for generating the sampling clock having a frequency determined based on the frequency characteristic of the filter circuit.

  According to the embodiment, it is possible to provide a signal conversion device that optimizes the sampling frequency while suppressing the occurrence of aliasing noise even if the filter circuit has manufacturing variations.

  Hereinafter, this embodiment will be described. The following embodiments can also be realized by processing a program by a processor. Combinations of configurations in the embodiments are also included in the embodiments of the present invention.

[Signal converter]
FIG. 1 is a block diagram showing an example of the configuration of the signal conversion apparatus 100 according to the present embodiment. The signal conversion apparatus 100 includes a reception unit 101, a filter circuit 102, an analog / digital conversion unit 103, a filter characteristic detection unit 2, a sampling clock generation unit 107, and a switch 108. The filter characteristic measuring circuit 2 detects the frequency characteristic of the filter circuit 102 by inputting the test signal 13 to the filter circuit 102 and detecting the output signal 11 which is the test signal output from the filter circuit 102. The sampling clock generation unit 107 controls the frequency of the sampling clock based on the frequency characteristic of the filter circuit detected by the filter characteristic measurement circuit 2. The filter characteristic detection unit 2 includes a control unit 106, a signal generation unit 104, and a level detection unit 105.

  The receiving unit 101 amplifies the amplitude of the received input signal with an amplifier or lowers the frequency of the received signal with a mixer. The receiving unit 101 outputs the processed received signal 10 to the filter circuit 102. The filter circuit 102 extracts only frequency components necessary for data transmission / reception from the reception signal 10. By processing the received signal 10 with the filter circuit 102, it is possible to eliminate the influence of an interference wave and an aliasing effect that interfere with data communication. Specific examples of the filter circuit 102 include a Butterworth filter, a Chebyshev filter, and an elliptic filter. The analog-digital conversion unit 103 samples the output signal 11 output from the filter circuit 102 with a sampling clock 16 having a specific sampling frequency, and converts it into a digital signal.

  The signal generation unit 104 gradually changes the frequency of the test signal 13 input to the filter circuit 102. The signal generator 104 outputs a test signal 13 having a frequency corresponding to the voltage value of the input control signal 12. The signal generation unit 104 gradually decreases the frequency of the test signal 13 to be output in accordance with the decrease in the voltage value of the input control signal 12. The signal generator 104 can realize its function by using, for example, a voltage controlled oscillator (VCO). The initial frequency of the test signal 13 output from the signal generation unit 104 is ½ of the sampling frequency of the analog-digital conversion unit 103 that is initially set in the control unit 106.

  The level detection unit 105 outputs a detection signal 14 corresponding to the voltage value of the other signal with respect to the voltage value of one signal. The level detection unit 105 receives the test signal 13 output from the signal generation unit 104 as one input. The level detection unit 105 uses the output signal 11 when the test signal 13 is input to the filter circuit 102 as the other input. The level detector 105 compares the amplitudes of the input test signal 13 and the output signal 11. The level detection unit 105 outputs a detection signal 14 having a logical value “0” when the amplitude ratio of the output signal 11 to the test signal 13 is larger than a predetermined value provided in the level detection unit 105. The level detection unit 105 outputs a detection signal 14 having a logical value “1” when the amplitude ratio of the output signal 11 to the test signal 13 becomes a predetermined value or less. Here, the predetermined value is set based on the filter characteristics of the filter circuit 102. That is, the ratio of the output signal to the input signal of the filter circuit when the signal passing through the filter circuit 102 is attenuated to an extent that suppresses the occurrence of aliasing noise is set to a predetermined value.

  The control unit 106 gradually changes the voltage value of the control signal 12 to be output. The control unit 106 fixes the voltage value of the control signal 12 output when the logic of the detection signal 14 output from the level detection unit 105 changes. The sampling clock generation unit 107 receives the control signal 12 having the same voltage value as the control signal 12 input to the signal generation unit 104 and outputs a sampling clock 16 having a frequency twice or more the frequency of the test signal 13.

  The sampling clock generation unit 107 can realize its function using, for example, a VCO. The mode signal 1 is a signal for switching the operation mode of the signal conversion apparatus 100 to either a normal mode for digitally converting a received signal or a test mode for detecting a minimum frequency at the time of digital conversion. The control unit 106 transmits a switch control signal 15 to the switch 108 according to the mode signal 1 to connect the signal generation unit 104 and the filter circuit 102. The control unit 106 gradually decreases the voltage value of the control signal 12 output to the signal generation unit 104.

  The controller 106 stores the voltage value of the control signal 12 immediately before the logic of the detection signal 14 changes. The control unit 106 outputs the stored voltage value of the control signal 12 to the sampling clock generation unit 107. The sampling clock generation unit 107 receives the same control signal 12 as the control signal 12 input to the signal generation unit 104 and outputs a signal having a frequency twice that of the signal generation unit 104. The sampling clock generation unit 107 supplies the sampling clock 16 having a frequency corresponding to the stored voltage value of the control signal 12 to the analog / digital conversion unit 103. Further, after the test operation is completed, the control unit 106 switches the switch 108 according to the mode signal 1 to connect the receiving unit 101 and the filter circuit 102.

  From the above, it is possible to provide the signal conversion apparatus 100 that optimizes the sampling frequency while suppressing the occurrence of aliasing noise even if the filter circuit 102 has manufacturing variations. Further, by optimizing the sampling frequency of the analog / digital conversion unit 103, the power consumption of the signal conversion device 100c can be suppressed.

[Filter characteristics]
FIG. 2 shows the frequency characteristics of the filter circuit 102. In FIG. 2, the horizontal axis indicates the frequency, the vertical axis indicates the attenuation, and the curve 203 indicates an example of the frequency characteristic obtained by actually measuring the attenuation of the output with respect to the input of the filter circuit 102 for each frequency. Here, as a required performance specification of the signal conversion apparatus 100, it is assumed that an upper limit frequency of a frequency band (hereinafter referred to as an effective frequency band) for accurately digitizing an input original analog signal is fp. The filter circuit 102 provides a small amount of attenuation that is almost flat so as not to distort the low frequency component (effective frequency band) of the frequency fp or less with respect to the input original analog signal. On the other hand, a high frequency component having a frequency of fp or higher is not necessary in specification even if it is included in the original analog signal. Therefore, it is desirable that the filter circuit 102 has a low-pass filter characteristic that removes high-frequency components higher than fp.

  In order to completely include the effective frequency band component up to the frequency fp of the original analog signal in the sampled and digitized signal and to reproduce the original analog signal component, it is necessary to perform sampling at a sampling frequency of at least 2 fp. Known as sampling theorem. However, if the original analog signal includes a high-frequency component exceeding fp, when sampling is performed at 2 fp, the high-frequency component exceeding fp is turned back to the low frequency side when viewed from the frequency fp. This folded high-frequency component is mixed in the sampled signal component as alias noise. The actual filter circuit 102 does not completely cut off frequency components above the upper limit frequency fp, and has a characteristic that the attenuation gradually increases as the frequency increases. Therefore, when the sampling frequency is 2 fp, a high frequency component of fp or more of the original analog signal is attenuated by the filter circuit 102 in the effective frequency band of fp or less, but is mixed as alias noise, Sampling and digitization processing signals will be degraded. The degree of signal degradation depends on the amount of attenuation in the filter circuit 102, and the allowable limit is determined as a required performance specification for the signal converter 100.

  In order to reduce the signal deterioration due to alias noise to an allowable limit, a frequency that allows the filter circuit 102 to attenuate the high-frequency component in the original analog signal to the allowable limit is estimated in advance and set to a sampling frequency higher than 2fp. If the allowable limit is, for example, −80 dB, a frequency f1 (FIG. 2) that can ensure attenuation of −80 dB by the filter circuit 102 is determined in advance, and if the sampling frequency is 2f1, alias noise into the effective frequency band. The mixing amount can guarantee -80 dB or less. In this case, the original signal components of fp to f1 outside the effective frequency band remain in the signal after sampling and digitization processing by the amount attenuated by the filter circuit 102. However, such residual components have little real harm compared to the problem of alias noise mixing in the effective frequency component band.

  The frequency f1 that secures the attenuation of −80 dB by the filter circuit 102 is set to a frequency at which the worst frequency characteristic curve 204 caused by the manufacturing variation of the filter circuit 102 takes the attenuation of −80 dB. That is, the frequency f1 in FIG. 2 is a frequency at which the frequency characteristic curve 204 and the line 201 representing the attenuation amount of −80 dB intersect. As described above, if f1 is set, the signal conversion apparatus can ensure attenuation of −80 dB even if there is a manufacturing variation.

  However, in the vicinity of the frequency f1, the frequency characteristic 203 of FIG. 2 of the actual filter circuit 102 may obtain an attenuation that greatly exceeds -80 dB. The frequency at which the frequency characteristic 203 in FIG. 2 intersects the line 201 representing the attenuation amount of −80 dB is the frequency f2. In this case, if the sampling frequency is 2f1, the alias noise suppression characteristic is excessive quality that greatly exceeds the required specifications.

  In order to satisfy the specification of the allowable limit of alias noise on the premise of the actual measurement characteristic of the filter circuit 102, a frequency equal to or lower than the frequency f2 at which the line 201 indicating the attenuation amount of −80 dB intersects the curve 203 of the actual measurement characteristic of the filter circuit 102. A sampling frequency of 2f2 may be used to sample the band. If it does so, the component more than f2 will attenuate | damp -80dB or more with a filter circuit, and it turns out that it is necessary and sufficient on a specification. If the sampling frequency can be set to 2f2, the operating frequency of the signal conversion device 100 can be lowered by the amount lower than 2f1, and the power consumption can be reduced by that amount.

[Level detector]
FIG. 3 is an example of a circuit diagram of the level detection unit 105. The level detection unit 105 detects that the attenuation amount of the output signal 11 output from the filter circuit 102 with respect to the test signal 13 input to the filter circuit 102 is equal to or greater than an attenuation amount that allows alias noise. In the present embodiment, the test signal 13 and the output signal 11 are differential signals.

  The level detection unit 105 outputs a detection signal 14 having a logical value corresponding to the magnitude relationship between the voltage amplitudes of the two differential signals. The level detection unit 105 includes transistors 400, 401, 402, 403, resistors 404, 405, 406, 407, a current source 408, capacitors 409, 410, and an operational amplifier 411.

  When the output signal 11 is input to the transistors 400 and 401, the resistance values of the transistors 400 and 401 change according to the voltage amplitude of the output signal 11. For this reason, the amplitude of the voltage waveform at the contact 420 is determined by the ratio of the resistance values of the transistors 400 and 401 and the resistor 405 and the current value of the current source 408. The voltage waveform generated at the contact 420 becomes a DC voltage by passing through a low-pass filter composed of a resistor 404 and a capacitor 409. This DC voltage becomes larger as the voltage amplitude of the output signal 11 is larger. The DC voltage that has passed through the low-pass filter becomes one input of the operational amplifier 411 through the wiring 422.

  The test signal 13 is attenuated by an attenuator 500 described later and input to the transistors 402 and 403. The transistors 402 and 403, the resistors 406 and 407, and the capacitor 410 perform the same operations as the transistors 400 and 401, the resistors 404 and 405, and the capacitor 409. As a result, a DC voltage having a value corresponding to the voltage amplitude of the test signal 13 is generated in the wiring 423. The voltage generated in the wiring 423 becomes the other input of the operational amplifier 411. Although the case where the attenuator 500 is used has been described here, the output signal 11 may be amplified by the amplifier 602 and input to the transistors 400 and 401 instead of using the attenuator 500.

  The operational amplifier 411 outputs a logical value “1” or “0” depending on the magnitude relationship between the voltages generated in the wirings 422 and 423. The operational amplifier 411 outputs a logical value “0” when the voltage value generated in the wiring 423 is equal to or lower than the voltage value generated in the wiring 422. The operational amplifier 411 outputs a logical value “1” when the voltage value generated in the wiring 423 is larger than the voltage value generated in the wiring 422. With the above operation, the level detection unit 105 can output the detection signal 14 having a logical value corresponding to the magnitude relationship between the voltage amplitudes of the output signal 11 and the test signal 13.

[Control unit]
FIG. 4 is a detailed block diagram of the control unit 106. When the control unit 106 detects that the attenuation amount of the output signal 11 with respect to the test signal 13 is equal to or greater than an attenuation amount that allows alias noise, the control unit 106 generates the sampling clock 16 having a frequency twice the frequency of the test signal 13. A control signal 12 is output. The control unit 106 includes a switch control unit 300, an arithmetic unit 301, a register 302, a register 303, a counter 304, and a digital analog converter (DAC) 305. In this embodiment, the registers 302 and 303 are 3-bit registers, but the present invention is not limited to this.

  The switch control unit 300 outputs a switch control signal 15 for switching the switch 108 so that the signal generation unit 104 and the filter circuit 102 are connected according to the mode signal 1. The switch control unit 300 sets all the bit values held in the register 302 to “1” by the reset signal 34. The switch control unit 300 switches the switch 306 to the output of the register 302. The DAC 305 outputs a control signal 12 having a voltage value corresponding to the control code 31 output from the register 302 to the signal generation unit 104.

  The switch control unit 300 outputs the clock 30 simultaneously with outputting the switch control signal 15. The switch control unit 300 continues to output the clock 30 while receiving the detection signal 14 having the logical value “0”. The counter 304 receives the clock 30 and counts up. When the count value exceeds a certain number, a signal 33 is output and the count value is returned to zero.

  The filter circuit 102 is usually composed of passive elements such as capacitors and inductors. For this reason, it takes a certain time for the amplitude of the output signal 11 output from the filter circuit 102 to stabilize. The maximum value of the count number provided in the counter 304 is determined so that the time from when the counter 304 is reset to when the signal 33 is output is longer than the time until the amplitude of the output signal 11 of the filter circuit 102 is stabilized. By determining the maximum value of the count number in this way, the level detection unit 105 can obtain the output signal 11 having a stable amplitude. By performing level detection using the output signal 11 with stable amplitude, the level detection unit 105 can perform level detection with higher accuracy.

  The value held in the register 302 is decremented by the arithmetic unit 301 in accordance with the signal 33 output from the counter 304. There is a delay time from when the registers 302 and 303 receive the signal 33 until the register 302 outputs the control code 31. By this delay time, the register 303 can hold the value before the value of the register 302 is decremented.

  When the switch control unit 300 receives the detection signal 14 having the logical value “1”, the switch control unit 300 stops the output of the clock 30. The switch control unit 300 switches the switch 306 to the output of the register 303. Since the output of the counter 304 stops when the output of the clock 30 stops, the value held in the register 303 is fixed. Since the control code 31 output from the register 303 is fixed, the voltage value of the control signal 12 output from the DAC 305 is also fixed. Further, when the switch control unit 300 receives the detection signal of the logical value “1”, the switch control unit 15 switches the switch 108 by the switch control signal 15 to connect the reception unit 101 and the filter circuit 102. With the above operation, the control unit 106 fixes the voltage value of the control signal 12 so as to maintain the frequency of the output signal 11 output from the filter circuit 102 immediately before the logical value of the detection signal changes to “1”. As a result, the control unit 106 can detect the minimum frequency of the filter circuit 102 that is an attenuation amount that suppresses the generation of aliasing noise.

  The sampling clock generation unit 107 generates and outputs a sampling clock 16 based on the control signal 12. The sampling clock generator 107 receives the control signal 12 having a fixed voltage value and outputs a sampling clock 16 having a frequency twice that of the output signal 11. Therefore, it is possible to provide the signal conversion apparatus 100 that optimizes the sampling frequency while suppressing the occurrence of aliasing noise even if the filter circuit 102 has manufacturing variations.

  FIG. 5 represents the relationship between the control code 31 and the frequency of the test signal 13 with two graphs. FIG. 5A shows the relationship between the control code 31 and the voltage value of the control signal 12 that is the output of the DAC 305. FIG. 5B shows the relationship between the voltage value of the control signal 12 and the frequency of the test signal 13 output from the signal generation unit 104.

  5A, the horizontal axis indicates the control code 31, and the vertical axis indicates the voltage value of the control signal 12 output from the DAC 305 when the control code 31 is input. The voltage value of the control signal 12 output from the DAC 305 increases as the value of the control code 31 increases from A in FIG. 5A, since the control code 31 is a digital value, the voltage value of the control signal 12 also changes discretely at a constant interval.

  5B, the horizontal axis indicates the voltage value of the control signal 12, and the vertical axis indicates the frequency of the test signal 13 output from the signal generator 104. The frequency of the test signal 13 output from the signal generation unit 104 increases as the voltage value of the control signal 12 increases from B in FIG. Therefore, from A and B in FIG. 5, the frequency of the test signal 13 output from the signal generator 104 can be gradually lowered by decreasing the value of the control code 31 at regular intervals. Note that it is only necessary that the optimum value of the frequency of the test signal 13 is finally found. Therefore, the voltage value of the control signal 12 may be gradually increased at regular intervals, or the amount of change in the voltage value of the control signal 12 may be reduced as the frequency approaches the optimum value.

[Operation flow of control unit]
FIG. 6 is an operation flow of the control unit 106. By operating the control unit 106 as shown in FIG. 6, it is possible to detect a sampling frequency that minimizes the power consumption of the signal conversion apparatus 100.

  The switch control unit 300 in FIG. 4 switches the switch 108 so that the signal generation unit 104 and the filter circuit 102 are connected according to the logic of the mode signal 1 (S10). The signal generator 104 outputs a test signal 13 having a frequency corresponding to the voltage value of the control signal 12 output from the controller 106 (S11).

  The level detection unit 105 outputs a detection signal 14 having a logical value corresponding to the magnitude relationship between the voltage amplitudes of the test signal 13 before being input to the filter circuit 102 and the output signal 11 processed by the filter circuit 102. When the control unit 106 receives the detection signal 14 having the logical value “0” (S12, NO), the control unit 12 decreases the voltage value of the control signal 12. The frequency of the test signal 13 output from the signal generation unit 104 gradually decreases in accordance with the decrease in the voltage value of the control signal 12 (S13).

  When the control unit 106 receives the detection signal 14 having the logical value “1” (S12, YES), the control unit 106 fixes the voltage value of the control signal 12 to a value immediately before receiving the detection signal 14 having the logical value “1” (S14). ). When the control unit 106 receives the detection signal 14, the switch 108 is switched by the switch control signal 15 to connect the reception unit 101 and the filter circuit 102 (S15).

  With the above processing, the signal conversion apparatus 100 having the control unit 106 tests the filter circuit after manufacturing, and sets the frequency twice as high as the frequency of the signal obtained by the test as the sampling frequency. Accordingly, it is possible to provide the signal conversion apparatus 100 that optimizes the sampling frequency while suppressing the occurrence of aliasing noise even if the filter circuit 102 has manufacturing variations. In addition, by optimizing the sampling frequency of the analog-digital conversion unit 103, the power consumption of the signal conversion device 100 can be suppressed.

  FIG. 7 is a block diagram of the signal conversion device 100a in which the configuration of the signal conversion device 100 is made more specific. 7, the same members as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted. 7 compares the test signal 13 whose voltage amplitude is attenuated by the attenuator 500 and the voltage amplitude of the output signal 11 by the level detection unit 105. When the same control signal 12 is input to the VCOs 600 and 601, the frequency of the sampling clock 16 output from the VCO 600 is set to be twice the frequency of the test signal 13 output from the VCO 601.

  The attenuation amount of the attenuator 500 is set to be equal to the attenuation amount at the frequency f2 in FIG. As the frequency of the output signal 11 decreases, the amplitude of the output signal 11 gradually increases. When the output signal 11 and the test signal 13 after passing through the attenuator 500 have the same amplitude, the logic of the detection signal 14 changes. The control unit 106 fixes the amplitude of the control signal 12 when the logic of the detection signal 14 changes. Since the amplitudes of the test signal 13 and the output signal 11 input to the level detection unit 105 are very small, it is desirable to use a level detection unit 105 with high accuracy of amplitude comparison used in this embodiment.

  At this time, the VCO 600 outputs a sampling clock 16 having a frequency twice that of the test signal 13 output from the VCO 601. As described above, it is possible to provide the signal conversion device 100a that optimizes the sampling frequency while suppressing the occurrence of aliasing noise even if the filter circuit 102 has manufacturing variations. Further, by optimizing the sampling frequency of the analog-digital conversion unit 103, the power consumption of the signal conversion device 100a can be suppressed.

  FIG. 8 is a block diagram of the signal conversion device 100b in which the configuration of the signal conversion device 100 is made more specific. In FIG. 8, the same members as those in FIG. 8 amplifies the output signal 11 by the amplifier 602 instead of attenuating the test signal 13 by the attenuator 500 with respect to the signal converter 100 a of FIG. By providing an amplifier in place of the attenuator, the level detection unit 105 can compare larger voltage amplitudes. Therefore, even if the level detection unit 105 does not have a high amplitude comparison accuracy at a low amplitude, a high level of accuracy can be obtained. Detection is possible.

  The amplification amount of the amplifier 602 is set to be equal to the reciprocal of the attenuation amount at the frequency f2 in FIG. As the frequency of the output signal 11 decreases, the amplitude of the output signal 11 gradually increases. When the amplitudes of the output signal 11 amplified by the amplifier 602 and the test signal 13 become equal, the logic of the detection signal 14 changes. The control unit 106 fixes the amplitude of the control signal 12 when the logic of the detection signal 14 changes.

  At this time, the VCO 600 outputs a sampling clock 16 having a frequency twice that of the test signal 13 output from the VCO 601. As described above, it is possible to provide the signal conversion device 100b that optimizes the sampling frequency while suppressing the occurrence of aliasing noise even if the filter circuit 102 has manufacturing variations. Further, by optimizing the sampling frequency of the analog-digital conversion unit 103, the power consumption of the signal conversion device 100b can be suppressed.

  FIG. 9 is a block diagram of a signal conversion device 100c in which the configuration of the signal conversion device 100 is made more specific. 9, the same members as those in FIG. 8 are given the same reference numerals, and the description thereof is omitted. The signal conversion apparatus 100c of FIG. 9 divides the sampling clock 16 output from the VCO 600 by 1/2, instead of using the VCO 601 that outputs a frequency of 1/2 of the VCO 600, with respect to the signal conversion apparatus 100b of FIG. A peripheral 700 is provided. By providing a frequency divider instead of the VCO, the circuit configuration of the signal conversion device 100c can be simplified as compared with the signal conversion device 100b.

  The amplification amount of the amplifier 602 is set so that when the amplitude of the output signal 11 amplified by the amplifier 602 becomes equal to the amplitude of the test signal 13, the frequency of the output signal 11 becomes the minimum frequency at which no aliasing noise occurs. As the frequency of the output signal 11 decreases, the amplitude of the output signal 11 gradually increases. When the amplitudes of the output signal 11 amplified by the amplifier 602 and the test signal 13 become equal, the logic of the detection signal 14 changes. The control unit 106 fixes the amplitude of the control signal 12 when the logic of the detection signal 14 changes.

  At this time, the VCO 600 outputs a sampling clock 16 having a frequency twice that of the test signal 13 output from the frequency divider 700. As described above, it is possible to provide the signal conversion device 100c that optimizes the sampling frequency while suppressing the occurrence of aliasing noise even if the filter circuit 102 has manufacturing variations. Further, by optimizing the sampling frequency of the analog / digital conversion unit 103, the power consumption of the signal conversion device 100c can be suppressed.

The above processing can also be realized by processing a program by a processor.

It is a block diagram of a signal converter. It is a frequency characteristic figure of the voltage gain of a filter circuit. It is a circuit diagram of a level detection part. It is a block diagram of a control part. A in the figure is a relationship diagram between the control code and the voltage value of the control signal. B in the figure is a relationship diagram between the voltage value of the control signal and the frequency of the test signal. It is an operation | movement flowchart of a switch control part. It is a block diagram of a signal converter. It is a block diagram of a signal converter. It is a block diagram of a signal converter.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Mode signal 2 Filter characteristic measuring circuit 11 Output signal 12 Control signal 13 Test signal 14 Detection signal 15 Switch control signal 16 Sampling clock 30 Clock 31 Control code 34 Reset signal 100 Signal converter 100a Signal converter 101 Receiver 102 Filter circuit 103 Analog to digital conversion unit 104 Signal generation unit 105 Level detection unit 106 Control unit 107 Sampling clock generation unit 108 Switch 201 Line 203 Curve 300 Switch control unit 301 Calculation unit 302, 303 Register 304 Counter 305 DAC
306 Switch 400, 401, 402, 403 Transistor 404, 405, 406, 407 Resistor 408 Current source 409, 410 Capacitor 411 Operational amplifier 420 Contact 422, 423 Wiring 500 Attenuator 600, 601 VCO
602 Amplifier 700 Divider

Claims (4)

In a signal converter comprising a filter circuit for filtering an input signal, and an analog-digital converter for sampling an output signal from the filter circuit with a sampling clock and converting the sampled signal into a digital signal,
A filter characteristic measuring circuit for measuring the frequency characteristic of the filter circuit;
A signal conversion apparatus comprising: a sampling clock generation unit configured to generate the sampling clock having a frequency determined based on the frequency characteristic of the filter circuit.   2. The signal conversion apparatus according to claim 1, wherein the filter characteristic measuring circuit inputs a test signal to the filter circuit and measures the frequency characteristic by comparing the test signal with an output signal of the filter circuit. .   The filter characteristic test circuit changes the frequency of the test signal input to the filter circuit, and determines the sampling clock based on the frequency when the attenuation amount of the output signal of the filter circuit becomes a predetermined value or less. The signal conversion apparatus according to claim 2.   The filter characteristic test circuit determines the sampling clock having a frequency that is twice the frequency of the predetermined attenuation amount based on a frequency when the attenuation amount of the output signal becomes equal to or less than the predetermined value. Signal converter.