JP5164133B2 - Power converter - Google Patents

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JP5164133B2
JP5164133B2 JP2007009243A JP2007009243A JP5164133B2 JP 5164133 B2 JP5164133 B2 JP 5164133B2 JP 2007009243 A JP2007009243 A JP 2007009243A JP 2007009243 A JP2007009243 A JP 2007009243A JP 5164133 B2 JP5164133 B2 JP 5164133B2
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noise
core
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cores
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JP2008178218A (en
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泰文 赤木
啓輔 山城
征輝 五十嵐
靖幸 小林
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Fuji Electric Co Ltd
Tokyo Institute of Technology NUC
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Tokyo Institute of Technology NUC
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この発明は、パワー半導体素子のスイッチング時に、伝導または放射される伝導性ノイズまたは放射ノイズを低減することを目的に、ノイズ電流が流れる回路にインピーダンスを追加または付加する電力変換装置に関する。   The present invention relates to a power converter that adds or adds impedance to a circuit through which a noise current flows for the purpose of reducing conductive noise or radiated noise that is conducted or radiated during switching of a power semiconductor element.

近年、EMC(電磁妨害:electromagnetic interference)規制が厳しくなる中、汎用インバータを始め、様々な産業機器で放射および伝導ノイズ(単にノイズとも言う)の低減が技術課題となっている。特に、これらの主部品であるパワー半導体、およびこれらを搭載したパワーモジュールがスイッチングすることにより発生するノイズの低減については、対策が必要とされている。その対策の1つとして、フェライトコアの挿入が挙げられ、例えば特許文献1に開示されている。   In recent years, EMC (electromagnetic interference) regulations have become stricter, and reduction of radiation and conduction noise (also simply referred to as noise) has become a technical problem in various industrial devices including general-purpose inverters. In particular, countermeasures are required for the reduction of noise generated by switching of these main components, which are power semiconductors, and power modules on which these are mounted. One countermeasure is the insertion of a ferrite core, which is disclosed in Patent Document 1, for example.

また、ノイズの発生源となるループは、ノルマルループとコモンループの2種類に分類され、これらはループの経路が異なるため、ノイズ電流を低減するためには、それぞれ個々にインピーダンスを追加する等の対策が講じられるのが一般的である。
そこで、ノルマルループとコモンループによって発生するノイズ電流を一度に低減できれば、インピーダンスを追加する上で必要なフェライトコア等の部材を少なくでき、なおかつコストや設置スペースの削減において有効である。このような効果を目指す技術として、例えば特許文献2〜4に示すものがある。
In addition, the loops that are the sources of noise are classified into two types, normal loops and common loops. Since these loop paths are different, in order to reduce the noise current, add impedances individually. In general, measures are taken.
Therefore, if the noise current generated by the normal loop and the common loop can be reduced at one time, it is possible to reduce the number of members such as ferrite cores required for adding impedance, and it is effective in reducing cost and installation space. As techniques aiming at such an effect, for example, there are those shown in Patent Documents 2 to 4.

特許第2851268号明細書Japanese Patent No. 2851268 特許第2671434号明細書Japanese Patent No. 2671434 特開2005−116792号公報JP 2005-116792 A 特開2001−237130号公報JP 2001-237130 A

通常、コモンモードノイズとノルマルモードノイズそれぞれの対策には、コモンループとノルマルループにそれぞれフェライトコアなどのインピーダンスを追加するのが一般的である。
図5に、コモンモードノイズとノルマルモードノイズを抑制するためのコアの挿入箇所例を示す。図5(a)はコモンモードノイズのみの対策例、図5(b)はノルマルモードノイズのみの対策例、図5(c)はコモンとノルマルの両方のノイズの対策例を示す。また、図5(a)〜(c)に示す各記号と、それぞれに対応するコアの具体例を図6(a)〜(c)の右側に示す。
Usually, as countermeasures against common mode noise and normal mode noise, it is common to add impedances such as ferrite cores to the common loop and normal loop, respectively.
FIG. 5 shows an example of a core insertion location for suppressing common mode noise and normal mode noise. FIG. 5A shows an example of countermeasures for only common mode noise, FIG. 5B shows an example of countermeasures for only normal mode noise, and FIG. 5C shows an example of countermeasures for both common and normal noise. Moreover, each symbol shown to Fig.5 (a)-(c) and the specific example of the core corresponding to each are shown on the right side of Fig.6 (a)-(c).

上記特許文献1では、ノルマルモードノイズ対策として、例えばダイオードの各端子にアモルファスコアを挿入している。この方法では、それぞれのノイズ発生モードに個別にコアを必要とするため、使用部材の個数が増大する。
そこで、コモンモードノイズとノルマルモードノイズを一括して対策する方法として、特許文献2,3に示す形状のコアが提案されている。
In Patent Document 1, for example, an amorphous core is inserted into each terminal of a diode as a countermeasure against normal mode noise. In this method, since a core is required for each noise generation mode, the number of members used increases.
Therefore, as a method for collectively dealing with common mode noise and normal mode noise, cores having the shapes shown in Patent Documents 2 and 3 have been proposed.

図7に特許文献2,3で用いられているコアの形状例を示す。
図示のように、貫通型コア1にギャップの付いた足を設けた形状をしており、ギャップが付いていない側の足に電線(巻線)2を巻き付け、ノルマルとコモンの両方に対してコアのループを作ることで、各モードにおいてインピーダンスを発生できる形状としている。しかし、図7に示す形状のものを採用する場合、中心の足にギャップを持たせるため、コアの加工性能と強度とを両立させることは難しい。
FIG. 7 shows an example of the shape of the core used in Patent Documents 2 and 3.
As shown in the figure, the penetrating core 1 has a shape with a gap, and a wire (winding) 2 is wound around the leg without a gap to both normal and common. By creating a core loop, the shape can generate impedance in each mode. However, when the shape shown in FIG. 7 is adopted, it is difficult to achieve both the processing performance and strength of the core because a gap is provided at the center leg.

具体的には、単純なギャップを形成するにも中足の加工であるため、切削加工では経常的な制約がある上、成型加工でも作製精度として、通常±0.1〜1mm程度の範囲でばらつきが発生する。ギャップ長のばらつきはインピーダンスのばらつきにつながり、微小なギャップの違いであっても、ばらつきは無視できないほど大きくなる。例えば、一般的なリングコアとして外径14mm×内径8mm×高さ7mmのものにギャップを設けて±1mmの誤差が発生した場合、インピーダンスの誤差は50%を超えるほど大きくなる。
また、フェライトなどの磁性材料の多くは、材質が陶磁器などと同じように粘らず脆性破壊が生じやすいため、中足にギャップを設けることで強度的な低下が著しく、微小な亀裂が生じやすい上に僅かな衝撃で破損し易くなるため、ハンドリングの面でも作業を煩雑化させることになる。
Specifically, since it is a process of the middle leg to form a simple gap, there are recurrent limitations in cutting, and the manufacturing accuracy is usually in the range of about ± 0.1 to 1 mm even in molding. Variation occurs. The gap length variation leads to impedance variation, and the variation becomes so large that it cannot be ignored even if the gap is very small. For example, when an error of ± 1 mm is generated by providing a gap in a general ring core having an outer diameter of 14 mm, an inner diameter of 8 mm, and a height of 7 mm, the impedance error increases as it exceeds 50%.
In addition, since many magnetic materials such as ferrite are not sticky like ceramics and are susceptible to brittle fracture, providing a gap in the middle leg causes a significant drop in strength and tends to cause microcracks. Therefore, it is easy to break with a slight impact, and the work is complicated in terms of handling.

さらに、上述のような形状のコアは、EI型やEE型として分割タイプのものが市販されているが、その用途はトランス用にほぼ限定されており、上述のギャップ精度を確保するために、合わせ面やギャップ間に面出しの加工が施されている。その上、E型とI型またはE型のコアを組み合わせて使用するためには、これらを支持・補強する治具が必要となり、磁性体の周囲を樹脂やセラミックスや金属材料などで補強して使用される。以上のように、ギャップや合わせ面の精度確保や補強治具の使用により、ギャップ付きEIコア,EEコア等には問題が残されている。   Furthermore, as for the core having the shape as described above, a split type of EI type or EE type is commercially available, but its use is almost limited to transformers, and in order to ensure the above gap accuracy, Chamfering is applied between mating surfaces and gaps. In addition, in order to use a combination of E-type and I-type or E-type cores, a jig for supporting and reinforcing them is required, and the periphery of the magnetic body is reinforced with resin, ceramics, metal materials, etc. used. As described above, problems remain in the EI core with a gap, the EE core, and the like by ensuring the accuracy of the gap and the mating surface and using the reinforcing jig.

したがって、この発明の課題は、上述のコアの問題に鑑み、一般的で廉価なコア部材の使用数を減らし、簡単にコモンモードノイズとノルマルモードノイズの両方を低減可能にすることにある。   Accordingly, an object of the present invention is to reduce the number of general and inexpensive core members in view of the above-described problems of the core, and to easily reduce both common mode noise and normal mode noise.

このような課題を解決するため、請求項1の発明では、ノイズ低減用のリングコアを電力変換装置の入力と出力の少なくとも一方の、3相以上の全相でない2相以上の相線に対し、相線の組み合わせが互いに重複せず、かつ相線の数が全てのリングコアで互いに等しくなるように、複数のノイズ低減用のリングコアが一括して設置され、各相間でノルマルインピーダンスにアンバランスが生じないようにすることを特徴とする。
前記の発明において、 請求項1に記載の電力変換装置において、3相の相線に対して、第1のノイズ低減用のリングコアにU相、V相の相線を通すとともに、この第1のノイズ低減用のリングコアが、V相、W相の相線との間および、U相、W相の相線との間に位置し、第2のノイズ低減用のリングコアにV相、W相の相線を通すとともに、この第2のノイズ低減用のリングコアが、U相、V相の相線との間および、U相、W相の相線との間に位置し、第3のノイズ低減用のリングコアにW相、U相の相線を通すとともに、この第3のノイズ低減用のリングコアが、V相、W相の相線との間および、U相、V相の相線との間に位置するように前記各リングコアを配置することができる。
Such problems in order to resolve, in the invention of claim 1, input with at least one of the output of the power converter the ring core for noise reduction, against the 2 or more phases lines not all phases of the three or more phases, Multiple noise reduction ring cores are installed together so that the combinations of phase wires do not overlap each other and the number of phase wires is the same for all ring cores, resulting in an unbalance in normal impedance between each phase. It is characterized by not.
In the above-described invention, in the power conversion device according to claim 1, the U-phase and V-phase lines are passed through the first noise reduction ring core with respect to the three-phase phase lines. The ring core for noise reduction is positioned between the V-phase and W-phase phase lines and between the U-phase and W-phase phase lines, and the second noise-reducing ring core has V-phase and W-phase. The second noise reduction ring core is located between the U-phase and V-phase phase lines and between the U-phase and W-phase phase lines, and the third noise reduction. The W-phase and U-phase phase lines are passed through the ring core for use, and the third noise-reducing ring core is connected between the V-phase and W-phase phase lines and between the U-phase and V-phase phase lines. Each said ring core can be arrange | positioned so that it may be located in between.

この発明によれば、これまでコモンモードとノルマルモードで個別に対策していたものについて、コアへの入出力線への挿入方法を工夫することにより、コモンモードとノルマルモードの両ノイズに同時に対処することが可能となる。従来のように、コア自体の中足にギャップを設けるコアでは、インピーダンス精度を確保するために、加工技術や加工精度が要求されるだけでなく、コストやハンドリングの面で取り扱い難いという難点があったが、この発明では汎用性のあるリングコアを用いるようにしたので安価で扱い易く、部品調達や部品交換も容易である。
さらに、コモンモードとノルマルモードで個別に対策する場合に比べ、少ない個数で対処できるため、低コストでかつ少ない部品数で簡単に対処することができる。
According to the present invention, both common mode and normal mode noise can be dealt with at the same time by devising the insertion method to the input / output line to the core of what has been individually countered in common mode and normal mode. It becomes possible to do. As in the past, a core having a gap in the middle of the core itself requires not only processing technology and processing accuracy to ensure impedance accuracy, but also has difficulty in handling in terms of cost and handling. However, since a versatile ring core is used in the present invention, it is inexpensive and easy to handle, and parts procurement and parts replacement are also easy.
Furthermore, since it is possible to cope with a small number of parts compared with the case where countermeasures are individually taken in the common mode and the normal mode, it is possible to easily cope with a low cost and a small number of parts.

図1はこの発明の原理を説明するための説明図、図2はこの発明の実施の形態を示す回路図である。
図1において、11〜13はコア、21〜23は電線(相線)を示し、3相の場合に適用する例である。すなわち、コア11を電線21,23に、コア12を電線21,22に、また、コア13を電線22,23にそれぞれ組み合わせて用いている。
コア11〜13はリング状(円環状)のものを用いたが、これに限らず、多角形,楕円などの形状でもよい。汎用のリングコアを適用することができるため、これを選択すると安価で扱いやすい。1つのコア内部には後述する必要本数の電線を通すことができる内径
(内寸)を有するものとする。
FIG. 1 is an explanatory diagram for explaining the principle of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the present invention.
In FIG. 1, 11 to 13 are cores, 21 to 23 are electric wires (phase wires), and are examples applied in the case of three phases. That is, the core 11 is used in combination with the electric wires 21 and 23, the core 12 is used in combination with the electric wires 21 and 22, and the core 13 is used in combination with the electric wires 22 and 23.
The cores 11 to 13 are ring-shaped (annular), but are not limited to this, and may be polygonal or elliptical. Since a general-purpose ring core can be applied, it is cheap and easy to handle when this is selected. One core has an inner diameter (inner dimension) through which a necessary number of wires to be described later can pass.

図1ではコア11に電線21,23を挿入しているが、コア12や13には電線21と23を挿入しないよう、その組み合わせが重複しないようにすること、また、各コアにはここでは2本の電線がそれぞれ挿入されるよう、コアに挿入する相線の数を等しくすることなどが必要である。対策する入出力線の総数は3相だけでなく何相でも良いが、1相や2相の場合は成り立たないので、3相以上の場合が対象となる。
また、上記のようにコア11〜13内に電線を通すことにより、3つのコアを用いてノルマルモードコアとコモンモードコアの作用を得るものである。
In FIG. 1, the wires 21 and 23 are inserted into the core 11, but the combinations of the wires 12 and 13 are not overlapped so that the wires 21 and 23 are not inserted into the cores 12 and 13. It is necessary to equalize the number of phase wires inserted into the core so that the two electric wires are respectively inserted. The total number of input / output lines to be dealt with is not limited to three phases, but may be any number, but the case of one phase or two phases does not hold, so the case of three or more phases is targeted.
Moreover, by passing an electric wire through the cores 11-13 as mentioned above, the effect | action of a normal mode core and a common mode core is obtained using three cores.

図1のような配置でノルマルモードとコモンモードの両方に効果を生む理由について説明する。例として、インダクタンスを用いて考える。
図1の配置にて、コア1つ当りのインダクタンスをLとすると、コア1つに2本の配線をしているため、コア1つがノルマルモードとして1本の線に与えるインダクタンスは(1/2)Lとなる。図1では1相当り2個のコアを通っているため、トータルでは、
(1/2)L+(1/2)L= L…(1)
の値のノルマルモードインダクタンスを与えることができる。
The reason why the arrangement as shown in FIG. 1 is effective in both the normal mode and the common mode will be described. As an example, consider using inductance.
In the arrangement of FIG. 1, assuming that the inductance per core is L, two wires are connected to one core, so the inductance given to one line by one core as a normal mode is (1/2 ) L. In FIG. 1, since one core passes through two cores,
(1/2) L + (1/2) L = L (1)
A normal mode inductance of a value of

一方、コモンモードについては、3相を一本の配線として考えると、コア1つがコモンモードLとして与えるインダクタンスは、2つの相しか通していないため、(2/3)Lとなる。しかし、各相でアンバランスが生じないように3つ配置しているため、
(2/3)L+(2/3)L+(2/3)L=2L…(2)
の値のコモンモードインダクタンスを与えることができる。
よって、コア11〜13を図1の如く配置することにより、ノルマルモードコアとコモンモードコアをそれぞれ設けることなく、ノルマルモードノイズ,コモンモードノイズの双方を同時に抑制することができる。
On the other hand, regarding the common mode, when the three phases are considered as one wiring, the inductance given by one core as the common mode L is (2/3) L because only two phases pass. However, because three are arranged so that there is no imbalance in each phase,
(2/3) L + (2/3) L + (2/3) L = 2L ... (2)
A common mode inductance of the value can be given.
Therefore, by arranging the cores 11 to 13 as shown in FIG. 1, both normal mode noise and common mode noise can be simultaneously suppressed without providing a normal mode core and a common mode core.

この発明をインバータの入力フィルタとして適用した場合の例を、図2に示す。
図2(a)は未対策時(L型フィルタのみ)、図2(b)はノルマルモードフィルタのみの対策時(ノルマルモード対策コアLdとコンデンサCxを追加)を、それぞれ示す。図2(c)は、この発明により配置したコア11〜13をノルマルモード対策コアLdとコモンモ−ド対策コアLcとして等価的に示したインバータ回路を示す。入力線は3相で、図1のような構成のリングコア11〜13を、2相ずつ3個挿入した場合を示している。なお、挿入するコアは入力側に限らず、出力側でも良い。
An example in which the present invention is applied as an input filter of an inverter is shown in FIG.
FIG. 2A shows a case where no countermeasure is taken (only the L-type filter), and FIG. 2B shows a case where only the normal mode filter is taken (the normal mode countermeasure core Ld and the capacitor Cx are added). FIG. 2C shows an inverter circuit in which the cores 11 to 13 arranged according to the present invention are equivalently shown as a normal mode countermeasure core Ld and a common mode countermeasure core Lc. The input line has three phases, and shows a case where three ring cores 11 to 13 having a configuration as shown in FIG. The core to be inserted is not limited to the input side but may be the output side.

図2(b)の対策を施したときの伝導ノイズベクトルの例を図3に、また、図2(c)の対策を施したときの伝導ノイズベクトルの例を図4にそれぞれ示す。
すなわち、図3のようにノルマルモードフィルタのみの対策を施した場合は、L型フィルタのみの場合(Y参照)に比べて600kHz付近のノイズが約7dB、4MHzのノイズが約10dB低減しているが、4MHzピークは抑制されずに完全に残っている(Z参照)。
An example of the conduction noise vector when the countermeasure of FIG. 2B is taken is shown in FIG. 3, and an example of the conduction noise vector when the countermeasure of FIG. 2C is taken is shown in FIG.
That is, when the countermeasure only for the normal mode filter is applied as shown in FIG. 3, the noise around 600 kHz is reduced by about 7 dB and the noise at 4 MHz is reduced by about 10 dB compared to the case of only the L-type filter (see Y). However, the 4 MHz peak remains unrestrained (see Z).

これに対し、図4では図1に示すこの発明のコアを挿入することにより、ノルマルモードコアとコモンモードコアを個々に追加することなく、600kHz付近のノイズに加え、4MHzピークも約15dB低減できることを示している(Z参照)。
なお、図3,図4の線XはIEC61800−3 Cat.C3インバータ等の電気機器における国際規格値を示していて、伝導ノイズが線Xを越えないようにすることが求められている。図に示すように、従来対策(Yのカーブ)では本規格を満たせなかったが、この発明を適用することにより、ほぼ規格内に収めることができる。特に規格に対してマージンが殆ど無い4MHz付近のピークを約10dBも低減することができる。
On the other hand, in FIG. 4, by inserting the core of the present invention shown in FIG. 1, it is possible to reduce the 4 MHz peak by about 15 dB in addition to the noise near 600 kHz without adding the normal mode core and the common mode core individually. (See Z).
The line X in FIGS. 3 and 4 indicates IEC61800-3 Cat. It shows international standard values for electrical equipment such as C3 inverters, and it is required to prevent conduction noise from exceeding line X. As shown in the figure, the conventional measure (Y curve) could not satisfy this standard, but by applying this invention, it can be kept within the standard. In particular, a peak around 4 MHz with almost no margin with respect to the standard can be reduced by about 10 dB.

この発明の原理を説明する説明図Explanatory drawing explaining the principle of this invention この発明の実施の形態を示すインバータ回路図Inverter circuit diagram showing an embodiment of the present invention 図2(b)の回路の伝導ノイズ評価結果を説明する説明図Explanatory drawing explaining the conduction noise evaluation result of the circuit of FIG.2 (b) 図2(c)の回路の伝導ノイズ評価結果を説明する説明図Explanatory drawing explaining the conduction noise evaluation result of the circuit of FIG.2 (c) ノイズの発生回路説明図Noise generation circuit explanatory diagram ノイズ対策用コアの具体例を説明する説明図Explanatory drawing explaining the specific example of the core for noise countermeasures 特許文献2,3で用いられるコアの例を示す構造図Structural diagram showing examples of cores used in Patent Documents 2 and 3

符号の説明Explanation of symbols

1,11〜13…コア、2,21〜23…電線。   1, 11-13 ... Core, 2, 21-23 ... Electric wire.

Claims (2)

ノイズ低減用のリングコアを電力変換装置の入力と出力の少なくとも一方の、3相以上の全相でない2相以上の相線に対し、相線の組み合わせが互いに重複せず、かつ相線の数が全てのリングコアで互いに等しくなるように、複数のノイズ低減用のリングコアが一括して設置され、各相間でノルマルインピーダンスにアンバランスが生じないようにすることを特徴とする電力変換装置。 Input at least one of the output of the power converter the ring core for noise reduction, against the 2 or more phases lines not all phases of the three or more phases, do not overlap the combination of the phase line each other, and the number of phase lines A power conversion device , wherein a plurality of noise reduction ring cores are collectively installed so that all ring cores are equal to each other, so that no imbalance occurs in normal impedance between phases. 請求項1に記載の電力変換装置において、
3相の相線に対して、
第1のノイズ低減用のリングコアにU相、V相の相線を通すとともに、この第1のノイズ低減用のリングコアが、V相、W相の相線との間および、U相、W相の相線との間に位置し、
第2のノイズ低減用のリングコアにV相、W相の相線を通すとともに、この第2のノイズ低減用のリングコアが、U相、V相の相線との間および、U相、W相の相線との間に位置し、
第3のノイズ低減用のリングコアにW相、U相の相線を通すとともに、この第3のノイズ低減用のリングコアが、V相、W相の相線との間および、U相、V相の相線との間に位置するように前記各リングコアを配置したことを特徴とする電力変換装置
The power conversion device according to claim 1,
For three phase lines
The U-phase and V-phase phase wires are passed through the first noise-reducing ring core, and the first noise-reducing ring core is placed between the V-phase and W-phase phase lines and between the U-phase and W-phase. Located between the phase line of
The V-phase and W-phase phase wires are passed through the second noise-reducing ring core, and the second noise-reducing ring core is placed between the U-phase and V-phase phase lines and between the U-phase and W-phase. Located between the phase line of
The W-phase and U-phase phase wires are passed through the third noise-reducing ring core, and the third noise-reducing ring core is placed between the V-phase and W-phase phase lines and between the U-phase and V-phase. Each of the ring cores is disposed so as to be positioned between the phase line of the power converter .
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