JP5163316B2 - Data transfer device, data transfer method and program - Google Patents

Description

  The present invention relates to a data transfer device, and more particularly to a data transfer device that transfers data in a rectangular area between memories, a processing method thereof, and a program that causes a computer to execute the method.

  In recent years, portable information terminals with small cameras have penetrated the market, and the resolution of cameras has been increasing. The higher the resolution of the camera, the larger the capacity of the frame memory that stores the image data captured by the camera, and the more the amount of calculation required for image processing tends to increase.

  When image processing is realized by an LSI, if image data held in a large-capacity frame memory is directly processed by a high-speed processor, latency for data reading increases, and therefore data transfer is generally performed in a hierarchical structure. For example, a method using a cache memory can be mentioned. Particularly in the case of image processing, since the data area to be processed is often determined in advance, there is a method in which a part of the image is transferred to the local memory and processed using a local memory having a smaller capacity than the frame memory. Since the local memory is used by exchanging only a part of the rectangular image area in the image data in the frame memory, the capacity of the local memory can be reduced and the latency can be reduced.

  In the case of using a local memory, a method of dividing the local memory into a plurality of memory areas (for example, divided into three) is known (for example, see Patent Document 1). In this technique, a part of the local memory is used for data transfer, another part of the area is used for calculation by the processor, and the areas are exchanged when both processes are completed. In many cases, since the computation time of the processor is longer than the time required for DMA (Direct Memory Access) transfer, the time required for data transfer can be concealed. For image transfer, DMA transfer is used, and a device called a DMA controller (DMAC) is used.

  A general DMAC sets a start address, an end address, and a transfer size as transfer parameters, and transfers data in successive memory areas according to these settings. On the other hand, in the rectangular image area shown above, some addresses are non-contiguous in the memory space, but a technique of a DMA transfer apparatus that transfers such a rectangular image area is also disclosed (for example, Patent Documents). 2).

  In an image processing LSI, a DSP (Digital Signal Processor) specialized for digital signal processing is used to perform image processing at high speed. A local memory is provided for the DSP to temporarily store data. The DMAC reads data from the frame memory and stores it in the local memory. Local memory is accessed from two masters, DSP and DMAC. This local memory is composed of, for example, three physically separated memories (areas # 0 to # 2) of 4 Kbytes, and is configured so that no stall occurs when each master accesses another area. As an example, image data is stored in region # 0 and region # 1, and a DSP program is stored in region # 2.

  The format of the input image may be only one color data, or may be a special arrangement structure such as three primary colors RGB (Red, Green, Blue) or luminance and color difference YCbCr arrangement. In some cases, the bit width is 1 byte length, or 10-bit data is arranged and stored as 2-byte length data. However, for the sake of simplicity of explanation, 1 bit of horizontal 1920 pixels × vertical 1024 lines is used here. This will be explained using byte-length luminance data. At this time, it may be assumed that all pixels are continuously arranged and stored every 1920 Kbytes. For ease of handling, a 128-byte blank area may be provided on the right side of the image, and the total horizontal size may be stored as 2048 pixels every 2048 Kbytes.

  The input image is temporarily stored in the frame memory and DMA-transferred to the local memory via the DMAC. If the capacity of the local memory area is, for example, 4 Kbytes, the input data is processed by dividing it into 480 rectangular image areas of 4 Kbytes of 64 horizontal pixels × 64 vertical lines. Among these, the data of the first rectangular image area is transferred to the area # 0.

  When the transfer is completed, the DSP processes the image processing of area # 0. In parallel with this, the DMAC transfers the rectangular image area to be processed next to the area # 1.

  When the DSP image processing and DMA transfer are completed, the next calculation and transfer are started. That is, the DSP processes the image in the region # 1, and in parallel with this, the DMAC transfers the processing result in the region # 0 to the frame memory. Then, the rectangular image area to be processed next is transferred to area # 0. The storage destination of the processing result may be an area where the original rectangular image data was present, or may be stored in another area while leaving the original rectangular image data.

In the same manner, the process is repeated for all the pixels of the image. As described above, in a method that can process image processing and DMA transfer in parallel, in many cases, the time required for DMA transfer is shorter than the computation time of the DSP, so that the time for DMA transfer can be concealed in the image processing time. The final result is formed as one piece of image data in the frame memory and displayed on, for example, a liquid crystal display (LCD).
JP-A-60-201443 (Fig. 2) Japanese Patent Laying-Open No. 2006-209552 (FIG. 4)

  Up to this point, the case where the size of the rectangular image area does not change by simple image processing has been shown. However, most image processing is performed using a plurality of pixels. For example, in the case of performing a 3-tap horizontal LPF (Low Pass Filter) process, a calculation result of horizontal 62 pixels × vertical 64 lines is generated from image data of horizontal 64 pixels × vertical 64 lines. When image processing of 17 horizontal taps × 17 vertical taps is performed, 48 horizontal pixels × 48 vertical lines are generated.

  Therefore, in order to perform image processing of 17 horizontal taps × 17 vertical taps, the horizontal 48 pixels × vertical 48 lines is considered as an effective area, and the input rectangular image area is vertical 64 pixels × 64 pixels with 8 pixels added vertically and horizontally. Prepare images of. Then, after image processing, it may be considered that only 48 pixels wide × 48 lines vertically are written in the frame memory. In order to add the surrounding pixels, if the rectangular image area is not located at the edge of the image, it is only necessary to use the upper, lower, left, and right 8 pixels. However, when the rectangular image area touches the edge of the input image, it is necessary to prepare another value.

There are several ways to extend the edge of an image. For example, in the rectangular image region located at the upper left of the image and having the left end and the upper end in contact with the end of the image data, the following three end expansion methods are conceivable.
(A) Neighborhood extension: The value of the extension is set to the value of the nearest pixel.
(B) Zero extension: The value of the extended part is set to zero.
(C) Set value extension: The value of the extended part is set to a set value (for example, “128”).
In many cases, (A) neighborhood extension is performed so that an erroneous image is not generated in a process involving a tap at the edge of the image. However, (B) zero extension and (C) set value extension are performed when it is not desired to perform erroneous detection in image extraction processing or the like. A program with a large processing scale may use a plurality of expansion methods.

Further, the following two timings are conceivable for the end extension processing.
(1) Perform on the image before image processing in the frame memory.
(2) After the image is transferred to the local memory, it is expanded before the image processing.
However, in (1), an extra memory is required for the frame memory as much as the end is expanded, and in (2), the case of DSP processing is required. In any case, since the end extension program is operated, the processing time is increased by the time during which the program is operating. In either case, there is a problem that the program code increases. Since the DSP specializes in signal processing such as product-sum operation, it is not good at dividing cases such as end extension, which tends to increase processing time and programs.

  The present invention has been made in view of such a situation, and an object of the present invention is to efficiently perform end extension processing when a rectangular image region is handled.

  The present invention has been made to solve the above problems, and a first aspect of the present invention is that a data holding unit that reads and holds data of the rectangular area from a transfer source memory that holds the rectangular area, and the rectangle Data alignment for generating extended data at the end of the rectangular area by aligning the data held in the data holding unit in accordance with the set extended width and the extended width setting section for setting the extended width at the end of the area A data transfer device or a processing method therefor, and a program therefor, and a data transfer unit that transfers the data held in the data holding unit and the extension data to a transfer destination memory. This brings about the effect that the extension data at the end in the rectangular area is generated when transferring from the transfer source memory to the transfer destination memory.

  In the first aspect, the rectangular area includes image data corresponding to a plurality of pixels, and the data alignment unit aligns the image data in units of pixels to obtain extended data at an end of the rectangular area. It may be generated. This brings about the effect | action of producing | generating the extended data of the edge in a rectangular area per pixel.

  In the first aspect, the rectangular area may include data having a two-dimensional structure, and the data alignment unit may use data on the upper, lower, left, and right ends of the two-dimensional structure data as the extension data. . This brings about the effect that data at the top, bottom, left, and right ends of the two-dimensional structure data is generated as extended data.

  According to a second aspect of the present invention, there is provided a data holding unit that reads and holds data of the rectangular area from a transfer source memory that holds the rectangular area, and an extended width setting unit that sets an extended width of an end of the rectangular area A data alignment unit that aligns zero value data according to the set extension width to generate extension data at the end of the rectangular area, and the data and extension data held in the data holding unit are transferred to A data transfer device including a data transfer unit that transfers data to a memory, a processing method thereof, and a program. As a result, when transferring from the transfer source memory to the transfer destination memory, the extended data at the end of the rectangular area is generated from the zero value data.

  The third aspect of the present invention provides a data holding unit that reads and holds data of the rectangular area from a transfer source memory that holds the rectangular area, and an extended width setting unit that sets an extended width of an end of the rectangular area A setting data holding unit that holds setting data extended to the end in the rectangular area, and data that generates the extended data at the end in the rectangular area by aligning the setting data according to the set extension width A data transfer apparatus, a processing method thereof, and a program including an alignment unit and a data transfer unit that transfers data held in the data holding unit and the extension data to a transfer destination memory. As a result, when transferring from the transfer source memory to the transfer destination memory, the extended data at the end of the rectangular area is generated from the setting data.

  Further, in the third aspect, the rectangular area includes image data corresponding to a plurality of pixels, and the data alignment unit aligns the setting data in units of pixels to obtain extended data at an end of the rectangular area. It may be generated. This brings about the effect | action of producing | generating the extended data of the edge in a rectangular area per pixel.

  According to a fourth aspect of the present invention, there is provided a data holding unit that reads and holds data of the rectangular area from a transfer source memory that holds the rectangular area, and an extended width setting unit that sets an extended width of an end of the rectangular area An extension mode setting unit that sets an extension mode at the end of the rectangular area, a setting data holding unit that holds setting data extended at the end of the rectangular area, and the set extension width and extension mode. Accordingly, the data alignment unit that generates the extended data at the end of the rectangular area by aligning the data, zero value data, or the setting data held in the data holding unit, the data held in the data holding unit, and the data A data transfer apparatus including a data transfer unit that transfers extension data to a transfer destination memory, or a processing method and program thereof. As a result, when transferring from the transfer source memory to the transfer destination memory, the extended data at the end of the rectangular area is generated according to the set extended mode.

  According to the present invention, it is possible to achieve an excellent effect that the edge expansion processing when handling a rectangular image region can be performed efficiently. In other words, edge extension processing is performed during DMA transfer, eliminating the need for the CPU and DSP to perform edge extension processing, so that the processing time of the program for edge extension processing can be concealed and the processing time for image processing is reduced. can do. In addition, since the present invention can perform edge expansion processing of tapped image processing with a simpler program, the program code can be reduced, and the memory capacity of a ROM or RAM for storing the program can be reduced. be able to.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration example of a data transfer apparatus according to an embodiment of the present invention. The data transfer apparatus includes a frame memory 140, a local memory 160, and a DMA control unit 170 that controls transfer between the two. The data transfer apparatus includes a CPU 110, a ROM 120, an image signal input / output unit 130, a DSP 150, and a bus 190. Note that the frame memory 140 and the ROM 120 may be provided outside the data transfer apparatus.

  A CPU (Central Processing Unit) 110 is a processor that performs overall control of the data transfer apparatus. A ROM (Read Only Memory) 120 is a memory that stores a program executed by the CPU 110 or the DSP 150. The image signal input / output unit 130 inputs and outputs image signals to and from the outside of the data transfer apparatus.

  The frame memory 140 is a memory that holds the image data input from the image signal input / output unit 130 in units of frames. As a frame of image data, for example, horizontal 1920 pixels × vertical 1024 lines are assumed.

  A DSP (Digital Signal Processor) 150 is a digital signal processor that performs image processing. The local memory 160 is a working memory for performing image processing in the DSP 150. In general, the capacity of the local memory 160 is smaller than that of the frame memory 140. Here, as an example, three physically separated 4 Kbyte areas (areas # 0 to # 2) are assumed, image data is stored in areas # 0 and # 1, and the program of the DSP 150 is stored in area # 2. Shall be stored. The local memory 160 is configured so that the DSP 150 and the DMA control unit 170 are masters, and a stall does not occur when each master accesses another area.

  A DMA (Direct Memory Access) control unit 170 controls data transfer between the frame memory 140 and the local memory 160. The configuration of the DMA control unit 170 will be described later with reference to the following diagram.

  The bus 190 is a bus that interconnects the CPU 110, the ROM 120, the image signal input / output unit 130, the frame memory 140, and the DMA control unit 170.

  The CPU 110 reads a program stored in the ROM 120 and executes this program. The CPU 110 controls the image signal input / output unit 130 and the DMA control unit 170. The CPU 110 also monitors the behavior of the entire data transfer device, such as control for starting and stopping the processing of the DSP 150, initial setting of the image signal input / output unit 130, and other resets, and performs control as necessary. The CPU 110 controls the DMA control unit 170 when transferring a program for operating the DSP 150 to the local memory 160. Further, the CPU 110 also divides the image into rectangular areas and calculates an address set in the DMA control unit 170.

  FIG. 2 is a diagram showing a configuration example of the DMA control unit 170 in the embodiment of the present invention. It is assumed that the DMA control unit 170 performs data transfer in units of 4 bytes. Therefore, the boundary of the image data is a 4-byte boundary.

  The DMA controller 170 performs transfer between the local memory 160 and the frame memory 140, but the operation is asymmetric depending on the transfer direction. At the time of DMA transfer from the frame memory 140 to the local memory 160, a rectangular image area can be specified in the transfer source frame memory 140, and written in a continuous area in the transfer destination local memory 160. On the other hand, during DMA transfer from the local memory 160 to the frame memory 140, the image data is stored in a continuous area in the transfer source local memory 160, and a rectangular area can be designated in the transfer destination frame memory 140. In addition, the end extension process can be specified in the transfer from the frame memory 140 to the local memory 160, but the end extension process cannot be specified in the transfer from the local memory 160 to the frame memory 140.

  The DMA control unit 170 includes a control register 171, a bus control unit 172, a buffer 173, a data alignment unit 174, a data control unit 175, and a transfer control unit 176.

  The control register 171 is a register that holds parameters for controlling the operation of the DMA control unit 170. The value of the control register 171 is set by the CPU 110 via the bus 190, but can be updated by the transfer control unit 176 during the DMA transfer. The control register 171 will be described later with reference to the next figure.

  The bus control unit 172 controls data exchange between the frame memory 140 and the buffer 173 by controlling the bus 190.

  The buffer 173 is a buffer that temporarily stores data during DMA transfer. The buffer 173 holds data read from the frame memory 140 or the local memory 160 by 4 bytes. At the time of transfer from the frame memory 140 to the local memory 160, end extension processing is performed using data held in the buffer 173. The buffer 173 is an example of a data holding unit described in the claims.

  The data alignment unit 174 rearranges the data arrangement in the buffer 173 and outputs the data to the local memory 160 when transferring from the frame memory 140 to the local memory 160. The data alignment unit 174 performs edge extension processing on the rectangular image area as necessary. The data alignment unit 174 is an example of a data alignment unit described in the claims.

  The data control unit 175 controls data exchange between the local memory 160 and the data alignment unit 174 via the signal line 169. The data control unit 175 is an example of a data transfer unit described in the claims.

  The transfer control unit 176 controls each unit of the DMA control unit 170. The transfer control unit 176 includes an internal register 177 and controls each unit of the DMA control unit 170 using the internal register 177. As the initial value of the internal register 177, the value of the control register 171 is used. When the DMA transfer is completed, the transfer control unit 176 notifies the CPU 110 of an interrupt via the signal line 179. Thereby, the CPU 110 recognizes the end of the DMA transfer.

  FIG. 3 is a diagram showing an example of an address map of the control register 171 in the embodiment of the present invention. Here, it is assumed that six words of 32-bit registers are held as the control register 171.

  The 0th word (register # 0) of the control register 171 holds a frame memory start address (AF) 610. This frame memory start address (AF) 610 is a start address in the frame memory 140.

  The first word (register # 1) of the control register 171 holds a local memory start address (AL: Address of Local Memory) 620. This local memory start address (AL) 620 is a start address in the local memory 160.

  The second word (register # 2) of the control register 171 holds the rectangular area vertical size (V: Vertical) 630 in 16 bits on the MSB side, and the rectangular area horizontal size (H: Horizontal) 640 in 16 bits on the LSB side. Hold. The rectangular area vertical size (V) 630 is the vertical size of the rectangular area in the frame memory 140. The rectangular area horizontal size (H) 640 is the horizontal size of the rectangular area in the frame memory 140.

  The third word (register # 3) of the control register 171 has an upper tap (U: Up) 651, a lower tap (D: Down) 652, a left tap (L: Left) 653 in an area of 4 bits from the MSB side. And the right tap (R: Right) 654 is held. The frame memory horizontal size (W: Width) 660 is held in 16 bits on the LSB side. The upper tap (U) 651 designates the width of the upper end extension of the image. The lower tap (D) 652 designates the width of the lower end extension of the image. The left tap (L) 653 is used to specify the width of the left end extension of the image. The right tap (R) 654 is used to specify the width of the right end extension of the image. The frame memory horizontal size (W) 660 is the horizontal size of the image in the frame memory 140. The upper tap (U) 651, the lower tap (D) 652, the left tap (L) 653, and the right tap (R) 654 are examples of the expanded width setting unit described in the claims.

  The fourth word (register # 4) of the control register 171 holds a transfer control register (CTL: ConTroL) 670. The transfer control register (CTL) 670 holds the transfer direction of DMA transfer, the transfer size, and the like.

  The fifth word (register # 5) of the control register 171 holds a set value register (PR: PReset) 680. The set value register (PR) 680 holds a set value when the set value is extended as the end extension processing.

  FIG. 4 is a diagram showing image data of one frame in the embodiment of the present invention. Here, as shown in FIG. 4A, one frame is constituted by image data composed of pixels of horizontal 1920 pixels × vertical 1024 lines. Each pixel represents 8-bit luminance. The image data will be described on the assumption that a 128-byte free area is provided between the lines and the line address is stored in the frame memory so that the head address of the line comes to the 2048-byte boundary.

  In this example, it is assumed that the DSP 150 performs image signal processing of 17 taps in the horizontal direction and 17 taps in the vertical direction. That is, as shown in FIG. 4B, by referring to the 8 taps on the left and right sides, the rectangular area is inserted and the “8 + 1 + 8” taps are formed in the horizontal direction. In addition, by referring to the upper and lower 8 taps each, the rectangular area is inserted, and “8 + 1 + 8” taps are formed in the vertical direction.

  As a result, when the frame memory 140 is loaded into the local memory 160, the DMA transfer of 64 vertical lines × 64 horizontal pixels is performed, and when the local memory 160 is stored in the frame memory 140, the DMA transfer of 48 vertical lines × 48 horizontal pixels is performed. Done. That is, a rectangular area of 40 blocks in the horizontal direction and (21 + 1/3) blocks in the vertical direction is transferred. It is assumed that the image data in the frame memory 140 is divided for each line and arranged at a 2048-byte boundary.

  When transferring a rectangular area that does not contact the edge of the image, when performing DMA transfer from the frame memory 140 to the local memory 160, the following values are set in the control register 171. The frame memory start address (AF) 610 is set to the start address of the rectangular area in the frame memory 140. In the local memory start address (AL) 620, the head address in the local memory 160 is set. In the rectangular area vertical size (V) 630, the vertical size “64” of the rectangular area is set. In the rectangular area horizontal size (H) 640, the horizontal size “64” of the rectangular area is set.

  In this example, since end expansion is not performed, the upper tap (U) 651, the lower tap (D) 652, the left tap (L) 653, and the right tap (R) 654 are all set to “0”. The frame memory horizontal size (W) 660 is set to “2048”.

  When a transfer command from the frame memory 140 to the local memory 160 is written in the transfer control register (CTL) 670, DMA transfer from the frame memory 140 to the local memory 160 starts.

  FIG. 5 is a diagram showing a designation example of end extension in the embodiment of the present invention. In this example, the rectangular area is at the upper left corner of the image data, and the upper and left sides are in contact with the edge of the image. When image signal processing of 17 taps in the horizontal direction and 17 taps in the vertical direction is performed as described above, when the rectangular area at the upper left end of the image data is DMA-transferred, the end is expanded by 8 taps upward and left. Therefore, in the control register 171, the upper tap (U) 651 and the left tap (L) 653 are set to “8”, and the lower tap (D) 652 and the right tap (R) 654 are set to “0”.

  The rectangular area vertical size (V) 630 is set to “56” obtained by subtracting 8 taps from “64”. Similarly, the rectangular area horizontal size (H) 640 is set to “56” obtained by subtracting 8 taps from “64”.

  Other than that, it is the same as the example of FIG. 4B, and the start address of the rectangular area in the frame memory 140 is set in the frame memory start address (AF) 610. The start address in the local memory 160 is set as the local memory start address (AL) 620. Further, the frame memory horizontal size (W) 660 is set to “2048”.

  Here, the setting example in the case of extending the edge to the left and the upper side is shown, but the setting is similarly performed in consideration of the number of taps when extending the other edge. For example, when the rectangular area is in contact with the right edge of the image, the right tap (R) 654 is set to “8”, and the upper tap (U) 651, the lower tap (D) 652, and the left tap (L) 653. Is set to “0”. The rectangular area vertical size (V) 630 is set to a rectangular area vertical size “64”. The rectangular area horizontal size (H) 640 is set to “56” obtained by subtracting 8 taps from “64”.

  The same can be done when the rectangular area extends beyond the image. For example, when the horizontal 64 pixels × vertical 16 lines are in the effective area of the image, the end extension of 48 lines is performed below. In this case, the lower tap (D) 652 is set to “48”, and the upper tap (U) 651, the left tap (L) 653, and the right tap (R) 654 are set to “0”. The rectangular area horizontal size (H) 640 is set to the horizontal size “64” of the rectangular area. The rectangular area vertical size (V) 630 is set to “16” in the effective area.

  FIG. 6 is a diagram showing types of end extension methods in the embodiment of the present invention. Here, as an example, a case where the rectangular region is located at the upper left of the image and the left end and the upper end are in contact with the end of the image data is shown.

  FIG. 6A shows an example of neighborhood extension in which the value of the extension portion is set to the value of the nearest pixel. In this neighborhood extension, the value of the pixel at the end of the rectangular area is used as the end extension value.

  FIG. 6B is an example of zero extension in which the value of the extension part is zero. In this zero extension, “0” is set in the end extension area.

  FIG. 6C is an example of setting value extension in which the value of the extension part is set as a setting value. In this set value extension, the value set in the set value register (PR) 680 of the control register 171 is used as the end extension value.

  In general, among these end extension methods, (A) neighborhood extension is often used. This is to prevent an erroneous image from being generated in a process involving a tap at the end of the image. However, (B) zero extension and (C) set value extension are performed when it is not desired to perform erroneous detection in image extraction processing or the like. (B) Zero value may be used for zero extension, but it may be better to use “128” when dealing with color difference, or black may be defined as “16” when dealing with luminance. In this case, (C) set value extension is used. Therefore, in the embodiment of the present invention, the transfer control register (CTL) 670 of the control register 171 can specify the end extension method, and (C) when the set value extension is specified, the set value register (PR ) A value of 680 is used as a set value.

  FIG. 7 is a diagram showing a field configuration example of the transfer control register (CTL) 670 in the embodiment of the present invention. As described above, the transfer control register (CTL) 670 is held as the fourth word (register # 4) of the control register 171.

  Two bits (0th to 1st bits) on the LSB side of the transfer control register (CTL) 670 are fields indicating a transfer command. In this field, “01” means transfer from the frame memory 140 to the local memory 160, and “10” means transfer from the local memory 160 to the frame memory 140.

  The second to third bits of the transfer control register (CTL) 670 are fields indicating the data width of the transferred data. In this field, “00” means a 1-byte length, “01” means a 2-byte length, and “10” means a 4-byte length. The size of the end extension is determined according to the data width. This will be described later with reference to FIG.

  The 4th to 5th bits of the transfer control register (CTL) 670 are fields indicating an extension method (extension mode) of end extension at the time of DMA transfer from the frame memory 140 to the local memory 160. In this field, “00” means neighborhood extension, “01” means zero extension, and “10” means set value extension. This field is an example of the extended mode setting unit described in the claims.

  FIG. 8 is a diagram showing a transition example of image data in the local memory 160 according to the embodiment of the present invention.

  As shown in FIG. 8A, the DSP 150 performs image processing on image data DMA-transferred to the local memory 160 with 64 pixels × 64 lines. In this example, one line of pixels is transferred in 16 transfers in units of 4 bytes.

  Assuming a 17-tap horizontal LPF, one line is reduced from 64 pixels to 48 pixels by this calculation. Therefore, when the calculation results are packed and stored in the local memory 160, as shown in FIG. 8B, 48 pixels × 64 Decrease in line.

  Next, assuming a 17-tap vertical LPF, the number of lines is reduced to 48 lines by this calculation. Therefore, if the calculation result is packed and written, continuous data of 48 pixels × 48 lines can be obtained as shown in FIG.

  When the conventional DMAC is installed, the edge extension is not performed at the same time as the transfer. Therefore, it is necessary to switch the processing in the DSP depending on whether the rectangular area is in contact with the edge of the image. According to the DMA control unit 170 of the embodiment of the present invention, the end extension is performed simultaneously with the DMA transfer. Therefore, it is sufficient to perform the same image processing regardless of whether the rectangular area is in contact with the end of the image.

  Conventionally, when edge extension processing is performed by a DSP, processing time is required for edge extension in addition to image processing time. In many cases, since the image processing time is longer than the DMA transfer time, according to the embodiment of the present invention, the processing time for edge extension can be executed during the processing time of the DSP. Time can be hidden. In the embodiment of the present invention, setting of the control register 171 by the CPU 110 is required, but the control program of the CPU 110 only needs to increase only the end expansion processing of the DMA control unit 170. Therefore, it becomes simpler than the increase in the program when the end extension is performed by the DSP 150, and the increase in the processing time can be suppressed.

  Next, the operation of the data transfer apparatus according to the embodiment of the present invention will be described with reference to the drawings.

  9 and 10 are diagrams showing an example of a processing procedure for DMA transfer from the frame memory 140 to the local memory 160 in the embodiment of the present invention.

  The transfer control is performed by the transfer control unit 176 in the DMA control unit 170. When a transfer command “01” for instructing loading from the frame memory 140 to the local memory 160 is written in the control register 171, the transfer control unit 176 instructs transfer according to the following procedure. In the following, it is assumed that processing is performed in units of 4 bytes. Therefore, frame memory start address (AF) 610, local memory start address (AL) 620, rectangular area horizontal size (H) 640, left tap (L) 653, right tap (R) 654, frame memory horizontal size (W) 660 is specified by a multiple of four. The data width of each data is assumed to be 1 byte.

  First, transfer for one line will be described. This line transfer is transfer accompanied by left and right end extension processing.

  When loading from the frame memory 140 to the local memory 160 is instructed, the transfer control unit 176 starts DMA transfer. Before the DMA transfer starts, a necessary value is set in the control register 171 in advance (step S910). Note that step S910 is an example of an extension width setting procedure described in the claims.

  First, among the data of the control register 171, the values of the registers of the rectangular area horizontal size (H) 640, the left tap (L) 653, the right tap (R) 654, and the frame memory start address (AF) 610 are as follows. It is held in the internal register 177 (step S911). In the following, in order to distinguish the value of the internal register 177 from the value of the control register 171, the rectangular area horizontal size (H0) 740, the left tap (L0) 753, the right tap (R0) 754, and the frame memory start, respectively. Address (AF0) 710 is described.

  The transfer control unit 176 determines whether or not the rectangular area horizontal size (H0) 740 is positive (step S912). If the rectangular area horizontal size (H0) 740 is positive, the process proceeds to step S913. Otherwise, the process proceeds to step S921. When the rectangular area horizontal size (H0) 740 is positive, the transfer control unit 176 controls the bus control unit 172 to read data from the address of the frame memory 140 indicated by the frame memory start address (AF0) 710. And temporarily stored in the buffer 173 (step S913). Then, “4” is added to the frame memory start address (AF0) 710 (step S913). Note that step S913 is an example of a data read procedure described in the claims.

  Next, the transfer control unit 176 determines whether or not the left tap (L0) 753 is positive (step S914). If the left tap (L0) 753 is positive, the process proceeds to step S915. Otherwise, the process proceeds to step S917. When the left tap (L0) 753 is positive, the data alignment unit 174 rearranges the first 1-byte data of the line among the data held in the buffer 173 into 4 bytes, and writes it to the local memory 160. This is performed (step S915). At this time, the local memory start address (AL) 620 is used as the address on the local memory 160 side. Then, “4” is added to the local memory start address (AL) 620 (step S915). Further, “4” is subtracted from the left tap (L0) 753 (step S916). Until the left tap (L0) 753 is not positive, the procedure from step S914 to S916 is repeated, and the left end expansion is performed in units of 4 bytes. Note that step S915 is an example of a data alignment procedure and a data transfer procedure described in the claims.

  When the left extension is completed, data is written in the first valid area. Since the data is already stored in the buffer 173, the data sorting unit 174 does not rearrange the data and writes 4-byte data to the local memory 160 (step S917). Then, “4” is added to the local memory start address (AL) 620 (step S917). Further, “4” is subtracted from the rectangular area horizontal size (H0) 740 (step S918). Until the rectangular area horizontal size (H0) 740 is not positive, steps S912 to S914, S917, and S918 are repeated, and the effective area is transferred in units of 4 bytes. Note that step S917 is an example of a data transfer procedure described in the claims.

  When the transfer of the valid area is completed, the right end expansion is performed next. The transfer control unit 176 determines whether or not the right tap (R0) 754 is positive (step S921). If the right tap (R0) 754 is positive, the process proceeds to step S922. Otherwise, the process proceeds to step S931. When the right tap (R0) 754 is positive, since the last data of the effective pixel is already stored in the buffer 173, the last 1 byte data of the line is rearranged into 4 bytes in the data alignment unit 174, and the local data Writing to the memory 160 is performed (step S922). At this time, the local memory start address (AL) 620 is used as the address on the local memory 160 side. Then, “4” is added to the local memory start address (AL) 620 (step S922). Also, “4” is subtracted from the right tap (R0) 754 (step S923). Then, until the right tap (R0) 754 is not positive, the procedure of steps S921 to S923 is repeated, and right end expansion is performed in units of 4 bytes. Note that step S922 is an example of a data alignment procedure and a data transfer procedure described in the claims.

  When the line transfer is completed, the upper end extension is performed next. The transfer control unit 176 determines whether or not the upper tap (U) 651 is positive (step S931). If the upper tap (U) 651 is positive, the process proceeds to step S932; otherwise, the process proceeds to step S933. When the upper tap (U) 651 is positive, “1” is subtracted from the upper tap (U) 651, and the process returns to the first process (step S911) (step S932). At this time, since the frame memory start address (AF) 610 is not updated, the same line in the frame memory 140 is transferred to the local memory 160 in the next line transfer. In this way, the procedure of steps S911 to S932 is repeated until the upper tap (U) 651 is not positive, and a copy of the data on the first line is transferred to the upper end extension region.

  If the upper tap (U) 651 is not positive after the line transfer and the rectangular area vertical size (V) 630 is larger than “1”, the process proceeds to step S934. Otherwise, the process proceeds to step S935. When the rectangular area vertical size (V) 630 is larger than “1”, “1” is subtracted from the rectangular area vertical size (V) 630 (step S934). Then, the frame memory horizontal size (W) 660 is added to the next frame memory start address (AF) 610, and the process returns to the first process (step S911) (step S934). However, only the final line is processed differently. When the rectangular area vertical size (V) 630 is “1” (step S935), “1” is subtracted from the rectangular area vertical size (V) 630, and then the frame memory start address (AF) 610 is added. Is not performed, and the process returns to the first process (step S911) (step S936). In this way, until the rectangular area vertical size (V) 630 is not positive, steps S911 to S931 and S933 to S936 are repeated to transfer the effective line.

  Finally, line transfer at the lower end outside the effective line is performed. If the rectangular area vertical size (V) 630 is not positive in step S935, the transfer control unit 176 determines whether or not the lower tap (D) 652 is positive (step S937). If the lower tap (D) 652 is positive, the process proceeds to step S938; otherwise, the DMA transfer process ends. When the lower tap (D) 652 is positive, after “1” is subtracted from the lower tap (D) 652, the process returns to the first process (step S911) (step S938). At this time, since the frame memory start address (AF) 610 has not been updated from the head address of the last line of the effective area, the last line is transferred to the local memory 160 in the next line transfer. In this way, the steps S911 to S932, S933, and S935 to S938 are repeated until the lower tap (D) 652 is not positive, and a copy of the data of the last line is transferred to the lower end extension region. Is done.

  If the lower tap (D) 652 is not positive, all transfers are completed, and the DMA transfer process ends. The end of the transfer is notified from the transfer control unit 176 to the CPU 110 as an interrupt.

  FIG. 11 is a diagram showing an example of a program for performing a DMA transfer process from the frame memory 140 to the local memory 160 in the embodiment of the present invention.

  The while statement on the first line forms a loop of the entire program. The second line initializes the internal register 177 and corresponds to step S911.

  The while statement on the third line forms a loop up to the thirteenth line while the rectangular area horizontal size (H0) 740 is positive, and corresponds to step S912. The fourth line substitutes the data read from the frame memory 140 for the variable data and advances the frame memory start address (AF) 610 by one (4 bytes), and corresponds to step S913. Here, the frame memory start address (AF) 610 is used as an address pointer of the frame memory 140. The while statement on the fifth line forms a loop up to the tenth line while the left tap (L0) 753 is positive, and corresponds to step S914.

  The sixth line substitutes the lower (leftmost) 1 byte of the read data for the variable temp. The seventh line connects four variables temp holding 1-byte data and substitutes them into a 4-byte variable wdata. The eighth line writes the contents of the variable wdata to the local memory 160 and advances the local memory start address (AL) 620 by one (4 bytes). These sixth to eighth lines correspond to step S915. The ninth line subtracts “4” from the left tap (L0) 753 and corresponds to step S916.

  The eleventh line writes the contents of the variable data to the local memory 160 and advances the local memory start address (AL) 620 by one (4 bytes), and corresponds to step S917. Here, the local memory start address (AL) 620 is used as an address pointer of the local memory 160. The ninth line is for subtracting “4” from the rectangular area horizontal size (H0) 740, and corresponds to step S918.

  The while statement on the 14th line forms a loop up to the 19th line while the right tap (R0) 754 is positive, and corresponds to step S921. The 15th line substitutes the upper byte (right end) 1 byte of the read data for the variable temp. The 16th line connects four variables temp holding 1-byte data and substitutes them into a 4-byte variable wdata. The 17th line writes the contents of the variable wdata to the local memory 160 and advances the local memory start address (AL) 620 by one (4 bytes). These 15th to 17th lines correspond to step S922. The 18th line is for subtracting “4” from the right tap (R0) 754 and corresponds to step S923.

  The 20th line subtracts “1” from the upper tap (U) 651 when the upper tap (U) 651 is positive, and corresponds to steps S931 and S932. The 21st line adds the frame memory horizontal size (W) 660 to the next frame memory start address (AF) 610 when the rectangular area vertical size (V) 630 is larger than “1”. In the 21st line, “1” is subtracted from the rectangular area vertical size (V) 630. The 21st line corresponds to steps S933 and S934. The 22nd line subtracts “1” from the rectangular area vertical size (V) 630 when the rectangular area vertical size (V) 630 is larger than “0”, and corresponds to steps S935 and S936. The 23rd line subtracts “1” from the lower tap (D) 652 when the lower tap (D) 652 is larger than “0”, and corresponds to steps S937 and S938. In the 24th line, when any of the conditions in the 20th to 23rd lines is not met, the process exits the loop of the while statement in the 1st line.

In the example of the program, an example in which neighborhood extension is used as the edge extension method has been described. However, other edge extension methods can also be used. In the case of zero extension, in the sixth to seventh lines and the fifteenth to sixteenth lines (steps S915 and S922) for generating write data,
wdata = 0;
This can be realized.

In the case of setting value extension, when the left and right ends are first extended, 4-byte extension data generated using a 1-byte setting value preset becomes the write data wdata.
temp = preset &0xFF;
wdata = (temp << 24) | (temp << 16) | (temp << 8) | temp;

  In the example of neighborhood extension, 4-byte data in the buffer 173 is written to the local memory 160 in the eleventh line (step S917), but when extending the upper and lower ends of extension in the setting value extension, Depending on the conditions, the value of the buffer 173 is not used. That is, when the upper tap (U) 651 is larger than “0”, or when both the upper tap (U) 651 and the rectangular area vertical size (V) 630 are “0” or less, the value of the buffer 173 is used. Instead, 4-byte extension data is used in the same manner as the left and right end extensions described above.

  FIG. 12 is a diagram showing an example of a processing procedure for DMA transfer from the local memory 160 to the frame memory 140 in the embodiment of the present invention.

  Since the transfer in this direction does not require end extension, the settings of the upper tap (U) 651, the lower tap (D) 652, the left tap (L) 653, and the right tap (R) 654 are ignored. In the rectangular area vertical size (V) 630, the vertical size “48” of the rectangular area after the LPF calculation is set. Similarly, in the rectangular area horizontal size (H) 640, the horizontal size “48” of the rectangular area after the LPF calculation is set. Further, “2048” is set in the frame memory horizontal size (W) 660.

  The transfer control is performed by the transfer control unit 176 in the DMA control unit 170. When a transfer command “10” for instructing storage from the local memory 160 to the frame memory 140 is written in the control register 171, the transfer control unit 176 instructs transfer according to the following procedure.

  The transfer control unit 176 first determines whether or not the rectangular area vertical size (V) 630 is positive (step S941). If the rectangular area vertical size (V) 630 is positive, the process proceeds to step S942, and otherwise, the DMA transfer process ends.

  Then, the transfer control unit 176 holds the values of the registers of the rectangular area horizontal size (H) 640 and the frame memory start address (AF) 610 among the data of the control register 171 in the internal register 177 (step S942). .

  In line transfer, the transfer control unit 176 determines whether or not the rectangular area horizontal size (H0) 740 is positive (step S943). If the rectangular area horizontal size (H0) 740 is positive, the process proceeds to step S944. Otherwise, the process proceeds to step S947. When the rectangular area horizontal size (H0) 740 is positive, 4-byte data is read from the local memory 160 (step S944). At this time, the local memory start address (AL) 620 is used as the address on the local memory 160 side. Then, “4” is added to the local memory start address (AL) 620 (step S944). The read 4-byte data is written into the frame memory 140 (step S945). At this time, the frame memory start address (AF0) 710 is used as the address on the frame memory 140 side. Then, “4” is added to the frame memory start address (AF0) 710 (step S945). Further, “4” is subtracted from the rectangular area horizontal size (H0) 740 (step S946), and the process returns to step S943. As described above, by repeating steps S943 to S946, transfer for one line is performed.

  When the rectangular area horizontal size (H0) 740 is not positive, “1” is subtracted from the rectangular area vertical size (V) 630 for the next line transfer (step S947). Then, the frame memory horizontal size (W) 660 is added to the frame memory start address (AF) 610, and the process returns to the first process (step S941) (step S947). As described above, while the rectangular area vertical size (V) 630 is positive, steps S941 to S947 are repeated, and finally the DMA transfer of the rectangular area is completed. The end of the transfer is notified from the transfer control unit 176 to the CPU 110 as an interrupt.

  FIG. 13 is a diagram showing an example of a program for performing a DMA transfer process from the local memory 160 to the frame memory 140 in the embodiment of the present invention.

  The while statement on the first line forms a loop up to the eighth line while the rectangular area vertical size (V) 630 is positive, and corresponds to step S941. The second line initializes the internal register 177 and corresponds to step S942.

  The while statement in the third line forms a loop up to the sixth line while the rectangular area horizontal size (H0) 740 is positive, and corresponds to step S943. The fourth line is for writing data read from the local memory 160 to the frame memory 140. At this time, the local memory start address (AL) 620 is used as a pointer for the address on the local memory 160 side, and the frame memory start address (AF0) 710 is used for the address on the frame memory 140 side. Then, the local memory start address (AL) 620 and the frame memory start address (AF0) 710 are each advanced by one (4 bytes). The fourth line corresponds to steps S944 to S945. The fifth line is for subtracting “4” from the rectangular area horizontal size (H0) 740 and corresponds to step S946.

  The seventh line adds the frame memory horizontal size (W) 660 to the frame memory start address (AF) 610 and transfers “1” from the rectangular area vertical size (V) 630 to transfer the next line. This is to be subtracted and corresponds to step S947.

  FIG. 14 is a diagram illustrating a relationship example between the data width of the transferred data and the end extension according to the embodiment of the present invention.

FIG. 14A shows an example in which the left end expansion is performed when the data width of the transferred data is 1 byte. In this example, 1-byte data “Y0” is the leftmost data, so that four “Y0” connected are 4-byte extension data. This is the case when the image data has only 1-byte luminance. The above-described program example of FIG. 11 also has a data width of 1 byte, and the sixth to seventh lines of the program example are portions where left end expansion is performed.
temp = (data &0xFF);
wdata = (temp << 24) | (temp << 16) | (temp << 8) | temp;

FIG. 14B shows an example in which right end expansion is performed when the data width of the transferred data is 1 byte. In this example, 1-byte data “Y3” is the rightmost data, so that four “Y3” connected are 4-byte extension data. The 15th to 16th lines in the program example of FIG.
temp = (data >> 24) &0xFF;
wdata = (temp << 24) | (temp << 16) | (temp << 8) | temp;

FIG. 14C shows an example in which the left end extension is performed when the data width of the transferred data is 2 bytes. In this example, since the 2-byte data “Y0a” and “Y0b” are the leftmost data, a combination of two “Y0a” and “Y0b” becomes 4-byte extension data. Specifically, this corresponds to a case where a pixel handles a 2-byte long luminance signal. This is also the case when the 1-byte long color difference signals Cb and Cr are arranged in order, and Cb and Cr are combined and handled as 2 bytes. The program in this case is as follows.
temp = (data &0xFFFF);
wdata = (temp << 16) temp;

FIG. 14D shows an example in which right end expansion is performed when the data width of transferred data is 2 bytes. In this example, since the 2-byte data “Y1a” and “Y1b” are the rightmost data, the data obtained by connecting two “Y1a” and “Y1b” is the 4-byte extension data. The program in this case is as follows.
temp = (data >> 16) &0xFFFF;
wdata = (temp << 16) temp;

  FIG. 14E shows an example in which left end expansion is performed when the data width of transferred data is 4 bytes. In this example, since 4-byte data “Y0a”, “Y0b”, “Y0c”, and “Y0d” are the leftmost data, “Y0a”, “Y0b”, “Y0c”, and “Y0d” are 4-byte extension data. Specifically, this corresponds to the case where four 1-byte data to which α representing transmittance is added in addition to RGB is assigned to one pixel.

FIG. 14F shows an example in which right end expansion is performed when the data width of the transferred data is 4 bytes. In this example, since 4-byte data “Y0a”, “Y0b”, “Y0c”, and “Y0d” are the rightmost data, “Y0a”, “Y0b”, “Y0c”, and “Y0d” are 4-byte extension data. Accordingly, the programs in FIGS. 14E and 14F are as follows.
wdata = data;

  The data sorting according to the data width is performed in the data sorting unit 174. The data width value is held in the data width of the transfer control register (CTL) 670 of the control register 171 shown in FIG. 7, and the transfer control unit 176 instructs the data alignment unit 174 to rearrange according to this value. Is done.

Here, an example of the relationship between the data width and end extension in the case of neighborhood extension has been described, but the present invention can be similarly applied to setting value extension. For example, in the case of handling 2-byte data in setting value extension, the setting value preset is set for 2 bytes, and extension data is generated as follows.
temp = preset &0xFFFF;
wdata = (temp << 16) | temp;
FIG. 15 is a diagram illustrating an example in which a 2-byte set value extension is performed in the embodiment of the present invention.

Also, when handling 4-byte length data in the set value extension, the set value preset is set for 4 bytes, and the 4-byte data is written as it is.
wdata = preset;

  FIG. 16 is a diagram showing another example of the relationship between the data width of transferred data and end extension in the embodiment of the present invention.

  As another aspect of the edge extension of the image data, it is conceivable to deal with luminance color difference data. There are cases in which two pixels are represented by four 1-byte data based on the sequence of luminance and color difference data {Y0, Cb, Y0, Cr}. In this case, when performing left end expansion, the left end luminance “Y0” is expanded by two pixels as shown in FIG. 16A, and “Cb” and “Cr” representing two pixels are used for the color difference. Can do. On the other hand, when performing the right end expansion, the right end luminance “Y1” is expanded by two pixels as shown in FIG. 16B, and “Cb” and “Cr” representing two pixels are similarly used for the color difference. be able to. These rearrangements are also performed in the data alignment unit 174.

  As described above, according to the embodiment of the present invention, the data transferred from the frame memory 140 to the buffer 173 is rearranged by the data alignment unit 174 and transferred to the local memory 160, so that the data is transferred in parallel with the DMA transfer. Extended processing can be performed. Thereby, the time required for the edge extension processing can be concealed, and the entire image processing time can be shortened.

  Further, according to the embodiment of the present invention, the end of image processing can be performed by a simpler program, so that the program code can be reduced. As a result, the amount of memory used to store the program can be reduced.

  In the embodiment of the present invention, the DMAC having the minimum function is shown for the sake of simplicity. However, a generally well-known DMAC function may be installed as long as the end extension can be realized. .

  A general DMAC uses a burst function in order to perform transfer at high speed. In the embodiment of the present invention, only transfer of 4 bytes length is shown, but the buffer 173 is configured by a buffer of 16 bytes width, for example, and the transfer control unit 176 determines whether burst transfer is possible and transfer is possible. In such a case, if the control is performed so that 4-burst transfer of 4 bytes is issued, a higher-performance DMAC can be realized.

  In a general DMAC, a transfer size in units of 1 byte or 2 bytes can be specified without being limited to a unit of 4 bytes, and an address corresponding to the transfer size can also be specified. In the embodiment of the present invention, it is assumed that only a 4-byte boundary is supported, but other units of transfer may be supported.

  A general DMAC supports transfer between the same buses, and the transfer specifications are often symmetric. In the embodiment of the present invention, the DMAC is used only for the transfer between the frame memory and the local memory, but may be used for the transfer between the same memories. Further, in the embodiment of the present invention, the end extension corresponds only to the case of transfer from the frame memory to the local memory, and the asymmetric specification in which the rectangular area is only the frame memory is assumed, but other types of memory transfer are also supported. The specifications may be symmetrical. For example, when the local memory also supports rectangular area transfer, there is an advantage that the processing is simplified because it is not necessary to pack pixels in the filtering process. In the embodiment of the present invention, since the specification is asymmetric, there are two types of flowcharts as described above, but other transfers are also controlled in accordance with the flowcharts of FIGS. 9 and 10 for transferring from the frame memory to the local memory. You may do it.

  Some known DMACs have a byte swap function. For example, when the endian of byte-length data is switched, the data transferred as {Y0, Y1, Y2, Y3} is rearranged to {Y3, Y2, Y1, Y0}. The DMA control unit 170 in the embodiment of the present invention may also have a byte swap function. In this case, the circuit scale can be reduced by integrating the rearrangement of the end extension and the rearrangement of the byte swap. The designation of the rearrangement is determined by the transfer control unit 176 and instructed to the data alignment unit 174.

  Among known DMACs, register settings necessary for DMA transfer are generated as a list on a memory, the address is set in a control register, the next list is read automatically after transfer is completed, and automatically Some have a linked list function that initiates the next transfer. The DMA control unit 170 in the embodiment of the present invention may also have a link list function. Since the CPU can generate the link list during the DMA transfer, the processing time required for the DMA transfer setting can be hidden, and the processing can be performed at high speed.

  In the embodiment of the present invention, the number of taps is assumed to be four, up, down, left and right, but is not limited to this. Normally, it does not expand both up and down, so for example, only one vertical tap register is prepared, a negative value means an upper expansion, a positive value means a lower expansion, If “0”, the specification may mean that it does not expand in the vertical direction. The same applies to the horizontal end extension. This specification can reduce the number of registers to be set.

In the embodiment of the present invention, the rectangle size and the start address are specified for the effective pixel portion when setting transfer with end extension processing. However, the specification is such that the rectangle size is specified for the entire invalid portion. May be. Here, as shown in FIG. 17, the frame memory start address (AF ′) 611, the rectangular area vertical size (V ′) 631, and the rectangular area horizontal size (H ') Assuming 641, the following relational expression holds.
H = H '-(R + L)
V = V '-(U + D)
AF = AF ′ + U × H ′ + L
Therefore, if the transfer control unit 176 performs processing such that the control register 171 is rewritten once at the start of transfer, the above configuration can be realized. With this specification, the rectangular area vertical size (V ′) 631 and the rectangular area horizontal size (H ′) 641 have the same value regardless of whether the rectangular area is the end of the image. The program to be set can be made simpler.

  The DMA control unit 170 according to the embodiment of the present invention controls transfer by directly rewriting the value of the control register 171. However, the control register 171 is provided in another set, and all registers are fetched at the beginning of DMA transfer. You may do it. With this configuration, the value of the register recognized by the CPU does not change even when DMA transfer is performed. Therefore, the value of the rectangular area vertical size (V) 630 and the rectangular area horizontal size (H) 640 is changed. When it is not necessary, it is not necessary to rewrite. Thereby, a program can be reduced. It is also possible to set the next DMA transfer during the DMA transfer.

  In the embodiment of the present invention, the end extension is performed simultaneously during the DMA transfer that can operate in parallel with the processor, so that the processing time for the end extension can be hidden. In particular, it is effective for an image processing LSI that processes two-dimensional data at high speed, and can be applied to a digital camera, a digital video camera, a game machine, or the like equipped with the image processing LSI.

  The embodiment of the present invention is an example for embodying the present invention, and has a corresponding relationship with the invention-specific matters in the claims as described above. However, the present invention is not limited to the embodiments, and various modifications can be made without departing from the scope of the present invention.

  The processing procedure described in the embodiment of the present invention may be regarded as a method having a series of these procedures, and a program for causing a computer to execute the series of procedures or a recording medium storing the program May be taken as As this recording medium, for example, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disk), a memory card, a Blu-ray Disc (registered trademark), or the like can be used.

It is a figure which shows one structural example of the data transfer apparatus in embodiment of this invention. It is a figure which shows the example of 1 structure of the DMA control part 170 in embodiment of this invention. It is a figure which shows an example of the address map of the control register 171 in embodiment of this invention. It is a figure which shows the image data of 1 frame in embodiment of this invention. It is a figure which shows the example of designation | designated of the end extension in embodiment of this invention. It is a figure which shows the classification of the edge expansion method in embodiment of this invention. It is a figure which shows the example of a field structure of the transfer control register (CTL) 670 in embodiment of this invention. It is a figure which shows the example of a transition of the image data in the local memory 160 in embodiment of this invention. It is a figure which shows the first half of the example of a process sequence of the DMA transfer from the frame memory 140 to the local memory 160 in embodiment of this invention. It is a figure which shows the second half of the example of a process sequence of the DMA transfer from the frame memory 140 to the local memory 160 in embodiment of this invention. It is a figure which shows an example of the program which performs the DMA transfer process from the frame memory 140 to the local memory 160 in embodiment of this invention. It is a figure which shows the example of a process sequence of the DMA transfer from the local memory 160 to the frame memory 140 in embodiment of this invention. It is a figure which shows an example of the program which performs the DMA transfer process from the local memory 160 to the frame memory 140 in embodiment of this invention. It is a figure which shows the example of a relationship between the data width of the data transferred, and an end extension in embodiment of this invention. It is a figure which shows the example which performed the setting value extension of 2 bytes in embodiment of this invention. It is a figure which shows the other example of a relationship between the data width of the data transferred in the embodiment of the present invention, and end extension. It is a figure which shows the other example of an end extension in embodiment of this invention.

Explanation of symbols

110 CPU
120 ROM
130 Image signal input / output unit 140 Frame memory 160 Local memory 170 DMA control unit 171 Control register 172 Bus control unit 173 Buffer 174 Data alignment unit 175 Data control unit 176 Transfer control unit 177 Internal register 190 Bus 610 Frame memory start address (AF)
620 Local memory start address (AL)
630 Rectangular area vertical size (V)
640 Horizontal size of rectangular area (H)
651 Upper tap (U)
652 Lower tap (D)
653 Left tap (L)
654 Right tap (R)
660 frame memory horizontal size (W)
670 Transfer control register (CTL)
680 Set value register (PR)

Claims (5)

A data holding unit that reads and holds data of the rectangular area from a transfer source memory that holds a rectangular area including data of a two-dimensional structure ;
An extension width setting unit for setting an extension width of an end in the rectangular area;
A data alignment unit for aligning data held in the data holding unit according to the set extension width to generate extended data at an end in the rectangular area;
A data transfer unit for transferring the data held in the data holding unit and the extension data to a transfer destination memory ;
The data alignment unit, wherein the data alignment unit uses end data in the vicinity of the two-dimensional structure data as the extension data . The rectangular area includes image data corresponding to a plurality of pixels,
The data transfer device according to claim 1, wherein the data alignment unit aligns the image data in units of pixels to generate extended data at an end in the rectangular area. A data holding unit that reads and holds data of the rectangular area from a transfer source memory that holds a rectangular area including data of a two-dimensional structure ;
An extension width setting unit for setting an extension width of an end in the rectangular area;
An extension mode setting unit for setting an extension mode of an edge in the rectangular area;
A setting data holding unit that holds setting data extended to an end in the rectangular area;
Wherein in accordance with the set expanded width and the extended mode, the data end in the vicinity of the data of the two-dimensional structure which is held in the data holding unit, in the rectangular region by aligning the zero value data or the configuration data A data alignment unit for generating end extension data;
A data transfer apparatus comprising: a data transfer unit that transfers data held in the data holding unit and the extension data to a transfer destination memory. An extension width setting procedure for setting an extension width of an end of the rectangular area when reading the data of the rectangular area from a transfer source memory holding a rectangular area including data of a two-dimensional structure ;
A data read procedure for reading data of the rectangular area from the transfer source memory;
A data alignment procedure for aligning the read data according to the set expansion width to generate extended data at an end of the rectangular area;
A data transfer procedure for transferring the read data and the extension data to a transfer destination memory ,
The data transfer method , wherein, in the data alignment procedure, end data in the vicinity of the two-dimensional structure data is used as the extension data . An extension width setting procedure for setting an extension width of an end of the rectangular area when reading the data of the rectangular area from a transfer source memory holding a rectangular area including data of a two-dimensional structure ;
A data read procedure for reading data of the rectangular area from the transfer source memory;
A data alignment procedure for aligning the read data according to the set extension width, and generating end data near the two-dimensional structure data as end extension data in the rectangular area;
A program for causing a computer to execute a data transfer procedure for transferring the read data and the extension data to a transfer destination memory.

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