JP2009100313A - Image processing device and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low cost image processing device can performing image rotation processing faster than central processing unit (CPU) processing while using a small-capacity memory. <P>SOLUTION: The image processing device includes: paired memories which alternately input and output image data; paired memories which alternately input and output image data output from the memories; and an address generating circuit which generates an address for rotating image databased on a rotation angle value and outputs the address to the memories, respectively. Source image data are divided, alternately input to the paired memories in order and data alternately output from the memories are input to the following paired memories using the generated address, and then output. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus that performs rotation processing on an image and an image forming apparatus that uses the image processing apparatus.

  In the invention described in Patent Document 1, an image processing apparatus that uses a large-capacity memory for an input unit and an output unit and performs rotation processing of an input image in the following processing order. First, image data is input to a first memory (large capacity). Next, a part of the image data is output from the first memory and input to the second memory (small capacity), and the image is rotated on the second memory. Further, the processed image data is output from the second memory and input to the third memory (large capacity). This process is repeated for all the image data in the first memory, and the image data after the rotation process of the image input to the first memory is input to the third memory. Finally, a technique for outputting image data in the third memory is disclosed.

Patent Document 2 discloses an image processing method for determining the direction and inclination of an input image and correcting the inclination of the image. This method is realized as a computer program, and is a technique for performing image rotation processing by a CPU (Central Processing Unit).
JP 2006-005499 A JP 2003-259111 A

  However, in the invention described in Patent Document 1, since a large capacity memory is used for the input unit and the output unit, there is a problem that the device becomes expensive. Further, in the invention described in Patent Document 2, since the image is rotated by the CPU, there is a problem that the processing is slow.

  The present invention has been made in consideration of the above circumstances, and provides a low-cost image processing apparatus that can perform image rotation processing using a small-capacity memory at a higher speed than CPU processing. Objective.

  In order to solve the above-mentioned problem, the invention according to claim 1 outputs a pair of first and second memories that alternately input and output image data, and the first and second memories. Based on the inputted third angle and fourth memory that alternately input and output image data to be output, and an input predetermined angle value, an address for rotating the original image data is generated to generate the first to the first memories. Each of the first and second memories is divided and sequentially input to the first and second memories, and the first image data is sequentially input to the first and second memories. Data is alternately output from the second memory and the output data is alternately input to the third and fourth memories using the address output from the address generation circuit, and the third and second memories are input. Output data alternately from 4 memory Characterized by an image processing apparatus for obtaining image data by rotating the image data by.

  According to a second aspect of the present invention, in the image processing apparatus according to the first aspect of the present invention, means for holding data of each of nine pixels including eight pixels around the target pixel, and rotation of the target pixel from the nine pixels An interpolation circuit further comprising: means for selectively outputting three pixels close to the later address; and means for calculating and outputting interpolation data from four pixels of the three pixels and the target pixel. Output data from a memory is input to the interpolation circuit, and output data from the interpolation circuit is input to the third and fourth memories.

  According to a third aspect of the present invention, a pair of first and second memories that alternately input and output image data and image data output from the first and second memories are alternately input. The fifth and sixth memories that form a pair to be output, and the third and fourth memories that form a pair that alternately input and output the image data output from the fifth and sixth memories are input Original image data held by an input image holding means, having an address generation circuit that generates an address for rotating the original image data based on a predetermined angle value and outputs the address to the first to fourth memories Are sequentially input to the first and second memories in order, and data are alternately output from the first and second memories, and the output data is output from the address generation circuit. Use the third and fourth memory Alternately input, alternately output data from the third and fourth memories, and alternately input the output data to the fifth and sixth memories and alternately from the fifth and sixth memories. And outputting data.

  According to a fourth aspect of the present invention, in the image processing apparatus according to the third aspect of the present invention, means for holding nine pixels including eight pixels around the target pixel, and an address after rotation of the target pixel from the nine pixels An interpolation circuit comprising: means for selectively outputting three pixels; and means for calculating and outputting interpolation data from the four pixels of the three pixels and the target pixel, and output data from the first and second memories It is input to the interpolation circuit, and output data from the interpolation circuit is input to the third and fourth memories.

  According to a fifth aspect of the present invention, a first first-in first-out type memory to which image data is input and a first and a first pair that input and output the image data output from the first first-in first-out type memory alternately. 2, an address generation circuit that generates an address for rotating the original image data based on the input predetermined angle value, and outputs the address to the first and second memories, and the first and second A second first-in first-out type memory that inputs data alternately output from the first memory, and divides the original image data held by the input image holding unit into the first first-in first-out type memory in order. And the output data from the first first-in first-out memory is alternately input to the first and second memories using the address output from the address generation circuit, and the first and second memories are input. The output data alternately from the memory and input to the second first-in-first-out memory, outputted from the second first-in-first-out memory, it is characterized.

  According to a sixth aspect of the present invention, in the image processing device according to the fifth aspect of the present invention, means for holding data of each of nine pixels including eight pixels around the target pixel, and after the rotation of the target pixel from the nine pixels An output from the first first-in first-out memory is further provided with an interpolation circuit comprising means for selectively outputting three pixels close to the address and means for calculating and outputting interpolation data from four pixels of the three pixels and the target pixel. Data is input to the interpolation circuit, and output data from the interpolation circuit is input to the first and second memories.

  According to a seventh aspect of the present invention, an image input unit that scans an image forming apparatus document to convert it into image data, an image forming unit that prints image data on a sheet, and a document or an image inclination in the scanned image are detected. And an image processing apparatus according to any one of claims 1 to 6.

  According to the present invention, it is possible to provide a low-cost and high-speed image processing apparatus that performs image rotation processing using a small-capacity memory. In particular, the apparatus including the interpolation circuit can prevent the deterioration of the image quality due to the image rotation.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a schematic diagram of a configuration of an image forming apparatus including an image processing apparatus as an embodiment according to the present invention. The present embodiment can be applied as an image forming apparatus in a copying machine, a printer, a multifunction machine (equipment having functions of a copying machine, a printer, a scanner, and a facsimile machine). The illustrated image forming apparatus 100 optically reads a document and outputs it from a scanner 1 as an image input unit that converts the image data into image data, a printer 2 as an image output unit that prints and outputs image data on paper, and outputs from the scanner 2. Hard disk device 3 for storing the image data and computer program for controlling the overall operation of the apparatus, operation unit 4 for operating the apparatus by a user (buttons, touch panel, liquid crystal display for displaying characters and images) CPU 5 (Central Processing Unit) for controlling the operation of this apparatus, main memory 6 that temporarily stores data and computer programs accessed by CPU 5 and functions as image storage means, and image data The image rotation processing unit 10 as an image rotation means for performing the rotation processing of Al is connected via a data bus 7 for exchanging various kinds of data.

  In order to correct the inclination of the document or image in the scanned image by the image rotation processing unit 10, first, the inclination angle α of the document or image is detected. As the detection method, for example, any one of the following known methods disclosed in Patent Document 1 described above may be used. In the first method, the CPU 5 detects the four vertex coordinates of the document and detects them from the positional relationship of these vertex coordinates. Alternatively, as a second method, a prescan image of a document is displayed on the liquid crystal display device of the operation unit 4, and the user reads the tilt angle based on the prescan image and inputs it as an image rotation angle α for correcting the tilt. Then, the CPU 5 performs a predetermined input process, and inputs the rotation angle α to the image rotation processing unit 10 via the data bus 7.

[First embodiment]
The configuration of the first embodiment of the image rotation processing unit is shown in the block diagram of FIG. The image rotation processing unit 10A includes a buffer circuit 11 that separates bidirectional data of the data bus 7 into input data and output data, a pair of first memory 12A and second memory 12B that alternately input input data, A first data selector 13 that selects and outputs the output data of the memory 12A and the second memory 12B, a pair of third memory 14A and a fourth memory 14B that alternately input the data output from the first data selector, A second data selector 15 that selects and outputs the output data of the third memory 14A and the fourth memory 14B, a first write address generation circuit 16 that generates a write address of the first memory 12A and the second memory 12B, and the first memory 12A And a first read address generation circuit 17 for generating a read address of the second memory 12B, an input after rotating the image by inputting the rotation angle. And a second write address generation circuit 18 (see FIG. 22) that outputs the write address of the third memory 14A and the fourth memory 14B, and a second address that generates a read address of the third memory 14A and the fourth memory 14B. Address selectors 21 to 24 (first address selector to fourth address) for switching addresses corresponding to input / output operations of the read address generation circuit 19, the first memory 12A and the second memory 12B, and the third memory 14A and the fourth memory 14B. And a control circuit 25 for switching input data of each address selector and each data selector, read / write control of each memory, and switching data input / output of the buffer circuit. The rotation angle data α is input to the image rotation processing unit 10 via the data bus separately from the image data, and is input to the second write address generation circuit, but the circuit for that is not shown.

  FIG. 3 shows the relationship between an input image and an output image when image rotation processing is performed according to this embodiment, and image data input / output to / from the first memory 12A to the fourth memory 14B. In order to simplify the description, here, a case will be described in which an input image is processed by being divided into five (A, B, C, D, E) in the sub-scanning direction. The input image is stored in the memory of FIG. Here, the data of one pixel is 8 bits (1 byte), and an address in byte units is assigned and stored in the memory. In the case of a monochrome image, the input image is processed for one surface, but in the case of a color image, three surfaces of R (red), G (green), and B (blue) are processed in order. The image data divided into five parts is read out in the order of the main scanning direction, and the pixel data is alternately input to the first memory 12A and the second memory 12B via the data bus 7.

  In FIG. 1, when transferring image data between the memory and the image rotation processing unit 10 via the data bus 7, in general, for example, 64 bytes, 128 bytes, etc., rather than transferring pixel data one by one. As described above, it is possible to transfer a large amount of data at high speed by continuously transferring the data. For this reason, the data input unit and data output unit of the image rotation processing unit 10 need a memory for temporarily storing data. The first memory 12A, the second memory 12B, the third memory 14A, and the fourth memory 14B also play this role.

  In particular, by using a pair of first memory 12A and second memory 12B for data input and a pair of third memory 14A and fourth memory 14B for data output, data input from the data bus Since data output to the data bus can be performed continuously, the processing can be efficiently and speeded up. FIG. 4 shows the internal configuration of the first memory 12A and the second memory 12B, and FIG. 5 shows the internal configuration of the third memory 14A and the fourth memory 14B.

  In FIG. 4, data input (writing) to the memory unit is performed in units of 16-bit data. The data output is output via a data selector in order to output the upper 8 bits and the lower 8 bits of the 16-bit data output from the memory unit as individual address data. The input data of the data selector is switched using the lower 1-bit data of the read address in 8-bit data units. Thus, data input (write) to the memory unit can be performed in units of 16-bit data, and data output (readout) can be performed in units of 8-bit data.

  In FIG. 5, data input (write) to the memory unit is performed in 8-bit data units, and data output (read-out) is performed in 16-bit data units. A memory unit is used in which the number of bits of input / output data is 16 bits and data can be written in 8-bit data units. The signal line of each bit of 8-bit input data is branched into two, and the input 8-bit data is changed to 16-bit data arranged in upper 8 bit data and lower 8 bit data. Whether the upper 8-bit data or the lower 8-bit data of the 16-bit data input to the memory unit is written to the memory unit is determined by a write address in units of 8-bit data. For example, if the write address of the 8-bit data unit is an even number, the lower 8 bit data is written into the memory unit, and if the write address is an odd number, the upper 8 bit data is written into the memory unit. As a result, data input (write) to the memory unit can be performed in 8-bit data units, and data output (read-out) can be performed in 16-bit data units.

  By configuring the first memory 12A, the second memory 12B, and the third memories 14A and 4 in FIG. 2 as shown in FIGS. 4 and 5, image rotation processing is performed in units of 8-bit data. In this case, data transfer can be performed in units of 16-bit data. As a result, the data input / output (write / read to / from memory) time from the data bus 7 is half the write / read time to / from the 8-bit data unit memory at the time of image rotation processing. As a result, the input / output of image data and the rotation processing can proceed simultaneously, and efficient high-speed processing becomes possible.

  Hereinafter, an input / output method of image data to the first memory 12A to the fourth memory 14B when image rotation processing is performed will be described with reference to FIG.

  First, the image data A is input to the first memory 12A. Thereafter, the image data B is input to the second memory 12B. The addresses output from the first write address generation circuit are used for these inputs. In parallel with the input to the second memory 12B, the image data A input to the first memory 12A is sequentially input from the first memory 12A in the main scanning direction using the address output from the first read address generation circuit. And outputs the rotated address output from the second write address generation circuit to the third memory 14A. At this time, A1, which is a part of the image data A, is a portion that protrudes from the output image after rotation, and thus is not input to the third memory 14A. The A2 portion is input to the third memory 14A and the A3 portion is input to the fourth memory 14B. In addition to A1, there is a portion that protrudes from the output image due to the rotation of the image, but this is also not input to the third memory 14A and the fourth memory 14B. At this time, since all the image data A input to the first memory 12A has already been output, the image data C is input to the first memory 12A.

  Next, in parallel with the input to the first memory 12A, the image data B input to the second memory 12B is output from the second memory 12B in the order of the main scanning direction and output from the second write address generation circuit. Using the post-rotation address, the B1 portion is input to the third memory 14A and the B2 portion is input to the fourth memory 14B. When the portion B1 is completely input to the third memory 14A, data output from the third memory 14A is started using the address output from the second read address generation circuit. After the data output from the third memory 14A is completed, the portion B3 is input to the third memory 14A. At this time, since all the image data B input to the second memory 12B has been output, the image data D is input to the second memory 12B. Thereafter, this process is repeated sequentially.

  A timing chart of data input / output (writing and reading) of each memory at this time is shown in FIG. When the image data A2 and B1 have been input to the third memory 14A, the data of the third memory 14A is output. When the image data A3, B2, and C1 have been input to the fourth memory 14B, the data of the fourth memory 14B is output. In the timing chart, image data such as A2, A3, B1, and B2 are written together to make the processing operation easy to understand. However, actually, the image data in the first memories 12A and 2 are read in the order of the main scanning direction, and therefore, one column in the main scanning direction (hereinafter, this may be referred to as one line). Since the data becomes A2 and A3 or B1 and B2, the data writing of A2 and A3 and the data writing of B1 and B2 are performed within the data writing time for one line.

  In this manner, the divided image data is alternately input to the pair of memories of the input stage unit of the image rotation processing unit 10, and the rotated address is used alternately for the pair of memories of the output unit. By inputting and outputting image data, the output image after rotation can be divided and output. The output image data is stored in the main memory 6 of FIG.

FIG. 7 shows the control timing of each control signal related to the control circuit 25 in FIG.
FIG. 7 will be described in detail. The symbols and functions of the control signals shown in FIG. 2 and FIG. 7 are collectively shown below.
a1: Address selector 1 switching signal
a2: Address selector 2 switching signal
a3: Address selector 3 switching signal
a4: Address selector 4 switching signal
d1: First data selector switching signal
d2: Second data selector switching signal
m1: Read / write switching signal of the first memory 12A
m2: read / write switching signal of the second memory 12B
m3: read / write switching signal of the third memory 14A
m4: read / write switching signal of the fourth memory 14B
bsel: Buffer circuit data input / output switching signal

  Address switching, output data switching, and read / write switching are performed in accordance with the operations of the first memory 12A, the second memory 12B, the third memory 14A, and the fourth memory 14B shown in the timing chart of FIG. In particular, the input / output switching operation of the data input / output switching signal (bsel) of the buffer circuit 11 and the data are read from the first memory 12A and the second memory 12B for the image rotation process, and the third memory 14A and the fourth memory 14B are read. A unique feature is that the operation of writing to the memory 14B proceeds simultaneously. Thereby, efficient high-speed processing is realized.

  FIG. 8 shows an address generation method after image rotation. The input image (original image data) before rotation is an image composed of W pixels in the main scanning direction and L lines in the sub-scanning direction. Assume that the main scanning direction is the x axis, the sub scanning direction is the y axis, and the coordinates of a certain pixel before rotation are (x, y). The upper left of the pre-rotation image in the figure is the origin (0, 0). Since the coordinates are addresses of the memory storing the pixel data, in the figure, the area on the right side of the origin is x> 0 and the left side is x <0, the area above the origin is y <0, and the area below y> 0 And

If the image is rotated by an angle θ around the origin as shown in the figure, and the coordinates of a certain pixel after being translated so that the center coordinates of the image are approximately the same before and after the rotation are (X, Y), The coordinates (x, y) and (X, Y) before and after the rotation have the following relationship.
X = xcosθ-ysinθ + W '(Formula 1)
Y = xsinθ + ycosθ-L '(Formula 2)
However,
W '= (L / 2) sinθ (Formula 3)
L '= (W / 2) sinθ (Formula 4)
Since (X, Y) is the coordinates of the entire output image, an address is generated by dividing this so as to correspond to the memory of the output unit.

  x and X indicate pixel numbers on one line, and y and Y indicate line numbers. The internal configuration of the second write address generation circuit in FIG. 2 is shown in a block diagram in FIG. The illustrated circuit includes a pre-rotation address generation circuit (which can be realized by a counter circuit) that generates a pre-rotation address (x, y), a table (which can be realized by a memory) that converts a rotation angle θ into cos θ and sin θ, a multiplier, It consists of an adder and a subtracter, and outputs X and Y shown in Equation 1 and Equation 2 based on the input rotation angle θ and the pre-rotation address (x, y) generated in accordance with the clock signal. . In the figure, values to be generated for each part are shown.

  In this embodiment, since the image is divided and input to the memory in the sub-scanning direction, the address (X: pixel number) in the main operation direction is directly stored in the divided memory (the third memory 14A and the fourth memory 14B). Used for main operation direction address. The sub-scanning direction address (Y: line number) of the divided memory (the third memory 14A and the fourth memory 14B) is generated as follows.

  For example, as shown in FIG. 10, it is assumed that the line number (Y) of the address after rotation is 16-bit data, and the number of lines in the divided memory is 1024 lines. The lower 10 bits are used for the addresses in the sub-scanning direction of the third memory 14A and the fourth memory 14B. The eleventh bit is used as a switching signal between the third memory 14A and the fourth memory 14B (from the second write address generation circuit). For example, if the 11th bit is “0”, the third memory 14A is selected, and if the 11th bit is “1”, the fourth memory 14B is selected. Accordingly, the third memory 14A and the fourth memory 14B are automatically switched alternately with an increase in Y (the line number after rotation).

  As described above, in this embodiment, the divided memory has at least the capacity of the pixel data in the main operation direction and divides the image in the sub-scanning direction, so that it is easy to generate the addresses of the divided memories and switch the memories. Is done.

  If the pixel number: X becomes negative or exceeds W, or if the pixel number: Y becomes negative or exceeds L, the pixel protrudes from the output image and is not input to the memory of the output unit (reflecting) Not) On the other hand, a portion without pixel data is generated in the output image due to the rotation. Therefore, in order to input (complement) pixel data that does not cause a sense of incongruity in this portion, as shown in FIG. 11, a specific pixel is set in a predetermined area of the memory (third memory 14A and fourth memory 14B) of the output unit. It is good to write data. For example, in the case of a white, black, gray, or color image, a specific color, a specific image data pattern such as a stripe pattern, a lattice pattern, or a polka dot pattern is written. Also, the first line and the last line of the input image, the first pixel and the last pixel of each line are read in advance, the data of the first line of the input image is at the upper part of the writing area of the figure, and the data of the last line is the figure. The first pixel data of each line may be written in the left part of the writing area in the drawing, and the data of the final pixel may be written in the right part of the writing area in the drawing. As a result, it is possible to eliminate a sense of incongruity in the area without the image data around the output image.

  As described above, in the image processing apparatus including the image rotation processing unit 10 according to the first embodiment, a pair of small-capacity memories that alternately input and output data are used for the input unit and the output unit, and the image data is divided. Then, the image is input in order to the memory of the input unit, and an address obtained by rotating the image corresponding to a predetermined angle value obtained separately is generated and input to the memory of the output unit. By using it, an image processing apparatus that performs image rotation processing at a higher speed than in the case of known CPU processing can be realized at a low price.

[Second Embodiment]
Next, FIG. 12 shows a second embodiment of the image rotation processing unit. The image rotation processing unit 10B has substantially all the configuration corresponding to the first embodiment, and further includes an interpolation circuit 30 between the first data selector 13, the third memory 14A, and the fourth memory 14B. It has an inserted configuration. The coordinate transformation calculation results shown in the above Equations 1 and 2 are rounded to an integer value because they are the addresses of the memory storing the pixel data. If it is a decimal number, it is rounded off to the nearest decimal place, and if it is a binary number, it is rounded to the nearest decimal point. For this reason, the position of the pixel data after rotation is often shifted from the address in the output image. As a result, for example, the straight line of the input image becomes a stepped line in the output image after rotation, and image quality deterioration occurs. In order to prevent this, in the second embodiment, an interpolation circuit 30 that generates pixel data on an address in the output image by interpolation calculation using the nearest four pixels is inserted.

  FIG. 13 shows an example of changes in the nearest four pixels used for the interpolation calculation depending on the positional relationship between the position after rotation of the target pixel (coordinates of the calculation result before rounding) and the address after rotation after rounding. Show. There are the following four positional relationships depending on the rounding method. Here, since the purpose is to rotate the image for correcting the inclination of the document, it is assumed that the rotation angle of the image is small and the rotation angle is less than ± 45 degrees.

(A) to (d) in FIG.
(a) .... Rounded down to the nearest X and rounded to the nearest Y.
(b) ... rounded up to the nearest X and rounded to the nearest Y
(c) ......... Rounded off the decimal point of X and rounded up the decimal point of Y
(d)... Rounds up the decimal point of X and rounds up the decimal point of Y.

As shown in the figure, when 9 pixels including 8 pixels around the pixel of interest are numbered from 1 to 9, the nearest 4 pixels in each of the above cases are as follows.
(a) ……… 1, 2, 4, 5
(b) ……… 2, 3, 5, 6
(c) ……… 4, 5, 7, 8
(d) ……… 5, 6, 8, 9

  Further, when the above nine pixels are extracted from the input image, there may be no adjacent pixel of the pixel of interest in the periphery of the image. FIG. 14 shows a method for extracting nine pixels in the peripheral portion of the input image. As shown in the figure, the target pixel is the first pixel on the line, the last pixel, or any other intermediate pixel, or the target pixel is the pixel on the first line, the pixel on the last line, or any other There are nine processes depending on whether the pixel is on the middle line. In this method, except for the case of the intermediate line intermediate pixel ((5) in FIG. 14), in correcting the pixel at the outer edge of the image, the pixel data of the peripheral portion of the image is copied by one pixel to the outside. Extract pixels.

  FIG. 15 is a block diagram showing an example of the configuration of an interpolation circuit that realizes the processing method shown in FIGS. In the interpolation circuit 30 of FIG. 15, pixel data is input one by one (1 byte), and a matrix arrangement of 3 pixels × 3 pixels is provided by the delay circuit 31 (31a to 31f) and the memory 32 (32a, 32b) for one line. 9 pixels are held. In the data selector 33 in the figure, the three-pixel selection condition data indicating which of the four types shown in FIG. 13 corresponds to the rounding method of the coordinate conversion calculation, and the target pixel is in any of the nine types shown in FIG. Peripheral processing selection condition data indicating whether it is applicable is input, three pixels other than the target pixel are selected and output, and input to the interpolation calculation circuit 34. Since the target pixel data 5 is always used for the interpolation calculation, it is input to the interpolation calculation circuit without passing through the data selector. In this way, the nearest four pixels necessary for the interpolation calculation are input to the interpolation calculation circuit.

  Hereinafter, processing in the interpolation calculation circuit will be described. FIG. 16 shows the positional relationship between the four pixels (P1, P2, P3, P4) used during the interpolation calculation and the output pixel (N) generated by the interpolation calculation. In the figure, the pixel of interest is P1. The difference between the position after rotation of the pixel of interest (coordinates of calculation results before rounding) and the address after rotation of the pixel of interest (coordinates of calculation results after rounding) is a rounding error. The rounding error in the main scanning direction is α, and the rounding error in the sub scanning direction is β.

In order to generate the pixel of interest N by interpolation calculation from the four pixels after rotation, it is necessary to calculate the distance between N and the four pixels P1, P2, P3, and P4 in the rotation coordinates. We define p and q in the figure as the distance. Assuming that P1, P2, P3, P4, N, N1, and N2 indicate pixel data values (8 bits), the output pixel N is calculated by the following equation.
N1 = p · P2 + (1−p) · P1 (Formula 5)
N2 = p.P4 + (1-p) .P3 (Formula 6)
N = q · N2 + (1−q) · N1 (Formula 7)
In order to perform the above equation, p and q are calculated from α and β. As shown in (1) to (4) of FIG. 13, there are four positional relationships between the position of the pixel of interest after rotation and the address after rotation. Correspondingly, the results of p and q expressed as α and β and the rotation angle θ are shown in FIGS.

In summary, p and q are expressed by the following equations.
In the case of (1) and (4), p = α / cosθ + (βcosθ-αsinθ) tanθ (Equation 8)
q = βcosθ-αsinθ (Equation 9)
In the case of (2) and (3), p = αcosθ-βsinθ (Equation 10)
q = β / cosθ + (αcosθ−βsinθ) tanθ (Expression 11)

If the rotation angle θ is small (θ≈0), further simplified p and q can be obtained using the following approximate expression. However, the unit of θ is radian.
cosθ≈1 (Formula 12)
sinθ≈θ (Formula 13)
tanθ≈θ (Formula 14)
θ ² ≈ 0 (Equation 15)
・ Approximate expression p in the case of (1) and (4) ≒ α + βθ (Expression 16)
q ≒ β-αθ (Equation 17)
・ Approximation formula p in the case of (2) and (3) ≒ α-βθ (Equation 18)
q ≒ β + αθ (Equation 19)

  As described above in detail, the image processing apparatus including the image rotation processing unit 10 according to the second embodiment includes the interpolation circuit 30 described in detail in addition to the configuration of the first embodiment, From the rounding method and the rounding error value in the post-rotation address generation circuit, the interpolation pixel 30 can calculate the pixel data at the post-rotation address of the pixel of interest from the nearest four pixels to generate output pixel data. Thereby, in addition to the effect of increasing the speed similar to that of the first embodiment already described, the effect of preventing the deterioration of the image quality due to the image rotation process is further obtained.

[Third embodiment]
Next, FIG. 21 shows a third embodiment of the image rotation processing unit. This image rotation processing unit 10C has a feature that the memory capacity of the input / output unit is small and rotation processing with a larger rotation angle is possible. The image rotation processing unit 10C includes substantially all the configuration corresponding to the first embodiment (see FIG. 2), and further includes a fifth memory 41A, a sixth memory 41B, a fifth address selector 42, and a sixth address. The configuration includes a selector 43, a third write address generation circuit 44, a third read address generation circuit 45, and a third data selector 46.

  That is, the image rotation processing unit 10C includes a buffer circuit 11 that separates bidirectional data on the data bus 7 into input data and output data, a pair of first memory 12A and second memory 12B that alternately input input data, A first data selector 13 for selecting and outputting the output data of the first memory 12A and the second memory 12B; a pair of fifth memory 41A and sixth memory 41B for alternately inputting the data output from the first data selector; A third data selector 46 that selects and outputs the output data of the fifth memory 41A and the sixth memory 41B, and a pair of third memory 14A and a fourth memory that alternately input the data output from the third data selector 46 14B, the second data selector 15 for selecting and outputting the output data of the third memory 14A and the fourth memory 14B, the first memory 12A and the second memo A first write address generation circuit 16 for generating a write address of 12B, a first read address generation circuit 17 for generating read addresses of the first memory 12A and the second memory 12B, and after rotating the image by inputting a rotation angle A third write address generation circuit 44 that generates addresses and outputs them as write addresses of the fifth memory 41A and the sixth memory 41B, and a third read address generation circuit 45 that generates read addresses of the fifth memory 41A and the sixth memory 41B. The second write address generation circuit 18 for generating the write addresses of the third memory 14A and the fourth memory 14B, the second read address generation circuit 19 for generating the read addresses of the third memory 14A and the fourth memory 14B, the first memory 12A and second memory 12B and third memory 14A and fourth memory 14B and fifth Address selectors 21 to 24, 42, and 43 (first address selector to sixth address selector) for switching addresses corresponding to input / output operations of the memory 41A and the sixth memory 41B, and input data of each address selector and each data selector , A read / write control of each memory, and a control circuit 25C for switching data input / output of the buffer circuit. The rotation angle data α is input to the image rotation processing unit 10C via the data bus separately from the image data, and is input to the third write address generation circuit 44, but the circuit for that is not shown. .

  This is because, with respect to the first embodiment shown in FIG. 2, a pair of fifth memory 41A and sixth memory 41A and related circuits are added as internal memories, and the address after image rotation is used. In this embodiment, image data is alternately input. In the first embodiment, when the image rotation angle increases, it is necessary to increase the capacities of the first to fourth memories (12A to 12D). However, in this embodiment, the rotation angle of the image is related only to the capacities of the fifth memory and the sixth memory, and is independent of the capacities of the first memory to the fourth memory. That is, the capacity of the first memory to the fourth memory can be made smaller than the data amount of each image obtained by dividing the input image. For example, a small capacity of 256 bytes or 512 bytes, such as an integer multiple of the data amount when continuously transferring data via the data bus, is sufficient. The capacity is not necessarily an integer multiple of one line of the input image, and the capacity can be further reduced. Therefore, the rotation angle of the image can be increased with a small increase in the capacity of the entire memory used for the rotation process.

  In this embodiment, the first memory 12A and the second memory 12B simply input data input from the data bus 7 alternately, and the fifth memory 41A passes through the first data selector in the input order. And output to the sixth memory 41B. Further, the third memory 14A and the fourth memory 14B simply input the data output from the third data selector alternately, and output to the data bus 7 via the second data selector in the input order. . As described above, the capacities of the first to fourth memories (12A, 12B, 14A, 14B) may be independent of the image rotation angle. The first to fourth memories are used only as temporary storage means for transferring data among the data bus 7, the fifth memory 41A, and the sixth memory 41B. The fifth memory 41A and the sixth memory 41B are used for the image rotation process.

  FIG. 22 shows the relationship between an input image and an output image when image rotation processing is performed, and image data input / output to / from the fifth memory 41A and the sixth memory 41B. First, the image data A is input to the fifth memory 41A via the first memories 12A and 2 using the rotated address output from the third write address generation circuit. At this time, A1, which is a part of the image data A, is a portion that protrudes from the output image after rotation, and thus is not input to the fifth memory 41A. The A2 portion is input to the fifth memory 41A, and the A3 portion is input to the sixth memory 41B.

  Next, the image data B is input to the fifth memory 41A via the first memories 12A and 2 using the rotated address output from the third write address generation circuit. When the portion B1 is completely input to the fifth memory 41A, data output from the fifth memory 41A is started. In parallel with the data output of the fifth memory 41A, the portion B2 is input to the sixth memory 41B. After the data output from the fifth memory 41A is completed, the portion B3 is input to the fifth memory 41A.

  Next, the image data C is input to the sixth memory 41B via the first memories 12A and 2 using the rotated address output from the third write address generation circuit. When the C1 portion is completely input to the sixth memory 41B, data output from the sixth memory 41B is started using the address output from the third read address generation circuit. In parallel with the data output of the sixth memory 41B, the portion C2 is input to the fifth memory 41A. After the data output from the sixth memory 41B is completed, the portion C3 is input to the sixth memory 41B. Thereafter, this process is repeated.

  FIG. 23 shows a timing chart of data input / output (writing and reading) between the fifth memory 41A and the sixth memory 41B. When the image data A2 and B1 have been input to the fifth memory 41A, the data of the fifth memory 41A is output. When the image data A3, B2, and C1 have been input to the sixth memory 41B, the data of the sixth memory 41B is output. In the timing chart, it is described that writing of image data such as A2, A3, B1, and B2 is performed collectively to make the processing operation easy to understand. However, since the pixel data of the input image is actually read in the order of the main scanning direction, the data for one line becomes A2 and A3, or B1 and B2, so the data of A2 and A3 And B1 and B2 data are written within the data write time for one line.

  In this way, by inputting and outputting the image data using the rotated address alternately to a pair of memories (the fifth memory 41B and the sixth memory 41B) as the internal memory, the output after the rotation The image can be divided and output. The output image is stored in the main memory 6 of FIG.

  As described above in detail, in this embodiment, a pair of small-capacity memories that alternately input and output data are used in the memory of the input unit and the output unit, and a pair of internal memories that alternately input and output data. Using the memory, the image data is divided and input to the memory of the input unit in order, an address obtained by rotating the image based on this is generated, input to the internal memory, and the data of the internal memory is output to the output unit By outputting to the main memory 6 via the memory, the input / output unit has a small memory capacity, and the rotation process with a larger rotation angle can be performed with a small increase in the capacity of all the memories used. Thus, it is possible to provide a low-cost image processing apparatus that performs image rotation processing using a small-capacity memory.

[Fourth embodiment]
FIG. 24 shows a fourth embodiment of the image rotation processing unit. This is a configuration in which an interpolation circuit 30 is inserted between the first data selector 13, the fifth memory, and the sixth memory with respect to the third embodiment. The interpolation circuit 30 is the same as the circuit described in the second embodiment. That is, the configuration of each part is the same as that of the third embodiment already described except for the interpolation circuit 30 (therefore, the same part as that of the second embodiment is also included). The same parts as those in the second embodiment and the third embodiment are denoted by the same reference numerals, and description thereof is omitted to avoid duplication. The image rotation processing unit 10D having the configuration shown in FIG. 24 is basically the same as the third embodiment, including a small-capacity memory of an input / output unit and an internal memory. Since an equivalent interpolation circuit 30 is also provided, image rotation processing with a large rotation angle can be performed at high speed while suppressing deterioration in image quality.

[Fifth embodiment]
Next, FIG. 25 shows a fifth embodiment of the image rotation processing unit. This is because a first-in first-out (FIFO) memory (first-in-first-out) (FIFO) memory (the first memory 12A and the second memory 12B of the input unit and the address selector, the data selector, and the address generation circuit in the third embodiment are used. Similarly, the first FIFO memory 52) and its driving circuit are replaced. Similarly, the third memory 14A and the fourth memory 14B of the output section and the associated address selector, data selector, and address generation circuit are also used in the first-in first-out second FIFO memory 54. And its drive circuit.

  In the third embodiment, the first memory 12A, the second memory 12B, the third memory 14A, and the fourth memory 14B of the input / output unit simply send image data to the data bus 7, the fifth memory 41A, and the sixth memory. Since it merely functions as a temporary storage means for transferring data to and from the memory 41B, an equivalent function can be realized using a FIFO memory. Unlike the third embodiment, since the equivalent operation is obtained by using one memory without using two memories alternately, the memory capacity can be further reduced.

  The image rotation processing unit 10E of the fifth embodiment shown in FIG. 25 is a pair of internal memories that use first-in first-out FIFO memories 52 and 54 for the input unit and the output unit, respectively, and that alternately input and output data. Using the fifth memory 41A and the sixth memory 41B, the image data is divided and input in order from the first FIFO memory 52 of the input unit, and an address obtained by rotating the image is generated, and is stored in the internal memories 41A and 41B. The data are alternately input, the data in the internal memories 41A and 41B are alternately output, and output via the first-in first-out first FIFO memory 52 of the output unit. In the figure, the same parts as those of the third embodiment are denoted by the same reference numerals, and the description thereof is omitted to avoid duplication. By adopting such a configuration, a low-cost image processing apparatus that can perform a rotation process with a large rotation angle at a higher speed than a CPU process and a small-capacity memory with a memory of an input / output unit having a smaller capacity is realized. .

[Sixth embodiment]
FIG. 26 shows a sixth embodiment of the image rotation processing unit. In the image rotation processing unit 10F, the interpolation circuit 30 is inserted between the output end of the first FIFO memory 52 and the parallel-connected inputs of the fifth memory 41A and the sixth memory 41B in the fifth embodiment. This is an example. The interpolation circuit 30 is the same as that in the second embodiment. As a result, although an overlapping description is omitted, in addition to the operations and effects equivalent to those of the fifth embodiment, an effect of preventing image quality deterioration due to image rotation by the operation described above of the interpolation circuit 30 is added.

  In another invention of the present application, any one of the image processing apparatuses according to the first to sixth embodiments described above is mounted as, for example, an image rotation processing unit of the image forming apparatus shown in FIG. Thus, it is possible to provide a high-speed and low-cost image forming apparatus that can correct the inclination of the original or image.

  The present invention is not limited to an image processing apparatus such as a copying machine, a printer, a scanner, and a facsimile machine, but can be applied to other apparatuses that perform rotation processing on an image.

1 is a block diagram illustrating a configuration of an image forming apparatus according to the present invention. It is a block diagram of the configuration of the second embodiment of the image rotation processing unit. It is a figure which shows the relationship between an input image, an output image, and the image data input / output to 1st memory-4th memory. It is a figure explaining the internal structure of a 1st memory and a 2nd memory. It is a figure explaining the internal structure of a 3rd memory and a 4th memory. It is a timing chart of data input / output (write and read) in the first memory to the fourth memory. It is a figure which shows the control timing of each control signal regarding a control circuit. It is explanatory drawing of the address generation method after the image rotation in an Example. It is a block diagram which shows the structure of a 2nd write address generation circuit. It is explanatory drawing of the subscanning direction address production | generation to an output part memory. It is a figure explaining the state of an output part memory. It is a block diagram of a structure of 2nd Example of an image rotation process part. It is explanatory drawing of the process in an interpolation calculation circuit. It is a figure which shows the extraction method of 9 pixels of the peripheral part of an input image. It is a block diagram which shows an example of a structure of the interpolation circuit in an Example. It is explanatory drawing of the process in an interpolation calculation circuit. It is explanatory drawing of the process in an interpolation calculation circuit. It is explanatory drawing of the process in an interpolation calculation circuit. It is explanatory drawing of the process in an interpolation calculation circuit. It is explanatory drawing of the process in an interpolation calculation circuit. It is a block diagram of a structure of 3rd Example of an image rotation process part. It is explanatory drawing of the input image at the time of an image rotation process, an output image, and the image data input / output to 5th memory and 6th memory. It is a timing chart explaining data input / output of the 5th memory and the 6th memory. It is a block diagram of a structure of 4th Example of an image rotation process part. It is a block diagram of a structure of 5th Example of an image rotation process part. It is a block diagram of a structure of 6th Example of an image rotation process part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Scanner 2 Printer 3 Hard disk device 4 Operation part 5 CPU (Central Processing Unit)
6 Main memory 7 Data bus 10, 10B, 10C Image rotation processing unit 10D, 10E, 10F Image rotation processing unit 11 Buffer circuit 12A First memory 12B Second memory 13 First data selector 14A Third memory 14B Fourth memory 15 First 2 data selector 16 first write address generation circuit 17 first read address generation circuit 18 second write address generation circuit 19 second read address generation circuit 21 to 24 address selector (first address selector to fourth address selector)
25 Control circuit 30 Interpolation circuit 31 (31a to 31f) Delay circuit 32 (32a, 32b) Memory (for one line)
33 Data selector 34 Interpolation operation circuit 41A 5th memory 41B 6th memory 42, 43 Address selector (5th address selector, 6th address selector)
44 Third read address generation circuit 45 Third write address generation circuit 46 Third data selector 52 First FIFO memory 54 Second FIFO memory 100 Image forming apparatus (image processing apparatus)
bsel Buffer circuit data input / output switching signal

Claims (7)

A pair of first and second memories for alternately inputting and outputting image data;
A pair of third and fourth memories that alternately input and output image data output from the first and second memories;
An address generation circuit that generates an address for rotating the original image data based on the input predetermined angle value and outputs the generated address to each of the first to fourth memories;
The original image data held by the input image holding means is divided and inputted alternately to the first and second memories in order,
Data is alternately output from the first and second memories, and these output data are alternately input to the third and fourth memories using addresses output from the address generation circuit,
Alternately outputting data from the third and fourth memories;
An image processing apparatus. Means for holding data of each of nine pixels including eight pixels around the target pixel;
Means for selectively outputting three pixels close to the address after rotation of the target pixel from the nine pixels;
Means for calculating and outputting interpolation data from the four pixels of the three pixels and the target pixel,
2. The output data from the first and second memories are input to the interpolation circuit, and the output data from the interpolation circuit are input to the third and fourth memories. Image processing device. A pair of first and second memories for alternately inputting and outputting image data;
A pair of fifth and sixth memories that alternately input and output image data output from the first and second memories;
A third and fourth memory forming a pair for alternately inputting and outputting image data output from the fifth and sixth memories;
An address generation circuit that generates an address for rotating the original image data based on the input predetermined angle value and outputs the generated address to the first to fourth memories;
The original image data held by the input image holding means is divided and inputted alternately to the first and second memories in order,
Data is alternately output from the first and second memories, and these output data are alternately input to the third and fourth memories using addresses output from the address generation circuit,
Data is alternately output from the third and fourth memories, and these output data are alternately input to the fifth and sixth memories;
Alternately outputting data from the fifth and sixth memories;
An image processing apparatus. Means for holding 9 pixels including 8 pixels around the pixel of interest;
Means for selectively outputting three pixels close to the address after rotation of the target pixel from the nine pixels;
An interpolation circuit comprising means for calculating and outputting interpolation data from the four pixels of the three pixels and the target pixel;
4. The output data from the first and second memories is input to the interpolation circuit, and the output data from the interpolation circuit is input to the third and fourth memories. Image processing device. A first first-in first-out memory into which image data is input;
A pair of first and second memories for alternately inputting and outputting image data output from the first first-in first-out memory;
An address generation circuit that generates an address for rotating the original image data based on the input predetermined angle value and outputs the generated address to the first and second memories;
A second first-in first-out memory for inputting data alternately output from the first and second memories;
The original image data held by the input image holding means is divided and sequentially input to the first first-in first-out memory,
The output data from the first first-in first-out memory is alternately input to the first and second memories using the address output from the address generation circuit,
Alternately outputting data from the first and second memories, inputting the data to the second first-in first-out memory, and outputting from the second first-in first-out memory;
An image processing apparatus. Means for holding data of each of nine pixels including eight pixels around the target pixel;
Means for selectively outputting three pixels close to the address after rotation of the target pixel from the nine pixels;
An interpolation circuit comprising means for calculating and outputting interpolation data from the four pixels of the three pixels and the target pixel;
6. The image according to claim 5, wherein output data from the first first-in first-out memory is input to the interpolation circuit, and output data from the interpolation circuit is input to the first and second memories. Processing equipment. Image input means for scanning a document and converting it into image data;
Image forming means for printing image data on paper;
Means for detecting the document or the inclination of the image in the scanned image;
An image forming apparatus comprising: the image processing apparatus according to claim 1.

Images