JP5151802B2 - Light emitting device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a light emitting device and a method for manufacturing the same.

  Display devices, page printers, and other output devices are provided with light-emitting devices using self-luminous EL (Electro Luminescence) elements. For example, the display device is provided with a display panel in which EL elements are arranged in a matrix. The page printer is provided with a line type exposure apparatus in which EL elements are linearly arranged.

When manufacturing a light emitting device, a plurality of first electrodes provided on a substrate is used. The substrate is provided with one or a plurality of transistors per one first electrode. The transistor is disposed in a part around the first electrode. Then, a resin is applied to the substrate, a resin film is formed on the transistor and the first electrode, and the resin film is patterned to remove a portion of the resin film above the first electrode. Leave the top part of. Then, the remaining resin film is provided around the first electrode, and the transistor is provided under the resin film. Thereafter, a liquid EL material is applied toward the exposed first electrode. At this time, since the adjacent first electrodes are separated by the remaining resin film, it is possible to prevent the liquid EL material from bleeding between the adjacent first electrodes, and the remaining resin film functions as a partition wall. (For example, refer to Patent Document 1). Thus, after forming an organic electroluminescent layer on a 1st electrode, a 2nd electrode is formed into a film on an organic electroluminescent layer and a resin film, and a light-emitting device is completed.
JP 2002-75640 A

By the way, the height of the partition (resin film) differs depending on whether or not a transistor is provided under the partition. If the height of the partition located around the first electrode is different, an organic electroluminescence layer is formed. However, there is a problem that the film thickness of the organic electroluminescence layer is not uniform. If the thickness of the organic electroluminescence layer is not uniform, light emission unevenness occurs.
Therefore, the present invention has been made to solve the above problems, and an object thereof is to make the film thickness of the organic electroluminescence layer uniform.

In order to solve the above problems, according to one aspect of the present invention,
A substrate,
A first electrode provided on the substrate;
A first transistor formed on the substrate on one side of the first electrode and connected to the first electrode;
A dummy member formed on the substrate on the opposite side of the first transistor with respect to the first electrode and disposed without being connected to the first electrode and the first transistor;
A pair of partition walls provided on each of the first transistor and the dummy member on both sides of the first electrode;
An organic electroluminescence layer formed on the first electrode;
A second electrode formed on the organic electroluminescence layer ,
The dummy member has a transistor structure,
A second transistor and a third transistor formed on the substrate on the opposite side of the first transistor with respect to the first electrode, connected to the first electrode and the first transistor, and covered with the partition together with the dummy member. A transistor;
The second transistor, the third transistor, and the dummy member are formed such that each semiconductor film forming a channel is positioned on a predetermined line .

  Preferably, the channel width of the first transistor is longer than the sum of the channel widths of the second transistor and the third transistor.

  Preferably, the dummy member is formed to have the same height as the first transistor, the second transistor, and the third transistor.

According to another aspect of the invention,
A first electrode is provided on the substrate,
A first transistor connected to the first electrode is formed on the substrate on one side of the first electrode, and a dummy member disposed without being connected to the first electrode and the first transistor Forming on the substrate on the opposite side of the first transistor with respect to the first electrode in the same step as forming the transistor;
A partition wall is formed on the first transistor, the dummy member, and the first electrode, and the first electrode is exposed by patterning the partition wall,
Forming an organic electroluminescence layer on the first electrode by a wet coating method;
The second electrode formed on the organic electroluminescent layer,
The second transistor and the third transistor connected to the first electrode and the first transistor are formed on the opposite side of the first transistor with respect to the first electrode in the same process as the first transistor and the dummy member. The light emitting device, wherein the second transistor, the third transistor, and the dummy member are formed on a substrate so that each semiconductor film forming a channel is positioned on a predetermined line. A method of manufacturing a device is provided.

  According to the present invention, the first transistor and the dummy member are respectively formed on both sides of the first electrode, and the pair of partition walls are provided on each of the transistor and the dummy member. can do. Therefore, even when the liquid applied on the first electrode rises up to the partition when forming the organic electroluminescence layer, the liquid is distributed with an equal thickness. Therefore, the thickness of the organic electroluminescence layer can be made uniform. Therefore, light emission unevenness of the organic electroluminescence layer can be suppressed.

  Hereinafter, preferred embodiments for carrying out the present invention will be described with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

  FIG. 1 is a plan view schematically showing the light emitting device 1.

  The light emitting device 1 is a self-luminous display panel. Pixels P to be light emitting regions are arranged in a matrix. The light emitting device 1 is a full-color display panel, the pixel P emits light in R (red), G (green), or B (blue), and the color arrangement is not particularly limited. If all the pixels P emit light in the same color, the light emitting device 1 becomes a monochromatic display panel.

  The plurality of scanning lines 2 extend in the row direction, the plurality of signal lines 3 extend in the column direction, and the plurality of voltage supply lines 4 extend in the row direction. The plurality of scanning lines 2 are arranged so as to be parallel to each other, the plurality of signal lines 3 are arranged so as to be orthogonal to the scanning lines 2 in plan view, and the voltage supply line 4 scans between the adjacent scanning lines 2. It is provided so as to be parallel to the line 2. The pixel P is arranged in a region surrounded by a pair of scanning lines 2 and voltage supply lines 4 and two adjacent signal lines 3.

  A plurality of strip-shaped partition walls 13 are provided on each signal line 3. These partition walls 13 extend in the column direction, and these partition walls 13 are parallel to each other. A plurality of pixels P are arranged in the column direction between two adjacent partition walls 13.

  FIG. 2 is a circuit diagram showing a circuit relating to one pixel P of the light emitting device 1 operating in the active matrix driving method.

  As shown in FIG. 2, three transistors 5 to 7, a capacitor 8, and an EL element 9 are provided for each pixel P. Hereinafter, the second transistor 5 is referred to as a switch transistor 5, the first transistor 6 is referred to as a drive transistor 6, and the third transistor 7 is referred to as a holding transistor 7.

  The gate 5a of the switch transistor 5 is connected to the scanning line 2, one electrode 5h of the drain and source of the switch transistor 5 is connected to the signal line 3, and the other electrode 5i is one electrode 8b of the capacitor 8 and the drive. The transistor 6 is connected to one electrode 6h of the drain and source. The other electrode 6 i of the drain and source of the driving transistor 6 is connected to the voltage supply line 4, and the gate 6 a of the driving transistor 6 is the other electrode 8 a of the capacitor 8 and one electrode of the drain and source of the holding transistor 7. 7h. The other electrode 7 i of the drain and source of the holding transistor 7 is connected to the voltage supply line 4 and the electrode 6 i of the driving transistor 6, and the gate 7 a of the holding transistor 7 a is connected to the scanning line 2. The anode 9a of the EL element 9 is connected to the electrode 5i of the switch transistor 5, the electrode 8 of the capacitor 8, and the electrode 6h of the drive transistor 6. The cathodes 9d of the EL elements 9 of all the pixels P are kept at a constant voltage Vcom, and specifically are grounded.

  Further, around the light emitting device 1, each scanning line 2 is connected to a scanning driver, each voltage supply line 4 is connected to a constant voltage source or a driver outputting an appropriate voltage signal, and each signal line 3 is connected to a data driver. Then, the light emitting device 1 is driven by the active matrix driving method by these drivers. A predetermined voltage is applied to the voltage supply line 4 by a constant voltage source or a driver.

  3 is a plan view corresponding to the three pixels P of the light-emitting device 1, FIG. 4 is a partial cross-sectional view taken along the line IV-IV in FIG. 3, and FIG. FIG. 5 is a cross-sectional view of a part of the surface along V-V in FIG. Note that FIG. 3 mainly shows electrodes and wiring.

  As shown in FIGS. 3 to 5, the light emitting region to be the pixel P is a portion where the anode 9 a, the hole injection layer 9 b, the light emitting layer 9 c, and the cathode 9 d of the EL element 9 are overlapped in plan view. As shown in FIG. 3, the drive transistor 6 is formed along the right side of the pixel P under one of the partition walls 13 on both sides of the pixel P, and includes a switch transistor 5, a holding transistor 7, and a dummy member (dummy Transistor) 20 is arranged below the other partition wall 13 along the left side of the pixel P. A capacitor 8 surrounds the pixel P.

  The signal line 3 is formed on the substrate 10, the gate insulating film 11 is formed on one surface of the substrate 10, and the signal line 3 is formed between the substrate 10 and the gate insulating film 11 and covered with the gate insulating film 11. ing. The scanning line 2 and the voltage supply line 4 are formed on the gate insulating film 11, and the protective insulating film 12 is formed on the gate insulating film 11. The scanning line 2 and the voltage supply line 4 are formed between the gate insulating film 11 and the protective insulating film 12 and covered with the protective insulating film 12. The gate insulating film 11 is made of silicon nitride or silicon oxide. The protective insulating film 12 is made of silicon nitride or silicon oxide. A substrate in which the gate insulating film 11 is formed on the substrate 10 corresponds to the substrate.

  The switch transistor 5 is an inverted staggered transistor. The switch transistor 5 includes a gate 5a, a semiconductor film 5b, a protective film 5d, impurity semiconductor films 5f and 5g, an electrode 5h, an electrode 5i, and the like.

The gate 5 a is formed between the substrate 10 and the gate insulating film 11. The gate 5a is made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film. A gate insulating film 11 is formed on the gate 5a, and the gate insulating film 11 covers the gate 5a.
An intrinsic semiconductor film 5b is formed on the gate insulating film 11 at a position corresponding to the gate 5a, and the semiconductor film 5b is opposed to the gate 5a with the gate insulating film 11 interposed therebetween.
The semiconductor film 5b is made of, for example, amorphous silicon or polycrystalline silicon, and a channel is formed in the semiconductor film 5b. An insulating protective film 5d is formed on the central portion of the semiconductor film 5b. The protective film 5d is made of, for example, silicon nitride or silicon oxide.
Further, an impurity semiconductor film 5f is formed on one end portion of the semiconductor film 5b so as to partially overlap the protective film 5d, and an impurity semiconductor film 5g is formed on the other end portion of the semiconductor film 5b. It is formed so as to partially overlap the protective film 5d. The impurity semiconductor films 5f and 5g are formed on both ends of the semiconductor film 5b so as to be separated from each other. The impurity semiconductor films 5f and 5g are n-type semiconductors or p-type semiconductors.
An electrode 5h is formed on the impurity semiconductor film 5f. An electrode 5i is formed on the impurity semiconductor film 5g. One of the electrodes 5h and 5i is a drain, and the other is a source. The electrodes 5h and 5i are made of, for example, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film.
A protective insulating film 12 is formed on the protective film 5d and the electrodes 5h and 5i, and the protective film 5d, the electrode 5h, and the electrode 5i are covered with the protective insulating film 12. Thus, the switch transistor 5 is covered with the protective insulating film 12.

  The driving transistor 6 is an inverted staggered transistor. The driving transistor 6 includes a gate 6a, a semiconductor film 6b, a protective film 6d, impurity semiconductor films 6f and 6g, an electrode 6h, an electrode 6i, and the like.

The gate 6a is made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, an AlTiNd alloy film, or MoNb. The gate 6 a is formed between the substrate 10 and the gate insulating film 11 similarly to the gate 5 a and is covered with the gate insulating film 11.
A semiconductor film 6b is formed on the gate insulating film 11 at a position corresponding to the gate 6a. The semiconductor film 6b is opposed to the gate 6a with the gate insulating film 11 interposed therebetween.
A protective film 6d is formed on the central portion of the semiconductor film 6b. The protective film 6d is made of, for example, silicon nitride or silicon oxide.
Further, an impurity semiconductor film 6f is formed on one end portion of the semiconductor film 6b so as to partially overlap the protective film 6d, and an impurity semiconductor film 6g is formed on the other end portion of the semiconductor film 6b. It is formed so as to partially overlap the protective film 6d. The impurity semiconductor films 6f and 6g are formed on both ends of the semiconductor film 6b so as to be separated from each other. The impurity semiconductor films 6f and 6g are n-type semiconductors or p-type semiconductors.
An electrode 6h is formed on the impurity semiconductor film 6f, and an electrode 6i is formed on the impurity semiconductor film 6g. One of the electrodes 6h and 6i is a drain, and the other is a source. The electrodes 6h and 6i are made of, for example, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film.
The protective insulating film 12 is formed on the protective film 6d, the electrode 6h, and the electrode 6i, and the protective film 6d, the electrode 6h, and the electrode 6i are covered with the protective insulating film 12. Thus, the driving transistor 6 is covered with the protective insulating film 12.

  The dummy transistor 20 includes a dummy gate 20a, a semiconductor film 20b, a protective film 20d, impurity semiconductor films 20f and 20g, a dummy electrode 20h, an electrode 20i, and the like.

The gate 20a is made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, an AlTiNd alloy film, or MoNb. Similar to the gate 5a, the dummy gate 20a is formed between the substrate 10 and the gate insulating film 11, and is covered with the gate insulating film 11.
A semiconductor film 20b is formed on the gate insulating film 11 at a position corresponding to the dummy gate 20a. The semiconductor film 20b is opposed to the dummy gate 20a with the gate insulating film 11 interposed therebetween.
A protective film 20d is formed on the central portion of the semiconductor film 20b. The protective film 20d is made of, for example, silicon nitride or silicon oxide.
Further, an impurity semiconductor film 20f is formed on one end portion of the semiconductor film 20b so as to partially overlap the protective film 20d, and an impurity semiconductor film 20g is formed on the other end portion of the semiconductor film 20b. It is formed so as to partially overlap the protective film 20d. The impurity semiconductor films 20f and 20g are formed on both ends of the semiconductor film 20b so as to be separated from each other. The impurity semiconductor films 20f and 20g are n-type semiconductors or p-type semiconductors.
A dummy electrode 20h is formed on the impurity semiconductor film 20f, and a dummy electrode 20i is formed on the impurity semiconductor film 20g. The dummy electrodes 20h and 20i are made of, for example, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlTiNd alloy film.
The protective insulating film 12 is formed on the protective film 20d, the dummy electrode 20h, and the dummy electrode 20i, and the protective film 20d, the dummy electrode 20h, and the dummy electrode 20i are covered with the protective insulating film 12. Thus, the dummy transistor 20 is covered with the protective insulating film 12.

  The cross-sectional shape of the holding transistor 7 is the same as that of the switch transistor 5 and the dummy transistor 20. The holding transistor 7 is also covered with the protective insulating film 12.

As shown in FIGS. 4 and 6, the capacitor 8 includes a pair of electrodes 8 a and 8 b facing each other. One electrode 8 a is formed between the substrate 10 and the gate insulating film 11, and the other electrode 8 b is formed between the gate insulating film 11 and the protective insulating film 12. The electrode 8a and the electrode 8b are opposed to each other with the gate insulating film 11 that is a dielectric interposed therebetween.
The electrode 8a of the capacitor 8 is integrated with the gates 5a and 6a of the switch transistor 5 and the driving transistor 6 and is connected to the gate 6a. The electrode 8b of the capacitor 8 is integrated with the electrodes 5i and 6i of the switch transistor 5 and the drive transistor 6, and is connected to the electrodes 5i and 6i.

The signal line 3, the electrode 8 a of the capacitor 8, the switch transistor 5, the drive transistor 6, the holding transistor 7, and the gates 5 a, 6 a, and 20 a of the dummy transistor 20 (the sign of the gate of the holding transistor 7 is omitted) are all over the substrate 10. The conductive films thus formed are collectively formed by shape processing by a photolithography method, an etching method, or the like.
Further, the scanning line 2, the voltage supply line 4, the electrode 8b of the capacitor 8, the switch transistor 5, the driving transistor 6, the holding transistor 7, and the electrodes 5h, 5i, 6h, 6i, 20h, and 20i of the dummy transistor 20 (of the holding transistor 7). The drain / source symbols are omitted), which is formed by processing a conductive film formed over the entire surface of the gate insulating film 11 by a photolithography method, an etching method, or the like.

In the protective insulating film 12, one opening 12a is formed for each pixel P. The plurality of openings 12a are arranged in the column direction between the adjacent partition walls 13, and as a whole, the plurality of openings 12a are arranged in a matrix so that the protective insulating film 12 is formed in a net shape.
A switch transistor 5, a drive transistor 6, a holding transistor 7, a dummy transistor 20, and a capacitor 8 are arranged around the opening 12a.

  Here, the dummy transistor 20 is arranged without being connected to the circuit shown in FIG. Then, it is considered that the dummy transistor 20 may not be formed between the switch transistor 5 and the holding transistor 7 as shown in FIG. However, the channel widths of the driving transistor 6, the switch transistor 5, and the holding transistor 7 are determined based on circuit design. Since the driving transistor 6 continues to flow a current for causing the EL element 9 to emit light directly in a non-selection period, which will be described later, which is sufficiently longer than a selection period, which will be described later, the channel width of the driving transistor 6 is increased. It is preferable to set the length so that a large current can flow. That is, the channel width of the driving transistor 6 is set longer than the sum of the channel widths of the switch transistor 5 and the holding transistor 7. Then, if the dummy transistor 20 is not formed, the semiconductor films 5b and 7b of the switch transistor 5 and the holding transistor 7 are located on a predetermined line on the side opposite to the driving transistor 6 and the channel width direction of the semiconductor film is coincident. Even so, the partition wall 13 on the side opposite to the drive transistor 6 has a lower portion than the partition wall 13 on the drive transistor 6 side, and the surface of the partition wall 13 becomes uneven. Therefore, the dummy transistor 20 is provided on the shorter of the sum of the channel widths of the transistors provided on one side of the pixel P and the sum of the channel widths of the transistors provided on the other side of the pixel P. That is, here, on the left side of the pixel P, the switch transistor 5, the holding transistor 7, and the dummy transistor 20 are formed so that the respective semiconductor films 5b, 7b, and 20b forming the channel are located on a predetermined line. The predetermined line may be a straight line, a curved line, or a bent line as long as it is a continuous line. In particular, it is preferable that the semiconductor films 5b, 7b, and 20b are formed so as to be in a straight line and in the same channel width direction. Further, if the semiconductor film 20b of the dummy transistor 20 is located on the same predetermined line as the semiconductor films 5b and 7b of the switch transistor 5 and the holding transistor 7, it is somewhat shifted in the channel length direction orthogonal to the channel width direction. May be. The dummy transistor is preferably formed so as to have the same height as the driving transistor 6, the switch transistor 5, and the holding transistor 7.

  As shown in FIGS. 3 to 5, a partition wall 13 is formed on the protective insulating film 12. The partition wall 13 is made of an insulating resin material, particularly a photosensitive resin material. Here, below the partition wall 13 on the right side of the pixel P, the drive transistor 6 is formed. On the other hand, a dummy transistor 20 disposed without being connected to the circuit of FIG. Then, in the cross section shown in FIG. 5, the heights of the partition walls 13 on both sides of the pixel P are substantially equal. If the dummy transistor 20 is not provided, the left partition 13 of the pixel P is lower than the right partition 13.

  The EL element 9 includes an anode 9a, a hole injection layer 9b, a light emitting layer 9c, and a cathode 9d. The anode 9a is a first electrode, and the cathode 9d is a second electrode. The cathode 9d is a single electrode common to all the pixels P, and the anode 9a, the hole injection layer 9b, and the light emitting layer 9c are separated for each pixel P and are independent for each pixel P. The hole injection layer 9b and the light emitting layer 9c are organic electroluminescence layers.

The anode 9 a is formed on the gate insulating film 11, the central portion of the anode 9 a is in the opening 12 a, and the outer edge portion of the anode 9 a is covered with the protective insulating film 12. The anode 9a includes tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), cadmium-tin oxide (CTO), aluminum It consists of other conductive materials. The end portion of the anode 9 a is in the layer of the protective insulating film 12 and the gate insulating film 11, and the portion is in contact with the electrode 8 b of the capacitor 8.

  In the opening 12a, the anode 9a, the hole injection layer 9b, the light emitting layer 9c, and the cathode 9d are laminated in order of the anode 9a, the hole injection layer 9b, the light emitting layer 9c, and the cathode 9d. A portion where these overlap is a light emitting region (pixel P). The hole injection layer 9b and the light emitting layer 9c are raised on the protective insulating film 12 from the opening 12a. However, the hole injection layer 9b and the light emitting layer 9c are separated by the partition wall 13 and are not in contact with the hole injection layer 9b and the light emitting layer 9c of the adjacent pixel P. Therefore, so-called color mixing does not occur.

  Further, since the left partition 13 and the right partition 13 of the pixel P have substantially the same height, the thicknesses of the hole injection layer 9b and the light emitting layer 9c are substantially equal.

Examples of the hole injection layer 9b include a material made of PEDOT (polyethylenedioxythiophene) which is a conductive polymer and PSS (polystyrene sulfonic acid) which is a dopant.
The light emitting layer 9c is made of, for example, a polyphenylene vinylene light emitting material or a polyfluorene light emitting material. Note that the pixel P that emits light in R (red), the pixel P that emits light in G (green), and the pixel P that emits light in B (blue) have different light emitting materials for the light emitting layer 9c.

A cathode 9d is formed on the light emitting layer 9c. The cathode 9d covers the partition wall 13 in addition to the light emitting layer 9c. The cathode 9d is made of, for example, indium, magnesium, calcium, lithium, barium, rare earth metal or a compound thereof, tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In ₂ O ₃ ), tin oxide ( SnO ₂ ), zinc oxide (ZnO), cadmium-tin oxide (CTO), metal (eg, aluminum, silver), metal alloy (eg, aluminum alloy, silver alloy) or metal compound (eg, aluminum compound, silver compound) ) And the like.

Either one or both of the anode 9a and the cathode 9d is a transparent electrode. When the anode 9a is a transparent electrode, the substrate 10 and the gate insulating film 11 are also preferably transparent. When the anode 9a, the substrate 10 and the gate insulating film 11 are transparent, the light emitted from the light emitting layer 9c is emitted below the substrate 10, and such a light emitting device 1 is referred to as a bottom emission type light emitting device. On the other hand, when the cathode 9d is a transparent electrode, the light emitted from the light emitting layer 9c is emitted from the cathode 9d thereon, and such a light emitting device 1 is referred to as a top emission type light emitting device. When both the anode 9a and the cathode 9d are transparent electrodes, if a reflective film (for example, aluminum) is formed under the anode 9a, the light-emitting device 1 becomes a top emission type light-emitting device, and the cathode 9d If a reflective film is formed thereon, the light emitting device 1 becomes a bottom emission type light emitting device. When the anode 9a and the cathode 9d are transparent electrodes, the materials are tin-doped indium oxide (ITO), zinc-doped indium oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO). ) Or cadmium-tin oxide (CTO).

  When the hole injection layer 9b or the light emitting layer 9c is formed by a wet method, the partition wall 13 oozes a liquid in which a material that becomes the hole injection layer 9b or the light emitting layer 9c is dissolved or dispersed in a solvent into an adjacent pixel P It is for not to be.

The light emitting device 1 is driven as follows to emit light.
In a state where a predetermined level of voltage is applied to all the voltage supply lines 4, the scanning driver sequentially applies voltages to the scanning lines 2, whereby the scanning lines 2 are sequentially selected. In synchronization with the selection of the scanning lines 2, the voltage supply lines 4 are sequentially selected by sequentially applying voltages to the voltage supply lines 4. The voltage level of the voltage supply line 4 when the voltage supply line 4 is selected is lower than Vcom, and the voltage level of the voltage supply line 4 when the voltage supply line 4 is selected is higher than Vcom.

  When each scanning line 2 is selected, a designated current flows through all the signal lines 3 by the data driver. The data driver is a current control type driver, and the level of the designated current flowing through each signal line 3 is a level corresponding to the gradation by the data driver.

  When a scanning line 2 in a certain row is selected (selection period), the switch transistor 5 and the holding transistor 7 connected to the scanning line 2 are turned on. A specified current flows through the voltage supply line 4 in that row. The direction of the designated current is a direction from the voltage supply line 4 to the data driver through the drive transistor 6, the switch transistor 5, and the signal line 3. As the specified current flows between the electrodes 6i and 6h of the drive transistor 6, the level of the specified current is converted to the voltage level of the gate 6a. In addition, since the voltage level of the selected voltage supply line 4 is lower than Vcom, no current flows through the EL element 9.

  After that, when the selection of the scanning line 2 is released (non-selection period), the switch transistor 5 is turned off, so that the designated current does not flow to the switch transistor 5. At this time, since the holding transistor 7 is turned off, the voltage level of the gate 6a of the driving transistor 6 is held. At that time, the selection of the voltage supply line 4 is released and the voltage level of the voltage supply line 4 becomes higher than Vcom, so that the drive current passes from the voltage supply line 4 through the drive transistor 6 to the EL element. The EL element 9 emits light with an intensity according to the level of the drive current. Since the voltage level of the gate 6a of the driving transistor 6 is maintained, the level of the driving current at the time of deselection is equal to the level of the designated current at the time of selection.

Next, a method for manufacturing the light emitting device 1 will be described.
First, a gate metal layer is deposited on the substrate 10 by a sputtering method, and the gate metal layer is shaped by a photolithography method and an etching method to form the signal line 3, the electrode 8a of the capacitor 8, the gate 5a of the switch transistor 5, and the drive. The gate 6a of the transistor 6, the gate of the holding transistor 7, and the dummy gate of the dummy transistor 20 are formed.
Next, a gate insulating film 11 of silicon nitride or silicon oxide is deposited by plasma CVD.
Next, after depositing the ITO film, the ITO film is shaped into the anode 9a.
Next, an amorphous silicon or polysilicon semiconductor layer (which is the basis of the semiconductor films 5b, 6b, 7b and 20b) and an insulating layer of silicon nitride or silicon oxide (which is the basis of the protective films 5d and 6d) are formed. After sequentially depositing, the insulating film is processed into the protective films 5d, 6d, and 20d by photolithography and etching. Subsequently, after depositing an impurity layer (which is a source of the impurity semiconductor films 5f, 5g, 6f, 6g, 20f, and 20g), the impurity layer is deposited on the impurity semiconductor films 5f, 5g, and 5g by a photolithography method and an etching method. Shape processing is performed to 6f, 6g, 20f, and 20g, and the semiconductor layer is continuously processed into semiconductor films 5b, 6b, and 20b. The shape of the impurity semiconductor film and the semiconductor film of the holding transistor 7 is simultaneously processed.
Next, a source / drain metal layer is deposited on the gate insulating film 11 and the like by a vapor deposition method, and the source / drain metal layer is deposited by a photolithography method / etching method on the scanning line 2, voltage supply line 4, capacitor 8. The electrode bb, the electrodes 5h and 5i of the switch transistor 5, the electrodes 6h and 6i of the driving transistor 6, the drain / source of the holding transistor 7 and the electrodes 20h and 20i of the dummy transistor 20 are processed. As described above, the drive transistor 6 is patterned along the right side of the anode 9a, and the switch transistor 5, the dummy transistor 20, and the holding transistor 7 are patterned along the left side of the anode 9a.
Next, the protective insulating film 12 is formed by a vapor deposition method, and the protective insulating film 12 is shaped by a photolithography method or a vapor deposition method, thereby forming an opening 12a in the protective insulating film 12. When the protective transistor 12 covers the switch transistor 5, the drive transistor 6, the capacitor 8, and the like and the opening 12a is formed, the central portion of the anode 9a is exposed in the opening 12a.

  Next, a photosensitive resin material is applied on the protective insulating film 12 and in the opening 12a, and the resin material is cured to form a photosensitive resin film. Next, when the photosensitive resin film is exposed with a stepper and the photosensitive resin film is developed, the photosensitive resin film is shaped into a plurality of partition walls 13. Since the switch transistor 5, the dummy transistor 20, and the holding transistor 7 are formed on the left side of the anode 9a and the switching transistor 5 is formed on the right side of the anode 9a, the heights of the partition walls 13 on both sides of the anode 9a are substantially equal.

  Subsequently, a liquid is apply | coated to the opening part 12a using a liquid applicator. In particular, it is preferable to use a droplet discharger (for example, an ink jet printer) among liquid applicators, and discharge the liquid into droplets into the opening 12a. The liquid to be applied is obtained by dissolving or dispersing an organic material (raw material of the hole injection layer 9b) in a solvent or a dispersion medium. By drying the applied liquid, the hole injection layer 9b is formed on the anode 9a. Since the heights of the partition walls 13 on both sides of the opening 12a are equal, even if the liquid climbs up to the partition wall 13, the liquid is distributed over the anode 9a with an equal thickness (depth). Therefore, the thickness of the hole injection layer 9b is uniform on the anode 9a.

  Then, by repeating the application of the liquid, the liquid is applied in all the openings 12a, and the hole injection layer 9b is printed in a matrix. Since the partition wall 13 is formed, when printing the hole injection layer 9b, the liquid does not spread between the adjacent openings 12a with the partition wall 13 interposed therebetween.

  Next, the light emitting layer 9c is printed in a matrix similar to the printing of the hole injection layer 9b. The liquid to be applied is obtained by dissolving or dispersing an organic material (a raw material of the light emitting layer 9c) in a solvent or a dispersion medium. Also in the light emitting layer 9c, the heights of the partition walls 13 on both sides of the opening 12a are equal, so that the thickness is uniform.

Next, a cathode 9d is formed on the partition wall 13 and the light emitting layer 9c.
Thus, the light emitting device 1 is completed.

  As described above, according to the present embodiment, since the thicknesses of the hole injection layer 9b and the light emitting layer 9c can be made uniform, uneven light emission can be suppressed.

  According to the present embodiment, the dummy member is a dummy transistor, but the present invention is not limited to this as long as the dummy member has the same height as the transistor.

It is the schematic plan view which showed the light-emitting device in embodiment of this invention. It is an equivalent circuit diagram of one pixel of the light emitting device. It is the top view which showed 3 pixels of the said light-emitting device. FIG. 4 is a cross-sectional view taken along the line IV-IV shown in FIG. 3. It is arrow sectional drawing of the surface along VV shown by FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Light-emitting device 5 Switch transistor 6 Drive transistor 7 Holding transistor 9a Anode 9b Hole injection layer 9c Light emitting layer 9d Cathode 13 Bulkhead 20 Dummy transistor

Claims (4)

A substrate,
A first electrode provided on the substrate;
A first transistor formed on the substrate on one side of the first electrode and connected to the first electrode;
A dummy member formed on the substrate on the opposite side of the first transistor with respect to the first electrode and disposed without being connected to the first electrode and the first transistor;
A pair of partition walls provided on each of the first transistor and the dummy member on both sides of the first electrode;
An organic electroluminescence layer formed on the first electrode;
A second electrode formed on the organic electroluminescence layer ,
The dummy member has a transistor structure,
A second transistor and a third transistor formed on the substrate on the opposite side of the first transistor with respect to the first electrode, connected to the first electrode and the first transistor, and covered with the partition together with the dummy member. A transistor;
The light emitting device , wherein the second transistor, the third transistor, and the dummy member are formed such that respective semiconductor films forming a channel are located on a predetermined line . The channel width of the first transistor, light emitting device according to claim 1, wherein longer than the sum of the channel width of the second transistor and the third transistor. The dummy member, the first transistor, light emitting device according to claim 1 or 2, characterized in that it is formed as the second transistor and the third transistor and the height is equal. A first electrode is provided on the substrate,
A first transistor connected to the first electrode is formed on the substrate on one side of the first electrode, and a dummy member disposed without being connected to the first electrode and the first transistor Forming on the substrate on the opposite side of the first transistor with respect to the first electrode in the same step as forming the transistor;
A partition wall is formed on the first transistor, the dummy member, and the first electrode, and the first electrode is exposed by patterning the partition wall,
Forming an organic electroluminescence layer on the first electrode by a wet coating method;
The second electrode formed on the organic electroluminescent layer,
The second transistor and the third transistor connected to the first electrode and the first transistor are formed on the opposite side of the first transistor with respect to the first electrode in the same process as the first transistor and the dummy member. The light emitting device, wherein the second transistor, the third transistor, and the dummy member are formed on a substrate so that each semiconductor film forming a channel is positioned on a predetermined line. Device manufacturing method.

Images