JP5147785B2 - Offset cancel circuit - Google Patents

Description

  The present invention relates to an offset cancel circuit used for adjusting the output of a Hall element.

  In recent years, in an imaging apparatus such as a digital still camera or a digital video camera, high image quality has been realized by increasing the number of pixels of an imaging element included therein. On the other hand, as another method for realizing high image quality of the image pickup device, the image pickup device is equipped with an image stabilization control circuit having a camera shake correction function in order to prevent subject shake caused by hand shake with the image pickup device. It is hoped to do.

  The image stabilization control circuit for camera shake correction receives a signal from a gyro sensor that detects an angular velocity component generated by vibration of the imaging device, and drives optical components such as a lens and an image sensor in accordance with the signal to blur the subject. To prevent. Accordingly, even when the imaging apparatus vibrates, the vibration component is not reflected in the acquired video signal, and a high-quality video signal without image blur can be acquired.

  At this time, a Hall element is used to detect the position of an optical component such as a lens to be driven. The equivalent circuit of the Hall element can be expressed as a bridge circuit of resistors R1 to R4 as shown in FIG. Therefore, depending on the combination of the terminal to which the power supply voltage Vcc is applied and the terminal from which the output signal is extracted, the output signal of the Hall element is affected by the variation of each resistor and includes an offset component.

  Therefore, as shown in FIG. 12, an offset cancel circuit 100 including a Hall element 10, an amplifier circuit 12, and an averaging circuit 14 is used. In the offset cancel circuit 100, the switching elements S1 to S19 are controlled to be turned on / off, a voltage is applied so that the current flowing through the Hall element 10 differs by 90 °, and the capacitors C1 and C2 are charged in each state. The charging voltages of C1 and C2 are added and averaged. When the current flowing through the Hall element 10 is changed by 90 °, the offset of the output voltage of the Hall element 10 is generated in the opposite direction, so that the offset value of the output voltage of the Hall element 10 is cancelled.

  By providing an offset cancel circuit, the offset value of the output voltage of the Hall element can be canceled.

  By the way, MOS transistors are used for the switching elements S1 to S19. The MOS transistor uses the characteristic that it is turned off when the gate-source voltage is smaller than the threshold voltage and turned on when the voltage is higher than the threshold voltage. When turning off the MOS transistor, the gate electrode is set lower than the threshold voltage from the power supply voltage. There is an overlap capacitance between the gate and the source and drain, and the charge in the channel of the MOS transistor is also absorbed by the source and drain when turning off. Therefore, when the MOS transistor is turned off, the amount of charge obtained by the product of the gate voltage variation and the overlap capacitance and a part of the amount of charge stored in the channel change. This is called charge injection (noise) of the switching element.

  Also in the offset cancel circuit 100, there is a possibility that noise is superimposed on the output voltage from the Hall element due to the charge injection noise of the switching elements S1 to S19.

  Therefore, a technique for reducing the influence of charge injection noise in an offset cancel circuit is desired.

  One aspect of the present invention is a Hall element offset cancel circuit, in which a voltage is applied from the outside so as to switch a plurality of capacitors and a current flowing through the Hall element, and the output voltage of the Hall element is changed for each state. A first switching element group that is controlled to be turned on / off so that is applied to any of the plurality of capacitors, and the charges charged in the plurality of capacitors in a state where the plurality of capacitors are connected in parallel. And a second switching element group that is controlled to be turned on / off so that a corresponding output voltage is output, and each of the plurality of capacitors has a configuration in which a parasitic capacitance is connected to one of both terminals thereof. In a state where the plurality of capacitors are connected in parallel, a reference voltage is applied to one output terminal of the plurality of capacitors connected in parallel, Wherein the parasitic capacitance to the terminal side of the reference voltage is applied, of the two terminals of each of the number of capacitors is connected.

  For example, each of the plurality of capacitors is formed on a semiconductor substrate, a first semiconductor layer formed on the semiconductor substrate, an insulating layer formed on the first semiconductor layer, and the insulating layer. In the state where the plurality of capacitors are connected in parallel, the reference voltage is applied to the first semiconductor layer, and the semiconductor substrate is preferably grounded.

  According to the present invention, the influence of charge injection noise in the offset cancellation circuit can be reduced.

It is a figure which shows the structure of the offset cancellation circuit in embodiment of this invention. It is a figure which shows the effect | action of the offset cancellation circuit in embodiment of this invention. It is a figure which shows the effect | action of the offset cancellation circuit in embodiment of this invention. It is a figure which shows the effect | action of the offset cancellation circuit in embodiment of this invention. It is a figure explaining the effect | action of the dummy switching element of the offset cancellation circuit in embodiment of this invention. It is a figure explaining the effect | action of the dummy switching element of the offset cancellation circuit in embodiment of this invention. It is a figure which shows the effect | action of the dummy switching element in an offset cancellation circuit. It is a figure which shows the structure of the capacitor | condenser used for the offset cancellation circuit in embodiment of this invention. It is a figure which shows the equivalent circuit of the capacitor | condenser used for the offset cancellation circuit in embodiment of this invention. It is a figure which shows the effect | action of the capacitor | condenser used for the offset cancellation circuit in embodiment of this invention. It is a figure which shows the equivalent circuit of a Hall element. It is a figure which shows the structure of the conventional offset cancellation circuit.

  FIG. 1 shows a basic configuration of a Hall element offset cancel circuit 100. The Hall element offset cancel circuit 200 includes a Hall element 10, an amplifier circuit 12, and an averaging circuit 20.

  The Hall element 10 can be represented as a bridge circuit of resistors R1 to R4. Switching elements S1 to S8 that switch connection points A to D of the resistors R1 to R4 to the power supply voltage Vcc, ground, or output are connected to the resistors R1 to R4.

  The amplifier circuit 12 includes operational amplifiers 12a and 12b. The operational amplifier 12a amplifies and outputs the voltage input to the non-inverting input terminal (+). The operational amplifier 12b amplifies and outputs the voltage input to the non-inverting input terminal (+).

  The averaging circuit 14 includes switching elements S9 to S19, dummy switching elements D1 to D3, capacitors C1 to C4, an operational amplifier 20a, and a reference voltage generation circuit 20b.

  The switching elements S9 to S19 mutually connect any one of the output terminals of the operational amplifiers 12a and 12b, the terminals of the capacitors C1 to C4, and the input terminal of the operational amplifier 20a. The switching elements S9 to S12 and S19 are on / off controlled so that an output voltage corresponding to the charge charged in the capacitors C1 and C2 is output in a state where the capacitors C1 and C2 are connected in parallel. That is, the switching elements S9 to S12 and S19 are connected to the capacitors C1 and C2 in parallel and connected to the output capacitor C3, and are controlled on / off so that the terminal voltage of the capacitor C3 is input to the operational amplifier 20a. The The switching elements S13 to S16 are configured such that when a voltage is applied from the outside so that the current flowing through the Hall element 10 is switched, the output voltage of the Hall element 10 is applied to one of the capacitors C1 and C2 for each state. ON / OFF controlled. That is, one of the capacitors C1 and C2 is charged by the output voltage of the Hall element 10 by performing on / off control of the switching elements S13 to S16. The switching element S17 is used for discharging the charging charge of the capacitor C3. The switching element S18 is used to connect the input terminal and the output terminal of the operational amplifier 14a. It is preferable that the switching elements S9 to S19 have similar element capacities regardless of P-type and N-type.

  The dummy switching element refers to a switching element that is on / off controlled exclusively with respect to the switching element to which the dummy switching element is connected. The dummy switching element can be configured to connect the input end and the output end of the switching element. The input terminal and the output terminal connected to each other of the dummy switching element are connected to the input terminal or the output terminal of the switching element to be connected. It is preferable that the dummy switching element has an element capacity of about ½ of the switching element to be connected.

  In the present embodiment, the dummy switching elements D1 to D3 are elements that are controlled to be turned off when the switching elements S11, S12, and S19 are turned on and turned on when the switching elements S11, S12, and S19 are turned off, respectively. is there. That is, the dummy switching elements D1 to D3 are connected to the switching elements S11, S12, and S19 that are connection destinations. The dummy switching elements D1 to D3 each have an element capacity that is about ½ of the switching elements S11, S12, and S19.

  Hereinafter, the operation of the offset cancel circuit 200 will be described. The offset cancel circuit 200 cancels and outputs the offset value of the output voltage of the Hall element 10 by switching between the first state, the second state, and the output state described below.

  First, as shown in FIG. 2, the offset cancel circuit 200 is set to the first state by performing on / off control of the switching elements S1 to S19 and the dummy switching elements D1 to D3. By turning on the switching element S1 and turning off the switching element S6, the power supply voltage Vcc is applied to the connection point A of the resistors R1 and R3, and turning on the switching element S2 and turning off the switching element S8 to connect the resistors R2 and R4. The point B is grounded, the switching element S7 is turned on and the switching element S4 is turned off to connect the connection point C of the resistors R1 and R2 to the non-inverting input terminal (+) of the operational amplifier 12b, and the switching element S5 is turned on and switched. By turning off the element S3, the connection point D of the resistors R3 and R4 is connected to the non-inverting input terminal (+) of the operational amplifier 12a. Further, by turning on the switching elements S14 and S16 among the switching elements S9 to S19 and turning off the others, the output of the operational amplifier 12a is connected to the positive terminal of the capacitor C1, and the output of the operational amplifier 12b is connected to the negative terminal of the capacitor C1. The capacitor C1 is charged by the output voltages of the operational amplifiers 12a and 12b. This state is the first state.

  At this time, since the switching elements S11, S12, and S19 are off, the dummy switching elements D1 to D3 are turned on.

  Next, as shown in FIG. 3, the offset cancellation circuit 200 is set to the second state by performing on / off control of the switching elements S1 to S19 and the dummy switching elements D1 to D3. By turning on the switching element S6 and turning off the switching element S1, the connection point A of the resistors R1 and R3 is connected to the non-inverting input terminal (+) of the operational amplifier 12a, and the switching element S8 is turned on and the switching element S2 is turned off. To connect the connection point B of the resistors R2 and R4 to the non-inverting input terminal (+) of the operational amplifier 12b, ground the connection point C of the resistors R1 and R2 by turning on the switching element S4 and turning off the switching element S7, The power supply voltage Vcc is applied to the connection point D of the resistors R3 and R4 by turning on the switching element S3 and turning off the switching element S5. Further, by turning on switching elements S15 and S16 among switching elements S9 to S19 and turning off others, the output of operational amplifier 12a is connected to the negative terminal of capacitor C2, and the output of operational amplifier 12b is connected to the positive terminal of capacitor C2. The capacitor C2 is charged by the output voltages of the operational amplifiers 12a and 12b. This state is referred to as a second state.

  At this time, since the switching elements S11, S12, and S19 are off, the dummy switching elements D1 to D3 are turned on.

  In this way, the first and second states are switched by applying a voltage so as to change the direction of the current flowing through the Hall element 10, and the four terminals of the Hall element 10 are changed to Hall voltages V1 and V2 in two directions (90 °). Capacitors C1 and C2 are charged respectively.

  The charging voltage V1 is a value obtained by adding the offset voltage Voff to the Hall voltage Vhall in the first state. That is, the charging voltage V1 = Vhall + Voff. When the current flowing through the Hall element 10 is changed by 90 °, the offset voltage Voff of the Hall element 10 is generated in the reverse direction. Therefore, the charging voltage V2 is obtained by subtracting the offset voltage Voff from the Hall voltage Vhall in the second state. Become. That is, the charging voltage V2 = Vhall−Voff.

  In the output state, as shown in FIG. 4, the switching elements S13 to S16 are turned off, and the operational amplifiers 12a and 12b and the capacitors C1 and C2 are cut off. Further, by turning on the switching elements S11, S12, and S19 and turning off the switching element S18, the positive terminals of the capacitors C1 and C2 are commonly connected to one end of the input terminal of the operational amplifier 20a via the capacitor C4. Further, by turning on the switching elements S9 and S10, the negative terminals of the capacitors C1 and C2 are commonly connected to the other end of the input terminal of the operational amplifier 20a. The other end of the operational amplifier 20a is Vref generated by the reference voltage generation circuit 20b. The switching element S17 for erasing the charge of the capacitor C3 is also turned off.

  At this time, since the switching elements S11, S12, and S19 are on, the dummy switching elements D1 to D3 are turned off.

  By setting the offset cancel circuit 200 to the output state, the capacitors C1 and C2 are connected in parallel, and the charges stored in the capacitors C1 and C2 are redistributed to the capacitors C1, C2 and C3, and the charging voltages V1 and V2 are obtained. Averaged. Thereby, the offset value of the output voltage of the Hall element 10 is canceled and output as the output voltage Vout.

  Here, the operation of the dummy switching elements D1 to D3 will be described with reference to FIGS. FIG. 5 and FIG. 6 schematically illustrate the movement of charge when switching from the state where charge is stored in the capacitors C1 and C2 to the output state after switching between the first state and the second state is completed. It is shown as an example.

  In the configuration in which dummy switching elements D1 to D3 are not provided, capacitors C1 and C2 are charged to voltages V1 and V2, respectively, when switching elements S11, S12, and S19 are off, as shown in FIG. 5A. . At this time, the charge Q1 = V1 / C1 is stored in the capacitor C1, and the charge Q2 = V2 / C2 is stored in the capacitor C2.

  When the switching elements S11, S12, and S19 are turned on, as shown in FIG. 5B, the positive terminals of the capacitors C1 and C2 and the positive terminal of the capacitor C3 are connected, but a part of the charges Q1 and Q2 ΔQ11 , ΔQ12, ΔQ19 are sucked into the channels of the switching elements S11, S12, S19. As a result, the charges Q1 + Q2-ΔQ11−ΔQ12−ΔQ19 are redistributed to the capacitors C1 to C3. This charge ΔQ11 + ΔQ12 + ΔQ19 minutes acts as charge injection noise that depresses the output voltage Vout.

  In the configuration in which the dummy switching elements D1 to D3 are provided, as shown in FIG. 6A, when the switching elements S11, S12, and S19 are off, the capacitors C1 and C2 are charged to the voltages V1 and V2, respectively. The charges QD1, QD2, and QD3 are also charged in the channels of the dummy switch elements D1 to D3.

  When the switching elements S11, S12, and S19 are turned on, the dummy switch elements D1 to D3 are turned off, and the positive terminals of the capacitors C1 and C2 and the positive terminal of the capacitor C3 are connected as shown in FIG. 6B. The At this time, by adjusting the element capacities of the switching elements S11, S12, and S19 and the element capacities of the dummy switching elements D1 to D3, the charges QD1, QD2, and QD3 are sucked into the channels of the switching elements S11, S12, and S19. The charge component can be compensated. As a result, the charges Q1 + Q2 are correctly redistributed to the capacitors C1 to C3, and the output voltage Vout also shows the Hall voltage more correctly.

  Specifically, the element capacities of the dummy switching elements D1 to D3 are preferably about 0.5 to 1.5 times the element capacities of the switching elements S11, S12, and S19.

  FIG. 7 shows a simulation result of the relationship with the output voltage Vout when dummy switching elements are provided in the switching elements S13 to S16. FIG. 7 shows the ratio of the difference with respect to the ideal value of the output voltage Vout when the dummy switching element is not provided and when it is provided. In FIG. 7, the minus sign indicates that the simulation result is lower than the ideal value. As shown in FIG. 7, even if the dummy switching elements are connected to the switching elements S13 to S16, the output voltage Vout is further pushed down, and the effect of reducing charge injection noise with respect to the output voltage Vout is small.

  This is because when the dummy switching elements are connected to the switching elements S13 to S16, the capacitors C1 and C2 are charged in the first state or the second state, and then the switching elements S13 to S16 are turned off and the dummy switching elements are turned on. It is estimated that this is because part of the electric charge stored in the capacitors C1 and C2 is absorbed by the dummy switching element.

  Therefore, it is preferable not to connect a dummy switching element to the switching elements S13 to S16. That is, in the offset cancel circuit 200, when a voltage is applied from the outside so that the current flowing through the Hall element 10 is switched, the output voltage of the Hall element 10 is applied to one of the capacitors C1 and C2 for each state. It is preferable that a dummy switching element is not connected to a switching element used for connecting the output terminals of the operational amplifiers 12a and 12b to the capacitors C1 and C2 in the first state and the second state. is there.

  Further, since the switching elements S9 and S10 have a low impedance after the output state, the effect of reducing charge injection noise with respect to the output voltage Vout is small even if a dummy switching element is connected to the switching elements S9 and S10. Therefore, it is preferable not to connect the dummy switching elements to the switching elements S9 and S10.

  FIG. 8 shows an example of the element structure of the capacitors C1 and C2 in the offset cancel circuit 200.

  The capacitors C1 and C2 are configured by stacking a polysilicon layer 32, an insulating layer 34, and a polysilicon layer 36 on a semiconductor substrate 30. An electrode 38 is formed on the surface of the polysilicon layer 32 in the opening formed by patterning the insulating layer 34 and the polysilicon layer 36. The insulating layer 34 is formed by being stacked on the polysilicon layer 32, and the polysilicon layer 36 is formed by being stacked on the insulating layer 34. An electrode 40 is formed on the surface of the polysilicon layer 36. Output terminals are drawn out from the electrodes 38 and 40.

  The capacitors C1 and C2 having such a structure utilize the capacitance between the electrode 38 and the electrode 40 in a state where the semiconductor substrate 30 is grounded. FIG. 9 shows an equivalent circuit of the capacitors C1 and C2. As shown in FIG. 9, capacitors C1 and C2 are connected to a parasitic capacitance Cx formed on the semiconductor substrate 30.

  When such capacitors C1 and C2 are used, as shown in FIG. 10A, they are connected to the operational amplifiers 12a and 12b so that the parasitic capacitance Cx is arranged on the positive terminal side of the capacitors C1 and C2 of the offset cancel circuit 200. Then, when the charge stored in the capacitors C1 and C2 in the output state is redistributed to the capacitors C1, C2 and C3, the charge is also added to the parasitic capacitance Cx in addition to the capacitors C1, C2 and C3 in the floating state. It will be reallocated. As a result, an output voltage Vout lower than the correct Hall voltage is output.

  On the other hand, as shown in FIG. 10B, when connected to the operational amplifiers 12a and 12b so that the parasitic capacitance Cx is arranged on the negative terminal side of the capacitors C1 and C2 of the offset cancel circuit 200, the capacitors C1 and C2 in the output state. When the charge stored in is redistributed to the capacitors C1, C2 and C3, the negative terminals of the capacitors C1 and C2 and the terminal of the parasitic capacitance Cx are set to the reference voltage Vref. Charges corresponding to the reference voltage Vref are supplied from the reference voltage generation circuit 20b and the like to the parasitic capacitance Cx, and the charges stored in the capacitors C1 and C2 are correctly redistributed to the capacitors C1, C2, and C3. As a result, the output voltage Vout becomes closer to the correct Hall voltage.

  There is a difference in reference voltage between charging the capacitors C1 and C2 and redistributing the charges to the capacitors C1, C2 and C3. This reference voltage difference is a difference between the center voltage of the Hall element 10 and the reference voltage of the reference voltage generation circuit 20b used in the operational amplifier 20a. In addition to this voltage difference, due to the influence of charges due to parasitic capacitance, an offset occurs during comparison in the operational amplifier 20a. By arranging the parasitic capacitance Cx as shown in FIG. 10B, it is possible to reduce the influence of the offset at the time of comparison in the operational amplifier 20a.

  As described above, according to the embodiment of the present invention, it is possible to cancel the offset voltage of the output voltage of the Hall element and reduce the influence of charge injection noise on the offset cancel circuit.

  10 Hall element, 12 amplifier circuit, 12a, 12b operational amplifier, 14 averaging circuit, 14a operational amplifier, 14b reference voltage generation circuit, 20 averaging circuit, 20a operational amplifier, 20b reference voltage generation circuit, 30 semiconductor substrate, 32 polysilicon layer, 34 Insulating layer, 36 Polysilicon layer, 38 electrodes, 40 electrodes, 100, 200 Offset cancel circuit.

Claims (2)

An offset cancel circuit for a Hall element,
Multiple capacitors,
A voltage is applied from the outside so that the current flowing through the Hall element is switched, and on / off control is performed so that the output voltage of the Hall element is applied to one of the plurality of capacitors for each state. A group of switching elements;
A second switching element group that is on / off controlled so that an output voltage corresponding to the electric charge charged in the plurality of capacitors is output in a state where the plurality of capacitors are connected in parallel;
Each of the plurality of capacitors has a configuration in which a parasitic capacitance is connected to one of its both terminals,
In a state where the plurality of capacitors are connected in parallel, a reference voltage is applied to one output terminal of the plurality of capacitors connected in parallel, and the reference voltage is applied among both terminals of the plurality of capacitors. An offset cancel circuit, wherein the parasitic capacitance is connected to the terminal side. The offset cancel circuit according to claim 1,
Each of the plurality of capacitors is
A semiconductor substrate;
A first semiconductor layer formed on the semiconductor substrate;
An insulating layer formed on the first semiconductor layer;
A second semiconductor layer formed on the insulating layer,
An offset cancellation circuit, wherein the reference voltage is applied to the first semiconductor layer and the semiconductor substrate is grounded in a state where the plurality of capacitors are connected in parallel.

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