JP5143542B2 - Source code conversion program and apparatus based on processor device - Google Patents

Description

  The present invention relates to a source code conversion program and apparatus.

  Various wireless communication systems such as mobile phones, PHS, and wireless LANs differ in output level, frequency band, modulation system, and the like. Therefore, in order to cope with a plurality of communication methods, the communication device has to be preinstalled with a dedicated signal processing circuit (hardware) for each communication method. However, the communication method of the communication device often differs depending on the usage mode or communication environment of the user. Assuming a plurality of communication methods that a user will use, it is difficult to pre-install hardware corresponding to them in the cellular phone from the viewpoint of processing capability, volume, and cost of the cellular phone.

  On the other hand, there is a software defined radio (SDR) technology corresponding to various different wireless communication systems by rewriting software of a wireless interface unit of a communication device. According to this technique, since the communication method of the communication device can be updated by updating the software module, it is not necessary to install hardware in advance, and it can be said that it is effective in terms of volume and cost.

  According to the software defined radio technology, the communication device can use general-purpose hardware, while realizing most of the processing depending on the communication method by software. Software modules are updatable and new communication schemes can be accommodated by downloading and executing new software modules without having to replace hardware.

  Here, in order to execute a program at high speed in hardware, a DSP (Digital Signal Processor) processor device provided with a high-speed arithmetic unit in addition to a general-purpose arithmetic unit is also commercially available (see, for example, Non-Patent Document 1). .

  There is also a technique for converting an original source code into an optimal source code in order to execute a program at high speed in terms of software (see, for example, Patent Document 1). According to this technique, dependency relationships between data are analyzed, and the number of instructions to be optimized is tabulated as an optimization factor based on the analysis result. The original source code is converted so as to select a plurality of optimization methods and their execution order according to the result of aggregation of the optimization factors.

Stretch Co., Ltd., “S5530”, [online], [December 10, 2007 search], Internet <URL: http://www.stretchinc.co.jp/_files/s5530chip_E.pdf> Japanese Patent Laid-Open No. 9-319586

  However, even if a processor device that executes a software radio software module is general-purpose, it is difficult to unify the characteristics of all communication devices. In reality, processor devices equipped with various types of high-speed arithmetic units are commercially available. On the other hand, all the source codes of software defined radio are the same, although the characteristics of the high-speed calculation unit of the processor device are different. In order to create an optimum source code for a specific high-speed operation unit, it is necessary to recode the source code manually. Moreover, even if such an optimal source code is created, it cannot be used in other high-speed arithmetic units, and eventually versatility is lost.

  According to the technique described in Patent Document 1, the program is optimized only in the original source code, and is not optimized in consideration of hardware characteristics. That is, even if different high-speed arithmetic units are used, the source code to be converted is the same. On the other hand, in order to spread software radio technology for communication terminals such as mobile phones, it is preferable to convert the original source code serving as a base into a program that takes advantage of the characteristics of each processor device.

  Therefore, an object of the present invention is to provide a source code conversion program and apparatus for converting an original source code into a source code that can be operated at high speed in accordance with the characteristics of a high-speed operation unit of a processor device.

According to the present invention, in a program for causing a computer to function as conversion means for converting original source code into source code adapted to a processor device having a general-purpose arithmetic unit and a high-speed arithmetic unit ,
Against
The conversion means converts the original source code into a function definition program to be executed by the high-speed calculation unit and a function call program to be executed by the general-purpose calculation unit .
The function definition program has a variable of the number of operation inputs when the number of operation inputs and / or the number of operation outputs described in the original source code is equal to or less than the number of input registers and / or output registers of the high-speed operation unit. An operation function and / or an output function having a variable of the number of operation outputs are defined.
The function calling program causes the computer to function so that the original source code is converted so as to call the calculation function and / or the output function of the function definition program .

According to another embodiment of the source code conversion program of the present invention,
The converting unit is configured to calculate the input data size and / or output data size of the output register of the high-speed operation unit and the plurality of operation input data sizes and / or operation output data sizes described in the original source code once. The number of array elements of variables that can be input and / or output is calculated, and according to the number of array elements of the variables, the functions and / or output functions between the function definition program and the function calling program are calculated. It is also preferred to have the computer function to define the passing of variables .

  According to another embodiment of the source code conversion program of the present invention, the function definition program and the function call program are preferably executed by the processor device to function as a software radio interface unit.

According to the present invention, there is provided a program conversion apparatus for converting an original source code into a source code adapted to a processor device having a general-purpose arithmetic unit and a high-speed arithmetic unit ,
The original source code is converted into a function definition program to be executed by the high-speed calculation unit and a function call program to be executed by the general-purpose calculation unit .
The function definition program has a variable of the number of operation inputs when the number of operation inputs and / or the number of operation outputs described in the original source code is equal to or less than the number of input registers and / or output registers of the high-speed operation unit. An operation function and / or an output function having a variable of the number of operation outputs are defined.
The function calling program is converted from the original source code so as to call the calculation function and / or the output function of the function definition program .

  According to the source code conversion program and apparatus of the present invention, the original source code is converted into the source code in which the function definition program is described according to the processing unit of the high-speed operation unit. It can be operated at high speed on the device.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a system configuration diagram based on software defined radio technology.

  According to FIG. 1, a communication terminal 1 is connected to a network 4 via a base station 3 connected by a wireless link. Further, the module distribution server 2 is further connected to the network 4.

  The radio interface unit of the communication terminal 1 functions as software radio. The communication terminal 1 receives the software radio software module from the module distribution server 2 via the network 4. According to FIG. 1, the communication terminal 1 transmits communication state information to the module distribution server 2. On the other hand, the module distribution server 2 transmits to the communication terminal 1 a software radio software module that is optimal for the communication state information. As a result, the communication terminal 1 can support different communication methods without changing the hardware.

  According to FIG. 1, the communication terminal 1 includes a processor device 10 that is a DSP chip based on hardware, a radio interface unit (software radio) unit 11, a module storage unit 12, and a module reconfiguration unit 13.

  The processor device 10 includes a general-purpose arithmetic unit 100 and a high-speed arithmetic unit 101. The high-speed calculation unit 101 is restricted in the number of input registers and output registers, the input data size, and the output data size in order to perform high-speed calculations. The general-purpose arithmetic unit 100 causes the high-speed arithmetic unit 101 to execute processing within the range of the constraint condition.

  The wireless interface unit 11 functions when a software module is executed by the processor device 10. The module storage unit 12 stores the software module received from the module distribution server 2. The module reconfiguration unit 13 transmits communication state information to the module distribution server 2 and receives an optimal software module from the module distribution server 2.

  FIG. 2 is an explanatory diagram of source code conversion in the present invention.

  According to FIG. 2, by executing the source code conversion program based on the present invention on a computer, the original source code is converted into a “function definition program” and a “function call program”. Each function described in the function definition program is generated in units that can be executed by the high-speed arithmetic unit. The function call program executes processing by calling each function described in the function definition program.

  FIG. 3 is an explanatory diagram of various high-speed arithmetic units.

  The high-speed calculation unit built in the processor device has various restrictions because it calculates at high speed. According to FIG. 3, there are two-input one-output and three-input two-output types. The input / output data size ranges from 128 bits to 64 bits. Furthermore, the size of the internal memory of the high-speed arithmetic unit also ranges from 256 Kbytes to 64 Kbytes. According to the present invention, each function described in the function definition program is defined according to the type of the high-speed arithmetic unit.

In the following description, the “function definition program” and the “function call program” converted from the original source code will be specifically described. In the high-speed calculation unit, there are the following description methods unique to the high-speed calculation unit.
WR: Variable type used in the high-speed calculation unit
WRGETINIT (): A function that sets the start address of the array to be passed to the high-speed computation unit
WRGETI (): How many bits from the start address set by WRGETINIT ()
Function to set whether to pass to the high-speed operation
WRS16I (): A function to extract an array from the high-speed calculation unit

First, an example of original source code for a high-speed arithmetic unit with two inputs and one output will be shown.
[Original source code (2 inputs, 1 output)]
start Filtering Baseband [S11]
alloc int TempI [S12]
alloc int iDataI
alloc int iTap

for (i = 0; i <(Num * CHIP_SAMP + TAP_NUM); i ++) {
init TempI = 0 [S13]
loop_init j = 0 [S14]
loop_condition j <48
loop_renew j + = 1
calc_input iDataI = FIDMADataI [DMAOffset + i-(2 * TAP_NUM-1) + j]
calc_input iTap = RxFilterFCHBBFTap [j] [S15]
calc_calc TempI + = iDataI * iTap
loop_end
output DataI [i] = TempI >> 14
}
end

The original source code described above is written in the standard C language and expanded using the following notation. The original source code is converted while sequentially judging these notations.
start: Start the program generation process
alloc: Variable used for operation
init: Variable initialization
loop_init: Initial value of the loop
loop_condition: Loop termination condition
loop_renew: Processing executed during iteration
loop_end: End of the loop
calc_input: Input used for calculation
calc_calc: Calculation processing
output: Output of operation
end: End of program generation process Further, according to the above-described original source code, it can be understood that there are two “calc_input” notations and one “output” notation, so that there are two inputs and one output.

This is a function definition program when the above-described two-input one-output original source code is converted.
[Function definition program (2 inputs, 1 output)]
static se_sint <32>TempI; [S12]
static se_sint <32>iDataI;
static se_sint <32>iTap;

SE_FUNC void Filtering_Baseband_init () {[S13]
TempI = 0;
}

SE_FUNC void Filtering_Baseband_calc (WR A, WR B) {[S16]
int i;
for (i = 0; i <4; i ++) {
iDataI = A (32 * i + 32, 32 * i); [S17]
iTap = B (32 * i + 32, 32 * i);
Temp I + = iData * iTap;
}
}

SE_FUNC void Filtering_Baseband_output (WR * A) {[S18]
* A = TempI >>14;
}

This is a function call program when the above-described 2-input 1-output original source code is converted.
[Function call program (2 inputs, 1 output)]
WR A, B; [S11]

for (i = 0; i <(Num * CHIP_SAMP + TAP_NUM); i ++) {
Filtering_Baseband_init (); [S13]
for (j = 0; j <48; j + = 4) {[S14]
WRGETOINIT (WRGET_INIT_INCREMENT,
& FIDMADataI [DMAOffset + i-(2 * TAP_NUM-1) + j]);
WRGETOI (& A, 32); [S15]
WRGETO1INIT (WRGET_INIT_INCREMENT, & RxFilterFCHBBFTap [j]);
WRGETO1I (& B, 32);
Filtering_Baseband_calc (A, B); [S16]
}
Filtering_Baseband_output (&A); [S18]
WRS16I (A, & DataI [i], 0);
}

  Hereinafter, how the above-described function definition program and function call definition program are derived will be described.

First, the characteristics of the high-speed calculation unit are defined. The processor device (DSP (Digital Signal Processor) chip) described in Non-Patent Document 1 has a general-purpose arithmetic unit and a high-speed arithmetic unit. The high-speed arithmetic unit has the following restrictions. According to the present invention, within these restrictions, the original source code is converted into source code that can optimally use the high-speed arithmetic unit.
(1) Maximum number of inputs (number of input registers) = 3 Maximum number of outputs (number of output registers) = 2 (2) Input register data size = 128 bits maximum Output register data size = 128 bits maximum

[S11] When “start” is written in the original source code, “calc_input” is searched until “end” is written. Then, the data size of the variable described in the “calc_input” notation is extracted. According to the above-mentioned original source code, the variables “iDataI”, “iTap”, and “TempI” are detected, and the data size of each variable can be extracted from the description of “alloc” notation as follows.
“IDataI”: int 32bit
"ITap": int 32bit
“TempI”: int 32bit

Next, the number of input variable array elements that can be input at one time based on the data size of the input register of the high-speed arithmetic unit and the maximum data size (32 bits) of all variables in the “calc_input” notation (Hereinafter referred to as “packing number”). According to the above-described example, the data size of the input / output register is 128 bits, and the packing number is calculated as follows.
128 bits (data size) / 32 bits (int) = 4

[S12] Next, as many static variables as the number of “alloc” are reserved in the function definition program. These variables are used in the function definition program, and the internal memory of the high-speed calculation unit is used.

[S13] If "init" is written in the original source code, an "initialization function" (Filtering_Baseband_init ()) is defined in the function definition program. Moreover, it describes so that the function may be called from a function calling program.

[S14] If “loop_init”, “loop_condition”, and “loop_renew” are written in the original source code, a for statement is written in the function calling program. As described above, four 32-bit variables can be input to the high-speed arithmetic unit at a time. In this case, the calculation repeated 48 times is reduced to 48 times / 4 pieces = 12 times. Therefore, the increment value based on the “loop_renew” notation is replaced with the packing number (4).

[S15] Next, in the for statement in the function calling program, the setting of the start address (WRGETINIT ()) of the array to be passed to the high-speed operation unit is described, and the definition of how many bytes are passed from the start address (WRGETI () )

[S16] When “calc_input” is written in the original source code, the number of “calc_input” is searched. If the number of “calc_input” is larger than the maximum number of inputs (number of input registers) of the high-speed computation unit, it is excluded from the source code conversion target. For example, when the maximum value of the number of inputs of the high-speed calculation unit is 3 and the number of “calc_input” is 4, it is excluded from the source code conversion target.

  On the other hand, for example, it is assumed that the maximum value of the number of inputs of the high-speed calculation unit is 3 and the number of “calc_input” is 2. In this case, a calc function having a variable corresponding to the number of “calc_input” is defined in the function definition program (Filtering_Baseband_calc (WR A, WR B)). In the calc function, a for statement is described so as to loop as many as the number of elements of the array to be passed to the high-speed calculation unit at a time. In the function call program, a call to the calc function having as many input variables as “calc_input” is described.

[S17] Copy the calculation contents of “calc_calc” written in the original source code into the for statement of the calc function of the function definition program.

[S18] When “output” is written in the original source code, the number of “output” is searched. If the number of “output” is larger than the maximum value of the number of outputs (number of output registers) of the high-speed operation unit, it is excluded from the source code conversion target. For example, when the maximum value of the number of outputs of the high-speed calculation unit is 2 and the number of “output” is 3, it is excluded from the source code conversion target.

  On the other hand, for example, it is assumed that the maximum value of the number of outputs of the high-speed calculation unit is 2 and the number of “output” is 1. In this case, an output function (Filtering_Baseband_output (WR * A)) having as many variables as “output” in the function definition program is defined in the function definition program. Then, the processing content of “output” notation of the original source code is copied into the function of the function definition program. In the function call program, describe a call to the output function having as many variables as “output” and write the final output (WRS16I ()).

Next, an example of the original source code for the high-speed arithmetic unit with three inputs and two outputs is shown. By comparing with the above-mentioned 2-input 1-output source code, the difference in the program according to the number of inputs and outputs is clearly shown.
[Original source code (3 inputs, 2 outputs)]
start Filtering Baseband [S21]
alloc int TempI [S22]
alloc int TempQ
alloc short iDataI
alloc short iDataQ
alloc short iTap

for (i = 0; i <(Num * CHIP_SAMP + TAP_NUM); i ++) {
init TempI = 0 [S23]
init TempQ = 0
loop_init j = 0 [S24]
loop_condition j <48
loop_renew j + = 1
calc_input iDataI = FIDMADataI [DMAOffset + i-(2 * TAP_NUM-1) + j]
calc_input iTap = RxFilterFCHBBFTap [j] [S25]
calc_input iDataQ = FIDMADataQ [DMAOffset + i-(2 * TAP_NUM-1) + j]
calc_calc TempI + = iDataI * iTap
calc_calc TempQ + = iDataQ * iTap
loop_end
output DataI [i] = TempI >> 14
output DataQ [i] = TempQ >> 14
}
end

  According to the original source code described above, since there are three “calc_input” notations and two “output” notations, it can be understood that there are three inputs and two outputs.

This is a function definition program when the above-described 3-input 2-output original source code is converted.
[Function definition program (3 inputs, 2 outputs)]
static se_sint <32>TempI; [S22]
static se_sint <32>TempQ;
static se_sint <16>iDataI;
static se_sint <16>iDataQ;
static se_sint <16>iTap;

SE_FUNC void Filtering_Baseband_init () {[S23]
TempI = 0;
TempQ = 0;
}

SE_FUNC void Filtering_Baseband_calc (WR A, WR B, WR C) {[S26]
int i;
for (i = 0; i <8; i ++) {
iDataI = A (16 * i + 15, 16 * i);
iTap = B (16 * i + 15, 16 * i);
iDataQ = C (16 * i + 15, 16 * i);
TempI + = iDataI * iTap; [S27]
TempQ + = iDataQ * iTap;
}
}

SE_FUNC void Filtering_Baseband_output (WR * A, WR * B) {[S28]
* A = TempI >>14;
* B = TempQ >>14;
}

This is a function call program when the above-described original source code with three inputs and two outputs is converted.
[Function call program (3-input 2-output)]
WR A, B, C; [S21]

for (i = 0; i <(Num * CHIP_SAMP + TAP_NUM); i ++) {
Filtering_Baseband_init (); [S23]
for (j = 0; j <48; j + = 8) {[S24]
WRGETOINIT (WRGET_INIT_INCREMENT, [S25]
& FIDMADataI [DMAOffset + i-(2 * TAP_NUM-1) + j]);
WRGETOI (& A, 16);
WRGET2INIT (WRGET_INIT_INCREMENT, & RxFilterFCHBBFTap [j]);
WRGET2I (& B, 16);
WRGETO1INIT (WRGET_INIT_INCREMENT,
& FIDMADataQ [DMAOffset + i-(2 * TAP_NUM-1) + j]);
WRGETO1I (& C, 16);
Filtering_Baseband_calc (A, B, C); [S27]
}
Filtering_Baseband_output (& A, &B); [S28]
WRS16I (A, & DataI [i], 0);
WRS16I (B, & DataQ [i], 0);
}

[S21] If there is a “start” notation in the original source code, the data size of the variable described in the “calc_input” notation is extracted. According to the above-mentioned original source code, the variables “iDataI”, “iDataQ”, and “iTap” are detected, and the data size of each variable can be extracted from the description of “alloc” notation as follows.
"IDataI""iDataQ": short 16bit
"ITap": short 16bit

Next, packing the array elements of input variables that can be input at once from the data size of the input register of the high-speed arithmetic unit and the maximum data size (16 bits) of all the variables in the “calc_input” notation Calculate the number. According to the above-described example, the data size of the input / output register is 128 bits, and the packing number is calculated as follows.
128 bits (data size) / 16 bits (int) = 8

[S22] Next, as many static variables as the number of “alloc” are reserved in the function definition program. These variables are used in the function definition program, and the internal memory of the high-speed calculation unit is used.

[S23] If "init" is written in the original source code, an "initialization function" (Filtering_Baseband_init ()) is defined in the function definition program. Moreover, it describes so that the function may be called from a function calling program.

[S24] If the original source code includes “loop_init”, “loop_condition”, and “loop_renew”, a for statement is described in the function call program. As described above, eight 16-bit variables can be input to the high-speed arithmetic unit at a time. In this case, the calculation repeated 48 times is reduced to 48 times / 8 pieces = 6 times. Therefore, the increment value based on the “loop_renew” notation is replaced with the packing number (8).

[S25] Next, in the for statement in the function call program, the setting of the start address (WRGETINIT ()) of the array to be passed to the high-speed calculation unit is described, and the definition of how many bytes to pass from the start address (WRGETI () )

[S26] When "calc_input" is written in the original source code, the number of "calc_input" is searched. The number of “calc_input” is the same as the number (3) of the “calc_input” notation because the maximum value (3) of the number of inputs (number of input registers) of the high-speed arithmetic unit is equal to “calc_input”. Define a calc function with a variable equivalent to the number of "(Filtering_Baseband_calc (WR A, WR B, WR C)). In the calc function, a for statement is described so as to loop as many as the number of elements of the array to be passed to the high-speed calculation unit at a time. In the function call program, a call to the calc function having as many input variables as “calc_input” is described.

[S17] Copy the calculation contents of “calc_calc” written in the original source code into the for statement of the calc function of the function definition program.

[S28] If there is "output" written in the original source code, the number of "output" written is searched. The number (2) indicated by “output” is equal to the maximum value (2) of the number of outputs (number of output registers) of the high-speed arithmetic unit. In this case, an output function (Filtering_Baseband_output (WR * A, WR * B)) having as many variables as “output” is defined in the function definition program. Then, the processing content of “output” notation of the original source code is copied into the function of the function definition program. In the function call program, describe a call to the output function having as many variables as “output” and write the final output (WRS16I ()).

  As described above in detail, according to the source code conversion program and apparatus of the present invention, the original source code is converted into the source code describing the function definition program according to the processing unit of the high-speed operation unit. The converted source code can be calculated at high speed by the processor device.

  In particular, according to the present invention, it is possible to input a plurality of array elements at once according to the number of inputs / outputs and / or the input / output data size of the high-speed arithmetic unit, and to execute the processing in the combined form. . As a result, a significant improvement in processing speed can be expected as compared with the case where one element of an array is calculated one by one. However, since the high-speed calculation unit performs high-speed calculations, there are restrictions on the number of input / output and / or the input / output data size. According to the present invention, the calculation speed as a processor device can be increased by converting into an optimal source code in consideration of this restriction.

  In the various embodiments of the present invention described above, various changes, modifications, and omissions in the scope of the technical idea and the viewpoint of the present invention can be easily made by those skilled in the art. The above description is merely an example, and is not intended to be restrictive. The invention is limited only as defined in the following claims and the equivalents thereto.

It is a system configuration diagram based on software radio technology. It is explanatory drawing of the source code conversion in this invention. It is explanatory drawing of various high-speed calculating parts.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Communication terminal 10 Processor device 100 General-purpose calculating part 101 High-speed calculating part 11 Wireless interface part (software radio)
12 Module storage unit 13 Module reconfiguration unit 2 Module distribution server 3 Base station 4 Network

Claims (4)

In a program for causing a computer to function as conversion means for converting original source code into source code adapted to a processor device having a general-purpose arithmetic unit and a high-speed arithmetic unit ,
The converting means converts the original source code into a function definition program to be executed by the high-speed arithmetic unit and a function call program to be executed by the general-purpose arithmetic unit ,
The function definition program determines the number of operation inputs when the number of operation inputs and / or operation outputs described in the original source code is equal to or less than the number of input registers and / or output registers of the high-speed operation unit. A function for calculation having a variable and / or a function for output having a variable of the number of operation outputs,
The function calling program causes the computer to function so as to be converted from the original source code so as to call the calculation function and / or the output function of the function definition program. A featured source code conversion program. The conversion means includes an input data size of an input register and / or an output data size of an output register of the high-speed arithmetic unit, and a plurality of arithmetic input data sizes and / or arithmetic output data sizes described in the original source code. Calculating the number of array elements of variables that can be input and / or output at a time, and depending on the number of array elements of the variables, the calculation function between the function definition program and the function call program and / or or source code converter according to claim 1, characterized by causing a computer to function in <br/> so defining the delivery of variables of the output function. 3. The source code conversion program according to claim 1, wherein the function definition program and the function call program function as a wireless interface unit of software defined radio when executed by the processor device. 4. A program conversion apparatus for converting an original source code into a source code adapted to a processor device having a general-purpose arithmetic unit and a high-speed arithmetic unit ,
The pre Kihara source code, and the function definition program to be executed by the high-speed arithmetic unit, which converts the in the function call program to be executed by the general-purpose arithmetic unit,
The function definition program determines the number of operation inputs when the number of operation inputs and / or operation outputs described in the original source code is equal to or less than the number of input registers and / or output registers of the high-speed operation unit. A function for calculation having a variable and / or a function for output having a variable of the number of operation outputs,
The program conversion apparatus , wherein the function calling program is converted from the original source code so as to call the calculation function and / or the output function of the function definition program. .

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