JP5136670B2 - Signal detection device, radio device, and signal detection method - Google Patents

Description

The present invention is, for example CDCSS (ContiuousDigital-Controlled-Squelch- System) relates to a device and method for detecting the presence or absence of the signal, such as, more particularly signals that detect accurately the signal to suppress the influence from the noise detection apparatus, and a radio及bicine No. detection method.

  One of the signaling used in the radio is CDCSS. In the CDCSS, the transmitter superimposes the 134.4 bps Golay (23, 12) code on the audio signal and transmits the signal, and the receiver controls the squelch by comparing the received detection code with a predetermined standby code. System.

  In Patent Document 1, a squelch control signal related to CDCSS (hereinafter, abbreviated as “CDCSS signal” as appropriate) is transmitted by FSK modulation from the transmission side to the reception side during a period in which PTT (PushToTalk) is operated on the transmission side. On the receiving side, it is disclosed that the squelch circuit is opened and the sound from the transmitting side is output during the reception period of the CDCSS signal.

  FIG. 15 is a block diagram of a CDCSS decoding processing device 150 in a conventional radio receiver. In the CDCSS decoding processing device 150, the same elements as those of the CDCSS decoding processing device 10 (FIG. 1) described in the best mode of the present invention to be described later are designated by the same reference numerals as those of the CDCSS decoding processing device 10. The main points of the CDCSS decoding processing device 150 will be described.

  The CDCSS inspection unit 151 includes a CDCSS bit determination unit 152 and a CDCSS code determination unit 153. In the CDCSS inspection unit 151, the CDCSS bit determination unit 152 performs CDCSS bit determination on the input signal from the DC follower unit 14 (hereinafter referred to as "CDCSS extraction detection signal component" as appropriate), and then the CDCSS code The determination unit 153 performs CDCSS code determination on the input from the CDCSS bit determination unit 152. The CDCSS bit determination is processing for determining whether the value of each bit period of the detection signal component for CDCSS is “1” or “0” by comparing the level of the detection signal component for CDCSS with a predetermined threshold value. It is.

  FIG. 16 is an explanatory diagram of CDCSS bit determination in the CDCSS decoding processing device 150. In FIG. 16, the upper part shows the detection signal component for CDCSS extraction (input of the CDCSS bit determination unit 152), and the lower part shows the CDCSS determination data signal (output of the CDCSS bit determination unit 152) as a bit determination result. If the level of the detection signal component for CDCSS extraction is + with respect to 0 of the reference, it is determined as a binary logical value “1”, and if it is −, it is determined as “0”. In this way, as an output of the CDCSS bit determination unit 152, a CDCSS determination data signal whose level is associated with “1” and “0” of the determination result is generated.

  In the CDCSS code determination unit 153, the 23 bits of the CDCSS determination data signal are set as one CDCSS determination data, and the value of each bit of the CDCSS determination data matches the value of the corresponding bit of the 23-bit predetermined standby CDCSS data. If the number of error bits (the number of bits whose values do not match) is equal to or less than a predetermined threshold value, it means that a CDCSS code match, that is, a CDCSS signal assigned to the radio receiver has been received. ,judge.

JP 2000-341046 A

  When intermittent audio frequency band signaling (for example, DTMF (DialToneMultiFrequency) signal or MSK (MinimumShiftKeyig) signal) is input to a radio equipped with such a CDCSS decoding processing device 150, these signals are detected in the detection signal component for CDCSS extraction. Noise due to the signaling will be mixed. If the intermittent period of the noise happens to be similar to the CDCSS code, it may be erroneously determined that the CDCSS code matches.

  FIG. 17 shows an example of a DTMF signal that may cause an error in CDCSS code determination in the CDCSS code determination unit 153 of the CDCSS decoding processing device 150. FIG. 18 shows the detection signal component for CDCSS extraction when the intermittent DTMF signal as shown in FIG. 17 is input to the CDCSS decoding processing device 150 and the CDCSS determination data signal generated by performing the CDCSS bit determination on the detected component. . In the conventional CDCSS decoding processing device 150, the CDCSS bit determining unit 152 determines “1” or “0” depending on whether the level of the input signal is + or − with respect to the reference 0, so that the DTMF signal is converted into the DTMF signal. If the resulting noise becomes the detection signal component for CDCSS extraction and the vertical fluctuation of the detection signal component for detection of CDCSS with respect to the reference level is periodically similar to the detection signal component for detection of CDCSS related to the genuine CDCSS signal, CDCSS There is a possibility that the code determination unit 153 erroneously makes a CDCSS code match determination on the detection signal component for CDCSS extraction related to noise.

  Although Patent Document 1 refers to decoding processing of a squelch control signal on the receiving side, it does not refer to measures for suppressing the influence of noise caused by a signaling signal in the audio frequency band on CDCSS code match determination.

An object of the present invention, even when variation is confusing and variation of the signal of the authenticity noise is mixed into the detection wave signal component, signal detecting apparatus that detect accurately the presence or absence of the signal, radio及bicine No. detected Is to provide a method.

A signal detection apparatus according to the present invention is a signal detection apparatus that determines whether or not a predetermined standby code is included in a detection code as a logical value sequence generated from a detection signal. Yes.
Detection code generation means for generating the detection code by comparing at least a part of the detection signal with a threshold value for bit determination every predetermined period;
Every predetermined period of time, by comparing the invalid determining threshold value which defines a predetermined range including the bit determining threshold value, or is valid or invalid detection sign-generated in a predetermined time period Determining means for determining
The detection code versus code waiting for each logical value, if said standby logic value of the code and the logical value of the generated detecting code in code generating means is different, or, detects a logic value of the detection marks No. predetermined Is determined by the error bit determination means in the error bit determination means having the logical value as an error bit and the detection code in the period corresponding to the standby code. Signal detection means for determining that the standby code is included in the detection signal when the ratio of error bits is less than a predetermined value.

In the signal detection apparatus of the present invention, the standby code is preferably a logical value sequence consisting of logical “0” or logical “1”,
The detection code generation means compares at least a part of the detection signal with a threshold value for bit determination every predetermined period, and detects the detection code as a logical value string composed of logic “0” or logic “1”. generates, determination means determines whether at least a portion of the component, every predetermined time period, is valid or invalid predetermined period by comparing the invalid determining threshold value of the detection signal In addition, if the predetermined period is valid, a logical “0” is generated, and if the predetermined period is invalid, an invalid bit string is generated that is logical “1”.
The error bit determination means calculates the exclusive OR of corresponding bits of the standby code and the detection code to generate exclusive OR data, and calculates the OR of the exclusive OR data and the invalid bit string. ,
The signal detection means compares the number of logic "1" with a predetermined threshold value, so that the ratio of error bits determined by the error bit determination means in the detection code in the period corresponding to the standby code is less than a predetermined value. Determine whether or not.

More preferably, the signal detection device of the present invention includes a standby code not included when the number of logical “1” s in the invalid bit string generated by the determination means in a period corresponding to the standby code is greater than or equal to a predetermined value. Signal detection means for determining is included.

The wireless device of the present invention is equipped with the signal detection device described above.

The signal detection method of the present invention is a signal detection method for determining whether or not a predetermined standby code is included in a detection code as a sequence of logical values generated from a detection signal, and includes the following steps.
A detection code generation step for generating a detection code by comparing at least a part of the detection signal with a threshold value for bit determination every predetermined period;
Every predetermined period of time, by comparing the invalid determining threshold value which defines a predetermined range including said bit determining threshold value, is valid or invalid detection sign-generated in a predetermined time period A determination step for determining whether or not
The detection code versus code waiting for each logical value, if the logical value of the code waiting the logical value of the detected code generated at code generating step is different, or, given that detects a logic value of the detection marks No. The error bit determined by the error bit determination step in the error bit determination step in which the logical value is an error bit and the detection code in the period corresponding to the standby code when the period is determined to be invalid by the invalidity determination means A signal detection step of determining that a standby code is included in the detection signal when the ratio is less than a predetermined value.

According to the present invention, the level determination of the detection wave signal component, to set the level range of "invalid", when該検wave signal component is in the level range of "invalid" is as invalid level determination,該検wave Since the extracted code from the signal component is evaluated, erroneous evaluation of the extracted code can be suppressed.

It is a block diagram of a CDCSS decoding processing device. It is a flowchart of the processing content in a CDCSS decoding processing apparatus. It is a figure explaining the basic concept about the process of a CDCSS test | inspection part. It is a figure which shows the relationship between the detection signal component for CDCSS extraction formed with the noise from a DTMF signal, and the bit determination signal about this detection signal component for CDCSS extraction. It is a detailed flowchart of a CDCSS bit determination processing routine.

It is a detailed flowchart of VI determination processing routine. It is a detailed flowchart of a CDCSS code check routine. 6 is a detailed flowchart of another CDCSS code check routine. FIG. 9 is a flowchart of a routine for counting invalid bits in the CDCSS code check of FIG. 8. FIG. 10 is a diagram showing a shift register for holding 23-bit VI determination data used in the routine of FIG. 9.

It is a block diagram of a squelch control signal detection device. It is a block diagram of another squelch control signal detection apparatus. It is a flowchart of a squelch control signal detection method. It is a flowchart of a squelch control signal detection method. It is a block diagram of the CDCSS decoding processing apparatus in the conventional radio | wireless receiver.

It is explanatory drawing of CDCSS bit determination in the conventional CDCSS decoding processing apparatus. It is a figure which shows an example of the DTMF signal which may cause an error in the CDCSS code determination in the CDCSS code determination part of the conventional CDCSS decoding processing apparatus. FIG. 18 is a diagram showing a detection signal component for CDCSS extraction when an intermittent DTMF signal as shown in FIG. 17 is input to the CDCSS decoding processing device and a CDCSS determination data signal generated by performing CDCSS bit determination on the detected component.

  FIG. 1 is a block diagram of the CDCSS decoding processing apparatus 10. The CDCSS decoding processing apparatus 10 is installed in a wireless communication device (not shown). The detection signal is output from a detection circuit (not shown) of the wireless communication device and input to the low pass filter 11. The low-pass filter 11 has a cutoff frequency set to 300 Hz, and outputs only a detection signal component of 300 Hz or less to the thinning unit 12. In the wireless communication device, the baseband signal is divided into an audio frequency band higher than 300 Hz and a squelch frequency band lower than the baseband signal. The detection signal component sent from the low-pass filter 11 to the thinning-out unit 12 is a signal component in the squelch frequency band.

  The thinning unit 12 thins the input signal from the low-pass filter 11 to lower the sampling frequency. In order to prevent blocking from the audio signal, the low-pass filter 13 sets the cutoff frequency to a predetermined value that is appropriately lower than the cutoff frequency 300 Hz of the low-pass filter 11. The predetermined value must be such that the turn-off signal can pass through the low-pass filter 13 together with the CDCSS signal.

  The CDCSS inspection unit 17 includes a CDCSS bit determination unit 18, a VI (Valid / Invalid) determination unit 19, and a CDCSS code determination unit 20. The processing contents of the CDCSS bit determination unit 18, the VI determination unit 19, and the CDCSS code determination unit 20 will be described later with reference to FIGS. 5, 6, and 7, respectively.

  FIG. 2 is a flowchart of processing contents in the CDCSS decoding processing apparatus 10. Steps S35, S36, S37, and S38 correspond to the processing of the low-pass filter 11, the thinning-out unit 12, the low-pass filter 13, and the DC tracking unit 14 in FIG. Each step of S41, S42, and S43 corresponds to the processing of the CDCSS bit determination unit 18, the VI determination unit 19, and the CDCSS code determination unit 20 of FIG. The specific processing contents of S41, S42, and S43 will be described later with reference to FIGS.

  FIG. 3 is a diagram for explaining the basic concept of the processing of the CDCSS inspection unit 17. In FIG. 3, the upper analog signal is an input signal of the CDCSS inspection unit 17 (hereinafter referred to as “CDCSS extraction detection signal component”), and the lower side is a bit determination signal for the detection signal component for CDCSS extraction. . In the bit determination of the detection signal component for CDCSS extraction in the conventional CDCSS inspection unit 151 (FIG. 15), “1”, “0” depending on whether the level of the detection signal component for CDCSS extraction is + side or − side from the reference 0. The CDCSS inspection unit 17 sets an invalid level range of −Fth to + Fth (where Fth is a positive predetermined value) for the level of the detection signal component for CDCSS extraction. When the level of the detection signal component for CDCSS extraction is in the invalid level range, “invalid” is determined.

  FIG. 4 shows the relationship between the detection signal component for CDCSS extraction formed by noise from the DTMF signal and the bit determination signal for the detection signal component for CDCSS extraction. The DTMF signal in FIG. 4 is the same as the DTMF in FIG. By introducing an invalid level range of −Fth to + Fth, a signal portion that does not belong to either “1” or “0” appears in the bit determination signal, and in this signal portion, the CDCSS data related to the determination result signal is Therefore, the CDCSS reference data (standby CDCSS data) does not coincide with the CDCSS reference data, so that it is possible to avoid a situation where the detection signal component for CDCSS extraction relating to the DTMF signal is erroneously determined as the CDCSS signal as shown in FIG.

  3 and FIG. 4 is “0” when the level of the detection signal component for CDCSS <−Fth, and the level of the detection signal component for CDCSS extraction ≦ + Fth. When the level is “invalid” and + Fth <detection signal component level for CDCSS extraction, the level is “1”. Although it is possible to make a CDCSS match determination by using such a bit determination signal of three logical values of “0”, “1”, and “invalid”, the CDCSS checking unit 17 performs later processing in FIG. As is apparent from the description of FIG. 9, although the “invalid” determination is used, the bit determination signal of three logical values in FIGS. 3 and 4 is not used.

  FIG. 5 is a detailed flowchart of the CDCSS bit determination processing routine (S41 in FIG. 2). The CDCSS bit determination processing routine corresponds to the processing content of the CDCSS bit determination unit 18. The content of the CDCSS bit determination processing routine is that the bit value of each bit period is determined as “0” if the level of the detection signal component for CDCSS extraction <0, and the level of the detection signal component for CDCSS extraction ≧ 0. If there is, it is determined as “1”. The CDCSS bit determination processing routine is started in synchronization with the bit period, for example, so that the bit determination is performed once in each bit period of the CDCSS signal.

  In S48, the level of the detection signal component for CDCSS extraction is compared with 0. If the level of the detection signal component for CDCSS extraction ≧ 0, the process proceeds to S49. If the level of the detection signal component for CDCSS extraction <0, the process proceeds to S50. In S49, the bit determination result is set to “1”, and in S50, the bit determination result is set to “0”. In S51, the current bit determination result is reflected. The specific contents of “reflect” include, for example, a 23-bit shift register that holds 23-bit bit determination data. Each time a determination is made, the shift register is set to 1 bit toward the MSB (MostSignificantBit), While shifting, the current determination result is set in the LSB (Least Significant Bit) of the shift register.

  FIG. 6 is a detailed flowchart of a VI (Valid / Invalid) determination processing routine (S42 in FIG. 2). The VI determination processing routine corresponds to the processing content of the VI determination unit 19. The contents of the V I determination processing routine are as follows: | the level of the detection signal component for CDCSS extraction | means the absolute value of the level of the detection signal component for CDCSS extraction. The level | of the detection signal component is compared with a predetermined threshold value, and if the absolute value is equal to or greater than the threshold value, it is determined as “0” (= “valid”), and the absolute value is the threshold value. If it is less than the value, it is determined as “1” (= “invalid”).

In S56, the level of | CDCSS extraction detection signal component | is detected. In S57, the level of | CDCSS extraction detection signal component | is compared with the threshold value.
The process proceeds to S58, and if the former is less than the latter, the process proceeds to S59. In S58, the bit determination in S49 and S50 of FIG. 5 is “0” (= “valid”), and in S59, it is “1” (= “invalid”).

  In S60, the determination results of S58 and S59 are reflected in the VI determination data. The specific contents of “reflect” include, for example, a 23-bit shift register holding 23-bit VI determination data, and each time a determination is made, the shift register is set to 1 bit toward the MSB (MostSignificantBit), The determination result is set in the LSB (Least Significant Bit) of the shift register while shifting.

  The threshold employed in S57 of the VI determination processing routine is, for example, Fth (FIG. 3). In the drawing, threshold values are used in S67 and S72 in addition to S57, but these threshold values can be set independently. In FIG. 3 described above, instead of −Fth and + Fth, −Fthl and + Fthu (Fthl ≠ Fthu. Fthl, Fthu> 0) can be used, respectively.

  FIG. 7 is a detailed flowchart of the CDCSS code check routine (S43 in FIG. 2). The CDCSS code check routine (including a CDCSS code check routine of FIG. 8 described later) corresponds to the processing content of the CDCSS code determination unit 20. The contents of the CDCSS code check routine are as follows: the corresponding bits of the 23-bit bit determination data reflected in S51 (FIG. 5) and the 23-bit V I determination data reflected in S 6 0 are compared with each other. The number of error bits in the bit is calculated, and if the number of error bits is less than a predetermined threshold, it is determined that the CDCSS code matches (there is a CDCSS signal associated with the receiver), and is equal to or greater than the predetermined threshold. If it is, it is determined that there is a CDCSS code mismatch (no CDCSS signal associated with the receiver).

  In S64, an exclusive OR (XOR) of corresponding bits of the 23-bit CDCSS determination data (generated in S51) and the 23-bit CDCSS reference data is calculated. The exclusive OR calculation result is held as 23-bit exclusive OR data. When the corresponding bits of the 23-bit CDCSS determination data and the 23-bit CDCSS reference data are compared with each other and the bit values match, the value of the corresponding bit of the 23-bit exclusive OR data is “0”. In the case of mismatch, the value of the corresponding bit of the 23-bit exclusive OR data is “1”.

  In S65, the logical sum (OR) of the corresponding bits of the 23-bit exclusive OR data and the 23-bit VI determination data is calculated. The logical sum calculation result is held as 23-bit error determination logical sum data. The value of each bit of the 23-bit error determination logical sum data is that the corresponding bit of the 23-bit exclusive OR data is “1” (= bit that does not match the CDCSS reference data in the CDCSS determination data) or 23 If the corresponding bit of the VI determination data of the bit is “1” (= “invalid” bit), it is “1”.

  In S66, the number of bits of which the bit value of the 23-bit error determination logical sum data is “1” is counted as the number of error bits. In S67, it is determined whether or not the number of error bits ≦ the predetermined threshold value. If the determination is positive, the process proceeds to S68, and if not, the process proceeds to S69. In S68, it is determined that the CDCSS code matches, and in S69, it is determined that the CDCSS code does not match.

  FIG. 8 is a detailed flowchart of another CDCSS code check routine. In the flowchart of FIG. 8, steps having the same processing contents as the steps of the flowchart of FIG. 7 are assigned the same step numbers as the steps of FIG. The difference between the flowchart of FIG. 8 and the flowchart of FIG. 7 is that S65 is deleted and, instead, S71 and S72 are added before S64.

  In S71, the number of bits that are “1” in the 23-bit VI determination data, that is, the number of invalid bits is counted. In S72, it is determined whether or not the counted number of invalid bits is less than a threshold value. If the result of this determination is positive, the process proceeds to S64, and if not, the process proceeds to S69.

  In the other CDCSS code check routine of FIG. 8, the detection signal component for extracting the CDCSS with many invalid bits is excluded from the processing targets of S64 and S65 depending on the determination of S72. Reduction is achieved.

  FIG. 9 is a flowchart of a routine for counting the number of invalid bits used in S71 and S72 (FIG. 8). FIG. 10 shows a shift register 80 for holding the 23-bit VI determination data used in the routine of FIG. In FIG. 8, the contents of the upper, middle and lower shift registers 80 are those before the processing of S81, after the processing of S81 and before the processing of S82, and after the processing of S82.

  In S81, the shift register 80 is shifted by 1 bit toward the MSB. Thereby, the MSB data of the shift register 80 before the shift is lost from the shift register 80 due to overflow. In S82, the result of the current VI determination is inserted into the LSB of the shifted shift register 80. In S83, the count number of the VI counter is updated. In this update, the logical value set in the LSB in S82 -the logical value overflowed from the MSB of the shift register 80 in S81 is added to the VI counter.

  In FIG. 10, the count number of the VI counter is 4 before S81, and “the logical value inserted into the LSB in S82” — “the logical value overflowed from the MSB of the shift register 80 in S81” is −1 (= 0-1), the count number of the VI counter is 3 after S84.

  FIG. 11 is a block diagram of the squelch control signal detection apparatus 100. The squelch control signal detection apparatus 100 includes an extraction unit 101, an invalid bit period detection unit 102, and a determination unit 103. A specific example of the squelch control signal detection device 100 is the CDCSS decoding processing device 10 (FIG. 1). The squelch control signal detection device 100 is installed in a wireless communication device, particularly a receiver portion of the wireless communication device.

  The extraction unit 101 extracts a squelch detection signal component from a squelch frequency band that is set to be distinguished from an audio frequency band as a frequency band of the squelch control signal. The invalid bit period detecting means 102 sets a level range of “invalid” between the logic “1” and logic “0” level ranges for the signal level of the squelch detection signal component, and detects the squelch detection signal. An invalid bit period in which the signal level of the component is in the “invalid” level range is detected. The determination unit 103 determines the presence or absence of a predetermined squelch control signal based on the detection of the invalid bit period.

  The squelch control signal is, for example, a squelch control signal related to CDCSS. The level ranges of the logic “1” and the logic “0” are the upper side and the lower side, respectively, with respect to the “invalid” level range in FIG. 3 described above, but may be reversed.

  The detection of the invalid bit period that is the basis of the determination by the determination unit 103 includes detection of the number of invalid bit periods or the ratio of invalid bit periods. Furthermore, the number of invalid bit periods is detected by detecting the number of invalid bit periods in a predetermined time or the number of invalid bit periods in a predetermined number of bits (for example, the number of bits set in the squelch control signal; 23 for a CDCSS signal). Detection of the number of. Detection of the ratio of invalid bit periods includes detection of the ratio of the number of invalid bit periods to a predetermined number of consecutive bit periods or the appearance probability of invalid bit periods in unit time. In S66 of FIG. 6, 23-bit VI determination data is generated, and the number of invalid bits in the VI determination data corresponds to the number of invalid bit periods for 23.

  Thus, even if a noise signal having a variation similar to that of the squelch control signal appears in the squelch frequency band, it is possible to avoid a situation where the noise signal is erroneously determined as the squelch control signal.

  The squelch control signal detection apparatus 100 can further include a bit string generation unit 107. The bit string generation means 107 sets two level ranges of logic “1” and logic “0” on the one side and the other side for the signal level of the detection signal component for squelch, and the detection signal component for squelch in each bit period A determination bit string is generated based on whether the signal level is in the logic “1” or “0” level range. In addition to detecting the invalid bit period, the determination unit 1 0 3 further determines the presence or absence of a predetermined squelch control signal based on the comparison between the determination bit string and the standby bit string.

  Specific examples of the bit string generation means 107 are the CDCSS bit determination unit 18 (FIG. 1) and the CDCSS bit determination processing routine of FIG.

  Preferably, the invalid bit period detection unit 102 generates an invalid identification bit string based on whether or not it is an invalid bit period, and the determination unit 103 includes an error bit identification unit 110 and an error bit type determination unit 111. . When each bit of the determination bit string is a value different from the value of the corresponding bit of the standby bit string, or when the corresponding bit of the invalid identification bit string is an invalid bit, the error bit identifying unit 110 sets the bit as an error bit. Certify. The error bit type determination unit 111 determines that there is a predetermined squelch control signal when the ratio of error bits is less than the first predetermined value.

  The processing content of the invalid bit period detection means 102 corresponds to S41 (FIG. 2), the processing content of the error bit recognition means 110 corresponds to S64 to S66 (FIG. 7), and the processing content of the error bit type determination means 111 is , S67, S68 (FIG. 7).

  The determination unit 103 can include an invalid bit type determination unit 112. The invalid bit type determination unit 112 counts the number of invalid bits in the invalid identification bit string, and determines that there is no predetermined squelch control signal when the count number is equal to or greater than a second predetermined value. The error bit recognition unit 110 and the error bit type determination unit 111 perform these processes only when the count number in the invalid bit type determination unit 112 is less than the second predetermined value.

  The processing contents of the invalid bit type determination means 112 correspond to S71 and S72 (FIG. 8). The error bit recognition unit 110 and the error bit type determination unit 111 perform processing when the invalid bit type determination unit 112 cannot determine that the predetermined squelch control signal is absent, so the load on the determination unit 103 is reduced. .

  Preferably, the invalid bit type determination unit 112 includes a shift register 113, a counter 114, a shift control unit 115, and a counter control unit 116. The shift register 113 holds an invalid identification bit string. The counter 114 uses the number of bit values related to invalid bits in the shift register as a count value.

  The shift control means 115 detects, for each bit period, whether the amplitude level of the detection signal component for squelch in the bit period is in an invalid or valid level range, and sets each bit value of the shift register in the MSB direction. And a bit value corresponding to the detected invalid or valid is set in the LSB.

  Each time the shift control unit 115 shifts the value of each bit of the shift register 113, the counter control unit 116 sets the counter 114 based on the bit value overflowing from the MSB of the shift register 113 and the bit value set in the LSB. Increment or decrement.

  The processing content of the shift control means 115 corresponds to S81 and S82 (FIG. 9). The processing contents of the counter control means 116 correspond to S83 and S84 (FIG. 9). Since the count value of the counter 114 is incremented or decremented by the difference for each bit period, the count processing is more efficient than counting the number of “invalid” of the shift register 113 from the beginning for each count value request. It becomes the target.

FIG. 12 is a block diagram of another squelch control signal detection device 125. The squelch control signal detection device 125 includes an extraction unit 126, an identification unit 1 2 7, and a determination unit 1 2 8.
The squelch control signal detection device 1 2 5 extracts a squelch detection signal component from a squelch frequency band that is set to be distinguished from an audio frequency band as a frequency band of the squelch control signal.

  The discriminating means 127 sets a level range of logic “1” and logic “0” for the signal level of the detection signal component for squelch and an invalid level range between them, and detects the detection signal component for squelch in each bit period. The signal level is detected in which level range, and each bit period is identified as “1”, “0”, and “invalid” bit periods.

  The determination unit 128 checks whether or not the identified logical value matches the logical value of the corresponding bit in the standby bit string for the bit periods identified as “1” and “0”, and detects the matching bit periods. The presence or absence of a squelch control signal is determined based on the above.

  Similar to the squelch control signal detection device 100, the squelch control signal detection device 125 is typically installed in a wireless communication device, particularly a receiver portion of the wireless communication device. The squelch control signal is, for example, a squelch control signal related to CDCSS. The logical “1” and logical “invalid” level ranges are on the upper and lower sides of the “invalid” level range in FIG. 3, respectively.

  The “number of matching bit periods”, which is the basis of the determination in the determination unit 128, is, for example, a predetermined number (for example, the number of bits set in the squelch control signal, 23 for the CDCSS signal). Among the bit periods, “the number of matching bit periods”.

  FIG. 13 is a flowchart of the squelch control signal detection method 133. In S134, the detection signal component for squelch is extracted from the squelch frequency band set to be distinguished from the audio frequency band as the frequency band of the squelch control signal.

  In S135, with respect to the signal level of the detection signal component for squelch, a level range of “invalid” between them is set for the level range of logic “1” and logic “0”, and the signal level of the detection signal component for squelch is An invalid bit period in the “invalid” level range is detected. In S136, the presence / absence of a predetermined squelch control signal is determined based on the detection of the invalid bit period.

  Also in the case of the squelch control signal detection method 133 and the next squelch control signal detection method 140 (FIG. 14), as in the case of the squelch control signal detection devices 100 and 125, the squelch control signal is, for example, a squelch control signal related to CDCSS. It is. The level ranges of the logic “1” and the logic “0” are the upper side and the lower side, respectively, with respect to the “invalid” level range in FIG. 3 described above, but may be reversed.

  Specific processing contents of the extraction unit 101, the invalid bit period detection unit 102, and the determination unit 103 of the squelch control signal detection apparatus 100 can be applied as specific procedure contents of S134, S135, and S136, respectively. In the squelch control signal detection method 133, a step corresponding to the processing content of the bit string generation means 107 can be added.

  FIG. 14 is a flowchart of the squelch control signal detection method 140. In S141, the detection signal component for squelch is extracted from the squelch frequency band set to be distinguished from the audio frequency band as the frequency band of the squelch control signal.

  In S142, a level range of logic “1” and logic “0” and an invalid level range between them is set for the signal level of the detection signal component for squelch, and the signal of the detection signal component for squelch in each bit period is set. By detecting which level range the level is in, each bit period is identified as a bit period of “1”, “0”, “invalid”. In S143, for the bit periods identified as “1” and “0”, it is checked whether or not the identified logical value matches the logical value of the corresponding bit in the standby bit string, and based on the detection of the matching bit period. The presence or absence of a squelch control signal is determined.

  Specific contents of the extraction means 126, identification means 127, and determination means 128 of the squelch control signal detection device 125 can be applied as specific procedure contents of S141, S142, and S143, respectively.

  Although the present invention has been described with respect to the best mode, the present invention is not limited to this, and each constituent element in the best mode can be modified and embodied without departing from the spirit of the invention. In addition, a plurality of constituent elements disclosed in the best mode are conveniently combined and added, or some constituent elements are deleted to form various inventions without departing from the gist of the invention. can do. Furthermore, various inventions can be formed by selecting predetermined components among a plurality of disclosed embodiments and combining them.

DESCRIPTION OF SYMBOLS 100: Squelch control signal detection apparatus, 101: Extraction means, 102: Invalid bit period detection means, 103: Determination means, 107: Bit string generation means, 110: Error bit recognition means, 111: Error bit type determination means, 112: Invalid Bit type determination means, 113: shift register, 114: counter, 115: shift control means, 116: counter control means, 125: squelch control signal detection device, 126: extraction means, 127: identification means, 128: determination means, 133 : Squelch control signal detection method, 140: squelch control signal detection method.

Claims (6)

A signal detection device for determining whether or not a predetermined standby code is included in a detection code as a sequence of logical values generated from a detection signal,
Detection code generation means for generating the detection code by comparing at least a part of the detection signal with a threshold value for bit determination every predetermined period;
For each of the predetermined time period, or invalid is valid the detector sign-generated in the predetermined time period by comparing the invalid determining threshold value which defines a predetermined range including said bit determining threshold value Determining means for determining whether or not
It said detecting codes versus the waiting code for each logical value, the case where the waiting logical value of the code and the logical value of the generated said detection code in code generating means is different, or the logic of the detection mark No. When it is determined that the predetermined period in which the value is detected is invalid in the invalidity determination unit, error bit determination unit that uses the logical value as an error bit, and the detection code in the period corresponding to the standby code A signal detection means for determining that the standby code is included in the detection signal when the ratio of the error bits determined by the error bit determination means is less than a predetermined value;
A signal detection device. The standby code is a bit string consisting of logic “0” or logic “1”,
The detection code generation means compares at least a part of the detection signal with the threshold value for bit determination for each predetermined period, and generates a logical value consisting of logical “0” or logical “1”. Generate detection codes as a sequence,
It said determination means, at least some of the components of the detection signal for each said predetermined time period, or is invalid the predetermined period is valid by comparing the previous kina efficiency determining threshold value And generating an invalid bit string that is logical "0" if the predetermined period is valid, and logical "1" if the predetermined period is invalid,
The error bit determination means generates an exclusive OR data by calculating an exclusive OR of corresponding bits of the standby code and the detection code, and generates the exclusive OR data and the invalid bit string. Calculate the logical sum,
The signal detection means compares the number of logic “1” with a predetermined threshold value, so that the ratio of the error bits determined by the error bit determination means in the detection code in the period corresponding to the standby code is The signal detection apparatus according to claim 1, wherein it is determined whether or not the value is less than a predetermined value. Signal detection means for determining that the standby code is not included when the number of logic "1" in the invalid bit string generated by the determination means in a period corresponding to the standby code is greater than or equal to a predetermined value; The control signal detection device according to claim 2. When the invalid bit is generated, the signal detection means uses only the oldest invalid bit of the predetermined period and the latest invalid bit of the predetermined period in the period corresponding to the standby code, The signal detection device according to claim 3, wherein it is determined whether or not the invalid bit is a predetermined value or more. A radio device comprising the signal detection device according to claim 1. A signal detection method for determining whether or not a predetermined standby code is included in a detection code as a sequence of logical values generated from a detection signal,
A detection code generation step of generating the detection code by comparing at least a part of the detected signal with a threshold value for bit determination every predetermined period;
For each of the predetermined time period, or invalid is valid the detector sign-generated in the predetermined time period by comparing the invalid determining threshold value which defines a predetermined range including said bit determining threshold value A determination step for determining whether or not
It said detecting codes versus the waiting code for each logical value, the case where the waiting logical value of the code and the logical value of the detected code generated at code generating step is different, or the logic of the detection mark No. When the predetermined period during which the value is detected is determined to be invalid in the invalidity determination means, an error bit determination step in which the logical value is an error bit, and in the detection code in a period corresponding to the standby code A signal detection step of determining that the standby code is included in the detection signal when the ratio of the error bits determined by the error bit determination step is less than a predetermined value;
A signal detection method comprising:

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