JP5121207B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

    The present invention relates to a semiconductor device having a silicide layer and a manufacturing method thereof.

    Along with the shrinking of integrated circuits, semiconductor devices constituting integrated circuits are required to have low resistance of contact with metal wiring and low resistance of impurity regions. For this reason, a technique for reducing contact resistance and the resistance of an impurity region by forming a silicide layer in a semiconductor film has been adopted in the semiconductor field (for example, Patent Document 1). When the resistance of the semiconductor film is reduced, the on-state current of the semiconductor device is improved and a semiconductor device with high characteristics can be manufactured.

On the other hand, the thicker the silicide layer of the semiconductor, the lower the sheet resistance, so that the on-current is expected to increase. However, as described in Non-Patent Document 1, it has been reported that when the silicide layer is actually formed thick, the resistance increases and the on-current decreases.
JP 2004-221115 A OPTIMIZATION OF SERIES RESISTANCE IN SUB-0.2 μm SOI MOSFETs: Lisa T. Su et al. , IEDM93, pp. 723-726, 1993

    A first object of the present invention is to obtain a semiconductor device having a high on-state current in a semiconductor device having a silicide layer.

    A second object of the present invention is to obtain a semiconductor device with low sheet resistance and high on-current.

    In order to increase the on-current, there is a method of increasing the activation rate of the impurity region by providing a silicide layer and increasing the temperature of heat treatment for activating the impurity region. Alternatively, there is a method of improving the crystallinity of the semiconductor film by annealing the semiconductor film by heating or laser irradiation.

    However, these methods have a problem that the manufacturing cost increases because one heat treatment step is added and an apparatus for heat treatment is additionally required. In addition, when a substrate having low heat resistance such as a glass substrate is used as the substrate, the substrate may shrink due to high-temperature heat treatment. Therefore, the substrate to be used is limited to a substrate having high heat resistance, and there is a problem that the degree of freedom of the substrate is lost.

    Therefore, a third object of the present invention is to obtain a semiconductor device having a high on-current without increasing the number of steps. Another object of the present invention is to increase the on-state current without limiting the substrate.

    One of the features of the present invention is that it includes a silicon film having a channel formation region, an impurity region, and a silicide layer, a gate insulating film, a gate electrode, and a wiring electrically connected to the impurity region through the silicide layer. The silicide layer cross section is a semiconductor device having a first region where the thickness of the silicide layer is increased from an end point on the channel formation region side and a second region where the film thickness is constant compared to the first region. . Further, the first region and the second region are separated by a straight line perpendicular to the horizontal line, and when the first point is a point where the straight line intersects the interface between the silicide layer and the impurity region, the first point and the silicide region The straight line passing through the layer end point forms an angle θ (0 ° <θ <45 °) with respect to the horizontal line, and the film thickness of the second region with respect to the film thickness of the silicon film is 0.6 or more.

    One of the features of the present invention is that it includes a silicon film having a channel formation region, an impurity region, and a silicide layer, a gate insulating film, a gate electrode, and a wiring electrically connected to the impurity region through the silicide layer. The silicide layer cross section has a first region where the film thickness increases from the end point on the channel formation region side, and a second region where the film thickness is equal to the film thickness of the silicon film. The region is divided by a straight line perpendicular to the horizontal line, and when the first point is a point where the straight line intersects the bottom surface of the silicon film, the straight line passing through the first point and the end point is at an angle θ (0 ° with respect to the horizontal line). <Θ <45 °) is a semiconductor device.

    Another feature of the present invention is that the silicon film included in the semiconductor device is replaced with a silicon substrate.

    In addition, one of the features of the present invention is to control the film formation conditions so that the metal film for forming the silicide layer is intentionally non-uniform in thickness. As a result, the first region where the thickness of the silicide layer is increased can be increased, or the length of the first region in the channel length direction can be increased.

    This will be described with reference to FIG. FIG. 1A is a cross-sectional view of a transistor, and a portion surrounded by a broken line in FIG. 1A is enlarged to be FIG. 1B. The silicon film or silicon substrate has a region 11, an impurity region 12, and a silicide layer 13. The region 11 only needs to include at least a channel formation region, and may include a low concentration impurity region or a high concentration impurity region in contact with the impurity region 12. A wiring 16 provided by etching an interlayer insulating film is connected to the silicide layer 13. As shown in FIG. 1B, the silicide layer 13 includes a first region 13a and a second region 13b. The film thickness of the first region 13a increases from the end point A on the channel formation region side. The second region 13b has a constant film thickness compared to the first region 13a.

    A gate insulating film 14 is provided on the silicon film or the silicon substrate, and a gate electrode 15 is provided thereon. The shape and width of the gate insulating film 14 are not limited to those shown in FIG. 1 and may be any shape and width. For example, the gate insulating film 14 may have a tapered shape and an inclined side surface. In addition, the gate electrode 15 is not limited to that shown in FIG. That is, the present invention does not depend on the gate electrode 15 and the gate insulating film 14.

    The first region 13a and the second region 13b are separated by a line passing through the point B and perpendicular to the horizontal line. Further, the point B is on the interface between the silicide layer 13 and the impurity region 12. A straight line passing through the point B and the end point A forms an angle θ with the horizontal line. Θ is 0 ° <θ <45 °, d1 / d2 ≧ 0.6, where d1 is the thickness of the silicon film d2, and d1 is the thickness of the second region 13b of the silicide layer. When d1 / d2 = 1.0, the point B is located on the bottom surface of the silicon film or silicon substrate.

    According to the present invention, a semiconductor device with high on-state current can be obtained by controlling the shape of the silicide layer. In addition, a semiconductor device with high on-current can be obtained while reducing the sheet resistance. In addition, the on-state current can be increased without increasing the number of manufacturing steps of the semiconductor device. Thereby, a high on-current can be obtained while maintaining the manufacturing cost of the conventional semiconductor device. In addition, since high temperature heat treatment is not required to obtain a high on-state current, a substrate having low heat resistance can be used, and the substrate can be used without limitation of heat resistance.

    Embodiments of the present invention will be described below. However, the present invention can be implemented in many different modes within a practicable range. It will be readily appreciated by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

(Embodiment 1)
In the present invention, in a transistor having a silicide layer, the influence of the film thickness and shape of the silicide on the on-current is analyzed by a computer.

    FIGS. 2A and 2B are schematic views of a part of a silicon film which is a semiconductor film of a top gate type transistor, and the structure of an element assumed in this analysis. 2A and 2B schematically show a silicon film portion surrounded by a broken line in FIG. The element used in the analysis includes any of a thin film transistor (TFT), a transistor formed directly on a silicon substrate, a transistor formed on an SOI (silicon on insulator) substrate such as a SIMOX (separation by imprinted oxygen) substrate.

    2A shows an element structure in the case where there is no low-concentration impurity region between the silicide layer 33 and the region 31, and FIG. 2B shows a low-concentration impurity region between the silicide layer 33 and the region 31. It is an element structure when there is. Both have a region 31, an impurity region 32, and a silicide layer 33. The region 31 is a region where a gate electrode is disposed on the upper portion through a gate insulating film, and includes at least a channel formation region. In addition to the channel formation region, the region 31 may have an impurity region in contact with the impurity region 32 in FIG. 2A, or the low concentration impurity in contact with the low concentration impurity region 32b in FIG. It may have a region. It is assumed that carriers flow from the silicide layer 33 and the impurity region 32 to the electrode 34. Therefore, the impurity region 32 or the high concentration impurity region 32a functions as a source region.

    2A and 2B, an electrode 34 is assumed above the region 31 as an inversion layer. Since the region 31 is a portion having an upper gate electrode, carriers flow on the surface of the silicon film under the gate electrode when the transistor is on. The path of the carrier was assumed as the electrode 34. The thickness of the electrode 34 is assumed to be 10 nm because the carrier flow path in the transistor, the so-called inversion layer generally has a thickness of about 10 nm or less. It is assumed that 5V is applied to the electrode 34 for an N-type transistor and -5V is applied for a P-type transistor.

    The length of the upper surface of the silicide layer 33 in the channel length direction is 1.0 μm, and the length of the impurity region between the silicide layer 33 and the region 31 is 0.1 μm. The film thickness of the silicon film includes the film thickness of the silicide layer.

    As shown in the table of FIG. 2C, several values were adopted for the thickness of the silicon film, the ratio of the thickness of the silicide layer to the silicon film, the carrier concentration, and the contact resistance Rc between the silicon film and the silicide layer. . The conductivity type was assumed to be N-type and P-type, respectively.

In the case of FIG. 2A where there is no low-concentration impurity region between the silicide layer 33 and the region 31, the carrier concentration of the impurity region 32 is 1 × 10 ²⁰ cm ⁻³ . In the case of FIG. 2B where the low concentration impurity region 32b is present between the silicide layer 33 and the region 31, the carrier concentration of the low concentration impurity region 32b is 1 × 10 ¹⁷ cm ⁻³ or 1 × 10 ¹⁸ cm ^−3. The carrier concentration of the high concentration impurity region 32a is 1 × 10 ²⁰ cm ⁻³ . Further, the length of the low concentration impurity region 32b in the channel length direction was set to 0.1 μm.

    Under all conditions, the relationship between the angle θ at the end of the silicide layer 33 on the channel formation region side (hereinafter referred to as angle θ) and the on-current was analyzed by calculation. This analysis was performed using Dessis made by Synopsys, and the on-currents were calculated at angles θ = 15 °, 30 °, 45 °, 60 °, and 75 °.

    The contact resistance varies depending on the type of silicide. Among the contact resistance values of silicide and silicon used in the semiconductor field, there are a total of three values: the minimum and maximum values that can be assumed, and the value between them. Assumed.

    A TEM photograph of the cross section of the silicide layer is shown in FIG. 3A is a cross-sectional photograph of a top-gate transistor, and FIG. 3B is an enlarged photograph of a region surrounded by a broken line in FIG. The structure of the transistor is similar to that of FIG. 1, and it can be seen that a black silicide layer is formed on the surface of the impurity region in the top gate type. As shown in the photograph of FIG. 3, the actual silicide layer cross section gradually increases in thickness from the end point on the channel formation region side, and has a shape with curvature. However, in the calculation, for convenience, it is assumed that the cross section of the silicide layer has no curvature, and the silicide layer has a side surface that forms an angle θ with the horizontal line.

    The analysis results by the computer are shown in FIGS. 4 to 6 show the results of the N-type transistor, and FIGS. 7 to 9 show the results of the P-type transistor. The horizontal axis is the angle θ at the end of the silicide layer 33 on the channel formation region side, and the vertical axis is the current flowing from the silicide layer 33 and the impurity region 32 to the electrode 34, the so-called on-current value.

    4A, FIG. 5A, FIG. 6A, FIG. 7A, FIG. 8A, and FIG. 9A are silicon film thicknesses of 150 nm, FIG. B), FIG. 6B, FIG. 7B, FIG. 8B, and FIG. 9B are silicon film thicknesses of 100 nm, FIG. 4C, FIG. 5C, FIG. 7C, 8C, and 9C show the evaluation results when the silicon film thickness is 50 nm. The results for each silicon film thickness were plotted according to the film thickness ratio of the silicide layer to the silicon film (hereinafter referred to as the film thickness ratio).

    4 and 7 show the results obtained when there is no low-concentration impurity region between the region 31 and the silicide layer 33 in the element structure shown in FIG. In FIGS. 4 and 7, the on-current when the film thickness ratio increases while the silicon film thickness is constant is seen. Then, when the film thickness ratio is 0.4 in FIGS. 4A-1, (B-1), and (C-1), the on-current does not depend much on the angle θ. It can be seen that the dependence of the on-current on the angle θ increases as the value increases.

4A having a silicon film thickness of 150 nm, each film of FIGS. 4A-1 to 4A-4 when the contact resistance Rc = 5 × 10 ⁻⁸ Ω · cm ² and the angle θ = 15 °. When comparing the on-current at the thickness ratio, the values are almost the same. However, as the film thickness ratio increases, the on-current decreases depending on the angle θ. This tendency is common to all the graphs in FIGS.

5, FIG. 6, FIG. 8 and FIG. 9 are the results shown in FIG. 2B, in which the carrier concentration of the low concentration impurity region 32b is 1 × 10 ¹⁷ cm ⁻³ or 1 × 10 ¹⁸ cm ^−3. . 5, 6, 8, and 9, as in FIGS. 4 and 7, the on-current tends to depend on the angle θ as the film thickness ratio is increased. On-state current at each film thickness ratio at the same silicon film thickness and angle θ = 15 ° is almost the same. On the other hand, as the film thickness ratio is increased, the on current depends on the increase in angle θ. There is a tendency for the current to decrease.

4 to 9, when the contact resistance Rc = 5 × 10 ⁻⁷ Ω · cm ^{2 with} the same silicon film thickness, the ON current value at the angle θ = 15 ° also increases the film thickness ratio. There is also a tendency to go down as you do.

    Therefore, when the film thickness ratio of the silicide layer to the silicon film is 0.4, the correlation between the angle θ and the on-current does not appear strongly, but when the film thickness ratio is 0.6 or more, the on-current decreases when the angle θ is increased. It was. This is in common with the report of Non-Patent Document 1 introduced in Background Art. When the thickness of the silicide layer is increased, the sheet resistance is lowered, so that the on-current is predicted to increase. However, actually, the on-current is reduced.

10 to 15 show the same evaluation results as those of FIGS. 4 to 9, but the results of the film thickness ratio of only 0.6 or more show that the contact resistance Rc is 5 × 10 ⁻⁷ Ω · cm ² and 1 × 10. It is plotted according to the silicon film thickness at ⁻⁷ Ω · cm ² and 5 × 10 ⁻⁸ Ω · cm ² . 10 to 12 show the results of the N-type transistor, and FIGS. 13 to 15 show the results of the P-type transistor. 10 and 13 show a structure in which there is no low-concentration impurity region between the region 31 and the silicide layer 33 in FIG. FIG. 11 and FIG. 14 show the result of the carrier concentration of 1 × 10 ¹⁷ cm ⁻³ in the low concentration impurity region 32 b in the structure having the low concentration impurity region 32 b between the region 31 and the silicide layer 33 in FIG. . FIG. 12 and FIG. 15 show the result of the carrier concentration of 1 × 10 ¹⁸ cm ⁻³ in the low concentration impurity region 32b in the structure having the low concentration impurity region 32b of FIG.

    In FIG. 10, it can be confirmed that the on-current tends to decrease as the angle θ increases. The rate at which the on-current decreases is greatly changed at the angle θ = 45 °. Comparing the rate of decrease in on-current with an angle θ ≦ 45 ° and the rate of decrease in on-current with an angle θ ≧ 45 °, the rate of decrease in on-current with an angle θ ≦ 45 ° is greater than the rate of on-current with an angle θ ≧ 45 °. Greater than the rate of down. At film thickness ratios of 0.6 and 0.8, the on-current is almost constant at an angle θ ≧ 45 °.

    In FIG. 11, under some conditions, the ON current decreases at the same rate as the angle θ increases as the angle θ increases from 15 ° to 75 °. On the other hand, in the remaining conditions, the rate of decrease of the on-current greatly changes at the angle θ = 45 °. The rate of decrease of the on-current with an angle θ ≦ 45 ° is larger than the rate of decrease of the on-current with an angle θ ≧ 45 °. When the film thickness ratio is 0.6 in FIGS. 11A-3, B-3, and C-3, the on-current is substantially constant at an angle θ ≧ 45 °.

    Also in FIG. 12, as in FIG. 11, under some conditions, the ON current decreases at the same rate as the angle θ increases as the angle θ increases from 15 ° to 75 °. On the other hand, in the remaining conditions, the rate of decrease of the on-current greatly changes at the angle θ = 45 °. The rate of decrease of the on-current with an angle θ ≦ 45 ° is larger than the rate of decrease of the on-current with an angle θ ≧ 45 °.

    In FIG. 13, the ratio of the on-current drop greatly changes at the angle θ = 45 ° under any condition. The rate of decrease of the on-current with an angle θ ≦ 45 ° is larger than the rate of decrease of the on-current with an angle θ ≧ 45 °. At film thickness ratios of 0.6 and 0.8, the on-current at an angle θ ≧ 45 ° is substantially constant.

    In FIG. 14, under some conditions, the on-current decreases at the same rate as the angle θ increases as the angle θ increases from 15 ° to 75 °. On the other hand, in the remaining conditions, the rate of decrease of the on-current greatly changes at the angle θ = 45 °. The rate of decrease of the on-current with an angle θ ≦ 45 ° is larger than the rate of decrease of the on-current with an angle θ ≧ 45 °. In the film thickness ratios 0.6 and 0.8 in FIG. 14A-3, the on-current is substantially constant at an angle θ ≧ 45 °.

    Also in FIG. 15, as in FIG. 14, under some conditions, the ON current decreases at the same rate as the angle θ increases as the angle θ increases from 15 ° to 75 °. On the other hand, in the remaining conditions, the rate of decrease of the on-current greatly changes at the angle θ = 45 °. The rate of decrease of the on-current with an angle θ ≦ 45 ° is larger than the rate of decrease of the on-current with an angle θ ≧ 45 °. In the film thickness ratios 0.6 and 0.8 in FIG. 15A-3, the on-state current is substantially constant at an angle θ ≧ 45 °.

    As described above, from the results of FIGS. 10 to 15 having a film thickness ratio of 0.6 or more, at least within θ = 45 ° (excluding θ = 0), the on-current is increased as the angle θ is increased, common to all conditions. Turned out to go down.

    Therefore, at a film thickness ratio of 0.6 or more where the on-current decreases depending on the angle θ, if the angle θ at the end of the silicide layer is 0 ° <θ <45 °, the transistor with an angle θ ≧ 45 ° can be obtained. It was found that a transistor with a high on-current was obtained.

    As shown in the photograph of FIG. 3, the actual silicide layer cross section of the transistor has a shape in which the film thickness increases from the end of the silicide layer on the channel formation region side and has a curvature. Therefore, the angle θ at the end of the silicide layer is not uniform. That is, the interface between the silicide layer and the impurity region is more swelled toward the channel formation region than the interface between the silicide layer and the impurity region indicated by a line that forms an angle θ from the horizontal line assumed in the calculation.

    Therefore, when the angle θ found by the above analysis is applied to an actual transistor, the following is considered. As shown in FIG. 1, the first region 13a and the second region 13b having a constant film thickness compared to the first region 13a are divided by a certain straight line. A point where the straight line intersects the interface between the silicide layer and the impurity region is defined as a point B. At this time, the straight line passing through the end point A and the point B on the channel forming region side of the silicide layer 13 only needs to be a straight line that forms an angle θ from the horizontal line.

    In FIG. 1B, when the angle θ is decreased while the thickness d1 of the silicide layer is kept constant, the point B moves away from the region 11 along the interface between the silicide layer 13 and the impurity region 12. Moving. That is, the length of the first region 13a in the channel length direction becomes larger. Therefore, setting the angle θ to 0 ° <θ <45 ° means that the length of the first region 13a of the silicide layer 13 in the channel length direction is longer than the angle θ ≧ 45 °. It means to increase the area. By doing so, a semiconductor device with a high on-state current can be obtained.

    As shown in FIG. 1B, a point where a horizontal line passing through the point B intersects with a line perpendicular to the horizontal line and passing through the point A is defined as a point C. At that time, when the area of the first region 13a protruding from the straight line passing through the points A and B toward the impurity region is ½ or less of the area of the triangle formed by the points A, B, and C However, this is particularly effective for obtaining a semiconductor device with a high on-current. The same applies when the impurity region 12 protrudes toward the first region 13a from the straight line passing through the points A and B, and the first region 13a is recessed from the straight line passing through the points A and B. You may think. That is, when the area where the impurity region protrudes from the line passing through the points A and B is ½ or less of the area of the triangle formed by the points A, B, and C, a semiconductor with a particularly high on-current It is effective to obtain the device.

    Although depending on the formation method of the transistor, the film thickness of the semiconductor film may not be constant in an actual transistor. At that time, the film thickness ratio may be calculated using the silicon film thickness of the portion where the silicide layer is formed.

    As described above, when the thickness ratio of the silicide layer to the silicon film is 0.6 or more, a semiconductor device with high on-state current can be obtained by setting the angle θ to less than 45 ° (excluding 0 °). Therefore, a high on-state current can be obtained only by controlling the angle θ of the end portion of the silicide layer on the channel formation region side without providing a heat treatment step. In addition, in order to obtain a high on-state current, it is not necessary to increase the number of steps for manufacturing a semiconductor device and to prepare a heat treatment apparatus, so that a transistor with high characteristics can be manufactured while maintaining manufacturing costs. Furthermore, a transistor with a high on-state current can be obtained while reducing the sheet resistance.

    In the analysis by the computer, as shown in FIG. 2, the on-current flowing from the impurity region 32 functioning as the source region or the high concentration impurity region 32a to the electrode 34 was calculated. However, even if the impurity region 32 or the high-concentration impurity region 32a is used as the drain region, the same is true except that the carrier flow direction changes from the electrode 34 to the impurity region 32 and the silicide layer 33. Therefore, the impurity region 32 may function as a source region or a drain region. Further, in the analysis by the computer, the shape of only the silicide layer on one side of the channel formation region was examined. However, in the silicide layer on both sides of the channel formation region, if the angle θ is 0 ° <θ <45 °, the on-current is further increased. Needless to say, the price increases.

(Embodiment 2)
A method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS.

    First, the insulating film 102 is formed with a thickness of 100 to 300 nm on the substrate 101. As the substrate 101, a glass substrate, a quartz substrate, a plastic substrate, an insulating substrate such as a ceramic substrate, a metal substrate, or the like can be used.

    The insulating film 102 includes silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide containing nitrogen (SiOxNy) (x> y) (also referred to as silicon oxynitride), silicon nitride containing silicon (SiNxOy) (x> y) ) (Also referred to as silicon nitride oxide) or a single-layer structure of an insulating film containing oxygen or nitrogen, or a stacked structure thereof. Although the insulating film 102 is not always necessary, the insulating film 102 is preferably formed when there is a concern about contamination from the substrate.

    The insulating film 102 in contact with the semiconductor film may be a silicon nitride film or a silicon nitride oxide film with a thickness of 0.01 to 10 μm, preferably 100 to 300 nm. In a later crystallization process, when a method of adding a metal element to a semiconductor film to crystallize is used, it is necessary to getter the metal element. At this time, if the insulating film is a silicon oxide film, the metal element in the silicon film reacts with the oxygen in the silicon oxide film at the interface between the silicon oxide film and the silicon film of the semiconductor film to become a metal oxide. In some cases, the metal element is difficult to getter. Therefore, the insulating film 102 in contact with the semiconductor film is preferably a silicon nitride film or a silicon nitride oxide film.

    Subsequently, an island-shaped semiconductor film 103 with a thickness of 10 to 150 nm is formed over the insulating film 102. The material of the semiconductor film is a silicon film. The island-shaped semiconductor film 103 is formed by forming a semiconductor film over the entire surface of the insulating film 102 by sputtering, LPCVD, plasma CVD, or the like, and then processing the semiconductor film using a mask formed by photolithography or the like. To form. When the island-shaped semiconductor film 103 is formed using a crystalline semiconductor film, a method of forming a crystalline semiconductor film directly over the insulating film 102 and a heat treatment after an amorphous semiconductor film is formed over the insulating film 102 There is a method of forming a crystalline semiconductor film by crystallization. In the latter method, the heat treatment at the time of crystallization is performed by using a heating furnace, laser irradiation, irradiation of light emitted from a lamp instead of laser light (hereinafter referred to as lamp annealing), or a combination thereof. Done.

    Alternatively, the crystalline semiconductor film may be formed by a thermal crystallization method in which the heat treatment is performed after nickel or the like is added to the amorphous semiconductor film. Note that in the case where a crystalline semiconductor film is obtained by performing crystallization using a thermal crystallization method using nickel, it is preferable to perform gettering treatment for removing nickel after crystallization.

In the case of manufacturing a crystalline semiconductor film by crystallization by laser irradiation, a continuous-wave (CW) laser beam or a pulsed laser beam (pulse laser beam) can be used. The laser beam that can be used here is a gas laser such as an Ar laser, a Kr laser, or an excimer laser, single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline ( (Ceramics) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta added as dopants A laser oscillated from one or more of laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor laser, or gold vapor laser as a medium can be used. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonic laser beams of these fundamental waves, a crystal having a large grain size can be obtained. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. This laser can be emitted by CW or pulsed oscillation. When injected at a CW, the power density of the laser is about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

Note that single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ , dopants Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta, a laser using a medium added with one or more, an Ar ion laser, or a Ti: sapphire laser should oscillate continuously It is also possible to perform pulse oscillation at an oscillation frequency of 10 MHz or more by performing Q switch operation, mode synchronization, or the like. When the laser beam is oscillated at an oscillation frequency of 10 MHz or more, the semiconductor film is irradiated with the next pulse during the period from when the semiconductor film is melted by the laser to solidification. Therefore, unlike the case of using a pulse laser having a low oscillation frequency, the solid-liquid interface can be continuously moved in the semiconductor film, so that crystal grains continuously grown in the scanning direction can be obtained.

    When ceramic (polycrystal) is used as the medium, it is possible to form the medium in a free shape in a short time and at low cost. When a single crystal is used, a cylindrical medium having a diameter of several millimeters and a length of several tens of millimeters is usually used. However, when ceramic is used, a larger one can be made.

    Since the concentration of dopants such as Nd and Yb in the medium that directly contributes to light emission cannot be changed greatly regardless of whether it is a single crystal or a polycrystal, there is a certain limit to improving the laser output by increasing the concentration. However, in the case of ceramic, since the size of the medium can be remarkably increased compared with the single crystal, the output can be greatly improved.

    Further, in the case of ceramic, a medium having a parallelepiped shape or a rectangular parallelepiped shape can be easily formed. When a medium having such a shape is used to cause oscillation light to travel in a zigzag manner inside the medium, the oscillation optical path can be made longer. For this reason, the amplitude becomes large, and it becomes possible to oscillate with a large output. Further, since the laser beam emitted from the medium having such a shape has a quadrangular cross-sectional shape at the time of emission, it is advantageous for shaping into a linear beam as compared with a round beam. By shaping the emitted laser beam using an optical system, it is possible to easily obtain a linear beam having a short side length of 1 mm or less and a long side length of several mm to several m. Become. In addition, by irradiating the medium with the excitation light uniformly, the linear beam has a uniform energy distribution in the long side direction.

    By irradiating the semiconductor film with this linear beam, the entire surface of the semiconductor film can be annealed more uniformly. When uniform annealing is required up to both ends of the linear beam, it is necessary to arrange a slit at both ends to shield the energy attenuating portion.

    When a semiconductor film is annealed using a linear beam having a uniform intensity obtained in this manner and an electronic device is manufactured using this semiconductor film, the characteristics of the electronic device are good and uniform.

Next, if necessary, a small amount of impurity element (boron or phosphorus) is doped into the semiconductor layer in order to control the threshold value of the transistor. Here, an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation is used.

    Next, a gate insulating film 104 is formed to have a thickness of 5 to 50 nm so as to cover the island-shaped semiconductor film 103. The gate insulating film 104 is formed by silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide containing nitrogen (SiOxNy) (x> y), silicon nitride containing silicon (SiNxOy) (x> y) by CVD or sputtering. ) And the like may be combined as appropriate to form a laminated structure. In this embodiment, the gate insulating film 104 has a stacked structure of a SiNxOy film and a SiOxNy film.

    Subsequently, a conductive film to be a gate electrode is formed with a thickness of 200 to 550 nm on the gate insulating film 104. As the conductive film, an aluminum (Al) film, a copper (Cu) film, a film containing aluminum or copper as a main component, a chromium (Cr) film, a tantalum (Ta) film, a tantalum nitride (TaN) film, or titanium (Ti) A film, a tungsten (W) film, a molybdenum (Mo) film, a film containing tantalum as a main component, or the like can be used. In this embodiment mode, a two-layer conductive film is used. As a material for the conductive film, a first layer was a tantalum nitride film, and a tungsten film was formed thereon as a second layer.

    Subsequently, a gate electrode 105 having a two-layer structure is formed using a photomask over the conductive film and using a photolithography technique (FIG. 16A). The gate electrode 105 may be a single layer or a stack of two or more layers.

    Next, the island-shaped semiconductor film 103 is doped with high-concentration impurity ions 106 (FIG. 16B). Impurity regions 107 and 108 and a channel formation region 109 are formed by doping the island-shaped semiconductor film 103 with an impurity element through the gate insulating film 104. As a doping method, an ion doping method or an ion implantation method can be used. For example, boron (B), gallium (Ga), or the like is used as an impurity element when a P-type semiconductor is manufactured, and phosphorus (P), arsenic (As), or the like is used when an N-type semiconductor is manufactured. .

Next, an insulating film is formed so as to cover the gate insulating film 104 and the gate electrode 105. Insulating film, for example, a plasma CVD method by a silicon oxide containing nitrogen (SiOxNy) (x> y) the 100 nm, by subsequent thermal CVD method is formed by 200nm silicon oxide film (SiO ₂ film).

    Next, the insulating film is selectively etched by anisotropic etching mainly in the vertical direction to form an insulating layer (hereinafter referred to as a sidewall) 110 in contact with the side surface of the gate electrode 105 (FIG. 16C). ). The sidewall 110 is used as a mask when forming silicide later. Further, part of the gate insulating film 104 is also removed by this etching to form the gate insulating film 111, and a part of the semiconductor film is exposed. In the case where the etching selectivity between the insulating film and the semiconductor film is low, the exposed semiconductor film is slightly etched and thinned. When the film thickness of the semiconductor film is not uniform as shown in FIG. 16C, the film thickness ratio of the exposed island-like semiconductor portion where the silicide layer is to be formed later is defined as the film thickness of the semiconductor film. It is good to calculate.

    Next, after removing the natural oxide film formed on the surface of the exposed semiconductor film portion, a metal film 112 is formed (FIG. 16D). The metal film 112 is made of a material that forms silicide by reacting with a silicon film that is a semiconductor. Examples of the metal film 112 include a nickel film, a titanium film, a cobalt film, a platinum film, or a film made of an alloy containing at least two of these elements. In this embodiment, a nickel film is used as the metal film 112, and the nickel film is formed by sputtering at a film formation power of 500 W to 1 kW at room temperature.

    After the metal film 112 is formed, a silicide layer 113 is formed by heat treatment (FIGS. 17A and 17B). RTA (Rapid Thermal Anneal), furnace annealing, or the like can be used for the heat treatment. In this embodiment mode, after the metal film 112 is formed, RTA treatment is performed under conditions of 600 ° C. and 30 seconds in a reduced pressure or vacuum atmosphere without being exposed to the air. As a result, a high-quality silicide layer 113 that is not affected by the oxidation of the metal film 112 is formed. The silicide layer 113 has an end point on the channel formation region side or a portion that coincides with the end of the gate insulating film 111, a region where the film thickness is increased from there, a region where the film thickness is constant, a silicon film And a region formed along the side surface of the substrate.

    The thickness of the silicide layer 113 formed by this heat treatment can be controlled by controlling the thickness of the metal film 112 formed in FIG. 16D and the conditions of the heat treatment. In FIG. 17A, the silicide layer 113 is formed only on the surface of the island-shaped semiconductor film 103, while in FIG. 17B, the silicide layer 113 extends over almost the entire silicon film thickness of the island-shaped semiconductor film 103. The structure is called silicide. As the thickness of the metal film 112 is increased, the heat treatment temperature is increased, or the heat treatment time is lengthened, the silicide layer 113 is likely to have a full silicide structure as the thickness of the silicide layer 113 increases. That is, when the heat treatment time is long and the metal film 112 is formed thick, the silicide layer 113 having a large film thickness can be formed.

    The length in the channel length direction of the region where the thickness of the silicide layer 113 is increased can be controlled by the method for forming the metal film 112.

    For example, as shown in FIG. 18A, the metal film 112 is formed with poor coverage, particularly with poor side coverage. The metal film 112 has the smallest film thickness on the side surface of the gate insulating film 111, and the film thickness is increased from the metal film 112 toward the upper surface of the gate electrode toward the side surface of the island-shaped semiconductor film 103. FIG. 18B shows the silicide layer 113 formed by heat treatment after forming the metal film 112 with poor coverage. Reflecting the film thickness of the metal film 112, the silicide layer 113 is also thicker from the channel formation region side toward the side surface of the island-like semiconductor film 103. That is, when the film thicknesses of the silicide layers 113 in the portions AA ′, BB ′, and CC ′ in FIG. 18B are compared, (A−A ′) <(BB ′) < (C-C ').

    Therefore, by controlling the degree of coverage of the metal film 112, the region where the film thickness increases at the end of the silicide layer 113 on the channel formation region side can be increased. That is, the first region 13a in FIG. 1B can be extended in the channel length direction, and the angle θ in FIG. 1B can be reduced.

    The coverage of the metal film 112 can be controlled by film forming conditions. If the metal film 112 is formed by sputtering, the shorter the distance between the semiconductor and the target, the more uneven the directions of the sputtered atoms jumping out of the target, and the coverage becomes worse. In addition, as the atmospheric pressure during sputtering is increased, the trajectory of the sputtered atoms to the semiconductor is disturbed, so that the coverage becomes worse. By controlling these conditions, a silicide layer having an angle θ of 0 ° <θ <45 ° can be formed.

    Further, if the metal film 112 has poor coating properties and the metal film 112 is formed thinner, the metal film 112 on the side surface of the gate insulating film 111 and the end portion of the island-shaped semiconductor film 103 are formed. The difference from the film thickness of the metal film 112 becomes smaller. By doing so, the length in the channel length direction of the region where the thickness of the silicide layer 113 increases (the first region 13a in FIG. 1B) can be increased, and the silicide layer 113 having a small angle θ can be formed.

    As described above, the film thickness and shape of the silicide layer can be controlled by controlling the film formation conditions of the metal film 112 or the heat treatment conditions when the silicide layer 113 is formed. In this embodiment, the metal film 112 is formed so that the thickness of the silicide layer 113 is 60% or more of the thickness of the island-shaped semiconductor film 103.

    Next, the unreacted metal film 112 is removed.

    After that, an interlayer insulating film 114 is formed (FIG. 17C). The interlayer insulating film 114 is formed using an organic material or an inorganic material. The interlayer insulating film 114 may have a single layer structure or a stacked structure. A contact hole for exposing the silicide layer 113 is formed in the interlayer insulating film 114 by etching. Next, a conductive layer is formed so as to fill the contact hole, and the wiring 115 is formed by etching.

    On the other hand, after the entire thickness of the semiconductor film becomes silicide as shown in FIG. 17B, an interlayer insulating film 114 is formed and a wiring 115 is formed as shown in FIG. D). In FIG. 17D, a source region and a drain region formed of the silicide layer 113 can be formed.

    Note that the impurity region may be thermally activated before the interlayer insulating film is formed or after the first or second film is formed if the interlayer insulating film is a stacked layer. For thermal activation, methods such as laser light irradiation, RTA, and heat treatment using a furnace can be used. In the thermal activation, since the structure is in contact with the wiring by silicide, the step of thermally activating the impurity region can be omitted.

    The structure in FIG. 17C has a larger area in which the silicide layer 113 is in contact with the impurity regions 107 and 108 than the structure in FIG. Therefore, the contact resistance between the silicide layer 113 and the impurity regions 107 and 108 becomes low, and the parasitic resistance becomes smaller than that in FIG.

    On the other hand, the structure in FIG. 17D has lower resistance in the source region and the drain region than the structure in FIG. The transistor formed in this embodiment corresponds to the structure in FIG. 2A assumed in the analysis by the computer, and a portion corresponding to the region 31 in FIG. In the case where the gate electrode 105 of this embodiment is formed to have a tapered cross section and the upper side is shorter than the bottom side, the end of the bottom side of the gate electrode is the interface between the channel formation region 109 and the impurity regions 107 and 108. Matches.

    Although the metal film 112 is formed after the sidewall 110 is formed, the present invention is not limited to this method. A mask may be used instead of the sidewall.

    Further, in this embodiment mode, it is described that a semiconductor device with high on-state current is manufactured by controlling the shape and film thickness of both the pair of silicide layers 113 formed with the channel formation region interposed therebetween. However, in the present invention, at least one of the silicide layers only needs to have a thickness ratio of 0.6 or more with respect to the silicon film and an angle θ = less than 45 ° (θ excludes 0), and thus the pair of silicide layers is not necessarily required. The shape and film thickness of 113 need not be controlled.

    In this embodiment mode, a method for manufacturing a TFT is described. However, a transistor may be formed by forming an impurity region and a silicide layer on a silicon substrate or an SOI substrate. When the above-described transistor manufacturing process is applied to a silicon substrate or an SOI substrate, the steps of forming the gate insulating film 104 and the gate electrode 105 may be sequentially performed after element isolation is performed using an isolation technique or the like.

    This embodiment mode can be freely combined with Embodiment Mode 1.

(Embodiment 3)
A method for manufacturing a semiconductor device having a low-concentration impurity region will be described with reference to FIGS. The same parts as those in the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

    First, the process until the structure 19 (A) is formed is the same as that in FIG. After that, doping with low-concentration impurity ions 201 is performed (FIG. 19B). The impurity element is doped into the island-shaped semiconductor film 103 through the gate insulating film 104, and low-concentration impurity regions 202 and 203 and a channel formation region 109 are formed. As a doping method, an ion doping method or an ion implantation method can be used. For example, boron (B), gallium (Ga), or the like is used as an impurity element when a P-type semiconductor is manufactured, and phosphorus (P), arsenic (As), or the like is used when an N-type semiconductor is manufactured. .

    Next, a sidewall 110 is formed, and a gate insulating film 111 is formed (FIG. 19C). This exposed semiconductor film portion later becomes a source region and a drain region. In the case where the etching selectivity between the gate insulating film and the semiconductor film is low, the exposed semiconductor film is slightly etched and thinned.

    After that, a metal film 112 is formed by a method similar to that in Embodiment 2 (FIG. 19D). Then, heat treatment is performed to form the silicide layer 113 shown in FIG. The thickness and shape of the silicide layer 113 are controlled by the method described in the second embodiment, and a silicide layer having a thickness ratio with respect to the silicon film of 0.6 or more and an angle θ of greater than 0 ° and less than 45 °. Form.

    Next, doping with high-concentration impurity ions 204 is performed using the gate electrode 105 and the sidewall 110 as a mask (FIGS. 20C and 20D). High-concentration impurity regions 205 and 206 are formed in the island-like semiconductor film 103. Accordingly, low concentration impurity regions 207 and 208 are formed. For example, boron (B), gallium (Ga), or the like is used as an impurity element when a P-type semiconductor is manufactured, and phosphorus (P), arsenic (As), or the like is used when an N-type semiconductor is manufactured. .

    Then, after the interlayer insulating film 114 is formed, etching is performed to form a wiring 115 connected to the silicide layer 113 (FIGS. 20E and 20F). According to this embodiment mode, low-concentration impurity regions 207 and 208 that do not overlap with the gate electrode can be formed. A low-concentration impurity region that does not overlap with the gate electrode is referred to as a Loff region. The Loff region has a high effect of suppressing the off-current value. Therefore, when a semiconductor device is manufactured in this embodiment mode, a semiconductor device with high on-state current and less leakage current can be formed.

    The transistor formed in this embodiment corresponds to the structure in FIG. 2B assumed in the analysis by the computer, and a portion corresponding to the region 31 in FIG.

    Note that the impurity region may be thermally activated before the interlayer insulating film is formed or after the first or second film is formed if the interlayer insulating film is a stacked layer. For thermal activation, methods such as laser light irradiation, RTA, and heat treatment using a furnace can be used. In addition, since this structure is in contact with the wiring by silicide, the step of thermally activating the impurity region can be omitted.

    19 and 20, the silicide layer 113 is formed and then doped with the high-concentration impurity ions 204. However, the metal film 112 may be formed and silicided after the impurity ions 204 are doped. In FIG. 20D, since it is fully silicided, it is not necessary to dope the impurity ions 204 if sufficient ohmic connection can be obtained.

    Further, although the metal film 112 is formed after the sidewalls are formed, the present invention is not limited to this method. A mask may be used instead of the sidewall.

    In this embodiment mode, a method for manufacturing a TFT is described. However, a transistor may be formed by forming an impurity region and a silicide layer on a silicon substrate or an SOI substrate. When the above-described transistor manufacturing process is applied to a silicon substrate or an SOI substrate, the steps of forming the gate insulating film 104 and the gate electrode 105 may be sequentially performed after element isolation is performed using an isolation technique or the like.

    This embodiment mode can be freely combined with Embodiment Modes 1 and 2 within a feasible range.

(Embodiment 4)
A method for manufacturing a semiconductor device having a gate electrode having a stacked structure in which the width of the gate electrode is different between the upper layer and the lower layer will be described. In this embodiment, the same components as those in Embodiments 1 to 3 are denoted by the same reference numerals and description thereof is omitted.

    First, the process is the same as that in Embodiment 1 until the insulating film 102, the island-shaped semiconductor film 103, and the gate insulating film 104 are formed over the substrate 101. Next, a first conductive film 301 for the first layer and a second conductive film 302 for the second layer, which will be gate electrodes later, are formed over the gate insulating film 104. However, the first conductive film 301 and the second conductive film 302 must be combined so that a selection ratio can be obtained in the mutual etching. For example, Al and Ta, Al and Ti, and TaN and W can be used as a combination of the first conductive film and the second conductive film that can be selected. In this embodiment mode, the first conductive film 301 is a tantalum nitride film, and the second conductive film 302 is a tungsten film.

    Subsequently, a first resist 303 is formed over the second conductive film 302 (FIG. 21A).

    Subsequently, first etching is performed using the first resist 303 as a mask (FIG. 21B). In the first etching, the second conductive film 302 is etched to form the conductive film 304. At this time, it is preferable to perform etching under an etching condition with a high selectivity with respect to the first conductive film 301 so that the first conductive film 301 is not etched. Note that the first resist 303 is also etched to become the second resist 305. However, the receding width from the first resist 303 to the second resist 305 is not shown in the drawing. At this time, the taper angle θ of the side surface of the conductive film 304 is 80 ° ≦ θ ≦ 90 °, and has a substantially vertical taper angle.

In the first etching, a mixed gas of Cl ₂ , SF ₆ , and O ₂ is used as an etching gas, and the flow rate ratio is Cl ₂ / SF ₆ / O ₂ = 33/33/10 sccm. Plasma is generated by supplying 2000 W of power to the coil-type electrode at a pressure of 0.67 Pa. A power of 50 W is applied to the substrate side (sample stage).

Subsequently, second etching is performed on the first conductive film 301 using the conductive film 304 as a mask (FIG. 21C). A first gate electrode 306 is formed from the first conductive film 301 by second etching. At this time, it is preferable to perform etching under an etching condition with a high selectivity with respect to the gate insulating film 104 so that the gate insulating film 104 is not etched. The second etching condition is that plasma is generated by supplying power of 2000 W to the coil-type electrode at a pressure of 0.67 Pa. A power of 50 W is applied to the substrate side (sample stage). Etching gas is Cl _2. The second resist 305 is also etched and receded to become the third resist 307, but the receding state is not shown.

Next, third etching is performed (FIG. 21D). The third etching condition is that plasma is generated by supplying power of 2000 W to the coil-type electrode at a pressure of 1.33 Pa. No power is supplied to the substrate side (sample stage). The etching gas is a mixed gas of Cl ₂ , SF ₆ , and O ₂ , and the flow rate ratio is Cl ₂ / SF ₆ / O ₂ = 22/22/30 sccm. In the third etching, the third resist 307 is retracted. At the same time, the length of the conductive film 304 in the channel length direction is also receded using the third resist 307 that recedes as a mask to form the second gate electrode 308. Note that the recessed third resist 307 becomes the fourth resist 309. Thereafter, the fourth resist 309 is removed.

    Through the above steps, a gate electrode having a stacked structure in which the length of the lower first gate electrode 306 in the channel length direction is longer than that of the upper second gate electrode 308 is formed. The gate electrode structure of the present embodiment is formed using the resist recession width at the time of etching. Specifically, the receding width from the third resist 307 to the fourth resist 309 during the third etching is the length of the first gate electrode and the length of the second gate electrode 308 in the channel length direction. It is a difference.

    In this embodiment mode, the difference between the length of the first gate electrode 306 in the channel length direction and the length of the second gate electrode 308 in the channel length direction can be set to 20 to 200 nm. It is possible to form an electrode structure.

    The first to third etchings in this embodiment can be performed by dry etching, and can be performed by using an ICP (Inductively Coupled Plasma) etching method.

Next, the island-shaped semiconductor film 103 is doped with low-concentration impurity ions 201 (FIG. 22A). The island-shaped semiconductor film 103 is doped with a low-concentration impurity element through the first gate electrode 306 and the gate insulating film 104, and a low-concentration impurity region 310 is formed in the island-shaped semiconductor film portion overlapping the first gate electrode 306. 311 is formed. At the same time, only the gate insulating film is allowed to pass through, and impurity elements are doped into both end portions of the island-shaped semiconductor film to form low concentration impurity regions 312 and 313. A channel formation region 314 is also formed. The element concentration of the low-concentration impurity regions 310 to 313 is 1 × 10 ¹⁶ to 1 × 10 ²⁰ atoms / cm ³ (preferably 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ ). As a doping method, an ion doping method or an ion implantation method can be used. For example, boron (B), gallium (Ga), or the like is used as an impurity element when a P-type semiconductor is manufactured, and phosphorus (P), arsenic (As), or the like is used when an N-type semiconductor is manufactured. .

    The doping to the low-concentration impurity regions 310 and 311 is performed not only through the gate insulating film but also through the first gate electrode 306. Therefore, the concentration of the impurity element in the low concentration impurity regions 310 and 311 is lower than that in the low concentration impurity regions 312 and 313.

    Next, an insulating film is formed so as to cover the gate insulating film 104, the first gate electrode 306, and the second gate electrode 308, and etched to form side surfaces of the first gate electrode 306 and the second gate electrode 308. A sidewall 110 in contact is formed (FIG. 22B). The sidewall 110 is used as a mask when forming silicide later. Further, part of the gate insulating film 104 is also removed by this etching to form the gate insulating film 111, and a part of the semiconductor film is exposed.

    Next, after removing the natural oxide film formed on the exposed surface of the semiconductor film, a metal film 112 is formed (FIG. 22C). The metal film 112 is formed by the method described in Embodiment Mode 2, and the shape and thickness of the silicide layer to be formed are controlled. Thereafter, a silicide layer 113 is formed by heat treatment.

    The silicide layer 113 is nickel silicide here. As the heat treatment, RTA, furnace annealing, or the like can be used. At this time, by controlling the film thickness, the heating temperature, and the heating time of the metal film 112, the structure of FIG. 22D or FIG. 22G is obtained.

Next, unreacted nickel is removed. Here, unreacted nickel is removed using an etching solution of HCl: HNO ₃ : H ₂ O = 3: 2: 1.

In FIG. 22D, heat treatment conditions for forming the silicide layer are controlled so that the silicide layer 113 has a thickness less than or equal to that of the semiconductor film. Alternatively, the thickness of the metal film 112 to be formed is controlled. Doping of high concentration impurity ions 315 is performed using the sidewall 110 as a mask. By this doping, high concentration impurity regions 318 and 319 functioning as a source region and a drain region are formed. The high-concentration impurity regions 318 and 319 are doped so that the impurity element is 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ . At the same time, low concentration impurity regions 316 and 317 are formed. As a doping method, an ion doping method or an ion implantation method can be used. Boron (B), gallium (Ga), or the like is used as an impurity element when a P-type semiconductor is manufactured, and phosphorus (P), arsenic (As), or the like is used when an N-type semiconductor is manufactured.

    After that, an interlayer insulating film 114 is formed, and a wiring 115 is formed (FIG. 22F).

    On the other hand, in FIG. 22G, a silicide layer 113 is formed in which the entire thickness of the semiconductor film is silicide. After that, high concentration impurity ions 315 are doped using the sidewall 110 as a mask to form low concentration impurity regions 320 and 321, and high concentration impurity regions 322 and 323 (FIG. 22H). Similarly to FIG. 22F, an interlayer insulating film 114 is formed, and a wiring 115 is formed, so that the structure of FIG.

    In the structure of this embodiment mode, the high-concentration impurity regions 318 and 319 serve as a source region and a drain region in FIG. Further, the low concentration impurity regions 316 and 317 which are portions of the semiconductor film which overlap with the bottom surface of the sidewall formed on the side surface of the first gate electrode 306 with the gate insulating film 111 interposed therebetween serve as a Loff region. In addition, although the low concentration impurity region overlapping with the gate electrode is referred to as a Lov region, the low concentration impurity regions 310 and 311 overlapping with the first gate electrode 306 through the gate insulating film 111 become Lov regions.

    In FIG. 22I, the silicide layer 113 becomes a source region and a drain region. The low concentration impurity regions 320 and 321 become Loff regions, and the low concentration impurity regions 310 and 311 become Lov regions.

    The structure in FIG. 22F has a larger area where the silicide layer 113 is in contact with the high-concentration impurity regions 318 and 319 as compared with the structure in FIG. Therefore, the contact resistance between the silicide layer 113 and the high-concentration impurity regions 318 and 319 becomes low, and the parasitic resistance becomes smaller than that in FIG.

    On the other hand, in the structure of FIG. 22I, the thickness of the silicide layer 113 is larger than that of the structure of FIG.

    This embodiment can prevent deterioration of the on-current value and achieve high reliability, and can form a structure with high on-current. Further, a fine TFT having a Lov length of 20 to 200 nm, a Loff length of 30 to 500 nm, and a channel length of 0.1 to 1.0 μm can be formed. Therefore, even for a very fine TFT, a low-concentration impurity region suitable for the size can be formed, and a predetermined on-current can be obtained.

    The transistor formed in this embodiment corresponds to the structure in FIG. 2B assumed in the analysis by the computer. Locations corresponding to the region 31 in FIG. 2B are a channel formation region 314 and low-concentration impurity regions 310 and 311.

    In FIG. 22, the high-concentration impurity ions 315 are doped after the silicide layer 113 is formed. However, the metal film 112 may be formed and silicided after the impurity ions 315 are doped. Further, in FIG. 22H, since it is fully silicided, it is not necessary to dope the impurity ions 315 if sufficient ohmic connection can be obtained.

    Further, although the metal film 112 is formed after the sidewalls are formed, the present invention is not limited to this method. A mask may be used instead of the sidewall.

    In this embodiment mode, a method for manufacturing a TFT is described. However, a transistor may be formed by forming an impurity region and a silicide layer on a silicon substrate or an SOI substrate. When the above-described transistor manufacturing process is applied to a silicon substrate or an SOI substrate, element isolation is performed by an isolation technique or the like, and then the gate insulating film 104, the first gate electrode 306, and the second gate electrode 308 are formed. The steps to be performed may be performed in order.

    This embodiment can be freely combined with Embodiments 1 to 3 within a feasible range.

(Embodiment 5)
In this example, FIG. 23 illustrates a method for manufacturing a semiconductor device having a gate electrode having a stacked structure in which the width of the gate electrode is different between an upper layer and a lower layer, and having only a Lov region. Moreover, in this Embodiment, the same code | symbol is used about the same thing as Embodiment 1-4, and detailed description is abbreviate | omitted.

    In this embodiment mode, a semiconductor device is formed through steps similar to those in Embodiment Mode 4 from FIG. 21A to FIG. Next, as in FIG. 22A, low-concentration impurity ions 201 are doped to form low-concentration impurity regions 310 and 311, low-concentration impurity regions 312 and 313, and a channel formation region 314 (FIG. 23A). )).

    Next, high-concentration impurity ions 401 are doped using the first gate electrode 306 as a mask to form high-concentration impurity regions 402 and 403 (FIG. 23B). Note that the order of doping of the low-concentration impurity ions 201 in FIG. 23A and the doping of the high-concentration impurity ions 401 in FIG. 23B may be reversed to obtain the state of FIG. good. Alternatively, the doping of the low-concentration impurity ions 201 may be omitted and only the high-concentration impurity ions 401 may be doped. When the high-concentration impurity ions 401 are doped to form the high-concentration impurity regions 402 and 403, the low-concentration impurity regions 310 and 311 overlapping with the first gate electrode 306 are also somewhat doped. By utilizing this phenomenon, the low-concentration impurity regions 310 and 311 can be formed only by doping the impurity ions 401 without doping the impurity ions 201. For example, boron (B), gallium (Ga), or the like is used as an impurity element when a P-type semiconductor is manufactured, and phosphorus (P), arsenic (As), or the like is used when an N-type semiconductor is manufactured. .

    Next, the sidewall 110 is formed, and the gate insulating film is etched to form a new gate insulating film 111 (FIG. 23C).

    Then, a metal film is formed so as to cover the sidewall 110 and the island-like semiconductor film 103, and then heat treatment is performed to form a silicide layer 113. After the silicide layer 113 is formed as shown in FIG. 23D or FIG. 23F, the interlayer insulating film 114 and the wiring 115 are formed to obtain the structure of FIG. 23E or FIG.

    The transistor formed in this embodiment corresponds to the structure in FIG. 2A assumed in the analysis by the computer. Locations corresponding to the region 31 in FIG. 2A are a channel formation region 314 and low-concentration impurity regions 310 and 311.

    As in Embodiment 1, the structure of the transistor of this embodiment may be formed using a mask instead of a sidewall.

    Through the above steps, the TFT having the low concentration impurity regions 310 and 311 as the Lov region is completed. Since the TFT formed in this embodiment does not have a Loff region, the parasitic resistance is lower than that of the TFT in Embodiment 4, and a high on-state current can be realized.

    In this embodiment mode, a method for manufacturing a TFT is described. However, a transistor may be formed by forming an impurity region and a silicide layer on a silicon substrate or an SOI substrate. When the above-described transistor manufacturing process is applied to a silicon substrate or an SOI substrate, element isolation is performed by an isolation technique or the like, and then the gate insulating film 104, the first gate electrode 306, and the second gate electrode 308 are formed. The steps to be performed may be performed in order.

    This embodiment mode can be freely combined with Embodiment Modes 1 to 4 within a feasible range.

(Embodiment 6)
The structure of the semiconductor device of the present invention will be described with reference to FIGS. The semiconductor device described in this embodiment is a DRAM (Dynamic Random Access Memory) used as a memory cell.

    As shown in FIG. 24A, an inorganic insulating film 614 is formed over a SIMOX substrate in which a first single crystal silicon layer 511, an insulating layer 512, and a second single crystal semiconductor layer 513 are stacked.

    Next, a gate electrode 616 made of a conductive material is formed. The gate electrode 616 may be a single layer or a stacked layer. At this stage, the state of FIG. 24B is obtained.

    Next, in order to form a low concentration impurity region, a first impurity region 617 is formed by introducing an impurity at a low concentration by an ion doping method. At this stage, the state of FIG. 24C is obtained.

    Next, a silicon nitride film is formed so as to cover the gate electrode 616 and anisotropically dry-etched. Thus, sidewalls 618 in contact with the side surfaces of the gate electrode 616 are formed as shown in FIG. Subsequently, the inorganic insulating film 614 is etched using the sidewall 618 as a mask to form the gate insulating film 510.

    Next, in order to form a high concentration impurity region functioning as a source region and a drain region, a second impurity region 619 is formed by introducing a high concentration impurity by an ion doping method. At this stage, the state shown in FIG. 24E is obtained.

    Next, a metal film which forms a silicide layer by reacting with the first single crystal silicon layer 511 is formed so as to cover the gate electrode 616, the sidewall 618, the second impurity region 619, and the gate insulating film 510. As described in the first to fifth embodiments, the metal film formation conditions are controlled so that the silicide layer shape of the present invention is obtained. Then, heat treatment is performed, a silicide layer 509 is formed, and an unreacted metal film is removed (FIG. 24F).

Next, the second impurity region 619 is activated. As activation here, laser annealing at an energy density of about 0.1 to 1 J / cm ² is performed using a YAG laser or a XeCl laser. Instead of this laser annealing, it is also possible to perform laser annealing using a laser beam having a fundamental wave and a pulse width of 10 ps or less. Note that the activation step may be omitted.

    Next, as shown in FIG. 25, a first silicon oxide film 620 is formed by a CVD (Chemical Vapor Deposition) method, and then planarized by CMP (Chemical Mechanical Polishing), and contact hole photolithography is performed. A contact hole formed by etching the first silicon oxide film 620 is filled with polysilicon, and an extraction terminal (also referred to as a plug) 621 in contact with the silicide layer 509 is formed. Capacitor plugs 624 and 625 are also formed at the same time.

    Next, after a second silicon oxide film 622 is formed on the entire surface, a portion for forming a bit line is opened. Next, a titanium nitride film and a tungsten film are stacked by sputtering, and shape processing is performed to form the bit line 623. Note that the bit line 623 is common to two memory cells.

    Next, a third silicon oxide film 626 and a silicon nitride film 627 are formed over the bit line 623 by a CVD method, planarized by CMP, and contact hole photolithography is performed. A contact hole formed by etching the third silicon oxide film 626 and the silicon nitride film 627 is filled with polysilicon, and a capacitor second plug 628 connected to the capacitor first plug 624, 625, 629 is formed.

    Next, a cylindrical capacitor is formed. First, the lower electrode of the capacitor is formed. A fourth silicon oxide film having a thickness corresponding to the height of the capacitor to be formed is formed by a CVD method. A hole is made in the fourth silicon oxide film by photolithography to form a hole for the lower electrode of the capacitor. Note that the hole for the lower electrode of the capacitor is designed so that the capacitor is as large as possible without contacting the adjacent capacitor.

    Next, a thin polysilicon film is formed by CVD on the entire surface of the fourth silicon oxide film including the inner surfaces of the holes of the fourth silicon oxide film. Next, etching back is performed to partially remove the polysilicon film other than the inner surface of the hole of the fourth silicon oxide film, so that the polysilicon film remains only on the inner surface of the hole, and the cylindrical electrode (lower electrode of the capacitor) ) 630 are formed. Thereafter, the fourth silicon oxide film is removed, and the outer peripheral portion of the lower electrode 630 is exposed.

    Further, the present invention is not limited to the structure of the memory cell shown in FIG. 25, and may be a planar type, a stack type, or a trench type, for example.

Next, a Ta ₂ O ₅ film is formed, and a TiN film is formed by a CVD method. Then, the TiN film is shaped to form an upper electrode (also called a plate) 631 made of the TiN film. The Ta ₂ O ₅ film functions as a capacitor dielectric 637. The memory cell is completed through the above steps. Note that BaSrTiO ₃ , SiO ₂ , Si ₃ N _4, or the like can be used as the dielectric 637 instead of the Ta ₂ O ₅ film.

    Then, after the first interlayer insulating film 632 is formed, a first wiring 634 including a stack of a TiN film 634a and a film 634b containing Al as a main component is formed. A second interlayer insulating film 633 is formed over the first wiring 634, and further, a second wiring 635 including a TiN film 635a and a film 635b containing Al as a main component is formed.

    A complementary metal oxide semiconductor (CMOS) circuit provided around the memory cell is connected through a first wiring 634 and a second wiring 635. As shown in FIG. 25, there is no wiring connection in the memory cell, and only the first wiring and the second wiring cross over the memory array in which the memory cells are arranged. For the peripheral CMOS circuit, the memory cell has a total three-layer wiring structure including a bit line, a first wiring, and a second wiring.

    Then, after annealing in a hydrogen atmosphere to recover damage, a protective film 636 such as a silicon oxide film or a silicon nitride film is formed. Although not shown, the protective film 636 has an opening so that the second wiring is exposed only at the bonding pad (connecting terminal portion to the package).

    Finally, the second single crystal semiconductor layer 513 is removed by scraping. Thus, a DRAM whose structure is partially shown in FIG. 25 is completed. As described above, a memory cell including a transistor with an optimized silicide shape can be manufactured, so that a memory cell with high reading speed can be manufactured.

Note that the removal of the second single crystal semiconductor layer 513 may be performed using a grinding / polishing apparatus such as a grindstone, or may be performed using an etching agent, or the grinding / polishing apparatus and the etching agent may be used in combination. You may go. Preferably, the second single crystal semiconductor layer 513 is ground and polished until the second single crystal semiconductor layer 513 becomes thin to some extent, and then the second single crystal semiconductor layer 513 is removed with an etchant until the insulating layer 512 is exposed. If the etching agent is wet etching, a mixture of hydrofluoric acid diluted with water or ammonium fluoride, a mixture of hydrofluoric acid and nitric acid, a mixture of hydrofluoric acid, nitric acid and acetic acid, a mixture of hydrogen peroxide and sulfuric acid, hydrogen peroxide And a mixed solution of ammonium water and water, a mixed solution of hydrogen peroxide, hydrochloric acid, and water. In the case of dry etching, a gas containing a halogen atom or molecule such as fluorine or a gas containing oxygen is used. Preferably, a gas or liquid containing halogen fluoride or a halogen compound is used. For example, chlorine trifluoride (ClF ₃ ) may be used as a gas containing halogen fluoride.

    Then, dicing is performed to separate individual chips having DRAMs from the wafer. Next, chips are picked up one by one from the wafer and mounted on a lead frame 701 shown in FIG. Then, the electrode terminals of the chip 702 and the inner leads of the lead frame 701 are connected by a gold wire 707 having a diameter of about 20 to 30 μm so as to be electrically connected. Next, sealing is performed with a mold resin layer 703 so as to facilitate handling. The leads are then solder plated to prevent rust. Next, the lead frame 701 is cut into individual packages, and leads are formed. Thus, packaging is performed.

    FIG. 26 is a perspective view showing a cross-sectional structure of a device in which packaging is performed. In the structure shown in FIG. 26, a chip 702 is connected to a lead frame 701 by a wire bonding method. The chip 702 is sealed with a mold resin layer 703. The chip 702 is mounted on the lead frame 701 with a mounting adhesive 704.

    The lead frame 701 is a ball grid array type provided with solder balls 705. The solder ball 705 is provided on the opposite side of the lead frame 701 from the side on which the chip 702 is mounted. The wiring 706 provided in the lead frame 701 is electrically connected to the solder ball 705 through a contact hole provided in the lead frame.

    In this embodiment mode, the wiring 706 for electrical connection between the chip 702 and the solder ball 705 is provided on the surface of the lead frame 701 on which the chip is mounted. However, the present invention is not limited to this. For example, the wiring may be provided in multiple layers inside the lead frame.

    In FIG. 26, the chip 702 and the wiring 706 are electrically connected by a gold wire 707. The chip 702 is provided with a semiconductor element including a DRAM, and a pad is provided on the side of the chip 702 opposite to the side on which the lead frame 701 is provided. The pad is electrically connected to the semiconductor element. The pad is connected to a wiring 706 provided on the lead frame 701 by a gold wire 707.

    In addition, this embodiment can be freely combined with Embodiments 1 to 5 within a feasible range.

(Embodiment 7)
The structure of the semiconductor device of the present invention will be described with reference to FIG. A semiconductor device 1100 of the present invention includes an arithmetic processing circuit 1101, a memory circuit 1103, an antenna 1104, a power supply circuit 1109, a demodulation circuit 1110, and a modulation circuit 1111. The semiconductor device 1100 includes the antenna 1104 and the power supply circuit 1109 as essential components, and other components are provided as appropriate in accordance with the use of the semiconductor device 1100.

    The arithmetic processing circuit 1101 performs instruction analysis, control of the storage circuit 1103, output of data to be transmitted to the modulation circuit 1111, and the like based on a signal input from the demodulation circuit 1110.

    The memory circuit 1103 includes a circuit including a memory element and a control circuit that controls data writing and data reading. The memory circuit 1103 stores at least an identification number of the semiconductor device itself. The identification number is used to distinguish from other semiconductor devices. The memory circuit 1103 includes an organic memory, DRAM, SRAM (Static Random Access Memory), FeRAM (Ferroelectric Random Access Memory), mask ROM (Read Only Memory Only), and PROM (Programmable Read Only Memory, PROM). Memory, EEPROM (Electrically Erasable Programmable Read Only Memory), and flash memory. An organic memory has a structure in which a layer containing an organic compound is sandwiched between a pair of conductive layers. Since the organic memory has a simple structure, the manufacturing process can be simplified and the cost can be reduced. In addition, since the structure is simple, the area of the stacked body can be easily reduced, and a large capacity can be easily realized. In addition, it is non-volatile and does not require a built-in battery. Therefore, it is preferable to use an organic memory as the memory circuit 1103.

    The antenna 1104 converts the carrier wave supplied from the reader / writer 1112 into an AC electrical signal. Also, load modulation is applied by the modulation circuit 1111. The power supply circuit 1109 generates a power supply voltage using the alternating electrical signal converted by the antenna 1104 and supplies the power supply voltage to each circuit.

    The demodulation circuit 1110 demodulates the AC electrical signal converted by the antenna 1104 and supplies the demodulated signal to the arithmetic processing circuit 1101. The modulation circuit 1111 applies load modulation to the antenna 1104 based on the signal supplied from the arithmetic processing circuit 1101.

    The reader / writer 1112 receives the load modulation applied to the antenna 1104 as a carrier wave. Further, the reader / writer 1112 transmits a carrier wave to the semiconductor device 1100. Note that the carrier wave is an electromagnetic wave emitted from the reader / writer 1112.

    Various circuits included in the semiconductor device 1100 can be formed using the transistors described in any of Embodiments 1 to 5. Further, the memory circuit 1103 may be formed by the DRAM of the sixth embodiment. Thus, a semiconductor device with high characteristics can be manufactured.

    The semiconductor device 1100 and the reader / writer 1112 are used to transmit and receive data without contact. Therefore, by attaching and embedding the semiconductor device 1100 to various articles and fixing them, information on the articles can be read and written by the reader / writer 1112.

    Articles include, for example, keys (see FIG. 28 (A)), banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc.), books, containers (such as petri dishes, 28B), accessories (such as a bag and glasses, see FIG. 28C), packaging containers (wrapping paper, bottles, etc., see FIG. 28D), recording media (discs and discs) Video tapes, etc.), vehicles (bicycles, etc.), foods, clothing, daily necessities, electronic devices (liquid crystal display devices, EL display devices, television devices, portable terminals, etc.).

    Further, a system can be constructed using the semiconductor device 1100 and the reader / writer 1112. The system includes a distribution / inventory management system, an authentication system, a distribution system, a production history system, a book management system, and the like. By using the semiconductor device 1100 of the present invention, a system that is fast in reading and writing and has high characteristics is constructed. it can.

    For example, a semiconductor device 1100 of the present invention is provided inside an identification card, and a reader / writer 1112 is provided at an entrance of a building or the like (see FIG. 28E). The reader / writer 1112 reads an authentication number in an identification card owned by each person, and supplies information related to the read authentication number to the computer 1122. The computer 1122 determines whether to allow entry or exit based on information supplied from the reader / writer 1112. As described above, by using the semiconductor device of the present invention, an entrance / exit management system with improved convenience can be provided.

    Note that this embodiment mode can be freely combined with Embodiment Modes 1 to 6 within a feasible range.

(Embodiment 8)
In this embodiment mode, an example in which a CPU (Central Processing Unit) is manufactured using the present invention is shown. Here, a CPU is manufactured using a transistor manufactured based on Embodiment Mode 5. In the present embodiment, the same components as those in the first to seventh embodiments are denoted by the same reference numerals, and detailed description thereof is omitted.

    First, based on the steps described in the fifth embodiment, a P-type transistor 820 and an N-type transistor 810 each having a Lov region are formed on a silicon substrate 900 as shown in FIG. P-type transistor 820 and N-type transistor 810 are separated by element isolation region 800. The element isolation region 800 is formed by a known isolation technique such as a LOCOS method (selective oxidation method) or an STI method (Shallow Trench Isolation), and an active layer is formed on the silicon substrate accordingly. Thereafter, a gate insulating film, a gate electrode, ion doping, and the like are performed as in the fifth embodiment.

    An insulating layer 901 is formed so as to cover the wiring 115 formed in Embodiment 5. The insulating layer 901 is formed as a single layer or a stacked layer using an inorganic material or an organic material. The insulating layer 901 is a thin film formed for the purpose of relaxing and planarizing unevenness caused by the transistor. Therefore, it is preferable to form with an organic material.

    Next, the insulating layer 901 is etched by photolithography to form contact holes that expose the wirings 115 functioning as a source electrode and a drain electrode. Subsequently, a conductive layer is formed so as to fill the contact hole, and the conductive layer is shaped to form conductive layers 902 and 903 that function as wirings or the like. The conductive layers 902 and 903 are an element selected from aluminum (Al), titanium (Ti), silver (Ag), and copper (Cu), or an alloy material or a compound material containing these elements as a main component, and is a single layer. Or it forms by lamination. For example, a three-layer structure in which an aluminum layer on the barrier layer and an aluminum layer are sandwiched between the barrier layers may be employed. The barrier layer corresponds to titanium, titanium nitride, molybdenum, molybdenum nitride, or the like.

    An element group including a plurality of N-type transistors 810 and a plurality of P-type transistors 820 and a plurality of conductive layers 902 and 903 functioning as wirings are collectively referred to as a thin film integrated circuit 904. Although not shown in this step, a protective layer may be formed by a known means so as to cover the thin film integrated circuit 904. The protective layer corresponds to a layer containing carbon such as DLC (Diamond Like Carbon), a layer containing silicon nitride, a layer containing silicon nitride oxide, or the like.

    A CPU can be manufactured by forming a plurality of thin film integrated circuits 904 formed as described above over the same substrate.

    However, the present invention is not limited to this transistor structure, and each structure of Embodiments 1 to 5 can be applied to each of the N-type transistor 810 and the P-type transistor 820 depending on the application. The thin film integrated circuit 904 may be formed using an SOI substrate or a TFT without being limited to a transistor using a silicon substrate.

    In order to make the completed CPU flexible or lighter, the silicon substrate 900 may be polished and thinned.

    Further, a specific configuration of the CPU of this embodiment will be described with reference to a block diagram.

    30 includes an arithmetic circuit (ALU) 3601, an arithmetic circuit control circuit unit (ALU Controller) 3602, an instruction analysis unit (Instruction Decoder) 3603, and an interrupt control unit (Interrupt Controller). 3604, Timing Controller 3605, Register 3606, Register Controller 3607, Bus Interface (Bus I / F) 3608, Rewriteable ROM 3609, ROM Interface (ROM I / F) 3620. The ROM 3609 and the ROM interface 3620 may be provided in separate chips. These various circuits constituting the CPU are configured by collecting a plurality of thin film integrated circuits 904.

    Needless to say, the CPU illustrated in FIG. 30 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application.

    An instruction input to the CPU via the bus interface 3608 is input to the instruction analysis unit 3603 and decoded, and then input to the arithmetic circuit control circuit unit 3602, the interrupt control unit 3604, the register control unit 3607, and the timing control unit 3605. Entered.

    The arithmetic circuit control circuit portion 3602, the interrupt control portion 3604, the register control portion 3607, and the timing control portion 3605 perform various controls based on the decoded instruction. Specifically, the arithmetic circuit control circuit portion 3602 generates a signal for controlling driving of the arithmetic circuit 3601. Further, the interrupt control unit 3604 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register control unit 3607 generates an address of the register 3606, and reads and writes the register 3606 according to the state of the CPU.

    In addition, the timing control unit 3605 generates a signal for controlling the driving timing of the arithmetic circuit 3601, the arithmetic circuit control circuit unit 3602, the instruction analysis unit 3603, the interrupt control unit 3604, and the register control unit 3607. For example, the timing control unit 3605 includes an internal clock generation unit that generates an internal clock signal CLK2 (3622) based on the reference clock signal CLK1 (3621), and supplies the clock signal CLK2 to the various circuits.

    FIG. 31 shows the form of a packaged CPU. A plurality of thin film integrated circuits 904 are provided in the transistor array 3801.

    In FIG. 31A, a transistor array 3801 having a CPU function formed over a substrate 3800 and electrodes (source and drain electrodes provided on the surface of the CPU, or an insulating film formed over them) are provided. The CPU is packaged in a face-down state with 3802 on the lower side. Further, a wiring board provided with wiring 3803 formed of copper or an alloy thereof, for example, a printed board 3807 is prepared. A connection terminal (pin) 3804 is provided on the printed circuit board 3807. Then, the electrode 3802 and the wiring 3803 are connected through an anisotropic conductive film 3808 and the like. Thereafter, the substrate 3800 is covered from above with a resin 3805 such as an epoxy resin to complete a packaged CPU. Further, the outer periphery may be surrounded by plastic or the like while the CPU is kept hollow without being covered with resin.

    In FIG. 31B, unlike FIG. 31A, the CPU is packaged in a face-up state in which the electrode 3802 provided on the surface of the CPU is on the upper side. Then, the substrate 3800 is fixed over the printed circuit board 3807, and the electrode 3802 and the wiring 3803 are connected by the wire 3818. Such connection by a wire is called wire bonding. Then, the electrode 3802 and the bump 3814 connected to the wiring 3803 are electrically connected. Thereafter, the CPU is surrounded by plastic 3815 or the like with the periphery of the CPU kept hollow, and a packaged CPU is completed.

    FIG. 31C illustrates an example in which a transistor array 3801 having a CPU function is fixed over a flexible substrate, for example, an FPC (Flexible Printed Circuit) 3817. The CPU is packaged with the transistor array 3801 formed on the substrate 3800 having the CPU function in a face-down state in which the electrode 3802 provided on the CPU surface is on the lower side. A flexible FPC 3817 is provided with a wiring 3803 formed of copper or an alloy thereof. Then, the electrode 3802 and the wiring 3803 are connected through an anisotropic conductive film 3808. Thereafter, a resin 3805 such as an epoxy resin is formed so as to cover the substrate 3800, and a packaged CPU is completed.

    The CPU packaged in this way is protected from the outside and becomes easier to carry. A CPU can be mounted at a desired location.

    A CPU which is an example of a semiconductor device of the present invention can manufacture a CPU with high arithmetic processing and high characteristics.

    This embodiment mode can be freely combined with Embodiment Modes 1 to 7 as long as practicable.

Sectional drawing which shows the semiconductor device of this invention. Sectional drawing which shows element structure assumed by analysis, and table | surface of each value employ | adopted by analysis. (Embodiment 1) TEM photograph of silicide layer cross section. (Embodiment 1) Evaluation results of N-type transistors. (Embodiment 1) Evaluation results of N-type transistors. (Embodiment 1) Evaluation results of N-type transistors. (Embodiment 1) Evaluation results of P-type transistors. (Embodiment 1) Evaluation results of P-type transistors. (Embodiment 1) Evaluation results of P-type transistors. (Embodiment 1) Evaluation results of N-type transistors. (Embodiment 1) Evaluation results of N-type transistors. (Embodiment 1) Evaluation results of N-type transistors. (Embodiment 1) Evaluation results of P-type transistors. (Embodiment 1) Evaluation results of P-type transistors. (Embodiment 1) Evaluation results of P-type transistors. (Embodiment 1) 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. (Embodiment 2) 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. (Embodiment 2) 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. (Embodiment 2) 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. (Embodiment 3) 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. (Embodiment 3) 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. (Embodiment 4) 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. (Embodiment 4) 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. (Embodiment 5) 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. (Embodiment 6) 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. (Embodiment 6) 1 is a perspective view of a semiconductor device of the present invention. (Embodiment 6) FIG. 11 illustrates a semiconductor device of the present invention. (Embodiment 7) 4A and 4B illustrate how to use a semiconductor device of the invention. (Embodiment 7) 4A and 4B illustrate a method for manufacturing a semiconductor device of the present invention. (Embodiment 8) 1 is a block diagram of a semiconductor device of the present invention. (Embodiment 8) FIG. 11 illustrates a semiconductor device of the present invention. (Embodiment 8)

Explanation of symbols

11 region 12 impurity region 13 silicide layer 14 gate insulating film 15 gate electrode 16 wiring 13a first region 13b second region

Claims (9)

A crystalline silicon film having a channel formation region, an impurity region and a silicide layer, and in contact with the insulating film;
A gate insulating film on the crystalline silicon film;
A gate electrode on the gate insulating film;
A wiring electrically connected to the impurity region through the silicide layer;
The silicide layer has a first region whose film thickness increases from an end point on the surface of the silicide layer on the channel formation region side, and a second region whose film thickness is equal to the film thickness of the crystalline silicon film. And
The first region and the second region are separated by a straight line perpendicular to a horizontal line, and the first point is defined as a point where the perpendicular straight line intersects the bottom surface of the crystalline silicon film. A straight line passing through the end points forms an angle θ (0 ° <θ <45 °) with respect to a horizontal line. A channel formation region, an impurity region and a silicide layer, and a silicon film on the substrate;
A gate insulating film on the silicon film;
A gate electrode on the gate insulating film;
A wiring electrically connected to the impurity region through the silicide layer;
The silicide layer has a first region whose film thickness is increased from an end point on the surface of the silicide layer on the channel formation region side, and a second region whose film thickness is equal to the film thickness of the silicon film,
The first region and the second region are separated by a straight line perpendicular to a horizontal line, and when the first point is a point where the perpendicular straight line intersects the bottom surface of the silicon film, the first point and the second region A semiconductor device, wherein a straight line passing through an end point forms an angle θ (0 ° <θ <45 °) with respect to a horizontal line. Oite to claim 1, wherein a said crystalline silicon film is a single crystal silicon. In any one of claims 1 to 3, a semiconductor device and an end portion of the gate insulating film and the end point of the silicide layer corresponds. In any one of claims 1 to 4, wherein a has a side wall in contact with the gate insulating film and the gate electrode. In any one of claims 1 to 5, the semiconductor device characterized in that it comprises an antenna. In the claims 1 to any one of claims 6, wherein a has a DRAM. In the claims 1 to any one of claims 6, a semiconductor device wherein the semiconductor device is a DRAM or CPU. Forming a gate insulating film on the silicon film on the substrate;
Forming a gate electrode on the gate insulating film;
By selectively removing the gate insulating film, the silicon film is selectively exposed,
Forming a metal film in contact with the exposed silicon film surface;
By performing heat treatment, a silicide layer is formed on a part of the silicon film,
Forming a wiring connected to the silicide layer;
The silicide layer includes a first region having a thickness increasing from an end point on the surface of the silicide layer coinciding with an end portion of the gate insulating film, and a second region having a thickness equal to the thickness of the silicon film, Have
The first region and the second region are separated by a straight line perpendicular to a horizontal line, and when the first point is a point where the perpendicular straight line intersects the bottom surface of the silicon film, the first point and the second region The straight line passing through the end point makes an angle θ (0 ° <θ <45 °) with respect to the horizontal line,
The metal film is formed to have the smallest thickness on the side surface of the gate insulating film, and the heat treatment is performed to form the first region and the second region. Method.