JP5117419B2 - Parallel transmission module - Google Patents

Description

  The present invention relates to a parallel transmission module that transmits multi-channel signals.

2. Description of the Related Art Conventionally, a parallel optical transmission device that transmits multi-channel signals is known (see, for example, Patent Document 1). The parallel optical transmission device includes an optical transmission module with an internal electrical wiring, an optical reception module with an electrical wiring, and a tape fiber.
Further, a semiconductor light receiving module in which a semiconductor light receiving element, a capacitor, and a preamplifier IC are mounted on a substrate is known (for example, see Patent Document 2). This capacitor is a chip capacitor, and is connected between the power source and the ground (GND) so as to cut noise of the power source supplied to the semiconductor light receiving element and the preamplifier IC.
Patent Document 3 describes that in a signal transmission system such as a device for large-capacity optical communication, a DC blocking capacitor for cutting a DC component is provided on the input side. Patent Document 3 discloses a technique related to a multilayer chip capacitor used as such a capacitor.

Japanese Patent Laid-Open No. 11-41177 JP 2008-294895 A JP 2000-243657 A

  By the way, it is desirable to dispose a noise removing capacitor as disclosed in Patent Document 2 and Patent Document 3 as close as possible to the IC on the substrate. However, in parallel transmission modules that transmit multi-channel signals, if the number of channels is increased to increase the transmission speed, signal lines formed on the substrate surface as the number of channels increases, for example, differential wiring that transmits signals (high frequency) Signal lines) and control lines for controlling the IC increase, it becomes difficult to dispose the capacitor close to the IC, thereby causing a problem that noise cannot be sufficiently reduced by the capacitor. This problem becomes prominent when the number of channels is increased to achieve multi-channel.

  In the parallel transmission module, a capacitor for suppressing noise is connected between a power line and a ground line formed on the substrate, and a current flows from the power line to the IC, and further flows from the IC to the ground line. In such a parallel transmission module, when the amount of current flowing through the power supply line and the ground line changes, an induced electromotive force is generated to generate a potential, thereby causing an unnecessary current to flow through each line. Such unnecessary current causes electromagnetic induction and noise is generated. Such noise is expected to increase in frequency as the operation speed of the IC increases, and to reduce the noise over a wide frequency band. In addition, such noise is desired to suppress the fluctuation of the power supply voltage supplied to the IC as much as possible as the operating voltage of the IC is lowered.

  The present invention has been made in view of such a conventional background, and provides a parallel transmission module in which a capacitor for suppressing noise can be disposed near an electronic element and noise can be effectively suppressed. The purpose is to do.

  In order to solve the above problems, a first aspect of the present invention is a parallel transmission module for transmitting a multi-channel signal, wherein a module substrate in which conductor layers and dielectric layers are alternately stacked, and the module An electronic element and a chip capacitor mounted on the uppermost conductor layer of the board, and the uppermost conductor layer of the module board includes a plurality of power supply terminals electrically connected to the electronic element, and A ground terminal electrically connected to the electronic element and a first ground pattern are formed, and any one of the plurality of conductor layers below the uppermost conductor layer includes the plurality of conductor layers. A power line electrically connected to the power terminal via the via conductor, and a ground line electrically connected to the first ground pattern and the via conductor in a position close to the power line. The first ground pattern and a second ground pattern electrically connected via a via conductor are formed, and the module substrate has a depth reaching the conductor layer where the power line and the ground line are located. The chip capacitor is disposed in the hole so as to be connected between the power line and the ground line.

  According to this configuration, a multilayer substrate is used as a module substrate, a capacitor is disposed in a hole provided in the substrate, and the power line and the ground line are formed on a conductor layer different from the uppermost conductor layer. Connected between. For this reason, a power supply line, a ground line, etc. can be divided into a plurality of conductor layers. As a result, even when multi-channeling is intended, a space for placing the capacitor is secured in the uppermost conductor layer, and the capacitor can be placed near the electronic element, thereby suppressing noise.

  In addition, a plurality of power supply terminals electrically connected to the electronic elements, a ground terminal, and a first ground pattern are formed on the uppermost conductor layer of the module substrate. At the same time, a power line electrically connected to any one of the conductor layers below the uppermost conductor layer via a plurality of electrode terminals and via conductors in the uppermost conductor layer, and the power line And a second ground pattern electrically connected to the first ground pattern via a via conductor. As a result, compared to the case where the wiring pattern and all the terminals are formed on the surface of the module substrate, the area of the power supply line can be increased to make the power supply line thicker, and the area of the entire ground line is also increased. The ground line can be strengthened. For this reason, potential fluctuations on the power supply line and the ground line can be made smaller than when the wiring pattern and all terminals are formed on the surface of the module substrate, and noise caused by these potential fluctuations is suppressed. be able to.

  Further, the chip capacitors as disclosed in Patent Document 2 and Patent Document 3 have a large thickness (dimension in the height direction) of about 300 μm. Since it is arranged on the substrate surface, there is a problem that the protrusion amount of the chip capacitor from the substrate surface becomes large and the module becomes large. On the other hand, according to this aspect of the present invention, since the capacitor is disposed in the hole provided in the module substrate, even when a chip capacitor such as a multilayer chip capacitor is used as the capacitor, the substrate of the chip capacitor The amount of protrusion from the surface is reduced, and the module can be reduced in size.

  An optical module of a parallel optical transmission device according to another aspect of the present invention is characterized in that any one of the plurality of conductor layers below the uppermost conductor layer is a second conductor layer. To do.

  In the optical module of the parallel optical transmission apparatus according to another aspect of the present invention, the third conductor layer of the module substrate is electrically connected to the ground line, the ground pattern, and the via conductor in the second conductor layer. Ground planes and a plurality of power supply terminals are formed, and the ground plane in the third conductor layer is connected to the ground lines and ground patterns in the second conductor layer and via conductors. The plurality of power supply terminals in the third conductor layer are connected to the power supply line in the second conductor layer and the power supply terminal and via conductor in the uppermost conductor layer. It is electrically connected via a via, and can be connected to an external power source via a via conductor.

  An optical module of a parallel optical transmission apparatus according to another aspect of the present invention is characterized in that the capacitor is a multilayer chip capacitor.

  According to the present invention, a capacitor for suppressing noise can be disposed near an electronic element, noise can be effectively suppressed, and a parallel transmission module can be realized. Further, the module can be miniaturized.

1 is an exploded perspective view showing a schematic configuration of a parallel optical transmission device in which an optical module according to an embodiment of the present invention is used. The figure which shows a part of optical module which concerns on one Embodiment of this invention, and is a perspective view which shows the state in which driver IC was mounted in the module board | substrate. The perspective view which shows the state in which the driver IC and the VCSEL array were mounted on the module substrate. Sectional drawing which shows the module substrate which is a multilayer substrate. The top view which shows the dielectric material layer and conductor layer of the uppermost layer of a module board. The top view which shows the 2nd dielectric material layer and conductor layer of a module board. The top view which shows the 3rd dielectric material layer and conductor layer of a module board | substrate. The top view which shows transparently the state which accumulated the uppermost conductor layer, the 2nd conductor layer, and the 3rd conductor layer. Sectional drawing along the XX line of FIG. The graph which shows the simulation result about the frequency dependence of the voltage amplitude on the power supply line in the optical module which concerns on one Embodiment. The graph which shows the simulation result about the frequency dependence of the voltage amplitude on the ground line in the optical module which concerns on one Embodiment. The graph which shows the simulation result about the frequency dependence of the voltage amplitude on the power supply line in the optical module of a comparative example. The graph which shows the simulation result about the frequency dependence of the voltage amplitude on the ground line in the optical module of a comparative example.

Next, an embodiment of the present invention will be described with reference to the drawings.
A schematic configuration of an optical module as a parallel transmission module according to an embodiment of the present invention and a parallel optical transmission apparatus using the optical module will be described with reference to FIGS.

(One embodiment)
As shown in FIG. 1, the parallel optical transmission device 1 includes an electric board 10, an electric pluggable socket 20, an optical module 30, a pressing plate 40, an optical connector 50, and an optical component 60. For example, the parallel optical transmission device 1 converts an electrical signal into an optical signal, and the optical signal is transmitted in parallel through a plurality of channels, for example, 12 channels (12 ch) through 12 optical fibers (10 Gbps / 1 ch × This is a parallel optical transmission device for transmission (12-channel transmission).

  Therefore, as shown in FIGS. 2 and 3, the optical module 30 of the parallel optical transmission device 1 includes a VCSEL array (optical element array) composed of a plurality of (in this example, 12) surface emitting semiconductor laser elements (VCSEL). ) 31, a driver IC (electronic element) 32 that drives each VCSEL of the VCSEL array 31, and a module substrate 33 on which the VCSEL array 31 and the driver IC 32 are mounted. A noise removing capacitor 35 is mounted on the module substrate 33.

  As shown in FIGS. 2 and 3, the VCSEL array 31 is disposed in a hole 91 described later formed in the module substrate 33. The driver IC 32 is mounted on the module substrate 33 by flip chip bonding (FCB). The module substrate 33 includes a plurality of sets (12 sets, 24 sets in this example) of high-frequency signal lines 36 which are transmission lines that electrically connect the VCSEL array 31 and the driver IC 32 to each other. Is formed. These high-frequency signal lines 36 and each VCSEL of the VCSEL array 31 are electrically connected by wires 37 (see FIG. 3). Thus, the VCSEL array 31 and the driver IC 32 are electrically connected by a plurality of sets (12ch) of high-frequency signal lines 36 and wires 37, and the high-frequency signal lines 36 and wires 37 of each set (ch) are connected. A drive signal (differential signal) is supplied from the driver IC 32 to each VCSEL of the VCSEL array 31.

  A plurality of electrical terminals and a wiring pattern (not shown) connected to each electrical terminal are formed on the front and back surfaces of the electrical substrate 10. The wiring pattern is a signal line for supplying a differential signal from the outside to the driver IC 32. In order to control the driver IC 32, a plurality of sets (12 sets) of high-frequency signal lines including two signal lines as one set. A plurality of control signal lines and a plurality of monitor signal lines are formed. In addition, as a plurality of electrical terminals, terminals connected to 12 sets of high-frequency signal lines, respectively, 12 sets (12ch) of signal input / output terminals, each having two terminals, and connected to a plurality of control signal lines A plurality of terminals and a plurality of terminals connected to the plurality of monitor signal lines are formed.

  The optical module 30 is mounted in the module receiving recess 21 (see FIG. 1) of the electric pluggable socket 20 that is positioned on the electric substrate 10 and fixed with screws. When the optical module 30 is mounted in the module housing recess 21 and the plate 40 pressed from above the module cover 34 is fixed to the electrical pluggable socket 20 with screws, each electrical terminal of the optical module 30 and each electrical terminal of the electrical substrate 10 are Are electrically connected via a plurality of connection terminal portions 22 of the electric pluggable socket 20. The plurality of connection terminal portions 22 are spring-like terminals configured such that when a predetermined pressing force is applied, a coil-like spring portion (not shown) contracts to electrically connect the upper contact pin and the lower contact pin. It is.

  As shown in FIG. 1, the optical connector 50 includes a tape fiber 51 in which a plurality (12 in this example) of optical fibers are arranged in a row, and a connector (ferrule) 52 that holds the plurality of optical fibers. And an optical component 60 that bends light (optical signal) emitted from each VCSEL of the VCSEL array 31 in a vertical direction by 90 degrees and optically couples the light to each end face of a plurality of optical fibers. The connector part 52 is a multi-core ferrule connector (MT connector). The tape fiber 51 is connected to another optical connector 53 and transmits optical signals in parallel with the optical module 30.

Next, the optical module 30 according to an embodiment of the present invention will be described in more detail.
As shown in FIGS. 2 to 4, the optical module 30 is mounted on a module substrate 33, which is a multilayer substrate in which conductor layers and dielectric layers are alternately stacked, and on the uppermost conductor layer m1 of the module substrate 33, respectively. The driver IC 32 and the VCSEL array 31 thus formed, and two capacitors 35 disposed in the hole 91 are provided. These capacitors 35 are multilayer chip capacitors that are small in size, have a large capacity, and are easy to mount.

  As shown in FIGS. 2 and 5, a plurality of power supply terminals (VDD terminals) 71 and 72 electrically connected to the driver IC 32 and the driver IC 32 are electrically connected to the uppermost conductor layer m1 of the module substrate 33. A ground terminal (GVD terminal) 80 and a ground pattern (first ground pattern) 81 are formed. The plurality of power supply terminals 71 are FCB pads that are electrically connected to a plurality of electrodes on the driver IC 32 side via Au bumps (not shown) when the driver IC 32 is mounted by flip chip bonding (FCB).

  As shown in FIG. 5, the uppermost conductor layer m1 includes a plurality of sets (12ch) of high frequency signal lines 36 shown in FIG. 2 and a plurality of sets (12ch) for supplying a differential signal to the driver IC 32. An uppermost line 38 a of the high-frequency signal line 38 and uppermost lines 39 a of a plurality of control signal lines 39 for supplying a control signal to the driver IC 32 are formed. The uppermost line 38a of each high-frequency signal line 38 is electrically connected to a plurality of signal input / output terminals provided on the driver IC 32 side when the driver IC 32 is FCB-mounted. Similarly, the uppermost line 39a of each control signal line 39 is also electrically connected to a plurality of control signal input terminals provided on the driver IC 32 side. Further, as shown in FIG. 5, two VT terminals 101 and 102 are formed in the uppermost conductor layer m1.

In FIG. 5, reference numerals “41” and “42” denote mounting positions for positioning the driver IC 32 when the driver IC 32 is mounted on the uppermost conductor layer m1 of the module substrate 33 by flip chip bonding. It is a marker. Reference numerals “43” and “44” are substrate recognition markers for positioning the VCSEL 32.
As shown in FIG. 5, the first ground pattern 81 extends in one direction (upward in FIG. 5) from the central portion of the uppermost dielectric layer d1 to the peripheral portion of the dielectric layer d1. Further, it is formed on the entire peripheral portion so as to surround a formation region of the plurality of high-frequency signal lines 36, a formation region of the plurality of uppermost lines 38a, and a formation region of the plurality of uppermost lines 39a.

Further, as shown in FIG. 5, the uppermost dielectric layer d1 is formed with the hole 91 in which the two capacitors 35 and the VCSEL array 31 are arranged, and holes 92 and 93. Capacitors can be arranged in the holes 92 and 93 as well.
The hole 91 has a region 91a for arranging the VCSEL array 31 and regions 91b and 91c for arranging the capacitors 35, so that the plurality of VCSELs in the VCSEL array 31 are arranged in the up-and-down direction (vertical direction in FIG. 5). It has become a long variant.

  As shown in FIG. 6, the second conductor layer m2 below the uppermost conductor layer m1 is electrically connected to the plurality of power supply terminals 71 and 72 in the conductor layer m1 via via conductors. A power supply line 73, a ground line 82 formed near the power supply line 73, a ground pattern (second notation) electrically connected via a ground pattern 81 in the conductor layer m1 and a via conductor (not shown). , Ground patterns) 83 and 84 are formed. Further, as shown in FIG. 6, the second conductor layer m2 has two VT patterns 103 electrically connected to the VT terminals 101 and 102 in the conductor layer m1 via via conductors (not shown). , 104 are formed.

  As shown in FIG. 6, the power supply line 73 is formed in a ring shape outside these regions so as to surround the region where the driver IC 32 is mounted and the region where the VCSEL array 31 and the two capacitors 35 are mounted. Has been. The ground pattern 83 is located below the region of the conductor layer m1 where the driver IC 32 is mounted, and is electrically connected to the ground pattern 81 in the conductor layer m1 via via conductors (not shown).

  The power supply line 73, the ground line 82, the ground pattern 83, and the VT patterns 103 and 104 are formed in the left half region on the second dielectric layer d2. The ground pattern 84 is formed over the entire right half area of the dielectric layer d2 using the space on the right half, and the ground pattern 81 and the via conductor (not shown) in the conductor layer m1. ) Through an electrical connection.

  As shown in FIG. 7, a ground plane (GND plane) 85, a plurality of power supply terminals 74, and two VT terminals 105 and 106 are formed on the third conductor layer m <b> 3 of the module substrate 33. The ground plane 85 is electrically connected to the ground line 82 and the ground patterns 83 and 84 in the conductor layer m2 via via conductors (not shown). The plurality of power supply terminals 74 are electrically connected to a power supply line 73 in the conductor layer m2 and power supply terminals (VDD terminals) 71 and 72 in the conductor layer m1 via via conductors (not shown). For example, a power supply voltage (Vcc) of 3.3 V is supplied from a power supply outside the optical module to the plurality of power supply terminals 74 via via conductors (not shown). The VT terminals 105 and 106 are electrically connected to the VT patterns 103 and 104 in the conductor layer m2 and the VT terminals 101 and 102 in the conductor layer m1 via via conductors (not shown).

  The plurality of power supply terminals 74 are formed in a line in a region overlapping the power supply line 73 in the conductor layer m2 around the third dielectric layer d3. The VT terminals 105 and 106 are formed on both sides of the plurality of power supply terminals 74. The ground plane 85 is formed over the entire area excluding the areas of the VT terminals 105 and 106 and the plurality of power supply terminals 74 on the third dielectric layer d3.

  As shown in FIGS. 8 and 9, the first dielectric layer d1 and the first conductor layer m1 of the module substrate 33 have a depth reaching the conductor layer m2 where the power line 73 and the ground line 82 exist. The hole 91 is formed. As shown in FIG. 9, the capacitors 35 and 35 are arranged in the hole 91 so as to be connected between the power supply line 73 and the ground line 82.

  In the optical module 30 having the above configuration, a power supply voltage (Vcc) of, for example, 3.3 V is supplied to the driver IC 32 from an external power supply. At this time, the IC drive current is supplied from the power source to the via conductor in the module substrate 33, the plurality of power terminals 74 in the conductor layer m3, the via conductor, the power line 73 in the conductor layer m2, and the plurality of power terminals in the conductor layer m1. 71, 72 and the driver IC 32. This current further flows from the driver IC 32 to the ground terminal 80 in the conductor layer m1, the via conductor, the ground line 82 and the ground patterns 83 and 84 in the conductor layer m2, the via conductor, and the ground plane 85 in the conductor layer m3. To the power supply.

According to an embodiment having such a configuration, the following operational effects are obtained.
A multilayer substrate is used as the module substrate 33, a noise removing capacitor 35 is disposed in the hole 91 provided in the module substrate 33, and the capacitor 35 is separated from the uppermost conductor layer m1 (second layer). Between the power line 73 and the ground line 82 formed in the conductor layer m2). For this reason, the power line, the ground line, the ground pattern, the high-frequency signal line and the control line that increase according to the number of channels can be divided into a plurality of conductor layers. As a result, even in the case of multi-channeling, a space for disposing the capacitor 35 is secured in the uppermost conductor layer m1, and the capacitor 35 can be disposed near the driver IC 32, and noise can be suppressed. .

  A plurality of power supply terminals 71 and 72 electrically connected to the driver IC 32, a ground terminal 80, and a ground pattern ground pattern 81 are formed on the uppermost conductor layer m1 of the module substrate 33. At the same time, a power line 73 electrically connected to the second conductor layer m2 via a via conductor with a plurality of electrode terminals 71 and 72 in the uppermost conductor layer m1, and a position close to the power line , And ground patterns 83 and 84 electrically connected to the ground pattern 81 via via conductors are formed. Thereby, compared with the case where a wiring pattern and all the terminals are formed on the surface of the module substrate 33, the area of the power supply line can be increased and the power supply line can be made thicker, and the area of the entire ground line can also be increased. The ground line can be strengthened by increasing the size. For this reason, when power is supplied to the driver IC 32, current flows from the power supply line to the driver IC 32 and from the driver IC 32 to the ground line as described above. However, the potential fluctuation on the power supply line and the potential fluctuation on the ground line are reduced. The wiring pattern and all the terminals can be made smaller than the case where they are formed on the surface of the module substrate, and noise caused by these potential fluctuations can be suppressed.

The graph of FIG. 10 shows a simulation result on the frequency dependence of the voltage amplitude on the power supply line in the optical module 30 according to the embodiment. The graph of FIG. 11 shows a simulation result on the frequency dependence of the voltage amplitude on the ground line in the optical module 30.
The test conditions here are as follows.
・ Power supply voltage Vcc: constant voltage of 3.3 (V) ・ AC current: 600 + 3 × sin (ωt) (mA)
・ Frequency band: DC, 0.01-10GHz

The graph of FIG. 12 shows the simulation result of the frequency dependence of the voltage amplitude on the power supply line in the optical module of the comparative example. In this comparative example, a wiring pattern such as a power supply line and a ground line and all terminals are formed on the surface of the module board, and a capacitor for noise removal is arranged on the surface of the module board, between the power supply line and the ground line. It is a connected optical module. The graph of FIG. 13 shows a simulation result on the frequency dependence of the voltage amplitude on the ground line in the optical module of the comparative example.
The test conditions here are as follows.
・ Power supply voltage Vcc: constant voltage of 3.3 (V) ・ AC current: 600 + 3 × sin (ωt) (mA)
・ Frequency band: DC, 0.01-10GHz

From the graph of FIG. 12, in the comparative example, voltage fluctuation occurs in the band of 3 GHz to 10 GHz on the power supply line, and the voltage amplitude is large. Further, from the graph of FIG. 13, voltage fluctuation occurs in the band of 1 GHz to 6 GHz on the ground line, and the voltage amplitude is large.
On the other hand, in the above embodiment, it can be seen from FIG. 10 that the voltage fluctuation occurs only in a limited narrow band on the power supply line, and the voltage amplitude is also small. In addition, it can be seen from FIG. 11 that on the ground pattern, almost no voltage fluctuation is observed in the entire band of 1 GHz to 10 GHz.
Therefore, noise can be reduced over a wide frequency band from the graphs of FIGS. 10 and 11. Thereby, the fluctuation | variation of the power supply voltage supplied to driver IC32 can fully be suppressed.

  The ground pattern 84 in the third conductor layer m3 is formed over the entire right half region of the dielectric layer d2 using the empty space in the right half, and the ground pattern in the conductor layer m1 81 and a via conductor (not shown) are electrically connected. For this reason, the area of the whole ground line (including the ground line and the ground pattern) can be further increased to further strengthen the ground line. Thereby, fluctuations in the power supply voltage supplied to the driver IC 32 can be further suppressed, and noise can be further suppressed.

In addition, this invention can also be changed and embodied as follows.
In the above embodiment, a transmission optical module having a function of converting an electrical signal into an optical signal has been described. However, the present invention can also be applied to a reception optical module having a function of converting an optical signal into an electrical signal. It is. In this configuration, a TIA (Transimpedance Amplifier) function that uses a photodiode array having a plurality of photodiodes as a plurality of optical elements and converts the output current of each photodiode into a voltage and amplifies it instead of the driver IC 33 as an electronic element. An amplification IC provided with

  In each of the above embodiments, the case where each of the plurality of transmission lines is a differential transmission line including two signal lines and transmits a differential signal from the driver IC to the VCSEL array has been described. It is not limited to a simple optical module. That is, the present invention is also applicable to an optical module in which a plurality of transmission lines are each composed of one signal line for each channel and a single-ended signal is transmitted from the driver IC to the VCSEL array.

  In the above embodiment, the power line 73, the ground line 82, and the ground patterns 83 and 84 are formed in the second conductor layer m2. However, the power line 73, the ground line 82, and the ground pattern are formed. The wave of the present invention can also be applied to an optical module in which 83 and 84 are formed on any one of a plurality of conductor layers below the uppermost conductor layer m1 (excluding the second conductor layer m2). is there.

30: Optical module 35: Capacitor 31: VCSEL array (optical element array)
32: Driver IC (electronic element)
33: Module substrate,
d1 to d7: dielectric layers m1 to m8: conductor layer m1: uppermost conductor layers 71 and 72: power supply terminal (VDD terminal)
74: Power terminal 74
80: Ground terminal (GVD terminal)
81: Ground pattern (first ground pattern)
83, 84: Ground pattern 85: Ground plane (GND plane)
91: Hole

Claims (4)

A parallel transmission module for transmitting multi-channel signals,
A module substrate in which conductor layers and dielectric layers are alternately laminated, and an electronic element and a chip capacitor mounted on the uppermost conductor layer of the module substrate,
A plurality of power supply terminals electrically connected to the electronic element, a ground terminal electrically connected to the electronic element, and a first ground pattern are formed on the uppermost conductor layer of the module substrate. And
A power supply line electrically connected to the plurality of power supply terminals and via conductors in one of the plurality of conductive layers below the uppermost conductive layer, and close to the power supply line A ground line electrically connected to the first ground pattern via a via conductor, and a second ground pattern electrically connected to the first ground pattern via a via conductor. Formed, and
The module board has a hole having a depth reaching the conductor layer where the power line and the ground line are provided, and the chip capacitor is connected between the power line and the ground line. A parallel transmission module arranged in a hole.   The parallel transmission module according to claim 1, wherein any one of the plurality of conductor layers below the uppermost conductor layer is a second conductor layer. A ground plane electrically connected to the ground line and ground pattern in the second conductor layer via via conductors and a plurality of power supply terminals are formed on the third conductor layer of the module substrate. And
The ground plane in the third conductor layer is electrically connected to the ground line and ground pattern in the second conductor layer via via conductors,
The plurality of power supply terminals in the third conductor layer are electrically connected to the power supply line in the second conductor layer and the power supply terminal in the uppermost conductor layer via via conductors. The parallel transmission module according to claim 2, wherein the parallel transmission module can be connected to an external power source via a via conductor.   The parallel transmission module according to claim 1, wherein the capacitor is a multilayer chip capacitor.

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