JP5115922B2 - Communication device for data-driven processing device having tree-type shunt and confluence channel and packet transfer method for data-driven processing device - Google Patents

Description

  The present invention relates to a data-driven processing device communication channel device and a data-driven processing device packet transfer system that are used in a data-driven semiconductor device and have a tree-type branching channel and a combined channel. Communication device for data-driven processing device and packet transfer method for data-driven processing device having a tree-type shunt path and a combined flow path in which a plurality of functional elements are a memory row array, a register array, a processing element array or a queue array About.

  In a data driven semiconductor device, local synchronization control is performed in a self-supporting and distributed manner by each of a plurality of elements. Therefore, the parallelism of processing is higher than that of a synchronous semiconductor device that centrally controls each element in synchronization with a system clock. It can be easily increased and power consumption can be reduced.

  However, the conventional data driven semiconductor device uses a normal memory or cache memory in which address input is not pipelined. Therefore, if random access is performed by a data driven processing device having a high degree of parallelism, the delay for each access is accumulated. Thus, the throughput (the number of data that can be processed per unit time) cannot be sufficiently improved.

  In order to solve this problem, in Patent Document 1 below, the system throughput is improved by using a common shared memory, first to fourth memories, and a plurality of cache memories.

In Patent Document 2 below, a normal cache memory is provided for each normal memory, and when the last word of a page is read by the cache memory, data of a predetermined page ahead is prefetched to improve the system throughput. ing.
JP 5-108852 JP2003-114825A

  However, even if any of the methods disclosed in any of the above patent documents is used, power consumption is large because a plurality of normal memories are used and a normal cache memory is used. In particular, when the degree of parallelism of processing increases, this problem becomes remarkable, and it is not suitable for mobile devices that require a long battery life.

  In addition, normal cache memory cannot perform parallel processing, and when discontinuous data is handled as in the case of automata, the number of misses increases and the waiting time increases, so each of the multiple elements is independent. It is incompatible with a multi-parallel data driven processing device that performs distributed processing, and the throughput cannot be sufficiently improved.

  Such a problem also occurs when a synchronous processor is used in a data driven processing apparatus. This problem can be solved by making the memory or the like a data driven type configuration capable of executing distributed processing with low power consumption.

  In view of such problems, the object of the present invention is to make it possible to easily configure a data driven semiconductor device that includes a functional element array such as a memory element array or a processing element array and that performs distributed pipeline processing. Another object of the present invention is to provide a data-driven processing device communication path device and a data-driven processing device packet transfer system having a tree-type branching channel and a combined channel.

In the first aspect of the present invention, the upstream channel that selectively transfers the packet supplied to the ingress node to one of a plurality of functional elements arranged according to the destination address of the packet is selected. In a data-driven processing device communication path device having a downstream path for transferring a packet generated by a functional element to an egress node,
The upstream flow path selectively diverts the first packet supplied to the ingress node sequentially to a downstream node according to a destination address in the packet, and selectively selects one of the plurality of functional elements. It is a tree-shaped branch channel to be transferred,
The downstream flow path is a tree-shaped combined flow path that selectively combines the second packet corresponding to the first packet downstream from the selected one of the plurality of functional elements to reach the egress node. And
Each node of the tree-shaped branch flow path and the tree-shaped combined flow path constitutes a pipeline stage, and the number of pipeline stages of the tree-shaped branched flow path and the tree-shaped combined flow path is 3 or more, respectively.

  In a second aspect of the present invention, in the first aspect, in the tree-shaped branch flow path, the paths of packets having destination addresses complementary to each other are logically symmetric with respect to an axis in the flow path direction. The tree-shaped branch channel is formed.

  According to a third aspect of the present invention, in the second aspect, for any destination address, the packet path in the tree-shaped branch path and the packet path in the tree-shaped combined path are perpendicular to the flow path. The tree-shaped branch channel and the tree-shaped combined channel are formed so as to be logically symmetric with respect to the direction axis.

In a fourth aspect of the data-driven processing device communication path device according to the present invention, in the first aspect, the packet has a system value,
The tree-shaped branch channel has the different entry nodes for each system, selectively joins packets from a plurality of systems at intermediate nodes, and each node of the output stage is common to each system,
In the tree-shaped joint channel, each node of the input stage is common to each system, and packets from a plurality of systems are selectively branched based on the system value at an intermediate node, and have different exit nodes for each system. .

  According to a fifth aspect of the present invention, in the fourth aspect, in the tree-shaped branch flow path, paths of packets having destination addresses complementary to each other are logically symmetric with respect to an axis in the flow path direction. The tree-shaped branch channel is formed.

  According to a sixth aspect of the present invention, in the fourth or fifth aspect, for any destination address, the path of the packet in the tree-shaped branch path and the path of the packet in the tree-shaped combined path are: The tree-shaped branch channel and the tree-shaped channel are formed so as to be logically symmetric with respect to an axis in a perpendicular direction.

  According to a seventh aspect of the communication path device for a data driven processor according to the present invention, in the sixth aspect, the packet on the tree-shaped branch channel includes a packet side branch stage identifier, and each node of the tree-shaped branch channel is fixed. It is determined whether or not the packet side branch stage identifier corresponds to the node side branch stage identifier.

  According to an eighth aspect of the data-driven processing device communication path device of the present invention, in the seventh aspect, a branch stage identifier generation node is further provided upstream of each inlet node of the tree-shaped branch channel, and the branch stage identifier generation is performed. The node generates the value of the packet side branch stage identifier based on the value of each destination address in the plurality of packets associated with each other.

  According to a ninth aspect of the communication path device for a data driven processor according to the present invention, in the sixth aspect, the packet on the tree-shaped merge channel includes a packet side merge stage identifier, and each node of the tree-shaped merge channel is fixed. It is determined whether or not the packet side merge stage identifier corresponds to the node side merge stage identifier.

  According to a tenth aspect of the data-driven processing device communication path device of the present invention, in the ninth aspect, a merging stage identifier generation node is further provided upstream of each inlet node of the tree-shaped branching channel, and the merging stage identifier generation is performed. The node generates the value of the packet side merge stage identifier based on the value of each destination address in the plurality of packets associated with each other.

  In an eleventh aspect of the data-driven processing device communication path device according to the present invention, in any one of the sixth to tenth aspects, each of the plurality of outlet nodes of the tree-shaped joining flow path is generated corresponding to the joining stage identifier. A communication path coupled to the node is further included.

  In a twelfth aspect of the data-driven processing device communication path device according to the present invention, in any one of the sixth to eleventh aspects, the tree-shaped branch flow path joins between the systems from each of the plurality of inlet nodes. A node in the next stage is provided at a position where the current is not divided.

  According to the configuration of the first aspect, the tree-shaped branch flow path and the tree-shaped combined flow path are disposed via the plurality of functional elements (there is not necessarily disposed at the opposing position. For example, depending on the functional element array, the flow path The angle formed by the direction may be 90 °.) With a simple configuration, a packet including a destination address is transferred to any one of a plurality of functional elements arranged in an integrated manner, and a packet corresponding thereto Can be taken out from the exit node of the tree-shaped joint flow path.

  In addition, packet congestion can be avoided on the channel outlet side and merge channel inlet side because of the relatively wide channel width, so processing delays in functional elements are absorbed by distributed parallel processing in multiple functional elements, and random access Alternatively, the processing throughput is relatively high.

  For example, if a memory is configured using the communication path device for a data driven processing device of the present invention and this is used as a shared memory of a multi CPU, even if a queue is formed, a multi-parallel processing by distributed pipeline processing is performed. Since the throughput is relatively high, the present invention is particularly effective for such applications.

  In addition, when a processor is configured with a data driven circuit, the power consumption can be greatly reduced by using one data driven memory rather than using a large number of ordinary memories to increase the degree of parallelism. It is suitable for use in mobile devices that require

  The shunt channel functions not only as a decoder but also as a queue. The combined flow path has a function of collecting and delivering packets and also functions as a queue. Therefore, when a packet is irregularly supplied to the inlet node of the diversion channel and the average time is approximately equal to the processing time of the processing element provided in the outlet node of the combined flow channel, for example, a queue is provided outside. Without any problem. This average time can be changed to an appropriate value by adjusting the parallelism of the circuit or device that supplies the packet to the ingress node.

  Even when a plurality of packets are extracted from the egress node for one packet to the ingress node, the downstream side of the egress node functions as a queue, and processing can be performed efficiently without providing a new queue.

  Therefore, even if the number of stages of the branch flow path and the combined flow path is relatively large, there may be an advantage in reverse.

  According to the configuration of the second aspect, it is possible to add logic to the node based on symmetry, so that the hardware design becomes easy.

  According to the structure of the said 3rd aspect, the said effect is heightened by the further symmetry.

  According to the configuration of the fourth aspect, it is possible to further increase the degree of parallelism, and in a plurality of systems, the downstream of the flow path and the previous stage of the combined flow path are shared by a relatively wide flow path width, so that the performance is reduced. There is an effect that the degree of parallelism with respect to the size of the communication path can be increased while being suppressed.

  According to the configuration of the fifth aspect, the effect of the second aspect is achieved even when a plurality of systems are provided.

  According to the structure of the said 6th aspect, the said effect is heightened by the further symmetry.

  According to the structure of the said 7th aspect, there exists an effect that the function which performs a process based on the relationship between a packet side branch stage identifier and a node side branch stage identifier can be added to a node.

  According to the configuration of the eighth aspect, since the branch stage identifier generation node is provided upstream of each inlet node of the tree-type branch path, it is necessary to add a branch stage identifier generation function to each node of the tree-type branch path. There is no effect, and the configuration is simplified.

  According to the structure of the said 9th aspect, there exists an effect that the function which performs a process based on the relationship between a packet side joining stage identifier and a node side joining stage identifier can be added to a node.

  According to the configuration of the tenth aspect, since the merge stage identifier generation node is provided upstream of each inlet node of the tree-shaped branch path, it is necessary to add a merge stage identifier generation function to each node of the tree-shaped branch path. There is no effect, and the configuration is simplified.

  According to the configuration of the eleventh aspect, since the plurality of exit nodes of the tree-shaped joining channel are further connected to the corresponding joining stage identifier generating nodes, there is an effect that repeated processing is possible.

  According to the configuration of the twelfth aspect, since the relatively narrow channel width on the inlet node side in the tree-shaped branch channel is enlarged, the effect that the packet congestion degree can be effectively reduced and the throughput can be improved. Play.

  Other objects, configurations and effects of the present invention will become apparent from the following description.

  FIG. 1 is a schematic block diagram showing an asynchronous (self-timing) type data driven memory 10.

  In the memory 10, a joint channel 40 is connected to the downstream side of the branch channel 20 via a memory row array 30 as a functional element array.

  FIG. 2A shows a specific example of the arrangement of the memory row array 30.

  The rows and columns of the memory row array 30 are identified by a set number and a page number, respectively. For simplicity of explanation, it is assumed that the memory row array 30 has 64 rows, 1 page has 8 words, and 1 word has 32 bits. Hereinafter, a case where reading and writing with respect to the memory row array 30 are performed in units of pages and words will be described.

  Returning to FIG. 1, the diversion channel 20 divides packets supplied to the ingress node 211 sequentially and selectively according to the destination address, and functions as an address decoder.

  FIG. 2B shows a packet format in the branch path 20.

  The packet 50 includes a 1-bit command field, an 11-bit address field, and a 32-bit data field. The command CMD indicates read when “0” and write when “1”. The address ADR is divided into an upper 6-bit destination address DA, a middle 2-bit page address PA, and a lower 3-bit word address WA.

  The destination address DA indicates the destination of the branch channel 20, that is, the row (set number) of the memory row array 30. The page address PA is used for identifying the read target in the memory row after the packet 50 reaches the destination address. The set of the page address PA and the in-page word address WA is used for identifying the write target in the memory row after the packet 50 reaches the destination address. Data DATA is write data, and is dummy in the case of reading.

  Hereinafter, packets in the branch channel 20 and the combined channel 40 when the command CMD is read are referred to as a read packet and a read data packet, respectively, and packets in the branch channel 20 in the case of write are referred to as a write data packet.

  The read data packet in the combined channel 40 is 43 bits obtained by removing one bit of the command CMD from the packet 50, and the address ADR is used for identifying data in the packet that has reached the exit node of the combined channel 40.

  Returning to FIG. 1, each of the branch flow path 20 and the combined flow path 40 is a six-stage pipeline, and a node in each pipeline stage includes a latch and a transfer control circuit.

  FIG. 3 is a schematic block diagram showing a shunt circuit composed of nodes of the first stage and the second stage when the shunt flow path 20 is configured by the bundle data method.

  The first-stage entry node 211 includes a latch 211L and a transfer control circuit 211C, the second-stage node 221 includes a latch 221L and a transfer control circuit 221C, and the second-stage node 222 includes a latch 222L. A transfer control circuit 222C and an inverter 222G are provided. The transfer control circuits 211C, 221C, and 222C perform input stage gate opening / closing in the latches 211L, 221L, and 222L by a handshake protocol, and the stages are cascaded.

  In any of the transfer control circuits, the SEND-IN (transfer request input) signal from the subsequent stage is active, that is, the data from the subsequent stage is determined, and the ACK-IN (transfer permission input) signal from the previous stage is active, that is, the previous stage. Is empty, a pulse is supplied to the clock input terminal CK of the latch to capture and hold data from the subsequent stage, and if there is no special restriction, the ACK-OUT signal to the subsequent stage is activated and the data to the previous stage is activated. The SEND-OUT signal to the previous stage is made active after a lapse of a predetermined time considered to have arrived.

  Each transfer control circuit has a control input terminal for enabling / disabling the output, and the destination address (DA5) of the packet held in the latch 211L is provided at each control input terminal of the transfer control circuits 221C and 222C. ... DA0) The most significant bit DA5 of DA and its inverted version by the inverter 222G are supplied. Therefore, when the bit DA5 is “1”, the latches 221L and 222L are enabled and disabled, respectively, and the contents of the latch 211L are held in the latch 221L. When the bit DA5 is “0”, the latches 221L and 222L are respectively It becomes invalid and valid, and the contents of the latch 211L are held in the latch 222L.

  Each transfer control circuit further has a reset input terminal (not shown), which is supplied with a reset pulse at the time of system reset so that ACK-IN and ACK-OUT are active, and SEND-IN and SEND-OUT are inactive. Become.

  Since various types of transfer control circuits are known, description of the configuration is omitted.

  Returning to FIG. 1, for example, the packet held in the node 221 is held in the node 231 or the node 232 according to the second bit of the destination address DA, and the packet held in the node 232 is, for example, the first address of the destination address DA. It is held in the node 243 or the node 244 according to 3 bits. Similarly, the packet arrives at one of the 32 exit nodes arranged in the sixth stage according to the contents of the destination address DA of the diversion channel 20. Each output node has two branch outputs.

  In each node, it is assumed that when the corresponding bit of the destination address DA is “1” / “0”, it is determined that data is branched upward / downward in FIG. For example, when the destination address DA is “111111”, this packet reaches the output node 261. At the node 261, when the least significant bit DA0 of the destination address DA is “1”, the memory row 31 of the memory row array 30 is enabled, and when the bit DA0 is “0”, the memory row 32 is enabled. The

  The 64 memory rows constituting the memory row array 30 have the same configuration. Each memory row has its input end and output end coupled to the corresponding output end and input end of the shunt channel 20 and the combined channel 40, respectively. A latch can be connected to each of the output end of the branch flow path 20 and the input end of the combined flow path 40, but in order to reduce the number of stages and shorten the turnaround time, these latches are omitted in FIG. It has become.

  FIG. 5 is a schematic block diagram showing the memory rows 31 and 32 connected between the output node 261 of the branch channel 20 and the inlet node 411 of the combined channel 40 in FIG.

  Memory rows 31 and 32 are connected between node 261 and entry node 411. The node 261 includes a latch 261L and a transfer control circuit 261C that opens and closes the input gate. The entry node 411 includes a latch 411L and a transfer control circuit 411C that opens and closes the input gate.

  The memory rows 31 and 32 are provided with a loop wiring 310 comprising a looped 32-bit data bus and an upper 8-bit address bus of the address ADR, which are arranged as a data output terminal of the latch 261L and a data input terminal of the latch 411L. It is connected to the. The data input terminal and the data output terminal of each of the 32 word memories 310W to 3131W that are constituent elements of the memory row 31 are connected to the data bus of the loop wiring 310. Similarly, the data bus 32 is a constituent element of the memory row 32. Data input terminals and data output terminals of the word memories 320W to 3231W are connected.

  A control circuit 311 is connected between the transfer control circuit 261C and the transfer control circuit 411C in order to control the clock input terminal CK and the output enable control input terminal OE of each of the word memories 310W to 3131W and 320W to 3231W. Yes.

  The control circuit 311 is supplied with the command CMD, page address PA, word address WA, and clock pulse CK1 supplied to the clock input terminal CK of the latch 411L held in the latch 261L. The control circuit 311 includes a counter 311a that counts the clock pulse CK1. In the case of reading, the control circuit 311 supplies the count as the word address WX to the word address WA section at the data input end of the latch 411L.

  When one or both of SEND1 from the transfer control circuit 261C and ACK2 from the transfer control circuit 411C are inactive, the control circuit 311 sets the clock input terminal CK and the output enable control input terminal OE of each word memory. Keep it inactive and close its input and output gates (disable word memory access).

  When both SEND1 from the transfer control circuit 261C and ACK2 from the 441C become active, the control circuit 311 clears the counter 311a to zero, and if the bit DA0 of the address ADR is “1”, the word circuits 320W to 3231W are accessed. Is disabled and the following control is performed.

  If the command CMD indicates a read, the control circuit 311 performs the following control while keeping ACK1 for the transfer control circuit 261C inactive.

  (1) Among the word memories 3131W to 310W, the output enable control input terminal OE of the word memory designated by the page address PA and the word address WX is activated, and the contents of the word memory are read onto the loop wiring 310. SEND2 is activated after a lapse of a predetermined time which is considered to be determined at the data input terminal of the latch 411L. In response to this, if the ACK from the next stage is active, the transfer control circuit 411C supplies the clock pulse CK1 to the clock input terminal CK of the latch 411L and the data (DATA, DA, and PA) on the loop wiring 310. The word address WX from the control circuit 311 is fetched and held in the latch 411L, and then ACK2 is activated. The control circuit 311 counts the clock pulse CK1 with the counter 311a, increments the word address WX, and makes SEND2 inactive in response to the activation of ACK2.

  (2) When the data transfer from the ingress node 411 to the next stage is completed, ACK2 becomes active. In response to this, the control circuit 311 returns to (1) if the value of the counter 311a is less than 8.

  When the value of the counter 311a becomes 8, ACK1 for the transfer control circuit 261C is made active so that the latch 261L can take in data from the subsequent stage.

  By such processing, the stored contents of 8 words indicated by the page address PA of the address ADR held in the node 261 are sequentially transferred from the memory row 31 to the latch 411L.

  If the command CMD indicates write, the control circuit 311 pulses the clock input terminal CK of the word memory specified by the page address PA and the word address WA of the address ADR while maintaining SEND2 inactive. Then, the data on the loop wiring 310 is taken in and held in the word memory, and then ACK1 is activated.

  Such memory access can be performed simultaneously on up to 32 memory rows in the memory row array 30.

  In the case of a read packet, returning to FIG. 1, it reaches the exit node 461 from any entrance node of the combined flow path 40. That is, in the joint channel 40, it is not necessary to use the destination address for route selection. In each node of the combined flow path 40, the data that has reached first among the two inputs is selectively held.

  FIG. 4 is a schematic block diagram showing a joining circuit that is a part of the second stage and the third stage when the joining channel 40 is configured by the bundle data method.

  The second stage node 421 includes a latch 421L and a transfer control circuit 421C, the second stage node 422 includes a latch 422L, a transfer control circuit 422C, and an inverter 422G, and the third stage node 431 includes a latch. 431L and a transfer control circuit 431C. The transfer control circuits 421C, 422C, and 431C perform input stage gate opening and closing in the latches 421L, 422L, and 431L, respectively, by a handshake protocol, and the stages are cascaded.

  The circuit of FIG. 4 is obtained by reversing the signal direction in the circuit of FIG. However, control by the bit of the destination address is not performed. Further, in order to avoid a collision between the output of the latch 421L and the output of the latch 422L, each latch has an output enable control input terminal OE, and the transfer control circuit 431C directly enters the latch 422L to the output enable control input terminal OE. The control signal is supplied to the output enable control input terminal OE via the inverter 422G. The transfer control circuit 431C sets the output enable control input terminal OE of the latch corresponding to the one that becomes active first among SEND-IN from the transfer control circuit 421C and SEND-IN from the transfer control circuit 422C to “1”. , Set the other to '0'.

  By such control, selective (exclusive) merging is performed.

  In the memory 10 configured as described above, when a write data packet is supplied to the ingress node 211 and the SEND-IN signal to the ingress node 211 is activated, the pipeline stage in the branch channel 20 according to the destination address. The data DATA in the write data packet is written in the word designated by the address ADR in the write data packet.

  Similarly, when a read packet is supplied to the ingress node 211 and the SEND-IN signal to the ingress node 211 is activated, the memory row array sequentially flows through the pipeline stage in the diversion channel 20 according to the destination address DA. 30, the data of the page specified by the page address PA in the read packet is sequentially read out in units of words, and sequentially passes through the pipeline stage in the junction 40 regardless of the value of the destination address DA. Eight words of data reach the egress node 461.

  When the packet in the ingress node 211 is transferred to the node 221 or the node 222 and the ACK-OUT signal becomes active, the next packet can be held in the ingress node 211. The type of packet to be supplied next is arbitrary regardless of whether the previously supplied packet is a read packet or a write data packet.

  According to the memory 10 of the first embodiment, an arbitrary configuration of the memory row array 30 arranged in an integrated manner can be obtained with a simple configuration in which the tree-shaped branch channel 20 and the tree-shaped merge channel 40 are disposed via the memory row array 30. There is an effect that a packet including a destination address is transferred to one row, and a packet corresponding to the destination address can be taken out from the exit node 461 of the tree-shaped merge channel 40.

  In addition, since congestion of packets is avoided on the outlet side of the branch channel 20 and the inlet side of the combined channel 40 having a relatively wide channel width, processing delays in the memory rows are absorbed by distributed parallel processing in a plurality of memory rows. As a result, the random access throughput is relatively high.

  Furthermore, when a processor is configured with data-driven circuits, the power consumption can be greatly reduced by using one data-driven memory rather than using many non-data-driven memories to increase parallelism. There is an effect that it is suitable for use in mobile devices that require battery life.

  In the first embodiment, reading in units of pages has been described, but it is needless to say that access may be performed in units of rows, words, or bytes. This also applies to the following embodiments.

  In the memory 10 of FIG. 1, the bottleneck is that there is one entrance node and one exit node each in spite of a high degree of parallelism. FIG. 6 shows a memory 10A according to the second embodiment of the present invention in which this point is improved.

  In this memory 10A, an inlet node 212 is added to the branch channel 20A, the output of the inlet node 212 is supplied to the nodes 221 and 222A, and the second-stage nodes 221A and 222A form a two-merging / two-branch circuit. . This merging is the above-described selection type. For example, the node 221A captures and holds data corresponding to the previously activated SEND-IN from the ingress nodes 211 and 212. Also in the diversion channel 20A, similarly to the diversion channel 20 of FIG. 1, the diversion channel 20A reaches the exit node determined only by the destination address DA. Therefore, it is not necessary to provide a new rule for the write data packet.

  In the combined flow path 40A, an exit node 462 is added to the output stage so that the node 451A or the node 462A can transfer to the exit node 462. Each of the nodes 451A and 462A is a two-merging / two-branch circuit.

  Here, a rule is required as to whether the data is transferred from the node 451A to the egress node 461 or the egress node 462. For example, when priority is given to the egress nodes 461 and 462 and both are empty (ACK-IN is active), the node 451A transfers the node to the higher priority node, and when only one is available, It can also be configured to be transferred to.

  In this embodiment, in order to make the data flow orderly, as shown in FIG. 7A, a 1-bit channel CH is added to the packet 50A, and when this value is “0”, the node 451A or the node 452A exits. Transfer to the node 462, and when “1”, transfer from the node 451A or the node 452A to the egress node 461. The value of the system CH is determined by which of the entry nodes 211 and 212 supplies the read packet. For example, when a packet is supplied to the ingress node 212, “1” is set to the system CH, and when supplied to the ingress node 211, “0” is set to the system CH.

  When the read packet is supplied to the ingress node 211 in this way, the data read from the memory row array 30 always reaches the egress node 461. When the read packet is supplied to the ingress node 212, the data read from the memory row array 30 is The egress node 462 is always reached. The packet path has logical symmetry. That is, the packet path is logically symmetric (first symmetry) between the branch flow path 20A and the combined flow path 40A with respect to the columns of the memory row array 30. Further, the path of a packet having a destination address complementary to each other, for example, the path of a packet having a destination address 0101111 and the path of a packet having a destination address 100100 are logically symmetrical (second symmetry) with respect to the axis in the flow path direction. Become. In the present invention, at least the second symmetry may be provided.

  FIG. 7B shows the path of the read packet that can pass through the first and second stages of the branch channel 20A and the combined flow path 40A through which the read data packet that has been read can pass when the system CH is “0”. The 5th and 6th stage routes are shown. A dotted line indicates a case where the system CH is “0”, and a solid line indicates a case where the system CH is “1”.

  The destination of the read packet is determined only by the value of the destination address DA regardless of the value of the system CH. For example, when the system CH is “1” and the most significant bit of the destination address DA is “1”, as described above, when “1” branches to the upper side of FIG. 7B and “0” branches to the lower side. If determined, the packet supplied to the ingress node 211 proceeds to the node 221A.

  In the merge channel 40A, even if there is a merge up to the fifth stage, there is no branch, so the path is uniquely determined regardless of the values of the system CH and the destination address DA. In this case, the read data packet reaches the node 451A. .

  Since the system CH is “1”, the process proceeds from the node 451A to 461A. Similarly, when the most significant bit of the destination address DA is “0”, the read data packet reaches the egress node 461. That is, when the path in the fifth to sixth stages of the combined flow path 40A is determined by the value of the system CH, the path is symmetrical between the branch path 20A and the combined flow path 40A with respect to the memory row array 30, and the system CH is '1'. In some cases, it always reaches the node 461A of the combined channel 40A corresponding to the inlet node 211 of the branch channel 20A.

  The other points are the same as in the first embodiment.

  According to the second embodiment, by adding and changing the nodes as described above, the number of input ports and output ports of the memory 10A is doubled, so that the throughput can be greatly improved.

  Further, since the two systems share the latter stage of the branch channel 20A and the former stage of the combined channel 40A with a relatively wide channel width, the parallelism with respect to the scale of the communication path can be increased while suppressing the performance degradation. Play.

  Further, by adding the system CH to the packet 50A and branching it according to the value of the system CH in the junction / branch circuit on the outlet side of the combined channel 40A, if the lead packet is supplied to which inlet node of the branch channel 20A, the combined channel 40A Since it is determined from which exit node the read data packet can be obtained, there is an effect that the processing of the data taken out from the combined channel 40A becomes easy.

  FIG. 8 shows the memory 10B according to the third embodiment of the present invention in which the number of input ports and output ports is doubled as compared with the second embodiment.

  In this memory 10B, nodes are added to the configuration of FIG. 6 so that the configuration is symmetric with respect to the axis of the packet flow direction.

  That is, inlet nodes 213 and 214 are added to the input stage of the diversion channel 20B, nodes 223A and 224A are added to the second stage, and the connection between them is between the nodes 211 and 212 and the nodes 221A and 222A. It is the same as the connection. Similarly to the second stage, each node of the third stage of the branch channel 20B is also a two-merging / two-branch circuit, and the second stage and the third stage are connected so as to be symmetrical.

  The path of the packet flowing through the branch path 20B is determined only by the destination address DA as in the second embodiment. Therefore, it is not necessary to provide a new rule for the write data packet.

  Similarly to the branch flow path 20B, the combined flow path 40B also includes nodes 463A and 464A added to the output stage, and nodes 453A and 454A added to the subsequent stage. The connection is the same. In addition, each node in the subsequent stage (fourth stage) of the combined flow path 40B is also a two-merging / two-branch circuit like the fifth stage, and the fourth stage and the fifth stage are connected so as to be symmetrical. ing.

  FIG. 9A shows the format of the packet 50B. In this packet 50B, the system CH has 2 bits, and the other points are the same as those in FIG. In the case of a read packet, when the packet is supplied to the ingress nodes 214 to 211, the value of the system CH is set to 0 to 3, respectively. As a result, the read data packet read from the memory row array 30 passes through a path that is symmetric with respect to the path in the diversion channel 20B with respect to the memory row array 30.

  In FIG. 9B, when the system CH is “01”, the path of the read packet that can pass through the first to third stages of the branch channel 20B and the path that the read data packet that has been read can pass are indicated by dotted lines. Show.

  As described above, the destination of the read packet is determined only by the value of the destination address DA regardless of the value of the system CH. For example, when the upper 2 bits of the destination address DA are “11”, if it is determined that “1” branches to the upper side of FIG. 11B and “0” branches to the lower side as described above, the most significant bit is Since it is “1”, the process proceeds from the ingress node 213 to the node 223A, and since the next bit is “1”, the process proceeds from the node 223A to 231A.

  In the merge channel 40B, there is no branch even if it merges up to the fourth stage. Therefore, the path is uniquely determined regardless of the values of the system CH and the destination address DA. In this case, the read data packet reaches the node 441A. .

  Since the system CH is “01” and the second bit is “0”, the process proceeds from the node 441A to 453A. Next, since the first bit is “1”, the process proceeds from the node 453A to the node 463A. The read data packet arrives at the node 463A in the same manner when the upper 2 bits of the destination address DA are in other cases. That is, when the route in the fourth to sixth stages of the combined channel 40B is determined by the value of the system CH, the path is symmetrical between the branch channel 20B and the combined channel 40B with respect to the memory row array 30, and the system CH is “01”. In some cases, it always reaches the node 463A of the combined channel 40B corresponding to the inlet node 213 of the branch channel 20B.

  In FIG. 9C, the path of the read packet that can pass through the first to third stages of the branch channel 20B when the system CH is “11” and the path that the read data packet that has been read can be shown by dotted lines. Show.

  According to the third embodiment, the effect described in the second embodiment can be further enhanced by slightly changing the configuration of the second embodiment.

  In addition, since the 4th to 6th stage nodes having a relatively wide channel width of the branch channel 20B and the 1st to 4th stage nodes having a relatively wide channel width of the combined channel 40B are shared in four systems, the performance degradation is suppressed. However, the parallelism with respect to the size of the communication path can be increased.

  FIG. 10 shows a memory 10C according to the fourth embodiment of the present invention in which the number of pipeline stages is reduced.

  In the diversion channel 20C, the input up to the third stage is the same as that of the diversion channel 20B in FIG. The difference from the branch flow path 20B is that the output of each node in the third stage and each node in the fourth stage has four branches. As a result, the branch channel 20B is a six-stage pipeline, whereas the branch channel 20C is a four-stage pipeline. The combined flow path 40C is configured to be symmetric with respect to the branch flow path 20C with respect to the memory row array 30 and the direction of the data flow is reversed, and is a four-stage pipeline.

  As in the case of the third embodiment, when the entry node is determined for the packet path in the branch channel 20C, the packet path is determined only by the destination address, and the combined channel 40D is sent from the node having the selective branch output. The packet path is determined by the system.

  If the number of merging at the node input end increases, it is a selective merging with the first priority, so if the number of packets transferred to the same merging node increases, transfer waiting occurs. However, when the packet is not congested, the number of pipeline stages is small, so that the latency can be shortened.

  When writing to the memory row array 30 is completed in one word like a write packet, it is effective because the waiting time at the exit node of the branch channel 20C is relatively short. On the other hand, in the read data packet, since 8 words of data are sequentially read from the memory row 31, the waiting time from the other memory row 31 to the same entrance node becomes relatively long at the input node of the joint channel 40C. In order to avoid this, the combined flow path 40B may be used instead of the combined flow path 40C. That is, the diversion channel 20C and the combined flow channel 40C may be combined.

  FIG. 11 shows a two-port input / two-port output type memory 10D according to the fifth embodiment of the present invention in which the waiting time for transfer to the selective merging node is shortened.

  In the diversion channel 20A of FIG. 6, the selective merge is the second stage nodes 221A and 222A, and a wait occurs in the first stage.

  Therefore, in the shunt channel 20D, nodes 223 and 224 are added to the second stage so that selective merging does not occur in the second stage. The node 223 branches to the node 231A or 233A and merges, and the node 224 branches to the node 235A or 237A to merge.

  As a result, each node in the third stage selectively joins, but since the number of nodes is 4, the number of nodes in the shunt 20D is larger than the packet transfer average waiting time in the first stage of the shunt 20A in FIG. It is about half that of the two stages, so that packet stagnation can be reduced and throughput can be improved.

  The other points are the same as those in the second embodiment.

  FIG. 12 shows a memory 10E according to the sixth embodiment of the present invention in which the number of input ports and output ports is doubled as compared with the fifth embodiment.

  In the memory 10E, nodes are added to the configuration of FIG. 11 so that the configuration is symmetric with respect to the axis of the packet flow direction.

  That is, inlet nodes 213 and 214 are added to the input stage of the diversion channel 20E, nodes 225 to 228 are added to the second stage, and nodes 232A, 234A, 236A, and 238A are added to the third stage, and The connection between these and the nodes 225 to 228 has the same shape as the connection between the second stage and the third stage of the diversion channel 20D of FIG. Further, each node of the fourth stage of the diversion channel 20E is also a two-merging / two-branch circuit like the third stage, and the third stage and the fourth stage are connected so as to be symmetrical.

  The combined flow path 40E is configured to be symmetric with respect to the branch flow path 20E with respect to the memory row array 30 and to reverse the direction of data flow.

  As in the case of the fifth embodiment, the packet path in the branch path 20E is determined only by the destination address when the entry node is determined, and the combined path 40E is sent from the node having the selective branch output. The packet path is determined by the system.

  According to the sixth embodiment, the effect described in the fifth embodiment can be further enhanced by slightly changing the configuration of the fifth embodiment.

  In a multi-CPU, if each CPU has a data cache memory for a shared memory, coherency (data consistency) cannot be maintained. According to a shared cache that can be referred to by a plurality of CPUs for one data cache memory, coherency can be maintained.

  However, in the case of the synchronous type, it is necessary to synchronize globally even with respect to random requests from a plurality of CPUs, resulting in insufficient throughput.

  On the other hand, although the asynchronous pipeline method has high throughput, the latency increases and the access time becomes longer as the number of pipeline stages increases, so the pipeline method is not suitable for a normal cache memory.

  However, in the case of a multi-CPU, even if an asynchronous pipeline method is used, the disadvantage of increased latency is relatively hidden, and the advantage of multi-parallel processing comes to life. The same applies to the multi-core CPU.

  FIG. 13 is a schematic block diagram of a cache memory 60 to which the present invention is applied. The cache memory 60 is embedded inside the processor or arranged outside the processor. When the cache memory 60 is used in a multi-CPU, it is necessary to include a CPU identifier in the packet, but for the sake of simplicity of explanation, a case where there is no CPU identifier will be described below.

  The cache memory 60 is provided with the memory 10 of the first embodiment, and a tag table 70 is provided corresponding to the memory 10. In the tag table 70, a combined flow path 73 is connected to the downstream side of the branch flow path 71 via a tag array 72. The branch flow path 71 and the combined flow path 73 can have the same configuration as the branch flow path 20 and the combined flow path 40 of the memory 10, respectively.

  The number of tag rows 721 constituting the tag array 72 is the same as that of the memory row array 30. The read packet or the write packet is supplied from the outside of the cache memory 60 to the branch path 71 via the interface 81 of the input / output unit 80.

  The packet format is different from that of FIG. 2B in that a tag address TA is added to the upper side in the address ADR and a hit bit HM is added. The format of the packet supplied to the diversion channel 20 of the memory 10 is the same as that of the packet supplied to the diversion channel 71.

  In the tag table 70, based on the supplied packet, the page data identified by the tag address TA, the destination address DA, and the page address PA on the external memory is identified by the destination address DA in the memory row array 30. It is determined whether or not the data is stored in the row and the page identified by the page address PA in this row, and processing corresponding to the result is performed.

  In the tag table 70, the value of the tag address TA included in the supplied packet is stored in the TAG of the column identified by the row in the tag array 72 identified by the destination address DA and the page address PA in this row. This determination is made based on whether the value matches the tag address value. If they match, the hit bit HM is set to '1'. Otherwise, it is set to '0' and eviction / writeback / update processing described later is performed.

  FIG. 14 is a schematic block diagram showing the configuration of adjacent tag rows 721 and 722 in the tag array 72.

  The tag rows 721 and 722 are connected between the node 711 and the node 731. The node 711 is an outlet node of the branch path 71 corresponding to the tag rows 721 and 722, and the node 731 is an inlet node of the combined channel 73 corresponding to the tag rows 721 and 722.

  The tag rows 721 and 722 include a loop wiring 740, which is connected to the data output terminal of the latch 711L and the data input terminal of the latch 731L. The loop wiring 740 is a signal line other than the command CMD, the hit bit HM, and the page address PA. That is, the command CMD, the hit bit HM, and the page address PA are directly transmitted from the latch 711L to the latch 731L. The tag address (TA) signal line included in the loop wiring 740 is connected to one input terminal of the comparators 760 to 763 that are components of the tag row 721, and the same applies to the tag row 722.

  A control circuit 741 is connected between the transfer control circuit 711C and the transfer control circuit 731C. The tag row 721 includes page information storage units 750 to 753 corresponding to the 0th to 3rd pages, all of which include a tag TAG, a valid bit V, a dirty bit D, a lock bit L, and a counter CNT.

  The contents of the tags TAG in the page information storage units 750 to 753 are supplied to the other input terminals of the comparators 760 to 763, respectively. Each of the comparators 760 to 763 outputs “1” only when the two inputs coincide with each other. The outputs of the comparators 760 to 763 are supplied to the OR gate 764 on the one hand to generate the hit bit HM, and on the other hand to the encoder 765 to generate the page address PA1.

  The multiplexer 766 is supplied with the page address PA1 and the hit bit HM1 of the tag row 721, the page address PA2 and the hit bit HM2 of the tag row 722 corresponding thereto, and the page address PA and the hit bit HM from the control circuit 741. One of these is selected by the selection control signal from the control circuit 741 and supplied to the corresponding data input terminal of the latch 731L. The hit bits HM1 and HM2 are also supplied to the control circuit 741. The control circuit 741 is further supplied with a bit DA0 of the destination address DA, a page address PA, a tag address TA, and a command CMD from the latch 711L.

  The control circuit 741 enables the tag row 721 side and disables the tag row 722 side when the bit DA0 is “1”, and vice versa when the bit DA0 is “0”. Hereinafter, a case where the bit DA0 is “1” will be described.

  Here, the node 77 in FIG. 13 branches and transfers the packet from the combined channel 73 according to the following rule.

  (R) If the command CMD is a read command or a write command and the hit bit HM is '1' or a eviction command, the packet from the combined channel 73 is transferred to the branch channel 20 side of the memory 10, and in other cases, that is, update In the case of a command or a write command to an external memory, this packet is transferred to the node 82 side of the input / output unit 80.

  If SEND3 from the transfer control circuit 711C is active and ACK4 from the transfer control circuit 731C is active, the control circuit 741 enables the output of the circuit on the tag row 721 side if the bit DA0 is “1”. After invalidating the output of the circuit on the tag row 722 side and performing the control described later, the following post-processing is performed.

  (A) The control circuit 741 activates SEND4 to the transfer control circuit 731C after the elapse of time when it is considered that the input data of the latch 731L has been confirmed. In response to this, if the ACK from the previous stage of the transfer control circuit 731C is active, the transfer control circuit 731C supplies a pulse to the clock input terminal CK of the latch 731L to capture and hold the input data in the latch 731L. Make ACK4 inactive. In response to this, the control circuit 741 makes SEND4 inactive. Control circuit 741 then activates ACK3 to allow latch 711L to capture data from the subsequent stage.

  If the command CMD indicates a read, the control circuit 741 performs the following control while maintaining ACK3 for the transfer control circuit 711C inactive.

(A) Cache hit by read If the hit bit HM1 is '1' after a lapse of a predetermined time when the output of the OR gate 764 is considered to be fixed, the control circuit 741 sends the page address PA1 to the multiplexer 766. A pair with the hit bit HM1 is selected and the command CMD from the latch 711L is supplied to the node 731 as it is, and on the other hand, the counter CNT of the page information storage unit 75i corresponding to the page address PA1 = i is incremented. However, the counter CNT is not incremented when the value reaches the maximum value.

  Next, the control circuit 741 performs the post-processing (A). The packet is transferred to the node 77 in FIG. In the node 77, the data is transferred to the memory 10 side according to the rule (R), the corresponding one page of data is read from the combined channel 40, and this is supplied to the interface 81 via the node 82 of the input / output unit 80. The data is output from the interface 81 to the CPU side.

(B) Cache miss hit by read and V = '0' in page The control circuit 741 has a hit bit HM1 of '0' and any valid bit V of the page information storage units 750 to 753 is '0'. If '(not used), the tag TAG to which this valid bit V belongs is rewritten with the tag address TA of this packet, the command CMD is used as an update command, and the page information 75i to which this valid bit V belongs (i is 0 to 3). (I) is set as the page address PA, and this and HM = '0' are supplied to the multiplexer 766, and the multiplexer 766 selects the pair of PA and HM. Do.

  According to the rule (R), the update command packet is supplied to the external memory controller side via the nodes 77 and 82 and the interface 81, and is sent from the external memory for one page specified by the tag address TA and page address PA of this packet. Are read in burst mode.

  This data is supplied on the one hand to the CPU that made the read request and on the other hand to the interface 81 in word units. At the interface 81, the update packet waits for the arrival of this data, and as shown in FIG. 15, one word of data is written in the data field of this update packet, and a copy thereof is supplied to the branch channel 71. . From the second time onward, the word address WA in the update packet is incremented by 1, and the same processing is repeated until WA = '11 '.

  In the tag array 72, the following processing is performed in FIG. When the command CMD is an update command, the control circuit 741 supplies a command CMD indicating a write to the latch 731L, and sets the lock bit L to “1” if the valid bit V is “0”. Then, the post-processing of (A) is performed.

  According to the rule (R), the write command packet branches from the node 77 to the memory 10, and one word of data is sequentially written at a location corresponding to the address.

(C) Cache miss hit in read and all V = '1' in page
If the hit bit HM1 is “0” and any valid bit V in the page information storage units 750 to 753 is “1”, the control circuit 741 determines the eviction page as follows.

  That is, of the counters CNT in the page information storage units 750 to 753, the minimum value of the counter CNT whose lock bit L is “0” is determined, and the page information 75i (i is 0) to which the counter CNT belongs. I in any of (3) to (3) is determined to be the eviction / update page i. By setting the lock bit L to “0” as a condition for determining the eviction / update page, rewriting of the tag TAG is prohibited if L = “1” and V = “1”.

  Next, if the dirty bit D is “1”, the control circuit 741 supplies a command CMD indicating eviction to the latch 731L, supplies PA = i and HM = “1” to the multiplexer 766, and supplies this command to the multiplexer 766. To select. Next, the post-processing (A) is performed.

  According to the rule (R), the packet is transferred to the memory 10 side via the node 77, and the same processing as in the case of the read command is performed, and the corresponding data for one page is read from the merge channel 40 in units of words. , The node 77, the node 82 of the input / output unit 80, and the interface 81 to the external memory controller side. As a result, data is written back to the page specified by the tag address TA and page address PA of the packet in the external memory.

  The control circuit 741 sets the tag address TA from the latch 711L when the dirty bit D is “0”, or immediately before or after transferring the packet of the eviction command to the latch 731L when the dirty bit D is “1”. Write to the tag TAG of the page information 75i, set the lock bit L to “1”, immediately after the transfer, supply the command CMD indicating the update to the latch 731L, and perform the packet generation processing of the update command described in (2R) above. Do.

  Therefore, when the dirty bit D is “1”, the update command packet is output immediately after the eviction command packet is output from the tag row 721, and then the eviction process and the update process are performed in parallel.

  If the command CMD indicates write, the control circuit 741 performs the following control while maintaining ACK3 for the transfer control circuit 711C inactive.

(D) Cache hit by write If the hit bit HM1 is '1' after a lapse of a predetermined time when the output of the OR gate 764 is considered to be fixed, the page address PA1 is sent to the multiplexer 766. A pair with the hit bit HM1 is selected, and the command CMD from the latch 711L is supplied to the node 731 as it is. On the other hand, the counter CNT is incremented, and the dirty bit D is set to “1”. Next, the post-processing (A) is performed. According to the rule (R), the packet is transferred to the memory 10 side via the node 77, and the data DATA in the packet is written in the word memory specified by the destination address DA, page address PA, and word address WA in the packet.

(B) Cache miss hit by write If the hit bit HM1 is “0”, the control circuit 741 supplies a command CMD indicating writing to the memory to the latch 731L, and the hit bit HM = “0” and the latch 711L The page address PA is supplied to the multiplexer 766, and the multiplexer 766 selects this set. Next, the post-processing (A) is performed. According to the rule (R), the packet is supplied to the external memory controller via the node 77, the node 82 of the input / output unit 80, and the interface 81, and is specified by the tag address TA and the page address PA of the packet in the external memory. Data DATA in the packet is written to the page.

  According to the cache memory 60 of the seventh embodiment, packets are distributed to each pipeline stage in the memory 10 and the tag table 70, the node 77, the interface 81, and the node 82, and the pipeline is synchronized locally with each node. Since processing can be performed, processing for a plurality of hits and a plurality of miss hits can be performed in parallel at the same time, the throughput is high, and the configuration is relatively simple. It is suitable for use in a drive type processing apparatus.

  FIG. 16 is a schematic block diagram showing the cache memory 60A according to the eighth embodiment of the present invention.

  In this cache memory 60A, four systems of memory 10A and tag table 70A are provided instead of the memory 10 and tag table 70 of FIG. Correspondingly, nodes 771 to 774 are arranged instead of the node 77 of FIG. 13, and input / output units 801 to 804 having the same configuration as the input / output unit 80 are provided instead of the input / output unit 80 of FIG. It is arranged.

  Since the operation of the cache memory 60A can be easily understood from the above description, it will be omitted.

  According to the cache memory 60A of the eighth embodiment, the system is four times that of the seventh embodiment, so that the throughput is high and the effects described in the above embodiments are high. Moreover, for each system, there are many nodes shared by the first to fourth systems in the memory 10A and the tag table 70A, and the memory row array 30 and the tag array 72 are shared by each system, so that resources can be used effectively. Further, since the configuration is prevented from being complicated, and it is shared by a relatively wide portion of the flow path width, an effect of suppressing a decrease in throughput due to packet congestion is obtained.

  In general, a CPU has a large number of instructions for processing two operands. When the number of pipeline stages is large, the latency becomes long. However, when time-shared n parallel processing is performed by one CPU core, the speed of each processing is 1 / n even if the switching time is assumed to be zero in the synchronous type. Therefore, for example, when the degree of parallelism is high as in a server computer, the asynchronous type is more advantageous.

  FIG. 17 is a schematic block diagram showing a data processing unit 10AP which is a part of a processor suitable for such a use of the ninth embodiment to which the present invention is applied.

  As indicated by the bold line in this figure, the exit node of the combined flow path 40AP is determined only by the system value, so that a plurality of packets are continuously supplied to the entrance node of the branch path 20A in the same system. Thus, a plurality of data packets corresponding to this can be collected at the same exit node of the combined channel 40AP. In other words, by making the system values the same, a plurality of packets can be automatically queued at the egress node.

  Therefore, in the joint channel 40AP, each of the exit nodes 461AP to 464AP includes a processing element. The processing content in each processing element may be the same or may be determined by the system value. The processing element may have a high function or a low function. 30R is used as a register file. The register file 30R can be freely divided into an area shared by these processing elements and an area dedicated to each.

  18A shows that when the first operand packet P1 including the command CMD and the second operand packet P2 are sequentially input to the ingress node 211, the corresponding packets P1A and P2A arrive at the node 461P. The case where the result packet P3 is obtained by the processing element is shown. The first operand packet P1 and / or the second operand packet P2 may be a plurality of packets that are sequentially supplied.

  When this packet P3 corresponds to the packets P1 and P2 in the next step as in the packets P1N and P2N shown in FIG. 18B, these are fed back to the ingress node 211 via the node 47. Thus, the processing can be continuously performed at high speed. The node 47 determines whether or not the processing is completed based on the packet P1N output from the node 461P. If the determination is affirmative, the node 47 outputs the result, and based on the processing mode (or CMD) included in the packet. , Abort or continue processing.

  The branch channel 20A functions as a decoder and also as a queue. Further, nodes other than the exit node of the combined channel 40AP collect and deliver packets to the processing elements of the same system, and also function as queues. Therefore, when packets are irregularly supplied to the ingress nodes 211 to 214 and the average time is approximately equal to the processing time of the processing elements provided in the egress nodes 461AP to 464AP, the data processing unit 10AP is externally connected. Processing can be performed efficiently without providing a queue. This average time can be changed to an appropriate value by adjusting the degree of parallelism of the circuits or devices that supply packets to the ingress nodes 211 to 214.

  In addition, even when a plurality of packets are read from the register file 30R for one read packet, the nodes other than the exit node of the merge channel 40AP function as a queue for these, and efficiently process without providing a new queue. It can be carried out.

  Therefore, even if the number of stages in the data processing unit 10AP is relatively large, it may be advantageous.

  When the degree of parallelism is high, a large number of data is used simultaneously. However, according to the data processing unit 10AP of the ninth embodiment, a relatively large number of registers can be selectively used in a plurality of processing elements. As described above, since random access can be performed with high throughput, there is an effect that processing can be performed efficiently.

  Conventionally, a matching memory equipped with a FIFO memory, a hash memory, an associative memory, a calculation unit, a control unit, and the like waits for packets of the same color and processes them with processing elements. However, in the ninth embodiment, since packet pairs are continuously joined, there is no need to use a matching memory, and the configuration is simplified and the throughput is increased. Play.

  In FIG. 18A, when the data read from the register file 30R for the packet P1 is, for example, 8 words as in the above-described read packet, the data is congested on the communication path. In this case, if the number of operation result packets is small, the data congestion degree on the downstream side can be reduced.

  Therefore, in the data processing unit 10BP of the processor of the present invention, in FIG. 19, each node of the combined channel 40BP is provided with a processing element, and the calculation is performed at the node where the packets P1 and P2 (FIG. 18) merge on the combined channel 40BP. And transfer the result downstream.

  The thick line shown in FIG. 19 indicates the route of the packet pair in the first system and the fourth system. These routes are determined by the destination address DA and the system CH. If the system CH is determined so that the path on the branch channel 20A and the path on the merge channel 40BP are logically symmetric with respect to the register file 30R, the merge point on the merge channel 40AP is determined only by the destination address DA. The branch point on the branch path 20A corresponding to this junction is determined by the number of coincidence bits from the most significant bit of the destination address DA of the packet pair.

  For example, the coincidence portion of the destination address bits DA1 and DA2 of the upper packet pair paths T1 and T2 in FIG. 19 is “10” of the upper 2 bits as shown in FIG. When the number of coincidence bits is represented by i, the packet pair branches at the (i + 1) -th stage on the branch channel 20A, and the packet pair joins at the (6-i) -th stage on the junction path 40AP.

  The packet merge stage identifier is represented by the value i as shown in FIG. 19, and each node on the merge channel 40AP has a fixed merge stage identifier value, which matches the merge stage identifier MA of the packet pair. If so, the packet pair is processed by the processing element of the node. FIG. 20 (B) shows a format of a packet including the merge stage identifier MA. As shown in FIG. 19, the branch stage ID on the branch channel 20 </ b> A used in a later embodiment is also represented by the value i.

  The determination of the merge stage identifier MA is performed in the nodes 201 to 204 on the rear stage side of the branch channel 20A. When a loop is configured as shown in FIG. 18B, the arrangement positions of the nodes 201 to 204 may be downstream of the combined flow path 40AP.

  FIG. 21 is a schematic block diagram showing the configuration of the node 201.

  In addition to the basic configuration of the latch 201L and the transfer control circuit 201C, the node 201 includes a packet pair determination unit 201P and a merging stage ID determination unit 201F.

  The packet pair determination unit 201P latches when the output of the latch 201L and the subsequent data output are fixed, that is, when SEND2 output from the node 201 and SEND1 supplied to the transfer control circuit 201C are simultaneously active. If the packet type PT (FIG. 20B) included in the downstream packet and the upstream packet of 201L indicates the first operand packet and the second operand packet, respectively, it is determined that the packet is a packet pair.

  In response to this determination, the merging stage ID determination unit 201F determines the merging stage identifier MA as described above based on the destination addresses DA of both packets, and supplies the merging stage identifier MA to the downstream latch. The identifier MA is fetched and held in the latch of the node 211 in FIG.

  When processing according to the command included in the first packet is performed on the read packet pair (first operand packet and second operand packet), each read packet is shown in FIG. The data field data DATA shown in B) is empty. On the other hand, since the flow path width on the entrance node side is relatively narrow in the branch path 20B, it is likely to be crowded if the number of packets is large. Further, even if packet pairs are sequentially supplied to the branch path 20B, the first node is given priority at the joining node, so it is conceivable that another packet may interrupt between the packet pairs.

  Therefore, the read packet pair is compressed into one packet as shown in FIG. In the figure, addresses ADR1 and ADR2 are a first operand address and a second operand address, respectively. These high-order bits are fields common to the first and second operand packets before compression, except for the destination addresses DA1 and DA2, thereby increasing the compression rate.

  In FIG. 22A, destination addresses DA1 and DA2, which are the upper bits of addresses ADR1 and ADR2, are located at positions away from page addresses PA1 and PA2, respectively. This is because it is divided into functional module layer data other than. The communication path layer control data is used only in the communication path, and the functional module layer data is used in a register file 30R as a functional module and a processing element included in each node on the combined path 40BP. Since the destination address of the compressed packet is the higher-order coincidence bit of DA1 and DA2, only one of them is sufficient, but since it is used in the nodes 201 to 204 described above, both are used as communication path layer control data.

  Here, since the destination addresses DA are generally different between the addresses ADR1 and ADR2, in FIG. 19, it is necessary to expand the compressed packet into a packet pair at the branch point of the packet paths T1 and T2 on the branch channel 20A. Which stage branches is determined by the value of the joining stage identifier MA (= branch stage identifier) determined by the nodes 201 to 204 as described above.

  Therefore, each node of the branch channel 20A has a function of expanding the compressed packet into a packet pair, and a fixed branch stage identifier is assigned to the node, and the merge stage identifier MA (= branch stage identifier) in the packet is assigned. When the value matches the branch stage identifier of the node, the compressed packet is expanded into a packet pair.

  Packets 50E and 50F obtained by expanding the compressed packet 50D of FIG. 22A into packet pairs are shown in FIGS. 22B and 22C, respectively. The packet 50E can use the packet 50D as it is. Accordingly, a copy of the packet 50D is first transferred to the next stage as a packet 50E. Next, the destination address bit DA1, the page address PA1, and the word address WA1 in the packet 50D are rewritten to the destination address bit DA2, the page address PA2, and the word address WA2, respectively, so that the packet 50F is transferred to the next stage.

  Next, for the read data packet read for one page from the register file 30R and the write packet for one page to the register file 30R, the format of the top packet is the same as that of the packet 50E, and FIG. The eight packets 50G having the format shown in FIG. Then, the packet 50G is transferred along the trajectory of the packet 50E, and the destination direction is not switched at each node, so that these nine packets are made continuous without being interrupted by other packets during the transfer.

  In order to allow such a transfer, on the one hand, each packet is provided with one concatenated bit CN. When the concatenated bit CN is “1”, it indicates that there is a subsequent packet, and when it is “0”, it indicates that there is no packet. FIGS. 23A and 23B respectively read the first operand packet (the first operand packet copied in the register file 30R) which is the first packet having the packet type PT of “0” and the subsequent packets. And an 8-word read data packet. FIGS. 23C and 23D respectively read the second operand packet (the second operand packet copied in the register file 30R) which is the first packet having the packet type PT of “1” and the subsequent packets. And an 8-word read data packet.

  The value of the order bit OD is determined in the functional element array 30R depending on whether or not the order needs to be maintained after leaving the branch flow path 40BP.

  On the other hand, each node on the joint channel 40BP is provided with a flip-flop (node-side connection bit) corresponding to the connection bit CN, and the state of this flip-flop is controlled as follows.

  FIG. 25 is a block diagram showing the state control circuit 47 for the node-side connection bit F1 of any merging node N1 other than the inlet node and the outlet node on the merging channel 40BP and elements related thereto. The flip-flops of the nodes N01 and N02 at the subsequent stage of the merging node N1 and the node N2 at the preceding stage are denoted as F01, F02, and F03, respectively.

  The joining node N1 preferentially selects and latches a packet from the node N01 as a first-priority exception if the flip-flop F01 is “1”, and a first-priority exception if the flip-flop F02 is “1”. Then, the packet from the node N02 is preferentially selected and latched.

  The state control circuit 47 controls the state of the node-side connection bit F1 as follows, so that when one of the flip-flops F01 and F02 is first “1”, the other is later “1”. Do not become.

  (1) The state control circuit 47 sets the flip-flop F1 to “1” when the flip-flop F2 is “0” and the concatenated bit CN of the packet latched by the node N1 is “1”.

  (2) If the concatenated bit CN of the packet latched by the node N1 is “0”, the state control circuit 47 sets the flip-flops F01 and F02 to “0”.

  (3) In the state control circuit 47, the concatenated bit CN of the packet latched by the node N1 is “0”, and the joining stage identifier of the node N1 matches the joining stage identifier MA of the packet held in the node N1. Then, the flip-flop F1 is set to “0”.

  The state control circuit 47 for the flip-flop F1 at the inlet node on the combined flow path 40BP performs only the processes (1) and (3). The state control circuit 47 for the flip-flop F1 at the exit node on the combined flow path 40BP performs the above processes (2) and (3), and regarding the above (1), the flip-flop F2 is considered to be '0'. I do.

  FIG. 24 shows the flip-flop set in this way by “1” on the node.

  Each processing element has a queue for holding a packet of 9 words × 2 to be processed. At the joining node of two sets of concatenated packets, the flip-flop is set to “1” first on a first-come-first-served basis. Nine packets from the new node can be captured and held continuously, and then the flip-flop of the other node becomes '1', so that 9 packets from this node can be captured and held continuously. It is possible to prevent one of a set of concatenated packets from being mixed into the other or another packet from being mixed into a concatenated packet.

  That is, 9 packets of the first operand and 9 packets of the second operand are connected to each other, and are connected to each other, and these are held in the processing element and processed. In this processing element, if there are two processing results, ie, the first operand packet and the second operand packet, the processing result is compressed as described above into one packet, thereby congesting packets on the downstream side. Can be avoided, and the packet can be prevented from being interrupted.

  Similarly to the case of the read data packet, the flip-flop causes the data packet to be transferred through the node “1” with respect to the 9-connected write packet on the branch channel 20A. In this case, since the interrupt to the concatenated packet does not occur in the shunt node, the state control circuit becomes simpler than that of the junction node. As for write packets, since computation between packets is not performed, the lower 11 bits in FIG. 22B are changed to 32 bits without using concatenated bits, and write processing may be performed in units of packets. Good.

  With respect to the concatenated packet, the order is maintained in the concatenated packet by the above configuration.

  However, first packet first packets, connected packets, and single packets and connected packets have first-come-first-served priority. The packet order at the input node of the shunt channel is not always the same. Between different systems, the packet system value is determined by the node position at the entrance node of the diversion channel and the exit node of the merge channel, so that the packet order does not matter.

  Next, a case where the packet order is maintained in the same system will be described as a twelfth embodiment of the present invention.

  In FIGS. 26A to 26C and FIGS. 27A and 27B, a circle indicates a packet, a symbol in the circle indicates a packet ID, and an arrow indicates a direction in which the packet proceeds. Packets with the same code are not the same packet, but correspond to each other. The packet ID is, for example, a stream ID to be processed. For simplicity, only one system is shown in these figures.

  In the data driven type processing circuit, as described above, different packets to be processed can be distributed and processed in parallel in each pipeline stage in the same loop.

  As shown in FIG. 26A, consider a case where the process PR1 is performed in the portion 101 on the loop 100, and then the process PR2 is performed in the portion 102 on the loop 100. The loop 101 may include one system having a configuration as shown in FIG.

  When the result of the process PR1 is used in the process PR2 or the result of the process PR2 is used in the process PR1, as shown in FIG. 26B, the loop 100 is divided into a loop 101A of the process PR1 and a loop 102B of the process PR2. By combining these at the combination node 103, the combination node 103 waits for the corresponding packets and transmits information from at least one to the other, so that at least one of the processing results is used by the processing PR1 and PR2. To do.

  Accordingly, one serial processing in FIG. 26A becomes two parallel processing, and the number of pipeline stages in the loop is reduced. Therefore, if the waiting time at the coupling node 103 is short, the throughput is improved.

  For example, when the packet 6 on the loop 101A is latched by the joining node 103, if the corresponding packet 6 on the loop 102A arrives at the joining node 103 immediately, the result can be received and moved to the next node immediately.

  However, for example, the packet 5 on the loop 101A overtakes the packet 6 and waits for the packet 5 on the corresponding loop 102A to obtain the result. After leaving the joining node 103, the packet 6 on the loop 101A joins. When latched by the node 103, the packet 6 on the loop 102A is after passing through the joining node 103, so that the result cannot be used.

  In order to avoid this, if the packet is temporarily stored and the content of the packet is acquired from the packet, the processing is delayed and the packet having the matching ID must be searched by sequential comparison, which makes the configuration complicated. At the same time, the processing time becomes longer, and the meaning of parallelization is lost.

  If the order of the packets is maintained, the processing result of each corresponding packet can be used without confirming the ID of the partner packet at the joining node 103, the throughput is improved, and the data width of the packet is increased. The circuit scale can be reduced by shortening, and further componentization is possible, so that the system can be easily constructed.

  The packet on the loop 102A may be a constant that is not processed. That is, the loop 102A may be a ring queue (circulation queue).

  For example, the first packet is input on the loop 101A, the second packet related to the first packet is input on the loop 102A, and the combining node 103 combines the command or specific bit included in the packet in the loop 101A. When the output from the node 103 indicates that the branch direction is the output side, the packet is taken out from the loop 102A corresponding to this, and the second packet together with the packet of the processing result corresponding to the first packet in the loop 101A Take out. Thereby, it is not necessary to always accompany the second packet on the loop 101A, and the configuration is simplified.

  When the loop 102A is a ring queue, the loop 101A can use the loop 102A as a stack. Even if there are a plurality of packets on the loop 102A corresponding to the loop 101A, the number n is included in the packet on the loop 101A, and when the SEND-IN on the loop 102A side becomes active in the joining node 103 The correspondence can be maintained by repeating this n times with the ACK-OUT on the loop 102A side active and the ACK-OUT on the loop 101A side maintained inactive.

  That is, the packet of the loop 101A includes the information of the number n, and one packet of the loop 101A is made to correspond to the n packet of the loop 102A by transferring one packet and transferring n packets of the loop 102A. If the command or specific bit of the packet in the loop 101A indicates that all or part of the packet (processing result) is copied and input to the loop 102A, the joining node 103 executes this and executes the loop 101A. The number n included in the packet is incremented (this may be performed by another node).

  In the above case, if the order synchronization cannot be achieved, the loop 102A cannot be provided, and the packet on the loop 101A must be connected by connecting the corresponding packets on the loop 101A. As the throughput decreases, the configuration and processing of the loop 101A become complicated.

  The order synchronization need not be performed for all packets depending on conditions. In such a case, as shown in FIG. 22, an order bit OD for order control is provided in the packet, and when this is “1”, it is determined that there is order control, and when it is “0”, there is no order control. When the joining node 103 waits for a corresponding packet on the loop 102A, if the order bit OD is “0”, the ACK-OUT on the loop 102A side is activated when the SEND-IN on the loop 102A side is active. By passing this, packets that do not require sequence control can be mixed on the loop 102A. The same applies to the loop 101A.

  The packets A to D in FIGS. 26 and 26 indicate that the order bit OD is “0”, and the other packets 1 to 6 indicate that the order bit OD is “1”.

  Note that it is only necessary to be able to handle the packets between the loops, so that the initial packet input to the loop 101A and the initial packet input to the loop 101B may be performed by different nodes.

  The loops 101A and 102A include conditional branch nodes, and information on the packet is extracted from the loop to the outside according to the command included in the packet or the value of the specific bit.

  FIG. 26C shows a more complicated relationship loop.

  In this example, it is assumed that the loops 101A and 101B are joined by the joining node 103A, and the packet on the loop 101A moves to the loop 101B or vice versa depending on the conditions. Similarly, it is assumed that the loops 102A and 102B are coupled by the coupling node 103A, and a packet on the loop 102A moves to the loop 102B or vice versa depending on the condition. In addition, it is assumed that packets with the same code cannot exist at the same time and exist in one of the loops at a certain time. Further, it is assumed that the packets 1 to 3 correspond to the packets 4 to 6, respectively.

  Even in such a complicated case, for example, when the packet 3 on the loop 101A moves to the loop 101B through the coupling node 103A, the packet 6 corresponding to the packet 3 moves from the loop 102A to 102B on the coupling node 103A. The above-described advantages can be obtained by moving the packets in the same manner and synchronizing the packet order.

  In order to shorten the waiting time and increase the processing speed of the order synchronization, as shown in FIG. 27A, the loops 102A and 102B are coupled via the queues 104 and 105, and the packet of the processing result is sent. It is only necessary to store them sequentially in the queue so that the other party can immediately take them out. In order synchronization, since the order can be predicted, the processing results can be used immediately by putting the processing results in a queue in advance.

  Dividing the loop as described above enables not only hardware componentization but also hierarchical structure. That is, as shown in FIG. 27B, if the above-described queues 104 and 105 are processed by the loop 106 of the upper hierarchy, a hierarchical structure is obtained. In this example, the processing result in the upper layer loop 106 is fed back to the lower layer loops 101A and 102A via the queues 107 and 108, respectively.

  Since the above is true for each system, it can be applied to each of a plurality of systems.

  Although the loop process is efficient, the process may not be a loop because order synchronization can be applied even when passing through the loop once.

  Conventional data-driven processing devices can perform autonomous distributed processing with local synchronization, but there is no one corresponding to the system clock of the synchronous circuit, so even if it is superior to autonomous distributed processing, it cooperates He lacked sex and was a minor being. In the asynchronous circuit, maintaining the packet order and synchronizing the order between the loops corresponds to synchronizing the system clock in the synchronous circuit.

  In asynchronous communication in a macro network, even if the packet order in the communication path cannot be maintained, the order can be restored in the TCP layer by a high-level function in combination with a synchronous CPU and storage device and software. Can perform autonomous distributed cooperative control with high-level functions regardless of direct relationship. On the other hand, in a data driven processing apparatus in which a micro network is internally configured, maintaining the order of packets is the basis of cooperative control.

  The order synchronization of the present invention greatly contributes to the enhancement of the functionality of a data driven processor by enabling cooperative control with a simple configuration while maintaining parallel processing by autonomous distribution.

  In order to realize the order synchronization, it is necessary to maintain the order of the packets in the same system on the loop communication path. A configuration example in which order merging is performed in order to maintain the packet order will be described as a thirteenth embodiment of the present invention.

  Even if the branching node branches in a direction where the packet is not congested and goes ahead, the same system then joins. The disorder of the packet order in the same system is caused by the packet overtaking at the node that selectively joins, that is, the packet order at the branch node is different from the packet order at the corresponding joining node.

  In order to examine what this difference corresponds to, attention is paid to the packet traveling direction at the branch node and the corresponding junction node. For example, a packet passing through the node 433P on the combined flow path 40BP in FIG. 28 passes through the node 243 on the corresponding branch path 20A before that. There is a regularity in which the packet proceeds from the node 243 to the next stage, and from which of the subsequent stage of the node 433P the packet proceeds to the node 433P. In FIG. 28, this relationship is symmetric with respect to the register file 30R. However, the relationship is not necessarily limited to this, and any logical correspondence may be used.

  For the sake of simplicity, consider a read packet and a corresponding read data packet when the read data packet is one word. If the order of the packets is maintained, the order of the branching direction at the node 243 of the packet that sequentially passes through the node 243 corresponds to the order of the branching direction at the node 433P of the packet that sequentially passes through the node 433P.

  If the packet order is maintained for all the systems, this correspondence relationship is established between an arbitrary joining node on the joint channel 40BP and a branch node (node pair) on the branch channel 20A corresponding thereto. If there is a disorder in the order between two packets, the corresponding relationship is not established in any node pair.

  Therefore, the node switching on the combined flow path 40BP is switched to the node switching information on the branch flow path 20A corresponding to this so as to maintain this correspondence relationship for all the node pairs (switching information at the time point before N stages). The packet order is maintained by controlling based on. However, regarding the outlet node of the branch channel 20A and the inlet node of the combined channel 40BP, N = 0, and the correspondence is already maintained. In the case of FIG. 28, N is 2, 4, 6, 8, and 10.

  In FIG. 28, for example, the trajectories of packets going up and down the node 243 are T1 and T2, respectively. Assume that the packet of the trajectory T1 is first held in the node 243, and then the packet of the trajectory T2 is held in the node 243. Assume that the packet is congested on the trajectory T1, the packet is covered on the trajectory T2, and the packet of the trajectory T2 arrives at the subsequent stage of the node 433P. In this case, information that the node 243 is switched to the upper side is transmitted to the node 433P, the node 433P waits for a packet from the upper side, and after this is held in the node 433P, the information that the node 243 is switched to the lower side is If the packet is transmitted to 433 and then the node 433P waits for a packet from the lower side, the packet order is maintained. If such control is performed for all node pairs, the order of packets is maintained at least within the same system.

  FIG. 29A shows a configuration provided between an arbitrary node 110 excluding the entrance node of the combined flow path 40BP for maintaining this order and the node 111 on the branch flow path 20A corresponding thereto. FIG. 30 is a detailed block diagram of FIG.

  In FIG. 29A, a flow path through which a packet can flow between the node 110 and the node 111 is represented as a branch / merging node 112.

  In this configuration, a queue 113 is provided between the nodes 110 and 111. If OD = '1', the corresponding bit DAi of the destination address DA indicating the branch destination direction from the node 111 (upper branch in the figure). "1" at the time of "1" and "0" at the time of the lower branch) are supplied to the data input terminal of the 1-bit latch of the input stage 113a of the queue 113. The data driven queue 113 has a buffering action that automatically fills if there is an empty in the middle by the handshake protocol used in the transfer control circuit, so the number of stages is between the nodes 111 and 110. The number of pipeline stages may be N or more. Data may be extracted sequentially from the output stage of the queue 113, and there is no need to consider the number of stages N when extracting.

  The configuration of the node 110 and the subsequent stages 115 and 116 is substantially the same as the corresponding configuration in FIG. That is, the multiplexer 110M is connected to the input side of the latch 110L in the node 110, which corresponds to the configuration of the output side gate and the output enable control input terminal OE in the latches 421L and 422L in FIG. . The difference from FIG. 4 is that the selection control of the multiplexer 110M is performed by the latch output SEL of the output stage 113b of the queue 113 in FIG.

  The configuration of the node 111 and the subsequent stages 117 and 118 is the same as the corresponding configuration of FIG. 3 except for the transfer control circuit 111C of the node 111. The transfer control circuit 111C of the node 111 is different from the transfer control circuit 211C in that signals are also exchanged with the transfer control circuit of the input stage 113a of the queue 113.

  30 is a part obtained by removing the nodes 115 to 118 from the branch / merging circuit 112 in FIG. 29 (A).

  When the SEND from the node 111 to the next stage node 117 or 118 is activated, the SEND to the input stage 113a of the queue 113 is simultaneously activated. In other words, the transfer control circuit 111C of the node 111 is connected to the next stage 117 or 118 and the input stage 113a when the ACK from the next stage 117 or 118 and the input stage 113a is both active and the SEND from the subsequent stage is active. Activate SEND.

  The node 110 selects one of the latch outputs of the subsequent stages 115 and 116 of the node 110 based on the output of the output stage 113b of the queue 113 out of the two inputs. That is, if the output SEL of the output stage 113b of the queue 113 is “1”, the data from the node 115 on the upper stage of the node 110 is selected, and if it is “0”, the node 116 on the lower stage of the rear stage of the node 110 is selected. Select data from. This selection is performed by selectively controlling the multiplexer 110M of the node 110 by the latch output SEL of the output stage 113b of the queue 110.

  When node 110 subsequently activates an ACK to stage 115 or 116, it activates an ACK for output stage 113b of queue 113. That is, the node 110 receives the latch 110L of the node 110 when both SEND from the subsequent stage 115 or 116 of the node 110 and SEND from the output stage 113b of the queue 113 become active and ACK from the next stage of the node 110 becomes active. The data is fetched and held in ACK, and both the ACK to the output stage 113b of the queue 113 and the subsequent stage 115 or 116 of the node 110 are made active.

  In FIG. 29B and FIG. 30, when DAi = “1”, the node 111 branches and transfers the packet to the node 117 (this branch is the first stage) and DAi = “1” to the input stage 113a of the queue 113. Let 's forward. After N stages, a packet corresponding to this is held on the node 115 on the one hand, and on the other hand, SEL = '1' corresponding to DAi = '1' is supplied to the selection control input terminal of the multiplexer 110M, and the node 110 selects the node 115 side. The same applies to FIG. 29C.

  Here, with respect to the write packet, the writing to the register file 30R is completed, and the corresponding packet is not transferred to the merge channel 40A side, so the order bit OD of this packet is set to “0”. When the order bit OD held in the latch 111L of the node 111 is “0”, the transfer control circuit 111C maintains SEND in the queue input stage 113 inactive. As a result, since the bit DAi is not transferred to the latch of the input stage 113a of the queue 113, the order maintenance is not changed.

  On the other hand, when one packet on the branch channel 20A side corresponds to a plurality of packets on the combined channel 40BP side like a read packet, it is necessary to maintain this correspondence also in the queue 113. In order to maintain this correspondence, the transfer control circuit 110C of the node 110 maintains the ACK to the output stage 113b of the queue 113 inactive, except when the concatenated bit CN is “1”. Thereby, it is possible to maintain the switching correspondence between the node 110 and the node 111 for the connection packet. Although the concatenated bit CN of the end packet of the concatenated packet is “0”, the concatenated bit CN of the previous packet is “1”, so as shown in FIG. However, the selection direction of the node 110 does not change.

  FIGS. 31A to 31J show the flow of one read packet on the branch flow path 20A side and the flow of a plurality of read data packets (concatenated packets) on the side of the combined flow path 40BP corresponding to this. Show. “1” in the figure indicates the value of the above-described node-side flip-flop. FIG. 31A collectively shows data transfer for four stages.

  (1) In FIG. 31A, if DAi = '1', data is transferred from the node 111 to the next upper stage ('1' side) 117, and if OD = '1', the destination address DAi Is transferred to the input stage 113 a of the queue 113.

  (2) In FIG. 31E, the concatenated leading packet is captured and held in the upper stage 115 following the node 110, and DAi = '1' held in (1) is captured in the output stage 113b of the queue 113. The multiplexer 110M of the node 110 selects data from the node on the upper stage 115 after the node 110 in response to “1” to the selection control input terminal.

  (3) Thereby, the node 110 captures and holds this data in FIG.

  (4) Thereafter, while the value of the concatenated bit CN of the packet held by the node 110 is “1”, the ACK from the transfer control circuit 110C of the node 110 to the queue 113 is maintained inactive, and the queue 113 The output SEL = “1” of the output stage 113b is maintained, and the concatenated packets sequentially reach the node 110 from the node 115 (FIG. 29).

  In this way, the order control information DAi → SEL is transmitted from an arbitrary node of the branch flow path 20A to the corresponding node of the combined flow path 40BP, and selection control is performed at the merge node accordingly, thereby The order of the packets is maintained for the system.

  Therefore, according to this configuration, the configuration described in FIGS. 26 and 27 can be realized to achieve the effect.

  The order bit OD can also be used as the order bit OD described with reference to FIGS.

  In addition, the pair of the node 110 and the node 111 on which the order merge control of the present invention is performed is not limited to the corresponding node pair of the tree-shaped branch channel and the tree-shaped merge channel, and if the first packet passes through the branch node, The second packet corresponding to the first packet passes through the junction node, and the branch direction of the first packet at the branch node corresponds to the junction direction of the second packet at the junction node; A pair of a branch node and a merge node that satisfy the condition that the number of pipeline stages between the branch node and the merge node is N (N ≧ 1) may be used.

  Further, although the packet passing through the node 110 corresponds to the packet passing through the node 111, both of these correspondences may be the same packet.

  Next, a CPU accelerator that performs a finite automaton operation will be described as an application example of the data driven processing apparatus of the present invention.

  Finite automata are used in various fields such as linguistics, information engineering, biology, mathematics, and logic. In the finite automaton, the next state is determined based on the current state and the input, and this state transition is repeatedly performed to determine whether or not the pattern matches.

  FIG. 37 is a state transition diagram showing an example of a simple finite automaton.

  In this example, it is determined whether or not the pattern “ABA” or “ABC” of the search data set RD is included in the data stream DS = “CAABABABCCCCBBABACC”. When the element “A”, “B” or “C” in the data stream DS is input to the current state, the next state is determined, and the process of inputting the next element to this is repeatedly performed and output. The time state corresponds to the detection pattern. The element is not limited to a character code, and may be data having a predetermined data width.

  In the virus detection example, each of the patterns included in the search data set RD corresponds to a virus. The pattern matching process of which of the many viruses the input data stream DS is infected with can be represented by one state transition diagram (pattern mulching).

  Hereinafter, a case where the finite automaton is applied to virus detection will be described. However, the CPU accelerator of the present invention is not limited to this, and can be applied to all finite automata.

  In the apparatus of the present invention, since the degree of parallelism is high, a large number of input data streams DS can be handled simultaneously.

  FIG. 32 shows a state transition table in which a row is a state S and an input column is a 1-byte stream element SE constituting a data stream. However, this state transition table includes a 1-bit result bit R.

  A memory in which the next state is stored at an address having the state S as the upper bit and the stream element SE as the lower bit is used. In hexadecimal notation, for example, when the initial value of the state S is “0000” and the stream element SE is “01”, the next state S is “0002”. The next state S is determined by this and the next stream element SE.

  The result bit R is 1 bit, and R = '1' when a virus pattern is detected. The address specified in the state S at this time does not have the next state, and stores the virus code VC. The CPU manages the virus name corresponding to the virus code VC. The result bit R serves as a command in the packet.

  FIG. 33 is a schematic block diagram showing a data driven CPU accelerator 60Q according to the fourteenth embodiment to which the present invention is applied.

  The state table memory 120 has, for example, a larger storage capacity of the memory 10B in FIG. 8, and the branching channel 121, the memory row array 122, and the combined channel 123 are respectively connected to the branching channel 20B, the memory row array 30, and the like in FIG. This corresponds to the combined flow path 40B. The read data packet corresponding to the read packet is one word as will be described later, and these formats are different from those described above. The memory row array 122 stores the table of FIG.

  FIG. 35 is a diagram showing a data flow regarding one system in the apparatus of FIG. 33 together with a data format.

  The system CH is a constant used in the combined channel 123 as described above. The result bit R and the state S are data read from the state table memory 120, and the address of the state table memory 120 is designated by this and the stream element SE as a lower bit. A plurality of data streams can be processed in each system, and the stream identifier SID is 3 bits in this example. The stream identifier SID and the system CH are a loop including the state table memory 120, and are unchanged for the same stream.

  Returning to FIG. 33, the plurality of data streams are temporarily stored in the RAM 126 as a buffer by the DMAC via the interface 124 and the memory controller 125, and then the contents of the RAM 126 are changed by the CPU 127 via the interface 124 and the memory controller 125. The data is read and supplied to the queue array 132 via the memory controller 125, the interfaces 124 and 128, and the diversion channel 131 of the stream buffer 130, and is held. The CPU 127, the RAM 126, the memory controller 125, and the interface 128 are synchronous, and the interface 128 includes a mutual conversion unit between a synchronous type and an asynchronous type.

  FIG. 34 is a schematic block diagram of the stream buffer 130 in FIG.

  The branch flow path 131 and the combined flow paths (multiplexers) 1330 to 1333 of the stream buffer 130 are extracted from the third to fifth stages of the divided flow path 20 of FIG. 1 and extracted from the second to fourth stages of the combined flow path 40, respectively. Is the same. The shunt flow path 131 is for reducing the number of terminals of the interface 124. In this example, four sets are provided, but one or more sets may be used.

  As shown in FIG. 35, the format of the packet supplied to the diversion channel 131 includes a 3-bit stream identifier SID field and an 8-bit stream element SE field.

  The stream identifier SID is associated with 8 queue IDs of 4 queues × 8 queue arrays 132. By associating such a queue ID with the stream identifier SID, the stream identifier SID used as the lower 3 bits of the destination address 5 bits in the branch channel 131 becomes unnecessary after exiting the branch channel 131. Only the bit stream element SE is retained. The multiplexers 1330 to 1333 select one of the eight queues of the systems 0 to 3 and supply them to the nodes 140 to 143, respectively. This selection is performed by a control signal obtained by decoding SID0 to SID3, which are stream identifiers SID included in a packet to be transferred to the diversion channel 121, by decoders 145 to 148, respectively.

  The multiplexers 1330 to 1333 can use a normal configuration, but may use a combined flow path of 8 inputs and 1 output as shown in FIG. In this case, it is only necessary to decode the stream identifier SID and activate ACK only for the output stage of one corresponding queue among the eight queues. The decoder in this case can use a diversion channel with 1 input and 8 outputs.

  When each queue constituting the queue array 132 becomes half-empty, this is detected by the half-empty detection circuit 134 and the queue CH and the stream identifier SID are sent to the CPU 127 via the interfaces 128 and 124. The interrupt request IRQ2 is activated. As a result, the CPU 127 reads data from the RAM 126 and replenishes it to the queue of the corresponding system CH and stream identifier SID. DMA transfer from the RAM 126 to the interface 124 is possible.

  The half sky detection can be detected, for example, when the difference between the number of SEND-OUT pulses at the head of the queue array 132 within the set time and that at the intermediate portion is a predetermined value or more. In addition, for each queue of the queue array 132, the number of output packets (the number of latch pulses) and the number of supplied packets (the number of latch pulses) are counted. The configuration may be such that the load request IRQ2 is activated. Of course, it may be detected that a predetermined percentage of the queue is not half empty.

  The packets of the nodes 150 to 153 need not include the result bit R. Each of the synthesis nodes 140 to 143 is supplied with packets from the nodes 150 to 153 on the one hand, and these stream identifiers SID are supplied as selection control signals for the multiplexers 1330 to 1333 as SID0 to SID3, respectively, and on the other hand, the multiplexers 1330 to 1333. Are added to the synthesis nodes 140 to 143 and synthesized, and are taken in and held by the synthesis nodes 140 to 143.

  The outputs of the synthesis nodes 140 to 143 are transferred to the branch channel 121. The synthesis nodes 140 to 143 may be omitted, and the inlet node of the branch path 121 may be used instead.

  An initial packet from the CPU 127 via the interfaces 124 and 128 and a packet from the merge channel 123 are selectively joined to the nodes 150 to 153. This initial packet is for activating the CPU accelerator 60Q. In FIG. 35, for example, S = 0 and R = 0, and a system CH and a stream identifier SID are given for each system.

  The value of the stream identifier SID may be any value as long as the CPU 127 supplies the data stream to the queue array 132 via the interfaces 124 and 128 and the diversion channel 131, and can be determined by the CPU 127.

  The CPU 127 sequentially supplies one or a plurality of initial packets to each of the nodes 150 to 153. At this time, the CPU 127 inactivates the ACK for the corresponding exit node of the combined path 123 and stops the flow of packets from the exit node. Then, when this stop is released, the packet is pipelined in a loop including the state table memory 120. In this embodiment, the maximum number of initial packets for each system is eight. Actually, since packets can be distributed in a loop, the maximum value can be obtained by adding 2 to the total number of stages in the state table memory 120.

  The output of the exit node of each system in the combined flow path 123 of the state table memory 120 is supplied to the output circuit 160.

  When any of the four system result bits R becomes “1”, the output circuit 160 captures and holds the system CH, the stream identifier SID, and the virus code VC, supplies them to the CPU 127, and requests an interrupt. Activate IRQ1. For each data stream, if one virus is detected, processing for that stream can be aborted. In this case, the stream in which the virus is detected in the stream buffer 130 is flushed and / or the addition of this stream is stopped, and if there is an unprocessed stream, another stream is supplied to the stream buffer 130 and correspondingly. The initial packet is supplied as described above, and processing for the other stream is started.

  According to the fourteenth embodiment, since the CPU accelerator 60Q is configured as a data driven type, and the state table memory 120 and the stream buffer 130 operate in parallel, the parallelism of processing is high, the throughput is high, and the low Power consumption is suitable for various mobile devices.

  FIG. 36 is a schematic block diagram showing a sequence synchronization / data driven type CPU accelerator 60QA according to the fifteenth embodiment to which the present invention is applied.

  In this CPU accelerator 60QA, first, the branch flow path 131A of the stream buffer 130A is constituted by five stages of the six-stage flow path 20 of FIG. 1, and the branch flow path 131A from the interface 128A, on the one hand, via the branch node 163 On the other hand, the initial packet is supplied to the nodes 150 to 153 via the branching node 161 and the demultiplexer (branch channel) 162, thereby reducing the number of output terminals of the interface 128A.

  The packet at the node 161 has a bit indicating whether or not it is an initial packet and a system CH, and the packet branch destination at the node 161 is determined by the former. In the demultiplexer 162, the system CH is used as the destination address, which is unnecessary at the output node.

  Next, since the respective queues of the stream buffer 130A maintain the order, the CPU accelerator 60QA uses the state table memory 120A including the branch flow path 121A and the combined flow path 123A in which the above-described sequential merge control is performed. By maintaining the packet order in the state table memory 120A, the state table memory 120A and the stream buffer 130A are synchronized in order.

  Since the order of the packets output from the state table memory 120A is maintained, selection control for the multiplexers 1330 to 1333 can be reliably predicted. This order is determined by the order of initial packets that the CPU 127 supplies to the nodes 150 to 153 via the interfaces 124 and 128, the node 161, and the demultiplexer 162. That is, the order is determined by the CPU 127.

  The stream ID prediction circuit 163 includes a ring queue (not shown) for each system CH, and sequentially stores the stream identifier SID in the packet from the node 161 in this ring queue for each system CH. Based on the output, The stream identifiers SID0 to SID3 are supplied to the multiplexers 1330 to 1333, the packets in the ring queue are advanced by one stage, and this is repeated each time an ACK from the head of the queues 170 to 173 becomes active, so that A plurality of stream elements SE are fetched and held in 170 to 173.

  When combining nodes 140-143 activate ACKs to nodes 150-153, they simultaneously activate ACKs to the output stages of the corresponding queues 170-173.

  In this way, when a packet arrives at the synthesis nodes 140 to 143 from the state table memory 120A via the nodes 150 to 153, respectively, the packets from the queues 170 to 173 reach the synthesis nodes 140 to 143 at the same time. And the waiting time lag at the synthesis nodes 140 to 143 is eliminated, so that higher-speed processing can be performed than in the 14th embodiment.

  Note that in the synthesis nodes 140 to 143 due to the order synchronization, the stream IDs of the respective packets to be synthesized coincide with each other. Therefore, in the loop including the state table memory 120, it is not necessary to include the stream ID in the packet.

  In this case, since it is necessary to output the stream identifier SID when a virus is detected by the output circuit 160, a ring queue is provided in the output circuit 160 for each system CH as in the SID prediction circuit 163, and the stream ID is held in this. In response to the SEND pulse from the exit node of the combined path 123A, the ACK for the predetermined stage in the corresponding ring queue is activated to advance one packet at the predetermined stage, and is output from the exit node of the combined path 123A. Identify the stream ID of the packet.

  Further, the stream of packets output from the exit node based on the ring queue in the SID prediction circuit 163, the number of pipeline stages from the multiplexer 1330 to the exit node of the combined flow path 123A, and the number of SEND pulses from the exit node. An ID can also be identified.

  Furthermore, it may be used as a finite automaton device other than the CPU accelerator.

  If attention is paid to the fact that one of the features of the present invention is using a prediction circuit, the present invention can be applied even if the loop including the state table memory 120A is replaced with a loop of another function. Good.

  Note that the present invention includes various other modifications.

  For example, the present invention includes a configuration that can achieve the function of a configuration in which the combination of the components in each of the above-described embodiments or modifications thereof is changed.

  Further, a configuration may be adopted in which the destination address of the diversion channel is used as an instruction code of the processor, and processing means corresponding to the instruction code is arranged on the output side of the diversion channel. In this case, each line of the register file 30R can be used as a register group corresponding to the instruction code.

  Furthermore, the stream buffer 130 or 130A can be used to reverse the data flow in the stream buffer, classify the processing results in other loop components, and output them to the CPU or the like.

1 is a schematic block diagram illustrating an asynchronous (self-timed) data driven memory according to a first embodiment of the present invention. It is a figure which shows the specific example of the arrangement | sequence of a memory row array. It is a schematic block diagram which shows the shunt circuit comprised by the 1st stage and 2nd stage at the time of comprising a shunt flow path by a bundle data system. It is a schematic block diagram which shows the confluence | merging circuit which is a part of 2nd stage and 3rd stage at the time of comprising a confluence | merging path by a bundle data system. FIG. 3 is a schematic block diagram showing memory rows 31 and 32 connected between an output node 261 of the diversion channel 20 of FIG. 1 and an inlet node 411 of the merge channel 40. It is a schematic block diagram which shows the data drive type memory of Example 2 of this invention. (A) shows the format of a packet, (B) is explanatory drawing which shows the relationship between a system | strain and a packet flow. It is a schematic block diagram which shows the memory of Example 3 of this invention which doubled the number of input ports and output ports in the case of Example 2. FIG. It is a figure which shows the format of a packet. It is a schematic block diagram which shows the memory of Example 4 of this invention which reduced the number of pipeline stages. FIG. 10 is a schematic block diagram illustrating a 2-port input / 2-port output type memory according to a fifth embodiment of the present invention in which waiting for transfer to a selective junction node is shortened. It is a schematic block diagram which shows the memory of Example 6 of this invention which doubled the number of input ports and output ports in the case of Example 5. FIG. It is a schematic block diagram which shows the cache memory of Example 7 of this invention. It is a schematic block diagram which shows the structure of the adjacent tag row in a tag array. It is explanatory drawing of the operation | movement which the update packet waiting in an interface receives word data, writes it in the data field, and makes it a packet. It is a schematic block diagram which shows the cache memory of Example 8 of this invention. It is a schematic block diagram which shows the data processing part which is a part of processor of Example 9 of this invention. (A) And (B) is a schematic explanatory drawing which shows the flow of a process after throwing a packet pair into a branching channel inlet node. It is a schematic block diagram which shows the data processor which is a part of processor of Example 10 of this invention. (A) is explanatory drawing of the method of determining confluence | merging stage ID based on a packet pair destination address, (B) is explanatory drawing which shows a packet format. It is a block diagram which shows schematic structure of a confluence | merging stage identification node. (A)-(D) are packet format explanatory views according to Embodiment 11 of the present invention, (A) is a format of a packet pair compressed into one packet, (B) and (C) are 2 The format of the packet expanded, (C) is a diagram showing the data packet following the head of the concatenated packet. (A) and (B) are explanatory diagrams showing the first packet of the concatenated packet of the first operand and the following data packet, respectively. (B) and (C) are the first packet of the concatenated packet of the second operand and It is explanatory drawing which shows the following data packet. It is explanatory drawing which shows the state by which the connection bit with which the node of the joint flow path was set with the connection bit of a packet pair. It is a block diagram which shows the state control circuit with respect to the node side connection bit F1 of the node N1, and the element relevant to this. (A) to (C) relate to the twelfth embodiment of the present invention, (A) shows a data driven type processing loop, (B) shows a circuit obtained by dividing (A) into two parts and connected in parallel, (C ) Is a schematic diagram showing a circuit in which complex processing loops are coupled in parallel. (A) and (B) are diagrams showing transmission of processing results via queues between parallel processing loops in which order synchronization is established in the same layer and different layers, respectively. It is explanatory drawing of disorder of the switching order which arises between the node of a combined flow path, and the node of a shunt path corresponding to this according to Example 13 of this invention. (A) shows a configuration in which switching synchronization is performed with respect to an arbitrary node of a combined flow path with a node of a branch flow path corresponding to the node, and (B) and (C) are diagrams illustrating operations of this configuration. FIG. 30 is a detailed block diagram of FIG. (A)-(J) is explanatory drawing which shows the flow of one read packet by the side of a shunt flow path, and the flow of several read data packets (connection packet) by the side of the joint flow path corresponding to this in time. . FIG. 10 is a diagram showing a state transition table with an output command in which a row is a state S and an input column is a 1-byte stream element SE constituting a data stream. It is a schematic block diagram which shows the CPU accelerator of Example 14 of this invention. It is a schematic block diagram of the stream buffer in FIG. It is a figure which shows the data flow regarding 1 system | strain in the apparatus of FIG. 33 with a data format. It is a schematic block diagram which shows the order synchronization type | mold CPU accelerator of Example 15 of this invention. It is a state transition diagram showing an example of a simple finite automaton.

Explanation of symbols

10, 10A to 10E, 120, 120A Memory 10AP, 10BP Data processing unit 20, 20A to 20E, 71, 121, 131, 131A Split channel 201C, 211C, 221C, 222C, 261C, 411C, 311C, 312C, 3131C, 411C , 421C, 422C, 431C, 711C, 731C Transfer control circuit 201L, 211L, 221L, 222L, 261L, 311L, 311L, 3131L, 411L, 421L, 422L, 431L, 711L, 731L Latch 110, 111, 115-118, 201 ~ 204, 221 to 228, 221A, 222A, 223A, 224A, 231A to 234, 231A, 232A, 241, 248, 251, 261, 411, 411A, 411B, 421, 431, 44 1-444, 441A, 451-454, 441A, 442A, 443A, 444A, 451A, 452A, 453A, 454A, 461A, 461AP, 462A, 463A, 464A, 47, 711, 731, 77, 771-774, 82, N01, N02, N1, N2 Node 201F Merged stage ID determination unit 201P Packet pair determination unit 211-214, 411 Ingress node 222G, 261G1, 411G, 422G Inverter 251, 461-464 Egress node 261G2, 3131G OR gate 30, 122 Memory row Array 30R Register file 310, 740 Loop wiring 31, 32 Memory row 311, 741 Control circuit 311a, 310C Counter 310W, 311W, 312W, 313W, 320W Word memory 4 0, 40A-40E, 40AP, 40BP, 73, 123, 123A Combined flow path 47 State control circuit 50, 50A-50G, P1-P3, P1A, P2A, P1N, P2N Packet 60, 60A Cache memory 60Q, 60QA CPU accelerator 70 , 70A Tag table 72 Tag array 721, 722 Tag row 750-753, 75i Page information 760-763 Comparator 764 OR gate 765 Encoder 766 Multiplexer 80, 801-804 Input / output unit 81, 124, 128, 128A interface 100, 101, 101A, 101B, 102, 102A, 102B Loop 103, 103A Join node 104, 105, 113, 170-173 Queue 125 Memory controller 126 RAM
127 CPU
130, 130A Stream buffer 132 Queue array 1330-1333 Multiplexer 134 Half empty detection circuit 140-143, 150-153 Node 160 Output circuit 163 Stream ID prediction circuit 162 Demultiplexer CK Clock input terminal CK1, CK2 Clock pulse OE Output enable control input terminal CMD command ADR, ADR1, ADR2 Address DA, DA1, DA2, DAi Destination address DA0-DA5, CH0, CH1 Bit PA, PA1, PA2 Page address WA, WX, WA1, WA2 Word address DATA Data CN Concatenated bit OD Order bit HM , HM1, HM2 hit bit CH system PT packet type TA, TAG tag address CNT counter MA merge stage identifier PR 1, PR2 processing V Valid bit D Dirty bit L Lock bit R Result bit VC Virus code S State SE Stream element SID, SID0 to SID3 Stream identifier IRQ1, IRQ2 Interrupt request DS Input data stream RD Search data set F01, F02, F1 F2 flip-flop

Claims (12)

An upstream flow path for selectively transferring a packet supplied to an ingress node to one of a plurality of arranged functional elements according to a destination address of the packet, and a packet generated by the selected functional element In a data-driven processing device communication path device having a downstream flow path to be transferred to an exit node,
The upstream flow path selectively diverts the first packet supplied to the ingress node sequentially to a downstream node according to a destination address in the packet, and selectively selects one of the plurality of functional elements. It is a tree-shaped branch channel to be transferred,
The downstream flow path is a tree-shaped combined flow path that selectively combines the second packet corresponding to the first packet downstream from the selected one of the plurality of functional elements to reach the egress node. And
Each node of the tree-shaped branch flow path and the tree-shaped combined flow path constitutes a pipeline stage, and the number of pipeline stages of the tree-shaped branched flow path and the tree-shaped combined flow path is 3 or more, respectively. Communication path device for mold processing equipment. In the tree-shaped branch flow path, the tree-shaped branch flow path has a packet flow path having a destination address complementary to the destination address for a flow path of a packet having an arbitrary destination address. 2. The communication path device for a data driven processing device according to claim 1, wherein the communication channel device is formed. The tree-shaped combined flow path is formed such that a packet corresponding to the flow path that flows backward through the flow path exists in the tree-shaped combined flow path with respect to the flow path of the packet having the one destination address. The data-driven processing device communication path device according to claim 2, wherein: The packet has a systematic value;
The tree-shaped branch channel has the different entry nodes for each system, selectively joins packets from a plurality of systems at intermediate nodes, and each node of the output stage is common to each system,
In the tree-shaped joint channel, each node of the input stage is common to each system, and packets from a plurality of systems are selectively branched based on the system value at an intermediate node, and have different exit nodes for each system. ,
The communication path device for a data driven processing device according to claim 1. In the tree-shaped branch flow path, the tree-shaped branch flow path has a packet flow path having a destination address complementary to the destination address for a flow path of a packet having an arbitrary destination address. 5. The communication path device for a data driven processing device according to claim 4, wherein the communication channel device is formed. The tree-shaped combined flow path is formed such that a packet corresponding to the flow path that flows backward through the flow path exists in the tree-shaped combined flow path with respect to the flow path of the packet having the one destination address. The data-driven processing device communication path device according to claim 4 or 5, characterized in that The packet on the tree-shaped branch channel includes a packet side branch stage identifier,
Each node of the tree-shaped branch channel has a fixed node-side branch stage identifier, and determines whether the packet-side branch stage identifier corresponds to the node-side branch stage identifier.
The communication path device for a data driven processing device according to claim 6.   A branch stage identifier generation node is further provided on the upstream side of each entry node of the tree-shaped branching channel, and the branch stage identifier generation node is configured to be connected to the packet side based on each destination address value in a plurality of packets related to each other. 8. The data path processing device communication path device according to claim 7, wherein a branch stage identifier value is generated. A packet on the tree-shaped merge channel includes a packet side merge stage identifier;
Each node of the tree-shaped merge channel has a fixed node-side merge stage identifier, and determines whether the packet-side merge stage identifier corresponds to the node-side merge stage identifier.
The communication path device for a data driven processing device according to claim 6.   A merge stage identifier generation node is further provided on the upstream side of each inlet node of the tree-shaped branching channel, and the merge stage identifier generation node is configured to receive the packet side based on the value of each destination address in a plurality of packets related to each other. The data-driven processing device communication path device according to claim 9, wherein the value of the merging stage identifier is generated.   The data driven type according to any one of claims 6 to 10, further comprising a communication path that couples each of the plurality of exit nodes of the tree-shaped merge channel to the corresponding merge stage identifier generation node. Communication device for processing device.   The tree-shaped branch channel includes a next-stage node at a position where the tree-shaped branch channel is branched from each of the plurality of inlet nodes without being merged between the systems. A communication path device for a data driven processing device.

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