JP4509175B2 - Integrated circuit and packet switching control method - Google Patents

Description

  The present invention relates to an integrated circuit having a plurality of processing modules and interconnection means for coupling the plurality of processing modules, and a packet switching control method in such an integrated circuit.

  System on silicon continues to increase in complexity as new features are added and existing features are improved. This is made possible by further increasing the density of components integrated on the integrated circuit. At the same time, the clock speed at which the circuit operates tends to increase. Higher clock speeds, coupled with higher component density, have narrowed the region that can operate synchronously within the same clock range. This creates a need for a modular approach. In accordance with such an approach, the processing system has a plurality of relatively independent and complex modules. In traditional processing systems, system modules typically communicate with each other via a bus. However, as the number of modules increases, this communication technique is no longer practical for the following reasons. That is, on the one hand, an overload is created on the bus by a large number of modules, and on the other hand, the bus only allows one device to send data to the bus, so the bus creates a communication bottleneck. Forming.

  A communication network is an effective technique for solving these drawbacks. Network on chip (NoC) has recently received considerable attention as a solution to the interconnection problem in highly complex chips. The reason consists of two elements. First, NoC helps solve electrical problems in new deep submicron technology. This is because NoC builds and manages the overall wiring. At the same time, the NoC shares wiring to reduce the number of wirings and increase its utilization rate. NoC can also be energy efficient, highly reliable, and scalable compared to buses. Secondly, NoC separates computation from communication, which is essential in managing the design of a vast number of transistor chips. NoC can achieve this separation, although NoC is traditionally designed with a protocol stack, which provides a sophisticated interface that separates the use of communication services from the performance of services. This is because.

  However, when using a network for on-chip communication when designing a system on chip (SoC), a number of new issues must be considered. This is because, in contrast to existing on-chip interconnects (eg, buses, switches, or point-to-point wiring) where communication modules are directly connected, NoC communicates remotely via network nodes. . As a result, interconnect arbitration has changed from centralized to distributed, and issues such as out-of-order transactions, longer latencies, and end-to-end flow control can be attributed to intellectual property blocks ( intellectual property block (IP) or network.

  Most of these problems have already been the subject of research in the field of local and wide area networks (computer networks) and as parallel machine interconnect networks. Both are closely related to on-chip networks, and many of the results in those areas are also applicable to chips. However, NoC's premise is different from off-chip networks, so most of the network design options must be re-evaluated. On-chip networks have different characteristics (eg, tighter link synchronization) and constraints (eg, higher memory costs) that lead to different design choices, which ultimately affect network services .

  NoC differs from off-chip networks mainly in terms of their constraints and synchronization. In an on-chip network, computing is certainly expensive compared to an off-chip network. An off-chip network interface typically has a dedicated processor that executes the protocol stack up to the network layer or higher layers to free the host processor from communication processing. Including a dedicated processor in the network interface is not practical on the chip. This is because the size of the network interface is equal to or greater than the IP connected to the network. Furthermore, it may not be practical to run the protocol stack on the IP itself. This is because these IPs have only one dedicated function and often do not have the performance to execute the network protocol stack.

  The number of wires and pins connecting the network components is one digit higher on chip than off chip. If they are not used on a large scale for purposes other than NoC communications, they enable wide area point-to-point interconnections (eg, 300 bit links). This is not possible off-chip where the link is fairly narrow, from 8 to 16 bits.

  Introducing a network as an on-chip interconnect is a fundamental change in communication compared to a direct interconnect such as a bus or switch. This is because of the multi-hop nature of the network, where communication modules are not directly connected but are separated by one or more network nodes. This is in contrast to typical existing interconnections (eg, buses) where modules are directly connected. What is expected from this change belongs to arbitration (which must be changed from centralized to distributed) and communication characteristics (eg sequencing or flow control).

  With the success of portable devices such as mobile phones, PDAs, notebook computers, MP3 players, etc., power consumption is becoming a major issue in modern integrated circuits and their designs. As such IC VLSI designs are moving to the nanometer range, the energy dissipated in system-on-chip interconnects becomes a significant part of overall system power consumption.

  The actual power consumption in the interconnect, ie the network, is not based solely on the interconnect's physical characteristics, such as voltage swings, wiring delays, interconnect shape, etc. It is also based on the flow, i.e., interprocessor communication and processor-memory communication. This communication is usually transaction-based and can originate from: cache and memory transactions (fetching data from shared memory), cache matching operations (update data in shared memory is updated in all cache copies and synchronous traffic Packet splitting overhead (dividing the data flow into packets introduces additional data overhead) or contention between packets (reselecting the packet path in case of conflict).

  In general, a packet on a system on chip has a header including a destination address, a source address, and a request operation such as read (READ), write (WRITE), invalidate (INVALIDATE), and the like. The payload of the packet has data to be transmitted. In some cases, the tail has error detection and correction codes. Several different data packets may be present on the system on chip. That is, there may be packets for memory access requests, cache match synchronization, data fetch, data update, and IO and suspend. The memory access request packet serves to request data from the shared memory, and has a header including a destination address of the target memory and a requested memory operation. When no data is transmitted, the payload is empty. The cache match synchronization packet is sent from the updated memory along with its copy to all caches. A packet may have data as a payload when the data in the cache is to be updated, and may not have data when the data in the cache is to be invalidated. At these times, the header may have a specific operation type. The data fetch packet acts as a reply packet from the memory and contains the requested data as the payload while the header contains the destination address. The data update packet serves to write data back to the memory, has a destination address in the header, and includes each data as a payload. The IO and suspend packets include a header with a destination address, and when data exchange is included, the payload can include data. Therefore, the contents of the header will depend on the transaction as well as the contents of the payload.

  The above-described operations such as cache misses, data fetches, memory updates and cache synchronization involve sending data to the interconnect. However, packet transmission to the interconnect causes energy dissipation in the interconnect wiring and logic gates within each switch. As data packets travel through the interconnect, the interconnect wiring and logic gates along the data path will switch if the data stream reverses its polarity. Therefore, energy is consumed in the interconnect lines and logic gates for each bit.

In a multi-hop interconnect, packets with the same source and destination that may change packet data paths depending on actual data traffic conditions do not necessarily have to go through the same data path, i.e., the same current path and number of hops. Absent. However, since all hops include interconnect wiring and a large number of logic gates, the number of hops through which the packet passes affects the energy dissipation of data transmission. Reference can be made to Non-Patent Document 1 for more information on energy dissipation in system on chip.
Ye et al., “Packetized On-Chip Interconnect Communication Analysis for MPSoC”, Design Automation and Test in Europe, 2003, pp. 344-349.

  It is an object of the present invention to provide a system on chip environment with reduced power consumption.

  In view of the above problems, there is provided an integrated circuit having a plurality of processing modules and interconnecting means for coupling the plurality of processing modules and enabling packet-based communication based on transactions between the plurality of processing modules. Each packet has a first predetermined number of subsequent words, and each subsequent word has a second predetermined number of bits. The first module of the plurality of processing modules initiates a transaction by transmitting at least one packet over the interconnection means to the second module of the plurality of processing modules. The integrated circuit further examines the bits of the at least one packet to determine bits that are not required for the outgoing transaction, and sets the unnecessary bits of the checked at least one packet to other bits of the same packet. It has at least one packet inspection unit that matches the bit.

  When matching is performed on other bits of one and the same packet, the matching depends only on the bits of the same packet and does not change along the data path through the interconnect, which is associated with the switching of logic gates in the switch. Energy loss is reduced across the interconnected data path.

  According to one aspect of the invention, the at least one packet inspection unit aligns the unwanted bits with previous or subsequent bits in the same packet. This reduces the energy loss associated with switching the logic gates in the switch when subsequent bits change their polarity.

  In accordance with a preferred aspect of the present invention, the at least one packet inspection unit matches the unwanted bits with corresponding bits of previous or subsequent words in the same packet. This solution is easy to implement because the packet is trimmed in subsequent words.

  In accordance with another preferred aspect of the present invention, the integrated circuit is coupled to the first module of the plurality of processing modules and controls communication between the first module of the plurality of processing modules and the connection means. And at least one network interface. Each of the at least one packet inspection unit is disposed within one of the network interfaces. Since the packet header exists in the network interface coupled to the first processing module, as well as its payload, and the packet bits do not change along the data path in the interconnect, the network interface matches unused bits. This is a suitable place to perform.

  The present invention also provides packet switching control in an integrated circuit having a plurality of processing modules and interconnection means for coupling the plurality of processing modules and enabling packet-based communication based on transactions between the plurality of processing modules. Regarding the method. Each packet has a first predetermined number of subsequent words, and each subsequent word has a second predetermined number of bits. The first module of the plurality of processing modules initiates a transaction by transmitting at least one packet over the interconnection means to the second module of the plurality of processing modules. The bits of the at least one packet are examined to determine bits that are not necessary for the outgoing transaction, and the unnecessary bits of the examined at least one packet are matched with other bits of the same packet.

  The following embodiments relate to system on chip, i.e., multiple modules on the same chip communicate with each other via some kind of interconnection. The interconnect is embodied as a network on chip NoC. A network on chip may have wiring, buses, time division multiplexing, switches, and / or routers in the network. At the transmission layer of the network, communication between modules is performed on the connection. A connection is considered as a set of channels between a first module and at least one second module, each having a set of connection characteristics. In a connection between a first module and a single second module, the connection has two channels. In other words, it has a request channel that is a channel from the first module to the second module and a response channel that is a channel from the second module to the first module. The request channel is reserved for data and messages from the first module to the second module, while the response channel is reserved for data and messages from the second module to the first module. However, if the connection includes one first module and N second modules, 2N channels are provided. Connection characteristics include ordering (sequential data transmission), flow control (only when a remote buffer is reserved for the connection and it is guaranteed that space is available for the generated data. Data generators can send data), processing power (guaranteed lower bound of processing power), latency (guaranteed upper bound of waiting time), lossiness (loss of data) Degradation), transmission limits, transaction integrity, data accuracy, priority, or data delivery.

  As will be described below, the module may be a so-called IP block (a computing element, a memory, or a subsystem including an interconnection module therein) that interacts with the network at the network interface NI. The network interface NI may be connected to one or more IP blocks. Similarly, an IP can be connected to more than one network interface.

  FIG. 1 shows a basic block diagram of a network on chip according to the first embodiment. Specifically, a master module M and a slave module S each having a network interface NI associated therewith are shown. Each module M, S is connected to the network N via its associated network interface NI. The network interface NI is used as an interface between the master and slave modules M and S and the network N. The network interface NI is provided to manage communication between each module M, S and the network N so that the module can perform its dedicated operation without having to process communication with the network or other modules. It is done. The network has a plurality of interconnected routers R. The router R serves to transfer commands and data to an adjacent router or network interface. For more details on router design concepts, see the literature (Rijpkema et al. “A Router Architecture for Networks on Silicon”, Process 2001, 2nd Workshop on Embedded Systems, or Rijpkema et al “Tradeoffs in the Design of a Router with Both Guaranteed. and Best-Effort Services For Networks on chip ”, Design, Automation and Test in Europe Conference and Exhibition, March 3-7, 2003, Germany). Since the network bandwidth in the network on chip is usually fixed for all types of transactions and communications between the master and slave modules M, S, in certain cases, some of the bits of the packet are It may be unnecessary for communication or transaction. An example is a memory access request as described above. This is because the payload of such a packet is empty. An alternative example where no bits are used is when the target or slave has an address range that requires fewer address bits compared to the address bits assigned in the header of the packet. The same may be made applicable to the payload data.

  Therefore, the packet inspection unit PIU is arranged in the network interface NI coupled to the master module M. The packet inspection unit PIU serves to control packet exchange for packets sent from the master module M.

  FIG. 2 shows the basic structure of a packet used in the present invention. Specifically, FIG. 2A shows two packets that follow each other on a link and packet switching based on standard bit matching techniques in two sequential packets. FIG. 2B shows a preferred example of packet and packet switching based on bit matching within the same packet. In both figures, the unused bits are marked with 'U', 'P' corresponds to the header bits for the path, and 'fc' corresponds to flow control but is conjugated in the header May be. The route “P” and the flow control “fc” are merely examples. Alternatively, the destination address may be included.

  Each packet is 8 bits wide and 3 words deep. However, other bit widths and word depths are possible as well.

  In FIG. 2A, the unused bit U of packet i is matched to the corresponding preceding bit in the word belonging to preceding packet i-1. This is done by making the unused bit U equal to the preceding bit, ie, the payload bit of the preceding packet, as represented by the dashed arrow in FIG. 2A. However, this matching process must be performed for each router R along the path, since the sequence of packets can change at every router along the path across the network. Therefore, the unit for controlling packet switching is implemented for each router, which is cost intensive.

  An improved alignment process for unused bits in accordance with the preferred embodiment is illustrated in FIG. 2B. In this embodiment, matching is preferably performed at the network interface NI of the master module M that is the origin of the packet. In addition or alternatively, matching may be performed at the network interface NI of the slave module S. Since the packet header information and payload are present in the network interface NI, matching can be done there. Since the packet, especially the payload, does not change while it passes through network N, the bits of the packet will minimize power consumption by reducing the exchange between bits of subsequent or previous words in the packet. Can be optimized. Preferably, the alignment is performed between bits of subsequent words. That is, the bit is aligned with the following bit. Since the bit will not change while it passes through the network, the internal packet switching sequence is the same for all routers R. Specifically, the unused bit in the header of packet i is matched with the P1 bit in the same packet.

  FIG. 3 shows a basic block diagram of a packet inspection unit according to standard techniques and according to the invention. FIG. 3A shows a packet inspection unit based on keeping unused bits equal to zero, while FIG. 3B shows a packet inspection unit PIU according to the preferred embodiment.

  The packet inspection unit PIU of FIG. 3A includes three multiplexers M1 to M3, first and second header generation units HCU1 and HCU2, and three first-in first-out (FIFO) F1 to F3. The outputs of the first and second header generation units HCU1, HCU2 are coupled to the first inputs of the first and second multiplexers M1, M2, respectively. The second inputs of the first, second, and third multiplexers M1-M3 are coupled to F1, F2, and F3, which are first, second, and third FIFOs, respectively. The first input of the third multiplexer M3 is set to '0'. Alternatively, the first input is set to '1'.

  The packet inspection unit PIU of FIG. 3B simply comprises two multiplexers M1 and M2, first and second header generation units HCU1, HCU2, and three first-in first-out (FIFO) F1-F3. The outputs of the first and second header generation units HCU1, HCU2 are coupled to the first inputs of the first and second multiplexers M1 and M2, respectively. The second inputs of the first and second multiplexers M1 and M2 are coupled to the first and second FIFOs F1 and F2, respectively. The output of the third FIFO F3 is used as the output of the packet inspection unit PIU together with the outputs of the first and second multiplexers M1 and M2.

  Hence, in addition to reducing power by reducing exchanges, the packet inspection unit PIU according to the present invention also keeps these unused bits fixed because multiplexing of payload or unused (and therefore fixed) bits can be omitted. Implementation costs are reduced compared to implementation. The power consumption is further reduced by the reduction of one multiplexer, and thus a certain amount of logic gates. This is because fewer logic gates need to be switched, thereby reducing the power dissipated in the switching. This is the exact opposite of the cost of implementation with standard technologies that require additional multiplexers and flip-flops.

  In an alternative embodiment, by performing internal packet matching at the network interface before the packet traverses the network, and by performing mutual packet matching at some routers R along the path through the network, FIG. Matching techniques as described according to 2B may be combined.

  In a further alternative embodiment, the internal and / or mutual packet bit matching described above may be performed at router R of network N.

  Reduced switching operations have a positive impact on the power consumption of some structural elements such as switches and FIFOs included in such networks, as well as the switching of logic gates within the structural elements.

  The switching technique described above is advantageous compared to known power reduction techniques that attempt to reduce switching operations by encoding / decoding information on the bus. Because the power required for an encoder / decoder, i.e., the power required to switch logic gates within the encoder / decoder, is very large, such encoding / decoding techniques are practical. This is because a long bus length does not save any power.

  An alternative approach to manipulating unused bits is to keep them at 0 or 1. However, this is undesirable because it results in an additional packet exchange such as (1-0-1).

  In the above embodiment, the interconnection has been described as a network with routers, but other multi-hop interconnections are possible as well.

  The above-described embodiments are illustrative of the present invention and are not intended to limit the present invention. In addition, many alternative embodiments can be designed by those skilled in the art without departing from the scope of the appended claims. In the claims, the term “comprising” does not exclude the presence of elements or steps other than those listed. The term “a” or “an” preceding an element does not exclude the presence of a plurality of such elements. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used effectively.

1 is a basic block diagram illustrating a network on chip according to the present invention. FIG. It is a figure which shows the basic structure of the packet used by this invention. It is a figure which shows the basic structure of the packet used by this invention. It is a basic block diagram showing a packet inspection unit according to the prior art. FIG. 3 is a basic block diagram showing a packet inspection unit according to the present invention.

Claims (5)

An integrated circuit having a plurality of processing modules and interconnecting means for coupling the plurality of processing modules and enabling packet-based communication based on transactions between the plurality of processing modules, each packet having a first A plurality of processing modules having a predetermined number of subsequent words, each subsequent word having a second predetermined number of bits, wherein the first module of the plurality of processing modules receives at least one packet on the interconnection means; A transaction by sending to the second module of the integrated circuit:
Examine at least one bit of the at least one packet to determine an unnecessary bit for the outgoing transaction, and match at least one of the unnecessary bit of the inspected packet with other bits of the same packet An integrated circuit comprising two packet inspection units.   The integrated circuit of claim 1, wherein the at least one packet inspection unit is adapted to match the unwanted bits to previous or subsequent bits in the same packet. Integrated circuit.   3. The integrated circuit of claim 2, wherein the at least one packet inspection unit is further adapted to match the unwanted bits to corresponding bits of previous or subsequent words in the same packet. An integrated circuit characterized by that. An integrated circuit according to claim 2 or 3, wherein:
And further comprising at least one network interface coupled to the first module of the plurality of processing modules to control communication between the first module of the plurality of processing modules and the interconnection means. An integrated circuit, wherein each of the two packet inspection units is located within one of the network interfaces. A method of packet switching control in an integrated circuit, comprising: a plurality of processing modules; and interconnection means for combining the plurality of processing modules and enabling packet-based communication based on transactions between the plurality of processing modules, comprising: Each packet has a first predetermined number of subsequent words, each subsequent word has a second predetermined number of bits, and the first module of the plurality of processing modules places at least one packet on the interconnection means. To initiate a transaction by transmitting to a second module of the plurality of processing modules, the method comprising:
Examining the bits of the at least one packet to determine bits that are not needed for the outgoing transaction, and matching the unwanted bits of the examined at least one packet with other bits of the same packet A method characterized by comprising:

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