JP5115346B2 - Semiconductor integrated circuit for power control - Google Patents

Description

  The present invention relates to a power supply control semiconductor integrated circuit having a built-in backflow prevention circuit, for example, a technique effective for use in a charge control IC (semiconductor integrated circuit) equipped with a charge control circuit.

  As shown in FIG. 3, the secondary battery charging apparatus includes a current control provided between an input terminal IN to which a DC voltage from an AC adapter or the like is input and an output terminal BAT to which the secondary battery is connected. An IC equipped with a charging control circuit that controls the charging current by the transistor Q1 is used.

  In such a charging control IC, when the voltage of the commercial power supply is reduced during charging or when a battery is used as the input DC source, the input voltage may decrease with time, but the input voltage (IC When the charge control transistor is turned off when the power supply voltage of the power supply voltage decreases, a reverse current (reverse current) flows to the input terminal IN side through the parasitic diode Ds existing between the drain and the back gate (substrate or well region). ) May flow.

  Therefore, as shown in FIG. 4, a backflow prevention transistor Q0 is provided in series with Q1 between the input terminal IN and the current control transistor Q1, and a backflow detection circuit is provided to turn off Q0. A backflow prevention circuit for preventing backflow has been proposed.

  The reverse current prevention transistor Q0 has a back gate (hereinafter referred to as a substrate) and a drain at the same potential as Q1, so that the parasitic diode Ds0 is opposite to the parasitic diode Ds1 of Q1. Backflow can be prevented from flowing through the diode. As an invention in which a backflow prevention transistor is provided in series with a current control transistor, for example, there is one disclosed in Patent Document 1.

  However, in the case where such a transistor for preventing a backflow is provided, the element size has to be made considerably large like the current control transistor in order to reduce the loss due to the on-resistance, thereby increasing the chip area and increasing the cost. There is.

In addition, a switch MOSFET for selectively applying an input voltage or an output voltage to the base of the current control transistor provided between the input terminal and the output terminal is provided, and the higher voltage is applied to the current. There has also been proposed an invention in which a reverse flow can be prevented from flowing through a parasitic diode by applying it to a base of a control transistor (Patent Document 2).
Japanese Patent Laid-Open No. 9-275639 JP 2004-280704 A

  However, in the invention described in Patent Document 2, a logic circuit that generates a gate control signal for controlling on / off of a switch MOSFET that allows an input voltage or an output voltage to be selectively applied to a base of a current control transistor, It is configured to operate at a voltage lower than the input voltage by the forward voltage of the diode. Therefore, there is a problem that when the input voltage is lowered, it is difficult to sufficiently turn on the switch MOSFET.

  The present invention has been made paying attention to the above-described problems. The object of the present invention is to provide an input voltage in a power supply control IC having a current control MOSFET provided between an input terminal and an output terminal. Even if the output voltage becomes higher than that, the backflow does not flow and the circuit can be surely operated.

  To achieve the above object, the present invention provides a current control MOS transistor connected between a voltage input terminal and an output terminal for controlling a current flowing from the voltage input terminal to the output terminal, the voltage input terminal and the current A first backflow prevention switch MOS transistor connected between the base of the control MOS transistor and a second backflow prevention connected between the output terminal and the base of the current control MOS transistor. Switch MOS transistor, a backflow detection circuit for detecting a backflow state between the voltage input terminal and the output terminal, and the first and second backflow prevention switch MOSs based on a detection signal of the backflow detection circuit A power supply control semiconductor integrated circuit comprising: a logic circuit that generates a signal for controlling on / off of the transistor; Parasitic diodes existing between the source or drain of the switch MOS transistor and the base are configured to be opposite to each other, and the potential of the base of the current control MOS transistor is supplied as a power supply voltage to the power supply voltage terminal of the logic circuit. It is configured to be supplied.

  According to the above-mentioned means, even if the output voltage becomes higher than the input voltage, it is possible to prevent the reverse flow from flowing, and the logic for generating the signal for controlling the on / off of the backflow prevention switch element. The circuit can be reliably operated by supplying the higher voltage.

  Here, it is desirable that the voltage from the voltage input terminal is supplied to the power supply voltage terminal of the logic gate in the first stage of the logic circuit. As a result, it is possible to avoid a situation in which the operation of the backflow prevention circuit becomes unstable immediately after the voltage supply is started.

  Preferably, the next stage of the first stage logic gate is connected in series between a MOS transistor having a gate terminal connected to the output node of the first stage logic gate, and the MOS transistor and the power supply voltage terminal. A logic gate having a resistance element is connected, and a potential of the base of the current control MOS transistor is supplied to a power supply voltage terminal of the logic gate. As a result, even if the supply of the input voltage is cut off and the output of the preceding logic gate becomes unstable, the substrate potential of the current control MOS transistor is input to the next logic gate via the resistance element, and the circuit Can be avoided from malfunctioning.

  Further, preferably, a drain terminal or a collector terminal is connected to a gate terminal of the current control MOS transistor, and a transistor for driving the current control MOS transistor with an open drain or an open collector is provided, according to an output feedback voltage. A first switch circuit comprising a control circuit for controlling the current control MOS transistor, wherein a resistor and a pair of switch MOS transistors are connected in series between a source terminal and a gate terminal of the current control MOS transistor; However, a second switch circuit in which a resistor and a pair of switch MOS transistors are connected in series is provided between the drain terminal and the gate terminal of the current control MOS transistor, respectively. A pair of switch MOS transistors The parasitic diodes existing between the source or drain of the pair of switch MOS transistors and the base of the pair of switch MOS transistors of the second switch circuit and the substrate are respectively opposite to each other, and the first switch circuit is formed by the logic circuit. The second switch circuit is turned on or off in synchronization with the first backflow prevention switch MOS transistor, and the second switch circuit is turned on or off in synchronization with the second backflow prevention switch MOS transistor by the logic circuit. Configure to be in a state. As a result, even when the current control transistor has a transistor driven by an open drain or an open collector, the current control transistor is surely turned off to prevent the reverse flow from flowing in a situation where the reverse flow flows. Can do.

  According to the present invention, in a power supply control IC having a current control MOSFET provided between an input terminal and an output terminal, backflow does not flow even if the output voltage is higher than the input voltage. In addition, there is an effect that it is possible to reliably operate a logic circuit that generates a signal for controlling on / off of a backflow prevention switch element.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.

  FIG. 1 shows a schematic configuration of an embodiment of a charge control IC for a secondary battery to which the present invention is applied.

  As shown in FIG. 1, the charging control IC 10 of this embodiment includes a voltage input terminal VIN to which a DC voltage from a DC power source 20 such as an external AC adapter is input, and lithium ions to be charged. A battery terminal BAT to which a secondary battery 40 such as a battery is connected, and a P-channel MOSFET (insulated gate field effect transistor; hereinafter referred to as MOS transistor) provided between the voltage input terminal VIN and the battery terminal BAT And a constant voltage control amplifier AMP1 for comparing the battery voltage Vbat and the reference voltage Vref1 to generate the gate control voltage of Q1 for constant voltage control.

  Further, in order to perform current control by detecting a current proportional to the current flowing through the transistor Q1, the source terminal is connected to the voltage input terminal VIN and has a magnitude 1 / N of Q1, and the same voltage as Q1. Is applied to the control terminal (gate terminal), an external terminal PROG to which the drain terminal of Q2 is connected and an external resistor Rp can be connected to the outside, and the terminal PROG for constant current control And a reference current control amplifier AMP2 for comparing the reference voltage Vcref with the reference voltage Vcref and generating a gate control voltage of Q1.

  Further, the charge control IC 10 of this embodiment compares a reference voltage Vref2 such as 5.8V with Vin in order to protect the chip from a DC voltage Vin inputted to the voltage input terminal VIN from the outside. The comparator CMP1 for detecting an abnormality, the comparator CMP2 for comparing the voltage of the battery terminal BAT as an output terminal with the reference voltage Vref3, and the monitored voltage becomes an abnormal voltage based on the outputs of the comparators CMP1 and CMP2. In the case of an abnormal voltage, the gate of an open drain (open collector) MOS transistor Q3 whose drain is connected to the gate of Q1 is controlled to turn off the current control MOS transistor Q1. An internal control circuit 11 for generating and outputting a voltage to be output.

  Further, a switch MOS transistor M1, connected between the source or drain of the current control MOS transistor Q1 and the base (back gate), for selectively applying the input voltage Vin or the output voltage VBAT to the base of Q1. A backflow detection preventing circuit 13 is provided for detecting a backflow state by comparing M2, the input voltage Vin and the output voltage VBAT, and controlling the switch MOS transistors M1 and M2 to prevent backflow. The transistors M1 and M2 are made of P-channel MOSFETs, and their bases have the same potential as the base of Q1.

  Further, the bases of the P-MOS transistors M1 and M2 are connected to the source and drain, respectively, so that the parasitic diodes Ds1 and Ds2 existing on the bases of the transistors are reversed. Further, the power supply voltage terminal of the backflow detection preventing circuit 13 is connected to these common potential points (bases) via a line L1, and the base potential of Q1 is supplied as the power supply voltage. Note that most of the internal circuit of the charge control IC 10 of this embodiment operates with the input voltage Vin (for example, 5 V) supplied as the power supply voltage VDD, with some exceptions. .

  FIG. 2 shows a specific circuit configuration example of the backflow detection preventing circuit 13.

  The backflow detection prevention circuit 13 of this embodiment includes a backflow detection circuit 31 and a backflow prevention circuit 32. Among these, the backflow detection circuit 31 receives the output voltage VBAT and the input voltage Vin via the resistors R1 and R2, respectively, and amplifies the potential difference between them, and the output voltage of the E-AMP is constant. The comparator CMP0 determines whether the output voltage VBAT is higher or lower than the input voltage Vin by comparing the voltage VZ with a voltage obtained by dividing the voltage VZ by a voltage dividing circuit including resistors R4 and R5. The comparator CMP0 outputs a signal RVS that is at a high level when the output voltage VBAT is higher than the input voltage Vin and at a low level when the output voltage VBAT is lower.

  The backflow prevention circuit 32 includes a CMOS inverter INV1 for inverting the output of the comparator CMP0, an inverter INV2 and a CMOS inverter INV3 having a resistor R6 for inverting the output of the inverter INV1, and a CMOS inverter for inverting the output of the inverter INV2. INV4 and INV5, and a CMOS inverter INV6 that inverts the output of the inverter INV4 are provided. The backflow prevention circuit 32 includes a first switch circuit SW1 provided between the source and gate of the current control MOS transistor Q1, and a first switch circuit SW1 provided between the drain and gate of the current control MOS transistor Q1. 2 switch circuit SW2.

  The first switch circuit SW1 includes a series resistor R11 and P-MOS transistors M11 and M12, and the second switch circuit SW21 includes a resistor R12 and P-MOS transistors M21 and M22 in series. The output of the inverter INV3 is commonly applied to the gate terminals of the P-MOS transistors M11 and M12. The base of M11 is connected to the source, and the base of M12 is connected to the drain. The parasitic diodes Ds11 and Ds12 are configured in the opposite direction.

  Similarly, the output of the inverter INV5 is commonly applied to the gate terminals of the P-MOS transistors M21 and M22, and the base of M21 is connected to the source, and the base of M22 is connected to the drain. Parasitic diodes present on the substrate are configured in the opposite direction. Further, the output of the inverter INV5 is applied to the gate terminal of the MOS transistor M2, and the output of the inverter INV6 is applied to the gate terminal of the MOS transistor M1.

  Further, in the backflow prevention circuit 32 of this embodiment, the input voltage Vin is supplied as the power supply voltage VDD only to the first-stage inverter INV1, and the power supply voltage terminals of the remaining inverters INV2 to INV6 are connected to the transistor Q1 as described above. A common substrate potential of M1 and M2 is supplied. If the base potential is supplied to the power supply voltage terminals of all the circuits of the backflow prevention circuit 32 to operate, the operation state of the backflow prevention circuit 32 immediately after the start of voltage supply may become unstable. By supplying the input voltage Vin to the first-stage inverter 1 as the power supply voltage VDD, it is possible to avoid such an unstable state.

  In FIG. 2, the current control circuit denoted by reference numeral 15 is a circuit block comprising the constant voltage control amplifier AMP1, the constant current control amplifier AMP2, the open drain MOS transistor Q3, the internal control circuit 11 and the like in FIG. It is shown by.

  Next, the operation of the backflow detection preventing circuit of this embodiment will be described.

  In this embodiment, when the input voltage Vin is higher than the output voltage VBAT, the output signal RVS of the comparator CMP0 becomes low level, the output of the inverter INV1 becomes high, the output of INV3 becomes low, and P− MOS transistors M11 and M12 are turned on. On the other hand, at this time, the output of the inverter INV5 becomes high, and the P-MOS transistors M21, M22 and M2 are turned off. Further, the output of the inverter INV6 becomes low, and the P-MOS transistor M1 is turned on.

  As a result, the input voltage Vin is applied to the common base potential of the transistors Q1 and M1 and M2 via M1. At the same time, the voltage generated by the voltage drop caused by the current control circuit 15 pulling the current through the resistor R11 and the transistors M11 and M12 is applied to the gate terminal of the current control transistor Q1, and a charging current corresponding to the voltage flows. It is. Further, an input voltage Vin (> VBAT), which is a common substrate potential of the transistors Q1 and M1 and M2, is supplied to the inverters INV2 to INV as a power supply voltage.

  On the other hand, when the output voltage VBAT is higher than the input voltage Vin, the output signal RVS of the comparator CMP0 becomes high level, the output of the inverter INV1 becomes low, the output of INV3 becomes high, and the P-MOS transistors M11, M11, M12 is turned off. At this time, the output of the inverter INV5 becomes low, and the P-MOS transistors M21, M22 and M2 are turned on. Further, the output of the inverter INV6 becomes high, and the P-MOS transistor M1 is turned off.

  As a result, the output voltage VBAT is applied to the common base of the transistors Q1 and M1 and M2 via M2. At the same time, the current control circuit 15 turns off the open drain MOS transistor Q3 (see FIG. 1). Then, the output voltage VBAT is applied to the gate terminal of the current control transistor Q1 via the resistor R11 and the transistors M21 and M22, and Q1 is turned off. At this time, the transistor M1 is in an off state, and if the common substrate potential is VBAT, the parasitic diode Ds1 does not pass a current in a reverse bias state, so the current path from the output terminal BAT to the input terminal IN is completely blocked. Become so.

  Further, an output voltage VBAT (> Vin), which is a common substrate potential of the transistors Q1 and M1 and M2, is supplied to the inverters INV2 to INV6 as a power supply voltage. If, at this time, Vin is supplied to the inverters INV2 to INV6 as the power supply voltage and Vin is much lower than VBAT, the outputs of the inverters INV2 to INV6 become low, and the P-MOS transistors M1, M11, and M12 are completely turned off. However, in this embodiment, such a problem is avoided.

  Further, in this embodiment, the input voltage Vin is always supplied to the power supply voltage terminal of the inverter INV1, and the inverter INV2 is composed of an inverter composed of a MOS transistor M4 and a resistor R6 that receives the output of the inverter INV1 at the gate terminal. One of the resistors R6 is supplied with a common substrate potential of Q1, M1, and M2, to which the higher one of VBAT and Vin is always applied.

  Therefore, even if the supply of the input voltage Vin from the AC adapter or the like is interrupted for some reason and the output of the inverter INV2 becomes unstable, the common substrate potential of Q1, M1, and M2 is used as the power supply voltage via the resistor R6. By being supplied to INV3 and INV4, and M1, M11, and M12 are turned off and M2, M21, and M22 are turned on, the common substrate potential of Q1, M1, and M2 is set to VBAT, thereby preventing the circuit from malfunctioning. There is an advantage of becoming.

  Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications can be made based on the technical idea of the present invention. For example, in the backflow detection preventing circuit 13 of the embodiment of FIG. 2, the inverters INV4 and INV6 are provided to generate the gate control signal of the MOS transistor M1, but the output of the inverter INV3 is supplied to the gate terminal of M1. Even if it is controlled, almost the same operation can be performed.

  In the above embodiment, the current control transistor Q1 is driven by the open drain MOS transistor Q3. However, the current control transistor Q1 can also be applied to a circuit configured to be driven by an open collector bipolar transistor. Can do.

  Further, in the embodiment, the monitoring transistor Q2 having a size 1 / N of the current control transistor Q1 is provided to detect the current and perform the constant current control. However, the current detection is performed in series with the current control transistor Q1. It is also possible to perform constant current control by detecting a current from the amount of voltage drop across the resistor and connecting a resistor. In that case, the backflow detection preventing circuit 13 can be configured to detect a backflow state by comparing the potential of the connection node between the current control transistor Q1 and the current detection resistor with the input voltage Vin.

  In the above description, the example in which the present invention is applied to a secondary battery charging control IC has been described. However, the present invention is not limited to this, and the present invention is applied to a power control IC for a DC power circuit such as a series regulator. Can also be used.

It is explanatory drawing which shows schematic structure of IC for charge control as an example of suitable IC for power supply control which applies this invention. It is a circuit block diagram which shows the Example of the backflow detection prevention circuit in this invention. It is a circuit block diagram which shows an example of the conventional backflow detection prevention circuit in a charge control circuit. It is a circuit block diagram which shows the other example of the conventional backflow detection prevention circuit in a charge control circuit.

Explanation of symbols

10 Charge control IC
DESCRIPTION OF SYMBOLS 11 Internal control circuit 13 Backflow detection prevention circuit 15 Current control circuit 20 DC power supply 31 Backflow detection circuit 32 Backflow prevention circuit 40 Secondary battery Q1 Current control transistor M1, M2 Backflow prevention switch MOS transistor E-AMP Error amplification circuit CMP Comparator

Claims (3)

A current control MOS transistor connected between the voltage input terminal and the output terminal for controlling a current flowing from the voltage input terminal to the output terminal;
A first switch MOS transistor for preventing reverse current connected between the voltage input terminal and the base of the current control MOS transistor;
A second back-flow prevention switch MOS transistor connected between the output terminal and the base of the current control MOS transistor;
A backflow detection circuit for detecting a backflow state between the voltage input terminal and the output terminal;
A logic circuit for generating a signal for controlling on and off of the first and second backflow prevention switch MOS transistors based on a detection signal of the backflow detection circuit;
A semiconductor integrated circuit for power supply control comprising:
Parasitic diodes existing between the source or drain of the first and second backflow prevention switch MOS transistors and the base are opposite to each other, and the potential of the base of the current control MOS transistor is Supplied to the power supply voltage terminal of the logic circuit as a power supply voltage ,
The power supply voltage terminal of the first stage logic gate of the logic circuit is configured to be supplied with a voltage from the voltage input terminal,
Next to the logic gate of the first stage, a MOS transistor having a gate terminal connected to the output node of the logic gate of the first stage, a resistance element connected in series between the MOS transistor and a power supply voltage terminal, And a power supply voltage terminal of the logic gate is supplied with the potential of the base of the current control MOS transistor . A drain terminal or a collector terminal connected to the gate terminal of the current control MOS transistor, and a transistor for driving the current control MOS transistor with an open drain or an open collector, and the current control MOS transistor according to an output feedback voltage A control circuit for controlling the transistor is provided.
A first switch circuit in which a resistor and a pair of switch MOS transistors are connected in series is provided between a source terminal and a gate terminal of the current control MOS transistor, and a drain terminal and a gate of the current control MOS transistor. Between the terminals, a second switch circuit in which a resistor and a pair of switch MOS transistors are connected in series is provided, respectively.
Parasitic diodes existing between the source or drain of the pair of switch MOS transistors of the first switch circuit and the pair of switch MOS transistors of the second switch circuit and the base are configured to be opposite to each other,
The first switch circuit is turned on or off in synchronization with the first backflow prevention switch MOS transistor by the logic circuit, and the second switch circuit is turned on or off by the logic circuit. 2. The semiconductor integrated circuit for power supply control according to claim 1, wherein the semiconductor integrated circuit is configured to be turned on or off in synchronization with the switch MOS transistor. A current control MOS transistor connected between the voltage input terminal and the output terminal for controlling a current flowing from the voltage input terminal to the output terminal;
A first switch MOS transistor for preventing reverse current connected between the voltage input terminal and the base of the current control MOS transistor;
A second back-flow prevention switch MOS transistor connected between the output terminal and the base of the current control MOS transistor;
A backflow detection circuit for detecting a backflow state between the voltage input terminal and the output terminal;
A logic circuit for generating a signal for controlling on and off of the first and second backflow prevention switch MOS transistors based on a detection signal of the backflow detection circuit;
A semiconductor integrated circuit for power supply control comprising:
Parasitic diodes existing between the source or drain of the first and second backflow prevention switch MOS transistors and the base are opposite to each other, and the potential of the base of the current control MOS transistor is Supplied to the power supply voltage terminal of the logic circuit as a power supply voltage,
A drain terminal or a collector terminal connected to the gate terminal of the current control MOS transistor, and a transistor for driving the current control MOS transistor with an open drain or an open collector, and the current control MOS transistor according to an output feedback voltage A control circuit for controlling the transistor is provided.
A first switch circuit in which a resistor and a pair of switch MOS transistors are connected in series is provided between a source terminal and a gate terminal of the current control MOS transistor, and a drain terminal and a gate of the current control MOS transistor. Between the terminals, a second switch circuit in which a resistor and a pair of switch MOS transistors are connected in series is provided, respectively.
Parasitic diodes existing between the source or drain of the pair of switch MOS transistors of the first switch circuit and the pair of switch MOS transistors of the second switch circuit and the base are configured to be opposite to each other,
The first switch circuit is turned on or off in synchronization with the first backflow prevention switch MOS transistor by the logic circuit, and the second switch circuit is turned on or off by the logic circuit. A semiconductor integrated circuit for power control, which is configured to be turned on or off in synchronization with a switch MOS transistor.

Images