JP5113460B2 - Imaging system - Google Patents

Description

  The present invention relates to an imaging system.

  In the imaging system, a pixel signal in one row in a pixel array in which a plurality of pixels are arranged in a row direction and a column direction is read by a readout circuit and transferred to a subsequent stage. In an image indicated by an image signal obtained by processing such a pixel signal two-dimensionally, uneven brightness, that is, shading may occur. Conventionally, a method for correcting such shading has been proposed.

  The technique disclosed in Patent Literature 1 discloses correcting shading using a frame memory.

Further, the technique disclosed in Patent Document 2 discloses a technique for digitally correcting shading by A / D converting an image signal and storing image data for one screen in a memory.
JP-A-11-112016 Japanese Patent Laid-Open No. 10-229506

  In the techniques shown in Patent Document 1 and Patent Document 2, an image signal for one screen is once held in a frame memory in order to correct shading. In this case, since a frame memory for correcting shading is required, the entire imaging system is increased in size. As a result, the manufacturing cost of the imaging system may increase.

  In particular, in recent years, the number of pixels in an imaging system tends to increase, and a large-capacity frame memory corresponding to a pixel array having a large number of pixels may be required. In this case, the manufacturing cost of the imaging system tends to increase.

  In the techniques shown in Patent Document 1 and Patent Document 2, in the shading, a gentle noise component generated in one entire screen due to a normal dark current variation or a difference in optical system is a main object of correction. That is, the gentle noise component generated in the entire screen has a small fluctuation range of the voltage.

  On the other hand, in the shading, the noise component caused by the fluctuation of the power supply potential has a particularly large voltage fluctuation range at the timing when the level of the drive signal for resetting the pixel changes.

  Alternatively, in shading, the noise component due to the fluctuation of the power supply potential is caused by the voltage depending on the number of bits in which the count value of the counter that counts the number of transfer pulses for transferring the pixel signal to the subsequent stage changes. The fluctuation range becomes large.

  An object of the present invention is to provide an imaging system capable of reducing noise components caused by fluctuations in power supply potential at low cost.

An imaging system according to a first aspect of the present invention reads a pixel array in which a plurality of pixels are arranged in a row direction and a column direction, and reads out pixel signals of one row in the pixel array, and each column in the read row A readout unit that sequentially transfers the pixel signals to the subsequent stage, and a drive that supplies a drive signal for resetting the pixels to the pixel array in a transfer period for the readout unit to transfer the pixel signals of each column to the subsequent stage. and parts, in the transfer period, at a timing when the level of the drive signal transitions, characterized in that a pixel signal transferred by the reading portion, provided with a correction unit for correcting the correction amount in accordance with the timing And

An imaging system according to a second aspect of the present invention reads a pixel array in which a plurality of pixels are arranged in a row direction and a column direction, and reads out pixel signals of one row in the pixel array, and each column in the read row For sequentially transferring the pixel signal of each column to the subsequent stage, and for the transfer of the pixel signal of each column to the subsequent stage after the transfer unit starts to transfer the pixel signal of each column to the subsequent stage. A counter that counts the cumulative number of transfer pulses and outputs a count value composed of a plurality of bits, and indicates which of the plurality of bits that constitute the count value output from the counter is a transition bit And a correction unit that corrects the pixel signal transferred by the readout unit with a correction amount corresponding to the number of transition bits according to the number of transition bits .

  According to the present invention, it is possible to reduce noise components resulting from fluctuations in the power supply potential at low cost.

  A schematic configuration and a schematic operation of the imaging system 1 according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration diagram of an imaging system 1 according to the first embodiment of the present invention.

  The imaging system 1 includes an imaging device 10 and a correction unit 20. The imaging device 10 images a subject and outputs an image signal to the correction unit 20. The correction unit 20 corrects the image signal output from the imaging device 10.

  The imaging device 10 includes a pixel array 11, a reading unit 12, and a driving unit 13.

  In the pixel array 11, a plurality of pixels are arranged in the row direction and the column direction. The pixel array 11 has an effective pixel area 11a and an optical black pixel area 11b. A plurality of pixels for outputting pixel signals corresponding to the optical image of the subject are arranged in the effective pixel area 11a. In the optical black pixel region 11b, a plurality of pixels for outputting a black reference signal are arranged.

  The readout unit 12 reads out pixel signals of one row in the pixel array 11 (the effective pixel region 11a thereof), and sequentially transfers the pixel signals of each column in the read row to the subsequent stage.

  The drive unit 13 supplies a drive signal (blank drive pulse shown in FIG. 2) for resetting the pixels to the pixel array 11 in a horizontal transfer period for the readout unit 12 to transfer the pixel signals of each column to the subsequent stage. .

  The correction unit 20 includes a horizontal counter 28, a first register (first holding unit) 27, a comparator (comparing unit) 23, a second register (second holding unit) 26, a register 25, an adder 21, A DA converter 24, a subtracter (subtractor) 22, and an AD converter (A / D converter) 29 are included.

  The horizontal counter 28 counts the cumulative number of horizontal transfer pulses for transferring the pixel signals of each column to the subsequent stage after the horizontal transfer period starts (see FIG. 2). Here, the horizontal transfer pulse is a signal for the reading unit 12 of the imaging device 10 to transfer the pixel signals of each column to the subsequent stage (the subtracter 22 of the correction unit 20).

  The first register 27 holds the number of transition pulses (for example, “4” and “103” shown in FIG. 2) indicating the timing at which the level of the drive signal changes during the horizontal transfer period.

  The second register 26 holds a correction amount corresponding to the number of transition pulses. Here, the correction amount is a noise component (noise due to power supply fluctuation) resulting from fluctuations in the power supply potential. As described above, this noise component is often generated in the pixel signal transferred at the timing when the level of the drive signal for resetting the pixel changes. Therefore, if the pixel signal transferred at least at the timing corresponding to the number of transition pulses is corrected, the noise component can be sufficiently reduced.

  For example, the second register 26 holds, as “pulse A rise 1 bit”, a correction amount “+6” corresponding to the number of transition pulses “4” when the blank drive pulse A transits from the L level to the H level ( (See FIG. 2). For example, the second register 26 holds, as “pulse A fall 1 bit”, the correction amount “−4” corresponding to the number of transition pulses “103” when the blank drive pulse A transits from the H level to the L level. (See FIG. 2).

  Similarly, for example, the second register 26 holds, as “pulse B rise 1 bit”, a correction amount corresponding to the number of transition pulses when the blank drive pulse B transits from the L level to the H level. For example, the second register 26 holds a correction amount corresponding to the number of transition pulses when the blank drive pulse B transits from the H level to the L level as “pulse B fall 1 bit”.

  In addition, a plurality of switches for selecting any value held in the second register 26 and supplying the selected value to the adder 21 are provided between the second register 26 and the adder 21. .

  The comparator 23 compares the count value output from the horizontal counter 28 with the number of transition pulses held in the first register 27. When the count value is equal to the number of transition pulses, the comparator 23 supplies a correction amount corresponding to the number of transition pulses from the second register 26 to the subtracter 22 via the adder 21 and the DA converter 24. Like that. Specifically, the comparator 23 selects a correction amount corresponding to the number of transition pulses among a plurality of switches and turns on a switch for supplying the correction amount to the adder 21. On the other hand, the comparator 23 does not turn on any of the plurality of switches when the count value and the number of transition pulses are not equal. In this case, all of the plurality of switches are in an off state.

  The register 25 holds an OB clamp reference signal corresponding to the black reference signal acquired from the optical black pixel area 11 b of the pixel array 11. The OB clamp reference signal is a signal for performing OB clamp processing. The OB clamping process is a process for adjusting the image signal so that the black gradation is appropriate.

  The adder 21 adds the OB clamp reference signal supplied from the register 25 and the signal supplied from the second register 26. Here, both signals are digital signals.

  Here, if any of the plurality of switches is turned on, the correction amount signal selected by the turned on switch is supplied from the second register 26 to the adder 21. The adder 21 adds the OB clamp reference signal and the correction amount signal, and outputs the added signal to the DA converter 24 as a signal having an amount corresponding to the correction amount.

  On the other hand, if the plurality of switches between the second register 26 and the adder 21 are all off, the adder 21 outputs the OB clamp reference signal supplied from the register 25 to the DA converter 24 as it is. To do.

  The DA converter 24 D / A converts the digital signal supplied from the adder 21 to generate an analog signal. Here, when the signal obtained by adding the OB clamp reference signal and the correction amount signal is supplied, the DA converter 24 performs D / A conversion on the added signal and outputs it to the subtractor 22. When the OB clamp reference signal is supplied, the DA converter 24 D / A converts the OB clamp reference signal and outputs it to the subtractor 22.

  The subtracter 22 receives the pixel signal (analog signal) transferred by the reading unit 12 of the imaging device 10. The subtractor 22 receives an analog signal from the DA converter 24. The subtracter 22 subtracts the analog signal from the pixel signal. Here, when the amount corresponding to the black reference signal, that is, the analog signal of the OB clamp reference signal is subtracted from the pixel signal, the subtracter 22 generates an OB clamp processed image signal and outputs it to the AD converter 29. When the subtracter 22 subtracts the analog signal of the added signal from the pixel signal, in addition to the OB clamping process, the subtracter 22 generates an image signal in which a noise component caused by the fluctuation of the power supply potential is corrected, and performs AD conversion. Output to the unit 29.

  The AD converter 29 A / D converts the analog signal output from the subtractor 22 to generate a digital signal. In other words, the AD converter 29 performs A / D conversion on the image signal subtracted by the subtractor 22 and outputs it to the subsequent stage.

  Next, the operation when the imaging system 1 corrects a noise component (noise component due to power supply fluctuation) caused by fluctuations in the power supply potential will be described with reference to FIG. FIG. 2 is a timing chart showing an operation when the imaging system 1 corrects a noise component caused by fluctuations in the power supply potential. FIG. 2 shows waveforms after the timing at which the horizontal transfer period starts. In FIG. 2, only the waveform related to the blank drive pulse A is shown for simplification, but the same applies to the blank drive pulse B.

  The waveform indicated by “horizontal counter” indicates the timing at which the horizontal counter 28 of the correction unit 20 counts the cumulative number of horizontal transfer pulses. Further, in the waveform indicated by “horizontal counter”, the count value indicating the cumulative number is indicated by a decimal number.

  The “blank drive pulse A” is a drive signal for resetting the pixel, and is a signal supplied from the drive unit 13 of the imaging device 10 to the pixel array 11. The waveform indicated by “blank drive pulse A” transitions from the L level to the H level during the period when the count value of the horizontal counter 28 is “4”, and during the period when the count value of the horizontal counter 28 is “103”. Transition from the H level to the L level. Here, the period for the transition of the blank drive pulse is called a blank period. That is, since the horizontal transfer period and the blank period overlap, the frame period is suppressed to be shorter than when the horizontal transfer period and the blank period are provided separately.

  The “horizontal transfer pulse” is a signal for the reading unit 12 of the imaging apparatus 10 to transfer the pixel signals of each column to the subsequent stage (the subtracter 22 of the correction unit 20). The waveform indicated by “horizontal transfer pulse” is toggled.

  The “image signal” is obtained by two-dimensionally processing the pixel signals of each column transferred by the reading unit 12. That is, the “image signal” is a collection of pixel signals. The waveform indicated by “image signal” indicates the signal level of the pixel signal (analog signal) of each column transferred by the reading unit 12. For example, the “image signal” indicates a signal level of “+6” during a period when the count value of the horizontal counter 28 is “4”, and a signal of “+3” during a period when the count value of the horizontal counter 28 is “5”. Indicates the level. Further, for example, “image signal” indicates a signal level of “−4” during a period when the count value of the horizontal counter 28 is “103”, and “−” during a period when the count value of the horizontal counter 28 is “104”. 2 "indicates the signal level. Here, since the pixel signal of each column in the row read by the reading unit 12 is sequentially transferred to the subsequent stage, the count value of the horizontal counter 28 corresponds to the column address of the pixel from which the transferred pixel signal is acquired. It has become a thing.

  “Power supply-induced noise component data” is noise component data resulting from fluctuations in the power supply potential, and is correction amount data held in the second register 26. The waveform indicated by “power supply-caused noise component data” indicates the signal level of the signal (analog signal) supplied from the second register 26 to the subtractor 22 via the adder 21 and the DA converter 24. Yes.

  That is, the comparator 23 compares the count value output from the horizontal counter 28 with the number of transition pulses (“4” or “103”) held in the first register 27.

  In a period in which the count value of the horizontal counter 28 is “1” to “3”, the comparator 23 determines that the count value and the number of transition pulses are not equal, and none of the plurality of switches is turned on.

  In a period in which the count value of the horizontal counter 28 is “4”, the comparator 23 determines that the count value is equal to the number of transition pulses “4”, and the correction amount “+6” corresponding to the number of transition pulses “4”. And a switch for supplying to the adder 21 is turned on. As a result, among the data held in the second register 26, the correction amount data “+6” corresponding to the transition pulse number “4” is supplied to the subtractor 22 via the adder 21 and the DA converter 24. .

  In a period in which the count value of the horizontal counter 28 is “5” to “102”, the comparator 23 determines that the count value and the number of transition pulses are not equal, and none of the plurality of switches is turned on.

  In the period in which the count value of the horizontal counter 28 is “103”, the comparator 23 determines that the count value is equal to the number of transition pulses “103”, and the correction amount “−4” corresponding to the number of transition pulses “103” is “−4”. "Is selected and a switch for supplying to the adder 21 is turned on. As a result, among the data held in the second register 26, the correction amount data “−4” corresponding to the transition pulse number “103” is supplied to the subtractor 22 via the adder 21 and the DA converter 24. The

  The “post-OB clamp image signal” is a collection of pixel signals, that is, an image signal after at least the OB clamp reference signal is subtracted by the subtractor 22 of the correction unit 20 and the OB clamp processing is performed. The waveform indicated by “image signal after OB clamping” is obtained by subtracting the waveform indicated by “power supply-induced noise component data” from the waveform indicated by “image signal”.

  In this manner, the pixel signal transfer operation by the readout unit 12 and the pixel reset operation by the drive signal (blank drive pulse) from the drive unit 13 are performed in parallel so that the horizontal transfer period and the blank period overlap. To be done. Thereby, the frame period can be kept short.

  On the other hand, the pixel signal transferred by the readout unit 12 is affected by a noise component resulting from the fluctuation of the power supply potential. Even in this case, this noise component is often generated in the pixel signal transferred at the timing when the level of the drive signal for resetting the pixel changes. Therefore, since the pixel signal transferred at the timing corresponding to at least the number of transition pulses is corrected, the noise component can be reduced.

  That is, the memory capacity necessary for reducing the noise component is at least the amount necessary to store the number of transition pulses and the correction amount corresponding to the timing indicated thereby (the first register 27 and the first register). It is sufficient if only two registers 26) are secured. Therefore, since the imaging system can be reduced in size by reducing the memory capacity necessary for reducing the noise component and the manufacturing cost can be suppressed, the noise component due to the fluctuation of the power supply potential can be reduced at a low cost.

  The data on the number of transition pulses may be held in the first register 27 by being supplied to the first register 27 from the overall control / arithmetic unit 99 or the timing generator 98 described later.

  Further, the correction amount data may be held in the second register 26 by being supplied from the overall control / arithmetic unit 99 to the second register 26. Alternatively, the correction amount data is obtained by supplying the value obtained by monitoring the power supply potential from the imaging device 10 to the second register 26 at the timing indicated by the number of transition pulses before the previous frame period. It may be held in the second register 26.

  An imaging system according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a configuration diagram of an imaging system 100 according to the second embodiment of the present invention. FIG. 4 is a timing chart illustrating an operation when the imaging system 100 corrects a noise component caused by fluctuations in the power supply potential. Below, it demonstrates centering on a different part from 1st Embodiment, and abbreviate | omits description about the same part.

  The imaging system 100 differs from the first embodiment in that it includes a correction unit 120. The correction unit 120 includes a second register 126 and a comparator 123.

  The second register 126 further holds a correction amount corresponding to each post-transition pulse number up to a value obtained by adding N (N: positive integer) to the transition pulse number. For example, the second register 126 further holds a correction amount corresponding to each post-transition pulse number up to a value obtained by adding 1 to the transition pulse number.

  For example, the second register 126 holds, as “pulse A rise 2 bits”, a correction amount “+3” corresponding to the post-transition pulse number “5” when the blank drive pulse A transits from the L level to the H level. (See FIG. 4). For example, the second register 126 holds the correction amount “−2” corresponding to the number of post-transition pulses “104” when the blank drive pulse A transits from the H level to the L level as “pulse A fall 2 bits”. (See FIG. 4).

  Similarly, for example, the second register 126 holds, as “pulse B rise 2 bits”, a correction amount corresponding to the post-transition pulse number when the blank drive pulse B transits from the L level to the H level. For example, the second register 126 holds, as “pulse B fall 2 bits”, a correction amount corresponding to the number of post-transition pulses when the blank drive pulse B transitions from the H level to the L level.

  The comparator 123 further obtains the number of post-transition pulses up to a value obtained by adding N (N: positive integer) to the number of transition pulses. The comparator 123 compares the count value output from the horizontal counter 28 with the obtained post-transition pulse number. When the comparator 123 determines that the count value is equal to the post-transition pulse number, the correction amount corresponding to each post-transition pulse number is subtracted from the second register 126 via the adder 21 and the DA converter 24. 22 to be supplied. Specifically, the comparator 123 selects a correction amount corresponding to the number of post-transition pulses from among a plurality of switches and turns on a switch for supplying the correction amount to the adder 21.

  Accordingly, the subtracter 22 subtracts an amount corresponding to the correction amount corresponding to each post-transition pulse number from the pixel signal transferred by the reading unit 12 at the timing indicated by each post-transition pulse number.

  In addition, “power supply-caused noise component data” is different from that of the first embodiment as shown in FIG.

  That is, the comparator 123 compares the count value output from the horizontal counter 28 with the obtained post-transition pulse number (“5” or “104”).

  In the period in which the count value of the horizontal counter 28 is “5”, the comparator 123 determines that the count value is equal to the post-transition pulse number “5”, and the correction amount “5” corresponding to the post-transition pulse number “5”. “+3” is selected and a switch for supplying to the adder 21 is turned on. As a result, among the data held in the second register 126, the correction amount data “+3” corresponding to the post-transition pulse number “5” is supplied to the subtractor 22 via the adder 21 and the DA converter 24. The

  In the period when the count value of the horizontal counter 28 is “104”, the comparator 123 determines that the count value is equal to the post-transition pulse number “104”, and the correction amount “104” corresponding to the post-transition pulse number “104”. -2 "is selected and a switch for supplying to the adder 21 is turned on. As a result, among the data held in the second register 126, the correction amount data “−2” corresponding to the post-transition pulse number “104” is supplied to the subtracter 22 via the adder 21 and the DA converter 24. Is done.

  Thus, in addition to the timing corresponding to the number of transition pulses, the pixel signal transferred at the timing corresponding to the number of post-transition pulses is corrected, so that the noise component can be further reduced.

  An imaging system according to a third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a configuration diagram of an imaging system 200 according to the third embodiment of the present invention. Below, it demonstrates centering on a different part from 1st Embodiment, and abbreviate | omits description about the same part.

  The imaging system 200 is different from the first embodiment in that a correction unit 220 is provided. The correction unit 220 includes a comparator 223 and a variable multiplier (multiplication unit) 231.

  The comparator 223 supplies the variable multiplier 231 with the result of comparing the count value output from the horizontal counter 28 with the number of transition pulses held in the first register 27.

  The variable multiplier 231 determines a weighting coefficient based on the result compared by the comparator 223. Specifically, the variable multiplier 231 determines the weighting coefficient according to the number of transition pulses or the number of post-transition pulses described above. Note that the weighting coefficient is determined in consideration of the attenuation characteristics of noise components after the timing corresponding to the number of transition pulses.

  For example, when the count value is equal to the number of transition pulses, the variable multiplier 231 determines the weighting coefficient as “1”. For example, when the count value is equal to the value obtained by adding 1 to the number of transition pulses (number of post-transition pulses), the variable multiplier 231 determines the weighting coefficient to be “0.5”.

  Then, the variable multiplier 231 supplies an amount obtained by multiplying the correction amount corresponding to the number of transition pulses by a weighting coefficient to the subtracter 22 via the adder 21 and the DA converter 24.

  For example, when the count value and the number of transition pulses “4” are equal, the variable multiplier 231 increases an amount “+6” obtained by multiplying the correction amount “+6” corresponding to the number of transition pulses “4” by the weighting coefficient “1”. , And supplied to the subtractor 22 via the adder 21 and the DA converter 24. For example, when the count value is equal to the value “5” obtained by adding 1 to the number of transition pulses, the variable multiplier 231 applies the weighting coefficient “0.5” to the correction amount “+6” corresponding to the number of transition pulses “4”. Is supplied to the subtractor 22 via the adder 21 and the DA converter 24.

  Thus, in addition to the timing corresponding to the number of transition pulses, the pixel signal transferred at the timing corresponding to the number of post-transition pulses is corrected, so that the noise component can be further reduced.

  Also, when correcting the pixel signal transferred at the timing corresponding to the number of post-transition pulses, the weighting coefficient is multiplied in consideration of the attenuation characteristics of the noise components, so that the correction amount corresponding to the number of post-transition pulses is stored. Can save memory capacity. Therefore, even when the noise component is further reduced, the imaging system can be downsized and its manufacturing cost can be suppressed.

  An imaging system according to a fourth embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a configuration diagram of an imaging system 300 according to the fourth embodiment of the present invention. FIG. 7 is a timing chart showing an operation when the imaging system 300 corrects a noise component caused by fluctuations in the power supply potential. Below, it demonstrates centering on a different part from 1st Embodiment, and abbreviate | omits description about the same part.

  The imaging system 300 is different from the first embodiment in that it includes a horizontal counter 328 and a correction unit 320. The horizontal counter 328 counts the cumulative number of horizontal transfer pulses after the horizontal transfer period starts, and outputs the count value to the correction unit 320. The horizontal counter 328 counts the cumulative number of transfer pulses with, for example, 4 bits. The correction unit 320 corrects the pixel signal transferred by the reading unit 12 according to the number of transition bits of the count value output from the horizontal counter 328.

  The correction unit 320 includes a third register (third holding unit) 332 and does not include the comparator 23, the first register 27, and the second register 26.

  The third register 332 holds a correction amount corresponding to the number of transition bits of the count value.

  For example, the third register 332 sets the correction amount “−” corresponding to the number of transition bits “1”, that is, “LSB” when the count value of the horizontal counter 328 transitions from 0 to 1 as “1 bit 0 → 1”. 3 ”is held (see FIG. 7). For example, the third register 332 sets the correction amount “2” corresponding to the number of transition bits “2”, that is, “2nd bit” when the count value of the horizontal counter 328 transits from 0 to 1 as “the second bit 0 → 1”. “0” is held (see FIG. 7). For example, the third register 332 sets “the third bit 0 → 1” and the correction amount “3” corresponding to the number of transition bits “3” when the count value of the horizontal counter 328 transits from 0 to 1, that is, “3rd bit”. +3 ”is held (see FIG. 7). For example, the third register 332 sets the correction amount “+5” corresponding to the number of transition bits “4”, that is, “MSB”, when the count value of the horizontal counter 328 transitions from 0 to 1 as “4th bit 0 → 1”. Is held (see FIG. 7). For example, the third register 332 holds, as “3 bits 1 → 0”, the correction amount “+6” corresponding to the number of transition bits “Reset 3 bits” when the count value of the horizontal counter 328 transitions from 1 to 0 ( (See FIG. 7).

  Similarly, for example, the third register 332 holds “1 bit 1 → 0” and holds a correction amount corresponding to the number of transition bits “Reset 1 bit” when the count value of the horizontal counter 328 transits from 1 to 0. For example, the third register 332 holds “2 bits 1 → 0” and holds a correction amount corresponding to the number of transition bits “Reset 2 bits” when the count value of the horizontal counter 328 transitions from 1 to 0. For example, the third register 332 holds “4 bits 1 → 0” and holds a correction amount corresponding to the number of transition bits “Reset 4 bits” when the count value of the horizontal counter 328 transitions from 1 to 0.

  A plurality of switches for selecting any value held in the third register 332 and supplying the selected value to the adder 21 are provided between the third register 332 and the adder 21. .

  Here, the horizontal counter 328 determines the number of transition bits of the count value. The horizontal counter 328 supplies a correction amount corresponding to the number of transition bits of the count value from the third register 332 to the subtracter 22 via the adder 21 and the DA converter 24. Specifically, the horizontal counter 328 selects a correction amount corresponding to the number of transition bits from among a plurality of switches and turns on a switch for supplying the correction amount to the adder 21. Thereby, the subtracter 22 subtracts an amount corresponding to the correction amount corresponding to the number of transition bits of the count value from the pixel signal transferred by the reading unit 12 at the timing indicated by the count value.

  Further, as shown in FIG. 7, the operation when the imaging system 300 corrects a noise component (noise component due to power supply fluctuation) caused by the fluctuation of the power supply potential is different from that of the first embodiment in the following points. .

  In the waveform indicated by “horizontal counter”, the count value indicating the cumulative number is indicated by a 4-bit binary number.

  The data indicated by “horizontal counter transition” indicates the number of transition bits from the previous count value to the current count value in the horizontal counter 328.

  “Power supply-induced noise component data” is noise component data resulting from fluctuations in the power supply potential, and correction amount data held in the third register 332. The waveform indicated by “power supply-caused noise component data” indicates the signal level of the signal (analog signal) supplied from the third register 332 to the subtractor 22 via the adder 21 and the DA converter 24. Yes.

  That is, in the period when the count value is “0100”, the horizontal counter 328 applies the correction amount corresponding to the number of transition bits of the count value from the third register 332 to the subtracter 22 via the adder 21 and the DA converter 24. To be supplied.

  For example, the horizontal counter 328 selects a correction amount “+3” corresponding to the number of transition bits “3rd bit” and turns on a switch for supplying to the adder 21. As a result, the subtracter 22 has transferred the amount “+3” corresponding to the correction amount corresponding to the number of transition bits “3rd bit” of the count value by the reading unit 12 at the timing indicated by the count value “0100”. Subtract from the pixel signal.

  Thereby, as shown in “Image signal after OB clamping”, an image signal with a reduced noise component is obtained.

  As described above, when the number of transfer pulses for transferring the pixel signal to the subsequent stage is counted by the reading unit 12, the pixel signal is affected by the noise component due to the fluctuation of the power supply potential. receive. Even in this case, this noise component depends on the number of bits at which the count value of the counter transitions. Therefore, since the pixel signal is corrected with a correction amount corresponding to the number of transition bits, the noise component can be reduced.

  That is, it is sufficient that the memory capacity necessary for reducing the noise component is ensured by the amount necessary for storing the correction amount corresponding to the number of transition bits (4 bits × 2 in the case of FIG. 7). is there. Therefore, since the imaging system can be reduced in size by reducing the memory capacity necessary for reducing the noise component and the manufacturing cost can be suppressed, the noise component due to the fluctuation of the power supply potential can be reduced at a low cost.

  An imaging system according to a fifth embodiment of the present invention will be described with reference to FIG. FIG. 8 is a configuration diagram of an imaging system 400 according to the fifth embodiment of the present invention. Below, it demonstrates centering on a different part from 1st Embodiment, and abbreviate | omits description about the same part.

  The imaging system 400 differs from the first embodiment in that it includes a correction unit 420. The correction unit 420 includes an AD converter 429 and an adder 422 and does not include the DA converter 24.

  The AD converter 429 A / D converts the image signal transferred by the reading unit 12 of the imaging device 10. The adder 422 subtracts an amount corresponding to the correction amount received from the adder 21 (OB clamp reference signal + correction amount signal) from the image signal A / D converted by the AD converter 429.

  Thus, since the pixel signal is subtracted after A / D conversion, it is not necessary to D / A convert the correction amount signal. For this reason, the structure of the correction | amendment part 420 can be simplified.

  Next, a configuration example of the entire imaging system is shown in FIG.

  As shown in FIG. 9, the imaging system 90 mainly includes an optical system, the imaging device 10, and a signal processing unit. The optical system mainly includes a shutter 91, a photographing lens 92, and a diaphragm 93. The signal processing unit mainly includes an imaging signal processing circuit 95, an A / D converter 96, an image signal processing unit 97, a memory unit 87, an external I / F unit 89, a timing generation unit 98, an overall control / calculation unit 99, and a recording. A medium 88 and a recording medium control I / F unit 94 are provided. The signal processing unit may not include the recording medium 88.

  The shutter 91 is provided in front of the photographic lens 92 on the optical path and controls exposure.

  The photographic lens 92 refracts incident light to form an image of a subject on the pixel array (imaging surface) of the imaging device 10.

  The diaphragm 93 is provided between the photographing lens 92 and the imaging device 10 on the optical path, and adjusts the amount of light guided to the imaging device 10 after passing through the photographing lens 92.

  The imaging device 10 converts an image of a subject formed in the pixel array into an image signal. The imaging device 10 reads out the image signal from the pixel array and outputs it.

  The imaging signal processing circuit 95 is connected to the imaging device 10 and processes an image signal output from the imaging device 10. Note that the imaging signal processing circuit 95 includes the first register, the second register, the register, the third register, a comparator, an adder, a subtracter, a multiplier, and the like.

  The A / D converter 96 is connected to the imaging signal processing circuit 95 and converts the processed image signal (analog signal) output from the imaging signal processing circuit 95 into a digital signal.

  The image signal processing unit 97 is connected to the A / D converter 96, and performs various kinds of arithmetic processing such as correction on the image signal (digital signal) output from the A / D converter 96 to generate image data. To do. The image data is supplied to the memory unit 87, the external I / F unit 89, the overall control / calculation unit 99, the recording medium control I / F unit 94, and the like.

  The memory unit 87 is connected to the image signal processing unit 97 and stores the image data output from the image signal processing unit 97.

  The external I / F unit 89 is connected to the image signal processing unit 97. Thus, the image data output from the image signal processing unit 97 is transferred to an external device (such as a personal computer) via the external I / F unit 89.

  The timing generation unit 98 is connected to the imaging device 10, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. Thereby, a timing signal is supplied to the imaging device 10, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. The imaging device 10, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97 operate in synchronization with the timing signal. Note that the timing generator 98 includes the above-described horizontal counter.

  The overall control / arithmetic unit 99 is connected to the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F unit 94, and the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F. The unit 94 is controlled as a whole.

  The recording medium 88 is detachably connected to the recording medium control I / F unit 94. Thereby, the image data output from the image signal processing unit 97 is recorded on the recording medium 88 via the recording medium control I / F unit 94.

  With the above configuration, if a good image signal is obtained in the imaging apparatus 10, a good image (image data) can be obtained.

1 is a configuration diagram of an imaging system 1 according to a first embodiment of the present invention. 6 is a timing chart illustrating an operation when the imaging system 1 corrects a noise component caused by fluctuations in the power supply potential. The block diagram of the imaging system 100 which concerns on 2nd Embodiment of this invention. 6 is a timing chart showing an operation when the imaging system 100 corrects a noise component caused by fluctuations in the power supply potential. The block diagram of the imaging system 200 which concerns on 3rd Embodiment of this invention. The block diagram of the imaging system 300 which concerns on 4th Embodiment of this invention. 6 is a timing chart showing an operation when the imaging system 300 corrects a noise component caused by fluctuations in the power supply potential. The block diagram of the imaging system 400 which concerns on 5th Embodiment of this invention. The figure which shows the structural example of the whole imaging system.

Explanation of symbols

1, 90, 100, 200, 300, 400 Imaging system 10 Imaging device 20, 120, 220, 320, 420 Correction unit

Claims (10)

A pixel array in which a plurality of pixels are arranged in a row direction and a column direction;
A readout unit that reads out pixel signals of one row in the pixel array and sequentially transfers pixel signals of each column in the read row to a subsequent stage;
A drive unit that supplies a drive signal for resetting the pixels to the pixel array in a transfer period for the readout unit to transfer the pixel signals of each column to a subsequent stage;
In the transfer period, at a timing when the level of the drive signal transitions, the pixel signal transferred by the reading unit, and a correcting unit for correcting the correction amount in accordance with the timing,
An imaging system comprising: The correction unit is
A first holding unit that holds the number of transition pulses indicating the timing at which the level of the drive signal transits in the transfer period;
A second holding unit that holds a correction amount corresponding to the number of transition pulses;
A subtraction unit that subtracts an amount corresponding to the correction amount corresponding to the number of transition pulses from the pixel signal transferred by the readout unit at a timing indicated by the number of transition pulses;
The imaging system according to claim 1, comprising: The correction unit is
A counter that counts the cumulative number of transfer pulses for transferring the pixel signals of each column to the subsequent stage after the start of the transfer period;
When the count value output from the counter is compared with the number of transition pulses held in the first holding unit, and the count value is equal to the number of transition pulses, the correction amount corresponding to the number of transition pulses Is supplied to the subtracting unit from the second holding unit;
The imaging system according to claim 2, further comprising: The second holding unit further calculates a correction amount corresponding to each number of post-transition pulses from a value larger than the number of transition pulses to a value obtained by adding N (N: positive integer) to the number of transition pulses. Hold and
The comparison unit further compares the count value output from the counter with each of the post-transition pulse number, and if the count value and the post-transition pulse number are equal, the transition equal to the count value A correction amount corresponding to the number of post-stage pulses is supplied from the second holding unit to the subtracting unit,
The subtracting unit subtracts an amount corresponding to a correction amount corresponding to each post-transition pulse number from the pixel signal transferred by the readout unit at a timing indicated by each post-transition pulse number. The imaging system according to claim 3, wherein The correction unit is
The method further includes a multiplying unit that determines a weighting coefficient based on a result of comparison by the comparison unit, and supplies the subtraction unit with an amount obtained by multiplying a correction amount corresponding to the number of transition pulses by the weighting factor. The imaging system according to claim 3. A pixel array in which a plurality of pixels are arranged in a row direction and a column direction;
A readout unit that reads out pixel signals of one row in the pixel array and sequentially transfers pixel signals of each column in the read row to a subsequent stage;
The readout unit is configured with a plurality of bits by counting the cumulative number of transfer pulses for transferring the pixel signals of each column to the subsequent stage after the transfer period for transferring the pixel signals of each column to the subsequent stage is started. A counter that outputs a count value
Depending on the number of transition bit indicating whether the bit is any of transition among the plurality of bits constituting the count value output from the counter, a pixel signal transferred by the reading unit, the number of the transition bits A correction unit for correcting with a correction amount according to
An imaging system comprising: The correction unit is
A third holding unit for holding a correction amount corresponding to the number of transition bits of the count value;
A subtraction unit that subtracts an amount corresponding to the correction amount corresponding to the number of transition bits from the pixel signal transferred by the readout unit at a timing indicated by the count value;
The imaging system according to claim 6, further comprising: The correction unit is
A subtraction unit that subtracts an amount corresponding to a correction amount from the pixel signal transferred by the readout unit;
An A / D converter for A / D converting the pixel signal subtracted by the subtractor;
The imaging system according to claim 1 or 6, characterized by comprising: The correction unit is
An A / D converter that A / D converts the pixel signal transferred by the readout unit;
A subtractor that subtracts an amount corresponding to a correction amount from the pixel signal that has been A / D converted by the A / D converter;
The imaging system according to claim 1 or 6, characterized by comprising: The pixel array is
An optical black pixel area for outputting a black reference signal;
An effective pixel area for outputting a pixel signal;
Have
The imaging system according to claim 8 or 9, wherein the subtraction unit subtracts the correction amount and an amount corresponding to the black reference signal from a pixel signal.

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