JP5109863B2 - Power amplifier - Google Patents

Description

  The present invention relates to a power amplifier used for a plurality of communication systems having different required saturation output power, for example, mobile communication terminals compatible with GSM (Global System for Mobile Communications) and W-CDMA (Wideband Code Division Multiple Access). Is.

  Mobile communication terminals represented by mobile phones have come to be widely used. A single mobile communication terminal compatible with a plurality of communication systems, for example, GSM and W-CDMA is demanded assuming use in various places. The saturation output power required for the power amplifier of each communication system is, for example, 3 W for GSM and about 1.2 W for W-CDMA. In W-CDMA, since it is necessary to operate with a power smaller than the saturated output power (so-called back-off operation) in order to satisfy the distortion characteristics, the saturated output power is the output power during operation (about 0.5 W). 2 times to 3 times.

  If a GSM power amplifier having a large saturated output power is operated as it is in a small output state (W-CDMA), the efficiency is greatly reduced. In order to avoid this, conventional mobile phone terminals are provided with power amplifiers for GSM and CDMA, respectively.

  Further, in order to reduce the cost and size of mobile communication terminals, the isolator provided between the power amplifier and the antenna is being omitted. FIG. 17 is a diagram illustrating a power amplifier in which an isolator is omitted. If the isolator is omitted, when the impedance Z_ant of the antenna ANT changes due to a change in the high frequency environment around the antenna ANT due to a human body or peripheral devices, the load impedance ZL viewed from the amplifier A changes.

  FIG. 18 is a Smith chart showing the characteristics of the power amplifier of FIG. As shown in FIG. 18, the efficiency characteristics and distortion characteristics of the amplifier change greatly with changes in the load impedance ZL.

  In order to reduce the characteristic change (load dependency) due to the change in the load impedance, a balance amplifier (balanced amplifier) is used. FIG. 19 is a diagram illustrating a balance amplifier (see, for example, Patent Documents 1 to 3). This balance amplifier distributes the input signal input from the input terminal IN to two amplification paths, amplifies, combines, and outputs from the output terminal OUT. The output terminal OUT is connected to the antenna ANT.

  Unit amplifiers A1 and A2 are provided in the two amplification paths, respectively. An input side phase shift circuit PIN1 is provided on the input side of the unit amplifier A1, and an output side phase shift circuit POUT1 is provided on the output side. An input side phase shift circuit PIN2 is provided on the input side of the unit amplifier A2, and an output side phase shift circuit POUT2 is provided on the output side.

  FIG. 20 is a Smith chart showing the balance amplification characteristics of FIG. 19 when the antenna impedance is 50Ω. The load impedances ZL1 and ZL2 viewed from the unit amplifiers A1 and A2 are substantially equal.

If the phase is advanced by + and the phase is delayed by-, the passing phase of each phase shift circuit is -45 degrees for PIN1, +45 degrees for PIN2, +45 degrees for POUT1, and -45 degrees for POUT2. That is, the difference between the passing phases of the output-side phase shift circuits POUT1 and POUT2 is 90 degrees. Thereby, even when the antenna impedance varies from 50Ω, the phases of the load impedances ZL1 and ZL2 are always different by 180 degrees as shown in FIG. Accordingly, in order to compensate for the characteristic variation due to the load impedance variation of each amplifier, the load dependency of the entire amplifier is small.
FIG. 7 of JP-A-9-64758 FIG. 2 of JP-T-2006-521060 FIG. 4 of JP-A-2006-311300

  There are the following Reference Example 1 and Reference Example 2 as power amplifiers for mobile communication terminals corresponding to two communication systems having different required output powers.

  FIG. 22 is a diagram illustrating a power amplifier according to Reference Example 1. One of the GSM balance amplifier B1 and the W-CDMA balance amplifier B2 is selected for each communication system by the switches SW1 and SW2. In the figure, the large number of unit amplifiers in the balance amplifier B1 means that a large (large area) transistor is used to obtain a large output power.

  FIG. 23 is a diagram illustrating a power amplifier according to Reference Example 2. A voltage control means CNT such as a DC / DC converter is provided between the unit amplifiers A1 and A2 and the power supply VCC. The voltage control means CNT controls the collector voltage or drain voltage of the unit amplifiers A1 and A2 composed of bipolar transistors, FETs, etc. according to the output power of the amplifier required in each communication system, so that the saturated output power of the amplifier is obtained. Change. Thereby, highly efficient operation | movement can be maintained in the communication system from which output power differs.

  In the reference example 1, the balance amplifier B1 and the balance amplifier B2 are provided for each communication system having different required output power. Therefore, when one communication system is used, the power amplifier for the other communication system is wasted. become. Therefore, there is a problem that the area of the semiconductor chip and the peripheral circuit constituting the power amplifier is increased, and the size and cost are large. Further, since the switch SW2 between the power amplifier and the antenna ANT needs to withstand a large amount of power, the passage loss is large. Therefore, it is necessary to increase the outputs of the unit amplifiers A1 and A2, and there is a problem that power consumption is large.

  In the reference example 2, in the case of a communication system in which required output power is greatly different, there is a problem that the switching range of the collector voltage or the drain voltage becomes too large and exceeds the voltage range in which the transistor operates satisfactorily. Further, since it is necessary to increase the current capacity of a DC / DC converter or the like that switches or varies the voltage, there is a problem that power consumption, size, and cost are large.

  The present invention has been made in order to solve the above-described problems, and an object thereof is to obtain power amplification capable of reducing power consumption, size, and cost because the load dependency of the entire amplifier is small. It is.

  The present invention relates to a power amplifier that distributes an input signal to at least three amplification paths, amplifies them, combines them, and outputs them. The input side phase shift circuit provided on the input side of each and the output side phase shift circuit provided on the output side of the unit amplifier of each amplification path, and in the first operation, all the amplifiers operate In the second operation in which the output power is smaller than that in the first operation, at least two unit amplifiers perform amplification operation, at least one unit amplifier is turned off, and the passing phases of the respective amplification paths are equal. However, the power amplifier is characterized in that the passing phases of the output-side phase shift circuits of the respective amplification paths are different from each other.

  According to the present invention, load dependency of the entire amplifier is small, and power consumption, size, and cost can be reduced.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a power amplifier according to Embodiment 1 of the present invention. This power amplifier distributes the input signal input from the input terminal IN to four amplification paths, amplifies, combines, and outputs from the output terminal OUT. The output terminal OUT is connected to the antenna ANT.

  Unit amplifiers A1 to A4 (first to fourth unit amplifiers) are provided in the four amplification paths, respectively. Input side phase shift circuits PIN1, PIN2 on the input side of the unit amplifier A1, input side phase shift circuits PIN1, PIN3 on the input side of the unit amplifier A2, input side phase shift circuits PIN4, PIN5 on the input side of the unit amplifier A3, unit amplifier Input-side phase shift circuits PIN4 and PIN6 are provided on the input side of A4.

  Output side phase shift circuits POUT1, POUT2 (first output side phase shift circuit) are provided on the output side of the unit amplifier A1, and output side phase shift circuits POUT3, POUT2 (second output side phase shift circuit) are provided on the output side of the unit amplifier A2. ), Output side phase shift circuits POUT4, POUT5 (third output side phase shift circuit) on the output side of the unit amplifier A3, and output side phase shift circuits POUT6, POUT5 (fourth output side shift circuit) on the output side of the unit amplifier A4. Phase circuit).

  The distributor D1 divides the input signal input from the input terminal IN into two and outputs it to the input-side phase shift circuits PIN1 and PIN4. The distributor D2 divides the output signal of the input side phase shift circuit PIN1 into two and outputs it to the input side phase shift circuits PIN2 and PIN3. The distributor D3 divides the output signal of the input side phase shift circuit PIN4 into two and outputs it to the input side phase shift circuits PIN5 and PIN6.

  The combiner C1 combines the output signals of the output side phase shift circuits POUT1 and POUT3 and outputs them to the output side phase shift circuit POUT2. The synthesizer C2 synthesizes the output signals of the output side phase shift circuits POUT4 and POUT6 and outputs them to the output side phase shift circuit POUT5. The synthesizer C3 synthesizes the output signals of the output side phase shift circuits POUT2 and POUT5 and outputs them to the output terminal OUT.

  A switch SW1 is provided between the input side phase shift circuit PIN4 and the distributor D1. A switch SW2 is provided between the output-side phase shift circuit POUT5 and the combiner C3. The unit amplifiers A1 and A2, the input side phase shift circuits PIN2 and PIN3, the output side phase shift circuits POUT1 and POUT3, the distributor D2 and the combiner C1 constitute a first balance amplifier B1. The unit amplifiers A3 and A4, the input side phase shift circuits PIN5 and PIN6, the output side phase shift circuits POUT4 and POUT6, the distributor D3 and the combiner C2 constitute a second balance amplifier B2.

  The phase shift circuit can be configured by a generally well-known LC circuit (lumped constant circuit). FIG. 2 is a diagram illustrating an example of a phase shift circuit for advancing the phase, and FIG. 3 is a diagram illustrating an example of a phase shift circuit for delaying the phase. By selecting the inductance of the inductor L and the capacitance value of the capacitor C, a desired passing phase can be obtained. Note that the phase shift circuit may be a circuit configuration also serving as an amplifier matching circuit. Further, the phase shift circuit may be constituted by a distributed constant circuit.

  If the phase advance is + and the phase delay is-, the passing phase of each phase shift circuit is as follows. PIN1 -22.5 degrees, PIN2 -45 degrees, PIN3 +45 degrees, PIN4 +22.5 degrees, PIN5 -45 degrees, PIN6 +45 degrees, POUT1 +45 degrees, POUT2 +22.5 degrees, POUT3 Is -45 degrees, POUT4 is +45 degrees, POUT5 is -22.5 degrees, and POUT6 is -45 degrees.

  Thus, although the passing phases of the respective amplification paths are equal, the passing phases of the output side phase shift circuits of the respective amplification paths are different. Specifically, the difference between the passing phase of the first output side phase shift circuits POUT1, POUT2 and the passing phase of the second output side phase shift circuits POUT3, POUT2 is 90 degrees. The difference between the passing phase of the third output side phase shift circuits POUT4 and POUT5 and the passing phase of the fourth output side phase shift circuits POUT6 and POUT5 is 90 degrees. The difference between the passing phase of the first and second output side phase shifting circuits and the passing phase of the third and fourth output side phase shifting circuits is 45 degrees or 135 degrees.

  The operation of the power amplifier of FIG. 1 will be described. In an operation such as GSM where a large (saturated) output power is required (first operation), the switches SW1 and SW2 are turned on, and all the amplifiers are operated. The input high frequency signal is distributed to the unit amplifiers A1 to A4, amplified, synthesized, and supplied to the antenna ANT. At this time, since the passing phases of the respective amplification paths are equal, the signals amplified in the respective amplification paths are synthesized with the same phase.

  Here, when the impedance Ζ_ant of the antenna ANT is a specified value (for example, 50Ω), the load impedances ZL1 to ZL4 viewed from the unit amplifiers A1 to A4 are substantially equal. On the other hand, when the impedance Ζ_ant is different from 50Ω, the phases of the load impedances ZL1 to ZL4 are different due to the influence of the output side phase shift circuit provided on the output side of each unit amplifier.

The phase of the wave that passes through the output-side phase shift circuit from the output end of each unit amplifier, is reflected by the antenna ANT, and returns is equivalent to the phase of the load impedances ZL1 to ZL4. Accordingly, the phases of the load impedances ZL1 to ZL4 are as follows.
ZL1 phase: + 45 + 22.5 + 22.5 + 45 = + 135
Phase of ZL2: −45 + 22.5 + 22.5−45 = −45
The phase of ZL3: + 45-22.5-22.5 + 45 = + 45
ZL4 phase: −45−22.5−22.5−45 = −135

Based on the phase of the load impedance ZL1, the phases of the load impedances ZL1 to ZL4 are different every 90 degrees as described below.
Phase of ZL1: 0
ZL2 phase: -180
ZL3 phase: -90
ZL4 phase: +90

  FIG. 4 is a Smith chart showing the characteristics of the power amplifier of FIG. When Ζ_ant deviates from 50Ω, the load impedances ZL1 to ZL4 of the unit amplifiers are equally divided in four directions at 360 degrees on the entire circumference of the Smith chart because the phases differ every 90 degrees. Therefore, since the load dependency of each unit amplifier characteristic complements, the load dependency in the whole amplifier is small. In particular, the load dependency of the entire amplifier is smaller than that of the balanced amplifier of FIG. 19 having two unit amplifiers.

  On the other hand, when the required (saturated) output power is relatively small (second operation), such as W-CDMA, the unit amplifiers A1 and A2 perform the amplification operation, and the unit amplifiers A3 and A4 are in the OFF state. It becomes. Then, the switches SW1 and SW2 are turned off and the amplification paths of the unit amplifiers A3 and A4 are disconnected. Specifically, the transistor is turned off (eg, pinch off) by the base or gate bias, or the collector or drain is controlled to be turned off (eg, voltage 0 V). The input high frequency signal is distributed to the unit amplifiers A1 and A2, amplified, synthesized, and supplied to the antenna ANT.

  When the impedance Ζ_ant of the antenna ANT is 50Ω, the load impedances ZL1 and ZL2 of the unit amplifiers A1 and A2 are approximately equal. When Ζ_ant deviates from 50Ω, the load impedances ZL1 and ZL2 are almost opposite in the Smith chart because the phases are different by 180 degrees. Accordingly, since the load dependency of the unit amplifiers A1 and A2 compensates, the load dependency of the entire amplifier is small.

  Further, unlike the first embodiment, the present embodiment does not have a useless amplifier that does not operate at the time of operation requiring a large amount of power such as GSM. Accordingly, the area of the semiconductor chip and the peripheral circuit constituting the power amplifier can be reduced, and the size and cost can be reduced. And since it is not necessary to provide a switch with a large passage loss between the power amplifier and the antenna ANT, power consumption can be reduced. Further, since two blocks (modules) having the same configuration may be used as the first balance amplifier B1 and the second balance amplifier B2, mass productivity is good.

  Note that the difference between the passing phase of the first output-side phase shift circuits POUT1 and POUT2 and the passing phase of the second output-side phase shift circuits POUT3 and POUT2 does not need to be completely 90 degrees, but 90 ± 25.5. It ’s fine. Similarly, the difference between the passing phase of the third output-side phase shift circuits POUT4 and POUT5 and the passing phase of the fourth output-side phase shift circuits POUT6 and POUT5 does not have to be completely 90 degrees, but 90 ± 25. It may be 5 degrees. The difference between the passing phase of the first and second output-side phase shift circuits and the passing phase of the third and fourth output-side phase shifting circuits is not necessarily 45 degrees or 135 degrees, and 45 ± 11 .25 degrees or 135 ± 11.25 degrees may be used. As a result, when the antenna impedance deviates from 50Ω, the load impedance seen by each unit amplifier is distributed almost evenly on the Smith chart, so the load dependency of the entire amplifier is small.

Embodiment 2. FIG.
FIG. 5 is a diagram showing a power amplifier according to Embodiment 2 of the present invention. The number of phase shift circuits and the passing phase are different from those of the first embodiment.

  Input side phase shift circuit PIN1 on the input side of unit amplifier A1, input side phase shift circuit PIN2 on the input side of unit amplifier A2, input side phase shift circuit PIN3 on the input side of unit amplifier A3, and input on the input side of unit amplifier A4 A side phase shift circuit PIN4 is provided.

  The output side phase shift circuit POUT1 (first output side phase shift circuit) is provided on the output side of the unit amplifier A1, the output side phase shift circuit POUT2 (second output side phase shift circuit) is provided on the output side of the unit amplifier A2, and the unit amplifier. An output side phase shift circuit POUT3 (third output side phase shift circuit) is provided on the output side of A3, and an output side phase shift circuit POUT4 (fourth output side phase shift circuit) is provided on the output side of the unit amplifier 4. .

  The passing phase of each phase shift circuit is -67.5 degrees for PIN1, +22.5 degrees for PIN2, -22.5 degrees for PIN3, +67.5 degrees for PIN4, +67.5 degrees for POUT1, and -22 for POUT2. .5 degrees, +22.5 degrees for POUT3, and -67.5 degrees for POUT4.

  As in the first embodiment, the pass phases of the amplification paths are the same, but the pass phases of the output side phase shift circuits of the amplification paths are different. Specifically, the difference between the passing phase of the first output side phase shift circuit POUT1 and the passing phase of the second output side phase shift circuit POUT2 is 90 degrees. The difference between the passing phase of the third output side phase shift circuit POUT3 and the passing phase of the fourth output side phase shift circuit POUT4 is 90 degrees. The difference between the passing phase of the first and second output side phase shifting circuits and the passing phase of the third and fourth output side phase shifting circuits is 45 degrees or 135 degrees. Thereby, the effect similar to Embodiment 1 can be acquired. In addition, since the number of phase shift circuits is smaller than that in the first embodiment, the size and cost can be further reduced.

Embodiment 3 FIG.
FIG. 6 is a diagram showing a power amplifier according to the third embodiment of the present invention. The passing phase of the phase shift circuit is different from that of the second embodiment. The passing phase of each phase shift circuit is -90 degrees for PIN1, 0 degrees for PIN2, -45 degrees for PIN3, +45 degrees for PIN4, +90 degrees for POUT1, 0 degrees for POUT2, +45 degrees for POUT3, and -45 for POUT4. Degree. Thereby, the same effect as Embodiment 2 can be acquired.

Embodiment 4 FIG.
FIG. 7 is a diagram showing a power amplifier according to Embodiment 4 of the present invention. This power amplifier distributes the input signal input from the input terminal IN to the three amplification paths, amplifies them, combines them, and outputs them from the output terminal OUT. The output terminal OUT is connected to the antenna ANT.

  A unit amplifier A1 (first unit amplifier), a unit amplifier A2 (second unit amplifier), and unit amplifiers A3 and A4 (third unit amplifier) are provided in the three amplification paths, respectively. Input side phase shift circuits PIN1 and PIN2 are provided on the input side of the unit amplifier A1, input side phase shift circuits PIN1 and PIN3 are provided on the input side of the unit amplifier A2, and input side phase shift circuits PIN4 and PIN5 are provided on the input side of the unit amplifiers A3 and A4. Is provided.

  Output side phase shift circuits POUT1, POUT2 (first output side phase shift circuit) are provided on the output side of the unit amplifier A1, and output side phase shift circuits POUT3, POUT2 (second output side phase shift circuit) are provided on the output side of the unit amplifier A2. ), Output-side phase shift circuits POUT4 and POUT5 (third output-side phase shift circuit) are provided on the output side of the unit amplifiers A3 and A4.

  The distributor D1 divides the input signal input from the input terminal IN into two and outputs it to the input-side phase shift circuits PIN1 and PIN4. The distributor D2 divides the output signal of the input side phase shift circuit PIN1 into two and outputs it to the input side phase shift circuits PIN2 and PIN3. The distributor D3 divides the output signal of the input side phase shift circuit PIN5 into two and outputs it to the unit amplifiers A3 and A4.

  The combiner C1 combines the output signals of the output side phase shift circuits POUT1 and POUT3 and outputs them to the output side phase shift circuit POUT2. The synthesizer C2 synthesizes the output signals of the unit amplifiers A3 and A4 and outputs them to the output side phase shift circuit POUT4. The synthesizer C3 synthesizes the output signals of the output side phase shift circuits POUT2 and POUT5 and outputs them to the output terminal OUT.

  A switch SW1 is provided between the input side phase shift circuit PIN4 and the distributor D1. A switch SW2 is provided between the output-side phase shift circuit POUT5 and the combiner C3. The passing phase of each phase shift circuit is +22.5 degrees for PIN1, -45 degrees for PIN2, +45 degrees for PIN3, -22.5 degrees for PIN4, -45 degrees for PIN5, +45 degrees for POUT1, and -22 for POUT2. .5 degrees, -45 degrees for POUT3, +45 degrees for POUT4, and +22.5 degrees for POUT5.

  Thus, although the passing phases of the respective amplification paths are equal, the passing phases of the output side phase shift circuits of the respective amplification paths are different. Specifically, the difference between the passing phase of the first output side phase shift circuits POUT1, POUT2 and the passing phase of the second output side phase shift circuits POUT3, POUT2 is 90 degrees. The difference between the passing phase of the first and second output side phase shifting circuits and the passing phase of the third output side phase shifting circuits POUT4 and POUT5 is 45 degrees or 135 degrees.

  The operation of the power amplifier of FIG. 7 will be described. In an operation such as GSM where a large (saturated) output power is required (first operation), the switches SW1 and SW2 are turned on, and all the amplifiers are operated. The input high frequency signal is distributed to the unit amplifiers A1 to A4, amplified, synthesized, and supplied to the antenna ANT. At this time, since the passing phases of the respective amplification paths are equal, the signals amplified in the respective amplification paths are synthesized with the same phase.

  Here, when the impedance Ζ_ant of the antenna ANT deviates from 50Ω, the load impedance of each unit amplifier is different in phase, so that it is divided into three directions at 360 degrees around the Smith chart. Therefore, since the load dependency of each unit amplifier characteristic complements, the load dependency in the whole amplifier is small. In particular, the load dependency of the entire amplifier is smaller than that of the balanced amplifier of FIG. 19 having two unit amplifiers.

  On the other hand, when the required (saturated) output power is relatively small (second operation), such as W-CDMA, the unit amplifiers A1 and A2 perform the amplification operation, and the unit amplifiers A3 and A4 are in the OFF state. It becomes. Then, the switches SW1 and SW2 are turned off and the amplification paths of the unit amplifiers A3 and A4 are disconnected. The input high frequency signal is distributed to the unit amplifiers A1 and A2, amplified, synthesized, and supplied to the antenna ANT.

  When the impedance Ζ_ant of the antenna ANT deviates from 50Ω, the load impedances ZL1 and ZL2 are almost opposite in the Smith chart because the phases differ by 180 degrees. Accordingly, since the load dependency of the unit amplifiers A1 and A2 compensates, the load dependency of the entire amplifier is small.

  In addition, the same effects as those of the embodiment can be obtained. In addition, since the number of phase shift circuits is smaller than that in the first embodiment, the size and cost can be further reduced.

  Note that the difference between the passing phase of the first output-side phase shift circuits POUT1 and POUT2 and the passing phase of the second output-side phase shift circuits POUT3 and POUT2 does not need to be completely 90 degrees, but 90 ± 25.5. It ’s fine. The difference between the passing phase of the first and second output side phase shifting circuits and the passing phase of the third output side phase shifting circuit need not be completely 45 degrees or 135 degrees, but 45 ± 11.25 degrees. Alternatively, it may be 135 ± 11.25 degrees.

  Further, the passing phase of the input side phase shift circuit PIN5 may be +45 degrees, and the passing phase of the output side phase shift circuit POUT4 may be -45 degrees. Further, it is possible to modify the input side phase shift circuits PIN4 and PIN5 as one phase shift circuit and the output side phase shift circuits POUT4 and POUT5 as one phase shift circuit.

  In addition, the unit amplifiers A3 and A4 have been described separately for comparison with the first embodiment, but this can be regarded as one unit amplifier because the in-phase synthesis is performed. Accordingly, a unit amplifier is provided in each of the three amplification paths.

Embodiment 5 FIG.
FIG. 8 is a diagram showing a power amplifier according to the fifth embodiment of the present invention. The number of phase shift circuits and the passing phase are different from those of the fourth embodiment.

  An input side phase shift circuit PIN1 is provided on the input side of the unit amplifier A1, an input side phase shift circuit PIN2 is provided on the input side of the unit amplifier A2, and an input side phase shift circuit PIN3 is provided on the input side of the unit amplifiers A3 and A4.

  The output side phase shift circuit POUT1 (first output side phase shift circuit) is provided on the output side of the unit amplifier A1, the output side phase shift circuit POUT2 (second output side phase shift circuit) is provided on the output side of the unit amplifier A2, and the unit amplifier. An output side phase shift circuit POUT3 (third output side phase shift circuit) is provided on the output side of A3 and A4.

  The passing phase of each phase shift circuit is -30 degrees for PIN1, +30 degrees for PIN2, -90 degrees for PIN3, +30 degrees for POUT1, -30 degrees for POUT2, and +90 degrees for POUT3.

  Thus, although the passing phases of the respective amplification paths are equal, the passing phases of the output side phase shift circuits of the respective amplification paths are different. Specifically, the difference between the passing phase of the first output-side phase shift circuit POUT1 and the passing phase of the second output-side phase shift circuit POUT2 is 60 degrees. The difference between the passing phase of the first and second output side phase shift circuits and the passing phase of the third output side phase shift circuit POUT3 is 60 degrees or 120 degrees.

  In this embodiment, the balance operation at the time of the low power operation (second operation) is not perfect, but the load dependency of the entire amplifier can be reduced to some extent. On the other hand, during high power operation (first operation), the impedance seen by each unit amplifier differs by 120 degrees and is evenly divided in three directions at 360 degrees around the Smith chart. Can reduce load dependency.

  Note that the difference between the passing phase of the first output-side phase shift circuit POUT1 and the passing phase of the second output-side phase shift circuit POUT2 does not need to be completely 60 degrees, but may be 60 ± 15 degrees. The difference between the passing phase of the first and second output-side phase shift circuits and the passing phase of the third output-side phase shift circuit POUT3 need not be completely 60 degrees or 120 degrees, but 60 ± 15 degrees or It may be 120 ± 15 degrees.

Embodiment 6 FIG.
FIG. 9 is a diagram showing a power amplifier according to the sixth embodiment of the present invention. Compared with the first embodiment, the arrangement of the input side phase shift circuit PIN4 and the switch SW1 is switched, and the arrangement of the output side phase shift circuit POUT5 and the switch SW2 is switched.

  During the low power operation (second operation), the switches SW1 and SW2 are turned OFF, and the unit amplifiers A3 and A4 do not operate. Since the phase shift circuit POUT5 is thus provided on the second balance amplifier B2 side, even when the impedance of the antenna ANT is 50Ω, the impedance ZL_b1 viewed from the first balance amplifier B1 on the antenna ANT side does not become 50Ω.

  In general, since the optimum load impedance is different when the output power of the amplifier is different, it is not necessarily optimal for the first balance amplifier that ZL_b1 is 50Ω during the low power operation. Further, since the balance amplifier operation can be performed if the passing phase of the phase shift circuit is a desired value, the order of the phase shift circuit and the switch is arbitrary. Therefore, it is only necessary to determine the arrangement of the switch and the phase shift circuit so that ZL_b1 is optimal during the low power operation. For example, the phase shift circuit POUT5 may be divided into 10 degree and 12.5 degree phase shift circuits, and a switch SW2 may be provided between them, or the switch SW2 may be provided between the unit amplifiers A3 and A4 and POUT4 and POUt6. It may be provided. Thus, by optimizing the load impedance at the time of low power operation, the efficiency and distortion characteristics can be further improved.

Embodiment 7 FIG.
FIG. 10 is a diagram showing a power amplifier according to the seventh embodiment of the present invention. The number and arrangement of switches and the passing phase of the phase shift circuit are different from those of the first embodiment.

  The switch SW1 is provided between the distributor D1 and the phase shift circuit PIN3, the switch SW2 is provided between the combiner C1 and the phase shift circuit POUT3, and the switch SW3 is provided between the distributor D3 and the phase shift circuit PIN6. The switch SW4 is provided between the combiner C2 and the phase shift circuit POUT6.

  The passing phase of each phase shift circuit is -45 degrees for PIN1, -22.5 degrees for PIN2, +22.5 degrees for PIN3, +45 degrees for PIN4, -22.5 degrees for PIN5, +22.5 degrees for PIN6, POUT1 is +22.5 degrees, POUT2 is +45 degrees, POUT3 is -22.5 degrees, POUT4 is +22.5 degrees, POUT5 is -45 degrees, and POUT6 is -22.5 degrees.

  An operation of the power amplifier of FIG. 10 will be described. During high power operation (first operation) such as GSM, the switches SW1 to SW4 are turned on, and all amplifiers operate. On the other hand, during the low power operation (second operation), the unit amplifiers A1 and A3 perform the amplification operation, and the unit amplifiers A2 and A4 are turned off. Then, the switches SW1 to SW4 are turned off and the amplification paths of the unit amplifiers A2 and A4 are disconnected.

  Thereby, the same effect as in the first embodiment can be obtained. Further, since the passing power of each of the switches SW1 to SW4 is smaller than that in the first embodiment, a switch with a relatively small loss can be used. Therefore, the efficiency of the entire amplifier can be improved. Furthermore, since the transistor elements operating during the low power operation are physically separated, this is advantageous in terms of heat dissipation.

  Note that the output side phase difference between the four amplification paths is every 45 degrees, and the output side phase difference between the two amplification paths operating at low power is 90 degrees. Is not limited to the above combinations.

Embodiment 8 FIG.
FIG. 11 is a diagram showing a power amplifier according to the eighth embodiment of the present invention. Compared to the seventh embodiment, the arrangement of the input side phase shift circuit PIN3 and the switch SW1 is switched, the arrangement of the input side phase shift circuit PIN6 and the switch SW3 is switched, and the arrangement of the output side phase shift circuit POUT3 and the switch SW2 is switched. The arrangement of the output side phase shift circuit POUT6 and the switch SW4 is switched.

  The switches SW1 to SW4 are turned off during the low power operation, but the phase shift circuits POUT3 and POUT6 are connected to the distributors C1 and C2. As a result, the load impedances ZL_e1 and ZL_e3 viewed from the unit amplifiers A1 and A3 operating at the time of the low power operation can be optimized, so that the efficiency and distortion characteristics can be further improved.

Embodiment 9 FIG.
FIG. 12 is a diagram illustrating a power amplifier according to the ninth embodiment of the present invention. In this power amplifier, the switches SW1 and SW2 in the configuration of the sixth embodiment are SPDT (Single Pole Double Throw) switches.

  The switches SW1 and SW2 are connected to the second balance amplifier B2 during high power operation, and are connected to the impedance elements Zti and Zto during low power operation. As a result, the load impedance ZL_b1 viewed from the unit amplifiers A1 and A2 operating at the time of the low power operation can be optimized, so that the efficiency and distortion characteristics can be further improved.

  Depending on the impedance conditions required for the unit amplifiers A1 and A3, the arrangement of the impedance elements Zti and Zto and the phase shift circuits PIN5, PIN6, POUT4 and POUT6 may be interchanged.

Embodiment 10 FIG.
FIG. 13 is a diagram showing a power amplifier according to the tenth embodiment of the present invention. In this power amplifier, the switches SW1 to SW4 are SPDT switches in the configuration of the seventh embodiment.

  The switches SW1 to SW4 are connected to the amplification path side during high power operation, and are connected to the impedance elements Zti and Zto during low power operation. As a result, the load impedances ZL_e1 and ZL_e3 viewed from the unit amplifiers A1 and A3 operating at the time of the low power operation can be optimized, so that the efficiency and distortion characteristics can be further improved.

Embodiment 11 FIG.
FIG. 14 is a diagram showing a power amplifier according to the eleventh embodiment of the present invention. Compared with the first embodiment, the switches SW1 and SW2 are not provided.

  In many cases, an OFF-state transistor is capacitive in terms of impedance (admittance Ytr_off) viewed from the output side due to its parasitic capacitance. Due to this capacitance, the impedance when the amplification path when the unit amplifier is in the OFF state is viewed from the outside is not opened. In the first embodiment, therefore, the amplification paths of the unit amplifiers A3 and A4 in the OFF state are separated by turning off the switches SW1 and SW2 during the low power operation.

  During the low power operation, the unit amplifiers A3 and A4 are turned off. The admittance Ytr_off viewed from the output side of the unit amplifiers A3 and A4 in the OFF state is often capacitive due to the parasitic capacitance of the transistor.

  FIG. 15 is a Smith chart showing the characteristics of the power amplifier of FIG. Due to the phase shift circuits POUT4 to POUT6 provided on the output side of the unit amplifiers A3 and A4, the admittances Yo_e3 and Yo_e4 at the output ends of the phase shift circuits POUT4 and POUT5 are on the opposite side on the Smith chart with reference to Ytr_off. The admittance at the point where these are combined is the sum of these values. The admittance Yo_b2 at the output terminal of the phase shift circuit POUT5 has a value close to the open point. Accordingly, the impedance of the unit amplifiers A3 and A4 in the OFF state when the small power operation is performed from the synthesizer C3 is opened. For this reason, even if the switches SW1 and SW2 for separating the amplification paths of the unit amplifiers A3 and A4 in the OFF state are omitted, the influence of the amplification paths of the unit amplifiers A3 and A4 in the OFF state can be eliminated.

  Here, since a matching circuit may be provided on the output side of the unit amplifier, Ytr_off is not necessarily capacitive. If it is inductive, the same effect as described above can be obtained by using a phase shift circuit of +22.5 degrees instead of the phase shift circuit POUT5 of -22.5 degrees.

  A circuit is similarly configured on the input side. At this time, the phase shift amount of the input side phase shift circuit is set so that the impedance when the amplification path of the unit amplifiers A3 and A4 in the OFF state is viewed from the input signal distribution point is opened. However, since the power is combined by the combiner, it is necessary to make the passing phases of the respective amplification paths equal. Since the sum of the passing phase amounts of the phase shift circuits PIN4 to PIN6 only needs to be a specified value, the passing phase amounts of the phase shift circuits PIN4 to PIN6 may be set to, for example, +12.5 degrees, −35 degrees, and +55 degrees. .

  As described above, the fact that the unit amplifiers A3 and A4 constitute a balance amplifier, and that the phase shift circuits having different phase shift amounts are provided at the input and output of each unit amplifier, pass through the phase shift circuit. By setting the phase amount, the impedance of the unit amplifiers A3 and A4 in the OFF state viewed from the amplification path can be opened. Thereby, since the switch can be omitted, loss due to the switch can be eliminated and the efficiency of the amplifier can be improved.

  In the configurations of the second to tenth embodiments, the switches SW1 to SW4 can be omitted by similarly adjusting the passing phase amount of the phase shift circuit.

Embodiment 12 FIG.
FIG. 16 is a diagram showing a power amplifier according to the twelfth embodiment of the present invention. Unlike the first embodiment, voltage control means CNT such as a DC / DC converter is provided between the unit amplifiers A1 and A2 and the power supply VCC. The voltage control means CNT controls the collector voltage or drain voltage of the unit amplifiers A1 and A2 composed of bipolar transistors, FETs, etc. according to the output power of the amplifier required in each communication system, so that the saturated output power of the amplifier is obtained. Change (switch).

  The operation of the power amplifier of FIG. 16 will be described. During high power operation, all unit amplifiers operate as in the first embodiment. At this time, the collector voltages or drain voltages of the four unit amplifiers are equal.

  On the other hand, at the time of the low power operation, the unit amplifiers A1 and A2 perform the amplification operation similarly to the first embodiment, the unit amplifiers A3 and A4 are turned off, and the switches SW1 and SW2 are turned off. Further, by changing the collector voltage or drain voltage of the amplifying elements of the first and second unit amplifiers, it is possible to realize the optimum saturation output power during the low power operation.

  Here, the difference in saturation output power required during high power operation and low power operation is generally not 3 dB. That is, the saturation output power of both is not 2 to 1. Therefore, in order to obtain an amplifier having an optimum saturation output power during each operation, it is necessary to use units amplifiers A1 and A2 and unit amplifiers A3 and A4 having different saturation output powers in the first embodiment. In this case, during the high power operation in which all the unit amplifiers operate, the balance operation by the four unit amplifiers cannot be realized completely, and the load dependency increases. On the other hand, when the saturated output powers of all the unit amplifiers A1 to A4 are made equal in the first embodiment, the balance amplifier operation at the time of high power operation in which all the unit amplifiers operate becomes good, but the optimum at the time of low power operation. An amplifier having a saturated output power cannot be obtained, and the efficiency may decrease.

  On the other hand, in this embodiment, since the saturated output power of all the unit amplifiers is equal, a perfect balance operation consisting of all the unit amplifiers is realized at the time of a large output operation, and the load dependency of the entire amplifier is small. And since the saturation output power of an amplifier can be optimized also at the time of a low electric power operation | movement, the efficiency of an amplifier can be improved.

  In addition, since the same balance amplifiers including the size of the transistors can be used as the first balance amplifier B1 and the second balance amplifier B2, the mass productivity can be further improved and the cost can be further reduced.

  In addition, the current value that must be controlled by the voltage control means CNT is significantly smaller than that of the reference example 2. Therefore, the size, loss, cost, etc. of the voltage control means CNT can be reduced.

  In addition, you may provide the voltage control means CNT similarly to Embodiment 2-11. Thereby, the same effect as this embodiment can be obtained.

  In the first to twelfth embodiments, the power amplifier that can be shared by a system that requires high power and a system that requires low power has been described. The present invention is not limited to this, and the above-described configuration can be applied to a power amplifier that operates to vary the output power depending on the distance from the base station, for example, in the same communication system.

  In the first to twelfth embodiments, the case where the number of amplification paths is three or four has been described. However, the present invention is not limited to this, and the number of amplification paths may be three or more. In this case, at the time of the second operation, at least two unit amplifiers perform an amplification operation, and at least one unit amplifier is turned off. In this case, when the number of unit amplifiers is n, it is preferable that the phase difference between the output side phase shift circuits of each unit amplifier is (180 / n) degrees.

  In addition, since the pass phase on the input / output side of each unit amplifier only needs to be a relatively specified value, a distribution / synthesis function such as a 90-degree hybrid coupler can be used instead of a phase shift circuit, a distributor and a combiner. A circuit in which a function of generating a phase difference in a plurality of input / output paths is integrated may be used.

It is a figure which shows the power amplifier which concerns on Embodiment 1 of this invention. It is a figure which shows an example of the phase shift circuit which advances a phase. It is a figure which shows an example of the phase shift circuit which delays a phase. 2 is a Smith chart showing the characteristics of the power amplifier of FIG. 1. It is a figure which shows the power amplifier which concerns on Embodiment 2 of this invention. It is a figure which shows the power amplifier which concerns on Embodiment 3 of this invention. It is a figure which shows the power amplifier which concerns on Embodiment 4 of invention. It is a figure which shows the power amplifier which concerns on Embodiment 5 of this invention. It is a figure which shows the power amplifier which concerns on Embodiment 6 of this invention. It is a figure which shows the power amplifier which concerns on Embodiment 7 of this invention. It is a figure which shows the power amplifier which concerns on Embodiment 8 of this invention. It is a figure which shows the power amplifier which concerns on Embodiment 9 of this invention. It is a figure which shows the power amplifier which concerns on Embodiment 10 of this invention. It is a figure which shows the power amplifier which concerns on Embodiment 11 of this invention. It is a Smith chart which shows the characteristic of the power amplifier of FIG. It is a figure which shows the power amplifier which concerns on Embodiment 12 of this invention. It is a figure which shows the power amplifier which abbreviate | omitted the isolator. It is a Smith chart which shows the characteristic of the power amplifier of FIG. It is a figure which shows a balance amplifier. 20 is a Smith chart showing the balance amplification characteristics of FIG. 19 when the antenna impedance is 50Ω. 20 is a Smith chart showing the balance amplification characteristics of FIG. 19 when the antenna impedance varies from 50Ω. 5 is a diagram illustrating a power amplifier according to Reference Example 1. FIG. 6 is a diagram illustrating a power amplifier according to Reference Example 2. FIG.

Explanation of symbols

A1 to A4 Unit amplifiers PIN1 to PIN6 Input side phase shift circuit POUT1 to POUT6 Output side phase shift circuit

Claims (6)

A power amplifier that distributes an input signal to at least three amplification paths, amplifies the signal, and combines and outputs the amplified signal.
A unit amplifier provided in each amplification path;
An input side phase shift circuit provided on the input side of the unit amplifier of each amplification path;
An output side phase shift circuit provided on the output side of the unit amplifier of each amplification path,
During the first operation, all amplifiers are operating,
At the time of the second operation in which the output power is smaller than that at the time of the first operation, at least two unit amplifiers perform amplification operation, and at least one unit amplifier is turned off,
While passing phase of the amplification paths are equal, the passing phase of the output-side phase shift circuit for each amplification path varies respectively,
There are four amplification paths,
The unit amplifiers provided in the four amplification paths are first to fourth unit amplifiers, respectively.
The output side phase shift circuits provided on the output side of the first to fourth unit amplifiers are first to fourth output side phase shift circuits, respectively.
At the time of the second operation, the first and second unit amplifiers perform an amplification operation, and the third and fourth unit amplifiers are turned off,
The difference between the passing phase of the first output side phase shifting circuit and the passing phase of the second output side phase shifting circuit is 90 ± 25.5 degrees,
The difference between the passing phase of the third output side phase shift circuit and the passing phase of the fourth output side phase shift circuit is 90 ± 25.5 degrees,
The difference between the passing phase of the first and second output side phase shifting circuits and the passing phase of the third and fourth output side phase shifting circuits is 45 ± 11.25 degrees or 135 ± 11.25 degrees. A power amplifier characterized by that.   A power amplifier that distributes an input signal to at least three amplification paths, amplifies the signal, and combines and outputs the amplified signal.
  A unit amplifier provided in each amplification path;
  An input side phase shift circuit provided on the input side of the unit amplifier of each amplification path;
  An output side phase shift circuit provided on the output side of the unit amplifier of each amplification path,
  During the first operation, all amplifiers are operating,
  At the time of the second operation in which the output power is smaller than that at the time of the first operation, at least two unit amplifiers perform amplification operation, and at least one unit amplifier is turned off,
  The passing phase of each amplification path is equal, but the passing phase of the output side phase shift circuit of each amplification path is different,
  The amplification path is 3,
  The unit amplifiers provided in these three amplification paths are first to third unit amplifiers, respectively.
  The output side phase shift circuits provided on the output side of the first to third unit amplifiers are first to third output side phase shift circuits, respectively.
  During the second operation, the first and second unit amplifiers perform an amplification operation, and the third unit amplifier is turned off.
  The difference between the passing phase of the first output side phase shifting circuit and the passing phase of the second output side phase shifting circuit is 90 ± 25.5 degrees,
  The difference between the passing phase of the first and second output side phase shifting circuits and the passing phase of the third output side phase shifting circuit is 45 ± 11.25 degrees or 135 ± 11.25 degrees. A power amplifier.   A power amplifier that distributes an input signal to at least three amplification paths, amplifies the signal, and combines and outputs the amplified signal.
  A unit amplifier provided in each amplification path;
  An input side phase shift circuit provided on the input side of the unit amplifier of each amplification path;
  An output side phase shift circuit provided on the output side of the unit amplifier of each amplification path,
  During the first operation, all amplifiers are operating,
  At the time of the second operation in which the output power is smaller than that at the time of the first operation, at least two unit amplifiers perform amplification operation, and at least one unit amplifier is turned off,
  The passing phase of each amplification path is equal, but the passing phase of the output side phase shift circuit of each amplification path is different,
  The amplification path is 3,
  The unit amplifiers provided in these three amplification paths are first to third unit amplifiers, respectively.
  The output side phase shift circuits provided on the output side of the first to third unit amplifiers are first to third output side phase shift circuits, respectively.
  During the second operation, the first and second unit amplifiers perform an amplification operation, and the third unit amplifier is turned off.
  The difference between the passing phase of the first output side phase shift circuit and the passing phase of the second output side phase shift circuit is 60 ± 15 degrees,
  The difference between the passing phase of the first and second output side phase shifting circuits and the passing phase of the third output side phase shifting circuit is 60 ± 15 degrees or 120 ± 15 degrees. . The power amplifier according to any one of claims 1 to 3 , further comprising a switch for disconnecting an amplification path in which the unit amplifier is in an OFF state during the second operation. The phase amount of the input side phase shift circuit and the output side phase shift circuit of each amplification path is set so that the impedance when the amplification path when the unit amplifier is OFF is viewed from the input signal distribution point and the synthesis point is opened. The power amplifier according to claim 1 , wherein the power amplifier is a power amplifier. 6. The power amplifier according to claim 1 , further comprising voltage control means for controlling a collector voltage or a drain voltage of a unit amplifier that operates in the second operation.

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