JP5100086B2 - Inductor element and manufacturing method thereof - Google Patents

Description

  The present invention relates to an inductor and a manufacturing method thereof. More specifically, the present invention relates to an inductor element formed of a conductive thin film deposited on a semiconductor substrate and a manufacturing method thereof.

  In an inductor element used for a high frequency device, a high Q value (Quality Factor) is required. However, in an inductor element formed by patterning a conductive thin film deposited on a silicon semiconductor substrate, the conductive thin film itself has a high conductor loss, and parasitic capacitance is generated between the conductive thin film pattern and the semiconductor substrate. It is difficult to obtain a high Q value.

  In a semiconductor device called a system-on-chip (SOC), a plurality of types of signal circuits such as a digital signal circuit, an analog signal circuit, and a high-frequency signal circuit are integrated in one chip. In such a semiconductor device, it is known that interaction between circuit blocks, in particular, digital switching noise coupled to an analog signal circuit and a high-frequency signal circuit through a silicon semiconductor substrate deteriorates device characteristics. In particular, an RF passive element that occupies a large area on the substrate, such as an inductor element, is easily coupled between the silicon semiconductor substrate and the passive element, and the characteristics are degraded.

  Therefore, Patent Document 1 below describes that a polysilicon layer having the same potential as that of a substrate is formed on a silicon semiconductor substrate, and an inductor element is formed by a conductive thin film formed thereon. Thereby, the capacitance between the inductor element and the polysilicon layer and the resistance of the polysilicon layer itself become a parasitic capacitance and a parasitic resistance to the inductor element, so that the parasitic resistance and the parasitic capacitance can be reduced.

Patent Document 2 below describes that a groove filled with an insulating material is formed on a semiconductor substrate and an inductor element is loaded thereon. This improves the insulation of the semiconductor substrate, prevents high-frequency current leakage from the inductor element to the substrate and induced current from the substrate to the inductor element, and reduces the loss of the inductor element.
JP 2000-188373 A JP 2000-77610 A

  However, in the structure described in Patent Document 1, the parasitic capacitance between the conductive thin film and the polysilicon layer forming the inductor element becomes large, and a large characteristic improvement cannot be obtained. Further, the structure described in Patent Document 2 does not contribute to blocking the substrate noise.

  Furthermore, it has also been proposed to use a bonding wire as an inductor element that has a high Q value and is not easily affected by noise through the substrate. However, there is a problem that a bonding wire is separately incorporated in an integrated circuit manufactured by a wafer process and productivity is lowered.

  In order to solve the above-mentioned problem, as a first embodiment of the present invention, a step of etching a semiconductor substrate to form a columnar portion whose surface parallel to the surface direction of the semiconductor substrate is separated from the surroundings, and a surface of the columnar portion And a step of forming a conductor layer on the inductor element. Thereby, the ratio of the conductor area with respect to a board | substrate becomes large, and an inductor with little fall of Q value resulting from the parasitic capacitance of a board | substrate can be manufactured. Moreover, it can escape from the influence of substrate noise.

  In the manufacturing method, the step of forming the columnar portion may be a step of forming a thinned region in which the semiconductor substrate is thinned in the thickness direction, and a pair of through holes in the thinned region. Thereby, an inductor having a high Q value can be manufactured by a semiconductor process. Therefore, the desired specification can be realized with high accuracy and is suitable for mass production.

  Furthermore, in the above manufacturing method, the step of forming the conductor layer may include a step of depositing the conductor layer on the inner surface of the through hole. Thereby, the conductor area can be further increased and the conductor loss of the inductor element can be reduced.

  Moreover, in the said manufacturing method, the process of forming a conductor layer may have the process of depositing a conductor layer on the perimeter of the surface of a columnar part. As a result, it is possible to manufacture an inductor having a larger conductor area and a lower parasitic capacitance and conductor loss even though the occupied area on the substrate is small.

  In the manufacturing method, the step of forming the conductor layer may include a step of forming the conductor layer to a thickness equal to a depth through which the high-frequency current flows. Thereby, the film thickness of the conductor layer can be reduced to save material, and the time required for manufacturing can be saved.

  Moreover, in the said manufacturing method, the process of forming a conductor layer may have the process of forming a conductor layer with a metal thin film. Thereby, an inductor with low conductor loss can be manufactured easily.

  Moreover, in the said manufacturing method, the process of forming a conductor layer may have the process of depositing a Cr layer on the said surface of a columnar part, and the process of depositing Au layer on a Cr layer. Thereby, the adhesion strength of the Au layer can be improved and the diffusion of Au into the substrate can be suppressed.

  In the manufacturing method, the step of forming the conductor layer may include a step of forming a Cr layer by a sputtering method and a step of forming an Au layer by a plating method. Thereby, the Cr layer and the Au layer can be collectively formed on the entire surface of the three-dimensional columnar portion.

  Furthermore, as a second aspect of the present invention, an inductor element manufactured by the above manufacturing method is provided. As a result, the material cost and the manufacturing cost are low, and an inductor having a high Q value is supplied despite its small size.

  Still further, as a third embodiment of the present invention, a columnar part formed by etching a semiconductor substrate and having a plane parallel to the plane direction of the semiconductor substrate spaced from the periphery, and a conductor attached to the surface of the columnar part An inductor element comprising a layer is provided. As a result, a semiconductor process is used to provide an inductor having a high Q value despite its low material cost and low manufacturing cost and small size. In addition, it is less susceptible to substrate noise.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. Therefore, a sub-combination of these feature groups can also be an invention.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 to FIG. 14 are diagrams showing the manufacturing process of the inductor element 300 according to one embodiment for each procedure. 4, 6, 8, and 10 are cross-sectional views corresponding to the perspective views shown in FIGS. 3, 5, 7, and 9, respectively. Further, in these drawings, common constituent elements are denoted by common reference numerals, and redundant description is omitted.

  FIG. 1 is a perspective view showing the shape of a semiconductor substrate 110 that is a processing target 100. However, although manufacturing of a single inductor element 300 will be described below, the semiconductor substrate 110 may be a part of a large semiconductor wafer 410 as described later.

  FIG. 2 is a perspective view showing a process of forming a resist layer 200 used for forming the thinned region 120. As shown in the figure, the resist layer 200 is formed in a pattern in which the central portion is removed so that the region to be thinned is exposed on the lower surface of the semiconductor substrate 110. Thereby, the area | region used as the thinning area | region 120 can be selectively processed.

  In the state shown in FIG. 2, the semiconductor substrate 110 is thinned by ion milling, chemical etching, or the like. Note that the resist layer 200 is removed after the thinning process.

  FIG. 3 is a perspective view showing the shape of the thinned region 120 in which the semiconductor substrate 110 is formed. As shown in the figure, the thinned region 120 is formed at the center of the lower surface of the semiconductor substrate 110. 4 is a cross-sectional view showing an XX cross section of the semiconductor substrate 110 shown in FIG. As shown in the figure, in the thinned region 120, the thickness of the semiconductor substrate 110 is reduced to about 100 μm.

  FIG. 5 is a perspective view showing a process of loading the resist layer 210 used when forming the through hole 130 on the semiconductor substrate 110 on which the thinned region 120 is formed. 6 is a cross-sectional view showing an XX cross section of the semiconductor substrate 110 shown in FIG. As shown in these drawings, the resist layer 210 is loaded on the upper surface of the semiconductor substrate 110. Here, the resist layer 210 is provided on the upper part of the center of the inductor. In the example shown in FIG. 6, the resist layer 210 in the region corresponding to the thinned region 120 is removed, and a pattern is formed in which the resist layer 210 is left in a region having a constant width that cuts through the center of the thinned region 120. . Therefore, the region where the resist layer 210 is removed is divided into two regions. For example, the width along the surface direction of the central resist layer 210 is about 100 μm.

  In the state shown in FIG. 5, the through hole 130 is formed in the semiconductor substrate 110 by ion milling, chemical etching, or the like. Further, after the through hole processing, the resist layer 210 is removed.

  FIG. 7 is a perspective view showing the shape of the semiconductor substrate 110 in which the through hole 130 is formed using the resist layer 210. 8 is a cross-sectional view showing an XX cross section of the semiconductor substrate 110 shown in FIG.

  As shown in these drawings, the semiconductor substrate 110 processed using the resist layer 210 has a pair of through holes 130 further inside the thinned region 120 whose thickness is reduced. In other words, the columnar portion 140 is formed in a region sandwiched between the pair of through holes 130. Note that the upper surface of the columnar portion 140 is separated from the peripheral surface of the semiconductor substrate 110.

  FIG. 9 is a diagram showing the shape of the Cr layer 310 that is the base of the conductor layer formed on the semiconductor substrate 110 processed as described above. 10 is a cross-sectional view showing an XX cross section of the semiconductor substrate 110 shown in FIG.

  As shown in the figure, a Cr layer 310 is deposited on the entire surface of the semiconductor substrate 110 by sputtering or the like. The Cr layer 310 preferably has a thickness of about several μm. Note that the Cr layer 310 may be formed by a CVD method. The adhesion strength of the Au layer 320 can be improved by depositing an Au layer 320 to be described later using the Cr layer 310 as a base. Further, since the dense Cr layer 310 serves as a barrier, it is possible to prevent the material of the Au layer 320 from diffusing into the columnar part 140 formed of a semiconductor material.

  FIG. 11 is a cross-sectional view showing a step of forming a resist layer 220 used when depositing the Au layer 320 on the columnar portion 140 of the semiconductor substrate 110 on which the Cr layer 310 is formed as described above. As shown in the figure, the resist layer 220 is formed on the surface of the semiconductor substrate 110 in a region other than the columnar portion 140. Accordingly, in the center of the resist layer 220, a columnar portion 140 having a square cross section perpendicular to the surface direction of the semiconductor substrate 110 is formed along the surface direction of the semiconductor substrate 110, and the side surfaces thereof are exposed.

  FIG. 12 is a cross-sectional view showing a process of forming the Au layer 320 on the semiconductor substrate 110. As shown in the figure, since the Cr layer 310 is already formed in the region where the Au layer 320 is to be formed, the Au layer 320 having a film thickness of several tens of μm can be formed by plating.

  According to the plating method or the like, a plating layer with a film thickness of several tens of μm can be formed. However, when the manufactured inductor element 300 is used in the microwave band, the region where current flows inside the conductor layer is from the surface. It is about several μm. Therefore, the thickness of the Au layer 320 may be as long as the current flows. Specifically, the Au layer 320 may be formed uniformly with a thickness of about 2 μm.

  As described above, in the steps up to FIG. 11, regions other than the thinned region 120 are masked by the resist layer 220 on both sides of the semiconductor substrate 110. Accordingly, the Au layer 320 can be formed by depositing Au of the columnar portion 140 on the surface by sputtering.

  By the procedure as described above, the cylindrical Au layer 320 is formed on the surface of the columnar portion 140. This cylindrical Au layer 320 can be used as an inductor having a wide effective cross-sectional area through which a frequency current flows. Such an inductor has a high Q value because it is away from the surrounding dielectric (semiconductor substrate 110). Further, since the inside becomes substantially equipotential, the dielectric loss is low, and the decrease in the Q value is small despite the presence of the columnar portion 140 of the semiconductor substrate 110. However, as will be described later, higher characteristics can be obtained by removing the columnar portion 140.

  FIG. 13 is a cross-sectional view showing a step of removing the columnar portion 140 from the inside of the Cr layer 310 and the Au layer 320. As shown in the figure, the core layer 140 and the Au layer 320 laminated on the Cr layer 310 are removed from the columnar portion 140 made of a semiconductor material to make an air core, and the characteristics as the inductor element 300 are obtained. Can be improved. Since the Cr layer 310 and the Au layer 320 are chemically stable, the columnar portion 140 can be removed by etching using any etching agent that removes the semiconductor material, for example, KOH.

  FIG. 14 is a perspective view independently showing the shape of a cylindrical inductor element 300 manufactured through a series of steps as described above. As shown in the figure, this inductor element 300 includes a hollow hollow, prismatic Cr layer 310 and an Au layer 320 laminated on the surface thereof. Therefore, the air core inductor element 300 has good characteristics.

  FIG. 15 is a diagram showing a process of manufacturing a plurality of inductor elements 300 from a single semiconductor wafer 410 in a lump. According to a wafer process technology such as a Si wafer, a minute structure having a dimension of about several hundreds of μm can be manufactured with good reproducibility. Therefore, according to the method described with reference to FIGS. 1 to 14, a plurality of processing objects 100 can be collectively processed on a single semiconductor wafer 410 as shown in FIG. Thereby, the inductor element 300 having the above-described good characteristics can be industrially manufactured and supplied with high productivity.

  13 and 14, the columnar portion 140 is removed from the inductor element 300, but it may be used without removing it. Further, the columnar portion 140 of the inductor element 300 of FIGS. 1 to 14 is a quadrangular column with a square cross section, but is not limited thereto, and may be a cylinder or the like.

  Since the central portion of the inductor element manufactured in this way is a non-conductor, it is not easily affected by parasitic capacitance and noise from the substrate. Therefore, it operates as an inductor element having a high Q value. Further, since the inductor element is formed of a metal conductor, the conductor loss is small, and a high Q value can be obtained from this point. Furthermore, since it can be manufactured by a wafer process, it can be efficiently manufactured with the same equipment as the integrated circuit.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. Further, it is apparent from the description of the scope of claims that the embodiment added with such changes or improvements can be included in the technical scope of the present invention.

1 is a perspective view showing a shape of a semiconductor substrate 110 to be processed 100. FIG. 5 is a perspective view showing a step of forming a resist layer 200 used for forming the thinned region 120. FIG. It is a perspective view which shows the shape of the semiconductor substrate 110 in which the thin area | region 120 was formed. It is sectional drawing which shows the XX cross section of the semiconductor substrate 110 shown in FIG. 2 is a perspective view showing a semiconductor substrate 110 loaded with a resist layer 210. FIG. It is sectional drawing which shows the XX cross section of the semiconductor substrate 110 shown in FIG. It is a perspective view which shows the shape of the semiconductor substrate 110 processed using the resist layer 210. FIG. It is sectional drawing which shows the XX cross section of the semiconductor substrate 110 shown in FIG. 4 is a perspective view showing a shape of a semiconductor substrate 110 loaded with a resist layer 220. FIG. It is sectional drawing which shows the XX cross section of the semiconductor substrate 110 shown in FIG. It is sectional drawing which shows the semiconductor substrate 110 in which Cr layer 310 was formed. It is sectional drawing which shows the semiconductor substrate 110 in which Au layer 320 was formed. 4 is a cross-sectional view showing a state where a columnar portion 140 is removed from the inside of a Cr layer 310 and an Au layer 320. FIG. 4 is a perspective view showing a shape of an inductor element 300. FIG. 5 is a diagram illustrating a process of manufacturing a plurality of inductor elements 300 from a single semiconductor wafer 410 at a time. FIG.

Explanation of symbols

100, 400 processing target, 110 substrate, 120 thinned region, 130 through hole, 140 columnar part, 200, 210, 220, 230 resist layer, 300 inductor element, 310 Cr layer, 320 Au layer, 410 semiconductor wafer

Claims (12)

Etching the semiconductor substrate to form a columnar portion whose surface parallel to the surface direction of the semiconductor substrate is separated from the surroundings;
Forming a conductor layer on the surface of the columnar portion ;
A method of manufacturing an inductor element, comprising: removing the columnar part .   The step of forming the columnar part includes a step of forming a thinned region in which the semiconductor substrate is thinned in a thickness direction, and a step of forming a pair of through holes in the thinned region. Production method. A step of forming a thinned region in which the semiconductor substrate is thinned in a thickness direction; and a step of forming a pair of through holes in the thinned region; Forming a columnar part having a plane parallel to
Forming a conductor layer on the surface of the columnar part;
A method of manufacturing an inductor element comprising:   The manufacturing method according to claim 3, wherein the step of forming the conductor layer includes a step of depositing the conductor layer on the inner surface of the through hole. The manufacturing method according to claim 4 , wherein the step of forming the conductor layer includes a step of depositing the conductor layer on the entire circumference of the surface of the columnar part. The manufacturing method according to any one of claims 1 to 5 , wherein the step of forming the conductor layer includes a step of forming the conductor layer to a thickness equal to a depth through which a high-frequency current flows. The manufacturing method according to any one of claims 1 to 6, wherein the step of forming the conductor layer includes a step of forming the conductor layer with a metal thin film. The manufacturing method according to claim 7 , wherein the step of forming the conductor layer includes a step of depositing a Cr layer on the surface of the columnar part and a step of depositing an Au layer on the Cr layer. Step forming the conductive layer, to form the Cr layer by sputtering, and process according to claim 8 that have a step of forming the Au layer by a plating method. The inductor element manufactured with the manufacturing method as described in any one of Claim 1- Claim 9 . The semiconductor substrate is formed by etching, the plane parallel to the surface direction of the semiconductor substrate comprises a conductive layer deposited on the surface of the columnar portion spaced from the ambient air core of the columnar portion is removed of the inductor element. The inductor element according to claim 11, further comprising a pair of through holes formed in the semiconductor substrate adjacent to the columnar portion, wherein the columnar portion is thinner than the semiconductor substrate.

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