JP5099780B2 - 3D integrated circuit - Google Patents

3D integrated circuit Download PDF

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JP5099780B2
JP5099780B2 JP2008271500A JP2008271500A JP5099780B2 JP 5099780 B2 JP5099780 B2 JP 5099780B2 JP 2008271500 A JP2008271500 A JP 2008271500A JP 2008271500 A JP2008271500 A JP 2008271500A JP 5099780 B2 JP5099780 B2 JP 5099780B2
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dimensional integrated
integrated circuit
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洋平 松本
帆平 小池
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National Institute of Advanced Industrial Science and Technology AIST
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Description

本発明は、３次元集積回路に関する。   The present invention relates to a three-dimensional integrated circuit.

特許文献１に見られるとおり、２次元半導体集積回路の発明とほぼ同時期にこれを３次元に積層した３次元集積回路は発明され、以後絶え間ない研究がなされてきた。これまでのところ、３次元集積回路は微細化に比してコストメリットが少ないため、実現されなかった。ところが、近年、MOSトランジスタの微細化の限界が近づき、微細化のコストメリットが低下した結果、等価的な性能向上を達成する方法として３次元集積回路がいよいよ実現されようとしている。   As seen in Patent Document 1, a three-dimensional integrated circuit in which a two-dimensional semiconductor integrated circuit is three-dimensionally laminated was invented almost at the same time as the invention of the two-dimensional semiconductor integrated circuit. So far, a three-dimensional integrated circuit has not been realized because it has less cost merit than miniaturization. However, in recent years, the limit of miniaturization of MOS transistors has approached and the cost merit of miniaturization has declined. As a result, a three-dimensional integrated circuit is finally realized as a method of achieving equivalent performance improvement.

３次元集積回路では従来の２次元集積回路と異なり、MOSトランジスタを垂直方向に配置し３次元的に接続することが可能となる。その結果、配線長が短くなり、配線遅延、配線容量による動的消費電力、長距離の配線を駆動するのに必要なリピータ回路などが削減でき、大幅な性能向上と消費電力削減が期待できる。
３次元集積回路化の候補として最も有望であるのはメモリやFPGA(Field Programmable Gate Array)などである。これらの回路は規則的でかつ冗長性を有しており、依然として信頼性が低い３次元積層化技術でも容易に実現できる。 In the three-dimensional integrated circuit, unlike the conventional two-dimensional integrated circuit, MOS transistors can be arranged in the vertical direction and connected three-dimensionally. As a result, the wiring length is shortened, dynamic power consumption due to wiring delay, wiring capacity, repeater circuits necessary for driving long-distance wirings, and the like can be reduced, and significant performance improvement and power consumption reduction can be expected.
Memory, FPGA (Field Programmable Gate Array), etc. are the most promising candidates for 3D integrated circuits. These circuits are regular and redundant, and can be easily realized even with a three-dimensional stacking technique with low reliability.

実際、３次元積層したDRAM(Dynamic Random Access Memory)やFlashメモリが登場している。３次元集積回路には依然として放熱や信頼性の面で課題が多いが近年多数の研究が行われた結果これらの問題は解決されつつあり、実用化に向かうことは確実な情勢である。   In fact, three-dimensional stacked DRAM (Dynamic Random Access Memory) and Flash memory have appeared. Three-dimensional integrated circuits still have many problems in terms of heat dissipation and reliability, but as a result of many studies conducted in recent years, these problems are being solved, and it is certain that the three-dimensional integrated circuit will be put to practical use.

３次元集積回路は基本的には、貫通電極を形成した２次元集積回路を多数張り合わせることで実現される(非特許文献１参照)。それぞれの積層方法の違いは、半導体製造工程のどの段階で貫通電極を形成するか、あるいは、張り合わせを行うかといった点と、貫通電極の穴を開ける方法や層を張り合わせる方法の違いである。   A three-dimensional integrated circuit is basically realized by bonding a large number of two-dimensional integrated circuits having through electrodes (see Non-Patent Document 1). The difference in each lamination method is in which stage in the semiconductor manufacturing process the through electrode is formed or pasted, and the method of making a hole in the through electrode or the method of laminating the layers.

２次元集積回路張り合わせのタイミングとしてはダイシングの前と後の２種類が存在する。量産を重視する場合、２次元集積回路張り合わせはダイシング前にウェーハレベルで行う方が都合がよい。貫通電極の形成のタイミングとしては、CMOS(Complimented Metal Oxide Semiconductor)プロセスの前、配線プロセスの前、２次元集積回路製造後、２次元集積回路張り合わせ後の４種類が存在する。貫通電極を形成する穴を開ける方法としてはレーザーを用いる方法(穴径〜10μm)と、RIE(Reactive Ion Etching)を用いる方法(穴径〜0.２μm)があるが、ウェーハレベルで多数の穴を開ける場合後者のほうが量産向きであり、また径の小さな穴を開けることが可能である。   There are two types of two-dimensional integrated circuit bonding timings before and after dicing. When mass production is important, it is more convenient to perform two-dimensional integrated circuit bonding at the wafer level before dicing. There are four types of timings for forming the through electrode: before the CMOS (Complimented Metal Oxide Semiconductor) process, before the wiring process, after manufacturing the two-dimensional integrated circuit, and after bonding the two-dimensional integrated circuit. There are two methods for drilling holes to form through-electrodes: a method using a laser (hole diameter up to 10 μm) and a method using RIE (Reactive Ion Etching) (hole diameter up to 0.2 μm). The latter is more suitable for mass production, and it is possible to make a hole with a small diameter.

また、貫通電極の材料としてはタングステンや銅などが主であるが、CMOSプロセス前に貫通電極を形成する場合はコンタミネーションの問題を避けるためにポリシリコンが好ましい。張り合わせの前に貫通電極を形成する場合は電極末端に金、もしくはインジウムのバンプ(〜10μm)を形成し層間の電極の位置を合わせて接合する。貫通電極を張り合わせ後に形成する場合は、張り合わせてから２層にまたがる電極を形成するので、層間の電極位置あわせは必要なく、バンプも必要としないことから、貫通電極の高密度化に適している。   The material of the through electrode is mainly tungsten or copper. However, when the through electrode is formed before the CMOS process, polysilicon is preferable in order to avoid the problem of contamination. When the through electrode is formed before bonding, a gold or indium bump (˜10 μm) is formed at the end of the electrode, and the positions of the electrodes between the layers are aligned and joined. When the through electrode is formed after bonding, an electrode that extends over the two layers is formed after bonding, and therefore it is not necessary to align the electrodes between layers, and no bumps are required, which is suitable for increasing the density of the through electrode. .

同一の２次元集積回路を単純に積み重ねることで３次元集積回路とする場合、２次元集積回路上で上の層へ接続する貫通電極には、必ず対応する下から接続する貫通電極を備えている必要がある。
図４は同一の２次元集積回路を３層積層する従来例であり、105、106は第１、第３層の金属配線を、103、104はそれぞれMOSトランジスタのゲートとソース・ドレイン領域を表している。 When a three-dimensional integrated circuit is formed by simply stacking the same two-dimensional integrated circuit, the through electrode connected to the upper layer on the two-dimensional integrated circuit is always provided with a corresponding through electrode connected from below. There is a need.
FIG. 4 shows a conventional example in which three layers of the same two-dimensional integrated circuit are stacked. 105 and 106 represent metal wirings of the first and third layers, and 103 and 104 represent gates and source / drain regions of MOS transistors, respectively. ing.

この従来例で、下層の右側のMOSトランジスタを通過した信号が、貫通電極を通じて、上層の左側のMOSトランジスタに入力するようになっている。この場合、各層では、上面に向けて101の貫通電極、下面に向けて102の貫通電極が必要になる。このような同一の２次元集積回路を積層する場合、平面上で同じ位置に上下方向への貫通電極が必要になる。いくつかの３次元集積回路ではこのような貫通電極の配置は不可能であり、可能であるにしても、積層時に再配線を行う新たな工程を追加する必要がある。
この問題は、特許文献３〜７に示されている方法、すなわち、上方へ接続する貫通電極と下層へ接続する貫通電極を、チップ中央を回転の中心とする回転対称な位置に配置し、チップを設定した角度ずつ回転しながら積層することによって回避できる。 In this conventional example, a signal that has passed through the lower right MOS transistor is input to the upper left MOS transistor through the through electrode. In this case, each layer requires 101 through electrodes toward the upper surface and 102 through electrodes toward the lower surface. When stacking such identical two-dimensional integrated circuits, through electrodes in the vertical direction are required at the same position on the plane. In some three-dimensional integrated circuits, it is impossible to arrange such through electrodes, and even if possible, it is necessary to add a new process for performing rewiring at the time of stacking.
This problem is caused by the methods disclosed in Patent Documents 3 to 7, that is, the through electrode connected to the upper side and the through electrode connected to the lower layer are arranged at rotationally symmetric positions with the center of the chip as the center of rotation. Can be avoided by stacking while rotating by a set angle.

図５は特許文献３〜７の例を示している。積層する２次元集積回路の下方向の貫通電極201と上方向への貫通電極202が２次元集積回路の中央の回転軸203を中心とするπ(rad)回転対称な位置に配置されている。
貫通電極201、202はそれぞれ、図４の102、101に対応している。図６において（ａ）及び（ｂ）はこの２次元集積回路上面及び下面の貫通電極の配置を示しており、破線は図５の断面位置を示している。 FIG. 5 shows examples of Patent Documents 3-7. The lower through electrode 201 and the upper through electrode 202 in the two-dimensional integrated circuit to be laminated are arranged at π (rad) rotationally symmetric positions around the rotation axis 203 at the center of the two-dimensional integrated circuit.
The through electrodes 201 and 202 correspond to 102 and 101 in FIG. 4, respectively. 6A and 6B show the arrangement of the through electrodes on the upper and lower surfaces of the two-dimensional integrated circuit, and the broken lines show the cross-sectional positions in FIG.

この２次元集積回路を３枚積層した実施例が図７である。図７の実施例において第二層は図６における回転軸203を中心にπ(rad)回転して貼りあわされる。下方の貫通電極201と上方の貫通電極202は回転軸203に対してπ(rad)回転対称な位置に配置されているので、第二層の下方の貫通電極は第一層の上方の貫通電極と、第二層の上方の貫通電極は第三層の下方の貫通電極と接続することが可能となる。より多くの層の積層は同様に図５のものを層ごとに交互に回転して張り合わせることで実現できる。
また、図５には上方、下方ともにそれぞれ１つの貫通電極を示したが、貫通電極が複数存在する場合は回転軸203に対して対称に配置すればよい。 FIG. 7 shows an embodiment in which three two-dimensional integrated circuits are stacked. In the embodiment of FIG. 7, the second layer is pasted by rotating by π (rad) about the rotation axis 203 in FIG. Since the lower penetrating electrode 201 and the upper penetrating electrode 202 are arranged at a position that is π (rad) rotationally symmetric with respect to the rotation axis 203, the lower penetrating electrode in the second layer is an upper penetrating electrode in the first layer. Then, the through electrode above the second layer can be connected to the through electrode below the third layer. Similarly, more layers can be stacked by alternately rotating and laminating the layers shown in FIG. 5 for each layer.
FIG. 5 shows one through electrode in both the upper and lower directions. However, when there are a plurality of through electrodes, they may be arranged symmetrically with respect to the rotation axis 203.

また、図５の例では２次元集積回路面に対して垂直な回転軸203に対してπ(rad)回転対称になるように上方と下方の貫通電極の配置を行うが、回転の角度についてはさまざまな角度が可能である。
図８の例において、（ａ）は下面の、（ｂ）は上面の貫通電極位置を表している。401(402)は403(404)を回転の軸405を中心として反時計回りにπ/２(rad)回転した位置に存在する。この２次元集積回路を積層する場合、π/２(rad)、あるいは３π/２(rad)回転して重ねて張り合わせれば、上下の貫通電極を適切に張り合わせることが可能である。ただし、その場合、２次元集積回路内部の回路は401(402)と403(404)を接続することを前提とした設計となっている必要がある。 In the example of FIG. 5, the upper and lower through electrodes are arranged so as to be π (rad) rotationally symmetric with respect to the rotation axis 203 perpendicular to the two-dimensional integrated circuit surface. Various angles are possible.
In the example of FIG. 8, (a) represents the position of the through electrode on the lower surface, and (b) represents the position of the through electrode on the upper surface. 401 (402) exists at a position obtained by rotating 403 (404) counter-clockwise by π / 2 (rad) about the axis of rotation 405. When this two-dimensional integrated circuit is stacked, the upper and lower penetrating electrodes can be appropriately bonded together by rotating and overlapping by π / 2 (rad) or 3π / 2 (rad). In this case, however, the circuit inside the two-dimensional integrated circuit needs to be designed on the assumption that 401 (402) and 403 (404) are connected.

一方、FPGAなどの同一の部分回路が複数、規則的に配列するような半導体集積回路に特許文献３〜７の方法を適用する場合、それぞれの部分回路内部での貫通電極を含む回路配置は同一であることが好ましいが、特許文献３〜７は、そのような同一の部分回路中の貫通電極の配置に関して言及していない。本発明は同一の部分回路を複数個含む同一の半導体集積回路を複数個積み上げる場合の貫通電極の配置方法を示す。
米国特許第３７４８５４８号明細書 米国特許第４５３３８３３号明細書 特開２００４−２９６８５３号公報 特開２００４−３５６２８４号公報 特開２００４−３４９６９４号公報 米国特許出願第２００７／００５７３８４号明細書 米国特許第６１６６４４４号明細書 A. W. Topol et al. “Three dimensional integrated circuits,” IBM J. RES. & DEV., VOL. 50, NO.4/5, 2006. On the other hand, when the methods of Patent Documents 3 to 7 are applied to a semiconductor integrated circuit in which a plurality of identical partial circuits such as FPGAs are regularly arranged, the circuit arrangement including through electrodes in each partial circuit is the same. However, Patent Documents 3 to 7 do not mention the arrangement of the through electrodes in the same partial circuit. The present invention shows a method of arranging through electrodes when a plurality of identical semiconductor integrated circuits including a plurality of identical partial circuits are stacked.
US Pat. No. 3,748,548 U.S. Pat. No. 4,533,833 JP 2004-296853 A JP 2004-356284 A JP 2004-349694 A US Patent Application No. 2007/0057384 US Pat. No. 6,166,444 AW Topol et al. “Three dimensional integrated circuits,” IBM J. RES. & DEV., VOL. 50, NO.4 / 5, 2006.

本発明は、２次元集積回路の３次元積層工程を複雑にすることなく、垂直方向の接続を有する同一の部分回路を複数含む同一の２次元集積回路を複数積層することを可能とすることを課題とする。   The present invention makes it possible to stack a plurality of identical two-dimensional integrated circuits including a plurality of identical partial circuits having vertical connections without complicating the three-dimensional stacking process of the two-dimensional integrated circuit. Let it be an issue

上記課題を解決するために第１の発明の３次元集積回路は、複数の２次元集積回路が積層された３次元集積回路であって、複数の２次元集積回路のそれぞれは、少なくとも２つの同一の部分回路が該２次元集積回路の平面の所定位置を積層方向の第１の回転軸として所定角度の回転対称な位置に配置され、部分回路は上層へ接続する第１の信号伝送路と下層へ接続する第２の信号伝送路とが該部分回路の平面の中心位置を積層方向の第２の回転軸として所定角度の回転対称な位置に配置され、複数の２次元集積回路が各々の第１の回転軸をその軸方向に同一位置に配置されて積層され、上下に隣接する２つの２次元集積回路の一方が第１の回転軸を中心に所定角度回転されたとき、一方の２次元集積回路の部分回路が所定角度回転されて、上下に隣接する２つの２次元集積回路上の部分回路同士が対向するようにされて、２つの２次元集積回路のうち上層の２次元集積回路の第１の信号伝送路と下層の２次元集積回路の第２の信号伝送路とが対向接続され、かつ、上層の２次元集積回路の第２の信号伝送路と下層の２次元集積回路の第１の信号伝送路とが対向接続されて張り合わされていることを特徴とする。
また、上記課題を解決するため、第２の発明の３次元集積回路は、第１の発明における２次元集積回路上で回転対称な位置に配置された少なくとも２つの部分回路の配置回転の中心である第１の回転軸は、２次元集積回路の平面の中央位置にあることを特徴とする。
また、上記課題を解決するため、第３の発明の３次元集積回路は、第１の発明における２次元集積回路上の少なくとも２つの部分回路は、第１の回転軸を中心としてπｎ／２ラジアン（ただし、ｎは自然数）回転対称な位置に配置されていることを特徴とする。
また、上記課題を解決するため、第４の発明の３次元集積回路は、第１〜第３の発明のいずれかにおける２次元集積回路は、部分回路が複数、２次元配列状に並べて構成されていることを特徴とする。
また、上記課題を解決するため、第５の発明の３次元集積回路は、上記第１及び第２の信号伝送路は、少なくとも導電体、コンデンサ、コイル及び光配線のいずれかであることを特徴とする。 Three-dimensional integrated circuit of the first invention to solve the aforementioned problems is a three-dimensional integrated circuits in which a plurality of two-dimensional integrated circuit is laminated, each of the plurality of 2-dimensional integrated circuit, even without least 2 Two identical partial circuits are arranged at rotationally symmetric positions of a predetermined angle with a predetermined position on the plane of the two-dimensional integrated circuit as a first rotation axis in the stacking direction, and the partial circuits are connected to the upper layer by a first signal transmission line And a second signal transmission line connected to the lower layer are arranged at rotationally symmetric positions of a predetermined angle with the center position of the plane of the partial circuit as the second rotation axis in the stacking direction , and each of the plurality of two-dimensional integrated circuits When one of two two-dimensional integrated circuits adjacent to each other in the vertical direction is rotated by a predetermined angle around the first rotation axis, one of the first rotation axes is stacked at the same position in the axial direction. When the partial circuit of the two-dimensional integrated circuit is rotated by a predetermined angle, The two partial circuits on two two-dimensional integrated circuits adjacent to each other face each other, and the first signal transmission path of the upper two-dimensional integrated circuit and the lower two-dimensional integrated circuit of the two two-dimensional integrated circuits And the second signal transmission line of the upper layer two-dimensional integrated circuit and the first signal transmission line of the lower layer two-dimensional integrated circuit are oppositely connected and bonded together. and it shall be the feature of that.
In order to solve the above problem, the three-dimensional integrated circuit of the second invention is arranged at the center of the rotation of the arrangement of at least two partial circuits arranged at rotationally symmetric positions on the two-dimensional integrated circuit of the first invention. The certain first rotation axis is at the center position of the plane of the two-dimensional integrated circuit.
In order to solve the above-described problem, the three-dimensional integrated circuit of the third invention is such that at least two partial circuits on the two-dimensional integrated circuit of the first invention are πn / 2 radians around the first rotation axis. (Where n is a natural number).
In order to solve the above-mentioned problem, the three-dimensional integrated circuit of the fourth invention is a two-dimensional integrated circuit according to any one of the first to third inventions, wherein a plurality of partial circuits are arranged in a two-dimensional array. It is characterized by .
In order to solve the above problem, in the three-dimensional integrated circuit of the fifth invention, the first and second signal transmission paths are at least one of a conductor, a capacitor, a coil, and an optical wiring. It shall be the.

本発明によれば、通常、同一の２次元集積回路を積層する場合の張り合わせ及びマスク枚数・再配線工程の削減等貫通電極形成工程を単純化することができる。また、上面と下面の貫通電極を２次元集積回路等の同一２次元位置に配置しないので、層当たりの厚さが減少し、より細密な貫通電極を形成することが可能となる。   According to the present invention, it is possible to simplify the through electrode forming process such as the lamination and the reduction of the number of masks and the rewiring process when the same two-dimensional integrated circuit is laminated. Further, since the through electrodes on the upper surface and the lower surface are not arranged at the same two-dimensional position of a two-dimensional integrated circuit or the like, the thickness per layer is reduced, and a finer through electrode can be formed.

本発明の基本的な考え方は、回転対称な位置に上方、下方へ接続する貫通電極が配置された部分回路を、チップ上の回転対称な位置に配置した２次元集積回路は、特許文献３〜７と同様に回転し積層することが可能であることである。   The basic idea of the present invention is that a two-dimensional integrated circuit in which a partial circuit in which a through electrode connected upward and downward is disposed at a rotationally symmetric position is disposed at a rotationally symmetric position on a chip is disclosed in Patent Documents 3 to 3. It is possible to rotate and laminate in the same manner as in FIG.

図１は上記の考え方にしたがって構成した２次元集積回路の例を示しており、2つの同一の部分回路１がチップの中心５を軸としてπ(rad)回転対称な位置に配置されており、部分回路１の内部には上方へ接続する貫通電極３と、下方へ接続する貫通電極２が、部分回路１の中心４を軸に部分回路１内でπ(rad)回転対称な位置に配置されている。この２次元集積回路をπ(rad)回転したものを、回転しないものに重ねると、上層と下層の貫通電極２と貫通電極３が重なり正常に接続できる。 FIG. 1 shows an example of a two-dimensional integrated circuit configured in accordance with the above-described concept, in which two identical partial circuits 1 are arranged at positions symmetric with respect to the center 5 of the chip by π (rad) rotation, Inside the partial circuit 1, a through electrode 3 connected to the upper side and a through electrode 2 connected to the lower side are arranged in a position symmetric with respect to π (rad) in the partial circuit 1 about the center 4 of the partial circuit 1. ing. When this two-dimensional integrated circuit rotated by π (rad) is overlapped with a non-rotated one, the upper layer and lower layer through electrodes 2 and through electrodes 3 overlap and can be normally connected.

このように、上方へ接続する貫通電極３と、下方へ接続する貫通電極２は部分回路１内部において回転対称な位置に配置し、かつ、当該部分回路１同士をチップの中心位置５に対して回転対称な位置に配置することで、回転して積層可能な、貫通電極を有する同一の部分回路を複数有する２次元集積回路を構成することができる。 In this way, the through electrode 3 connected to the upper side and the through electrode 2 connected to the lower side are arranged at rotationally symmetric positions inside the partial circuit 1 , and the partial circuits 1 are arranged with respect to the center position 5 of the chip. By disposing at rotationally symmetric positions, a two-dimensional integrated circuit having a plurality of identical partial circuits having through electrodes that can be rotated and stacked can be configured.

図２は、FPGA(Field Programmable Gate Array)などを含む同一の回路を繰り返し配列状に並べてできる２次元集積回路に同様の考えを適用した実施例を示している。
図２の実施例において、503は図１の２次元集積回路を構成する部分回路１に相当し、ここでは基本タイルと呼ぶ。
この２次元集積回路は、基本タイル503を４×４の二次元配列状に並べて構成されている。本発明によれば、部分回路が集積回路上で対称な位置に配置されている必要があるが、部分回路を２次元配列状に並べた場合、２次元集積回路の中心に対して例えばπ(rad)対称な位置に必ず同一の部分回路が存在するため、２次元配列は本発明が要求する条件を満たしている。 FIG. 2 shows an embodiment in which the same idea is applied to a two-dimensional integrated circuit in which the same circuit including an FPGA (Field Programmable Gate Array) is repeatedly arranged in an array.
In the embodiment of FIG. 2, reference numeral 503 corresponds to the partial circuit 1 constituting the two-dimensional integrated circuit of FIG.
This two-dimensional integrated circuit is configured by arranging basic tiles 503 in a 4 × 4 two-dimensional array. According to the present invention, the partial circuits need to be arranged at symmetrical positions on the integrated circuit. However, when the partial circuits are arranged in a two-dimensional array, for example, π ( rad) Since the same partial circuit always exists at a symmetrical position, the two-dimensional array satisfies the conditions required by the present invention.

基本タイル503において、504は機能ブロックを示しており、何らかの論理、又は、算術演算を実行するための回路を備えている。機能ブロック504の入出力は505のスイッチブロックに接続されている。基本タイルの機能ブロック同士は２次元集積回路の平面方向の配線506、507あるいは、垂直方向の配線501、502によってスイッチブロック505を通じて接続されており、任意の２つの機能ブロックの入出力を接続することが可能となっているものとする。   In the basic tile 503, reference numeral 504 denotes a functional block, and includes a circuit for executing some logic or arithmetic operation. The input / output of the function block 504 is connected to the switch block 505. The functional blocks of the basic tiles are connected through the switch block 505 by the wirings 506 and 507 in the planar direction of the two-dimensional integrated circuit or the wirings 501 and 502 in the vertical direction, and the input / output of any two functional blocks is connected. It is possible that

なお、501及び、502貫通電極の一方が上あるいは下の層の基本タイルに接続する。ここでは、501は２次元集積回路下方へ接続する貫通電極、502は下方へ接続する貫通電極を示すものとする。この図において、貫通電極501、502は508を中心にタイル内部でπ(rad)回転対称な位置に配置されている。   One of the 501 and 502 penetrating electrodes is connected to the basic tile of the upper or lower layer. Here, 501 denotes a through electrode connected to the lower side of the two-dimensional integrated circuit, and 502 denotes a through electrode connected to the lower side. In this figure, the through electrodes 501 and 502 are arranged at π (rad) rotationally symmetric positions inside the tile with 508 as the center.

図３において（ａ）は２次元集積回路上面の、（ｂ）は２次元集積回路下面の貫通電極の配置を示している。積層される上下２つの２次元集積回路の一方を図２の509を回転中心としてπ(rad)回転させた場合、図３（ａ）に示す上方へ接続する貫通電極と図３（ｂ）に示す下方へ接続する貫通電極は上下２つの２次元集積回路間においてすべて重なるため、図７の場合と同様に層ごとにπ(rad)回転させて張り合わせることで上方、下方の貫通電極をすべて接続することが可能である。ここで、すべての基本タイルは同一であるので、回転しても回路の基本的な機能に変わりがない。 3A shows the arrangement of the through electrodes on the upper surface of the two-dimensional integrated circuit, and FIG. 3B shows the arrangement of the through electrodes on the lower surface of the two-dimensional integrated circuit. If one 509 of FIG. 2 is rotated [pi (rad) as the center of rotation of the upper and lower two 2-dimensional integrated circuits to be stacked, the through electrode and FIG connecting upward as shown in FIG. 3 (a) 3 (b) As shown in FIG. 7 , all the upper and lower through-electrodes are connected to each other by rotating π (rad) for each layer as shown in FIG. It is possible to connect. Here, since all the basic tiles are the same, the basic function of the circuit remains unchanged even when rotated.

また、図２の実施例のようにすべての部分回路(基本タイル)が同じでなくても本発明は実施できる。例えば、実際のFPGAでは異なる機能ブロックを有するタイルを混在しており、そのような異なる基本タイルが存在する場合、貫通電極の位置を他の基本タイルと共通にするか、あるいは、同一の基本タイルを回転軸509に対して対称な位置に配置すればよい。
また、図２のような複数の同一の部分回路を有する場合も、図８で見たように、貫通電極の配置位置の回転角度を変更可能である。 Further, the present invention can be implemented even if all the partial circuits (basic tiles) are not the same as in the embodiment of FIG. For example, in an actual FPGA, tiles with different functional blocks are mixed, and if there are such different basic tiles, the position of the through electrode should be shared with other basic tiles, or the same basic tile May be arranged at a position symmetrical with respect to the rotation axis 509.
In addition, even when a plurality of identical partial circuits as shown in FIG. 2 are provided, the rotation angle of the through electrode arrangement position can be changed as seen in FIG.

なお、特許文献２などでは層間を光配線で接続している。また、その他にも磁気、静電容量によって層間を接続する方法がある。実施例では一つの導体で層間を接続する場合のみ示したが、本発明は光、磁気、容量などによって層間を接続する場合にも適用できる。   In Patent Document 2, the layers are connected by optical wiring. In addition, there is a method of connecting layers by magnetism and electrostatic capacity. In the embodiment, only the case where the layers are connected by one conductor is shown, but the present invention can also be applied to the case where the layers are connected by light, magnetism, capacitance or the like.

例えば、層間を光で接続する場合には、発光素子(受光素子)を図６（ｂ）の202の位置に、受光素子(発光素子)を図６（ａ）の201の位置に配置し、光配線を図５の202、201の位置に形成すればよい。また、容量で接続する場合はコンデンサを形成する２つの導体を図６（ａ）、図６（ｂ）の201、202の位置に配置し、磁気で接続する場合は図６（ａ）、図６（ｂ）の201、202の位置にコイルを配置すればよい。   For example, when the layers are connected by light, the light emitting element (light receiving element) is disposed at the position 202 in FIG. 6B, and the light receiving element (light emitting element) is disposed at the position 201 in FIG. Optical wiring may be formed at positions 202 and 201 in FIG. When connecting by capacitance, the two conductors forming the capacitor are arranged at positions 201 and 202 in FIGS. 6A and 6B, and when connecting by magnetism, FIG. 6A and FIG. Coils may be arranged at positions 201 and 202 in 6 (b).

以上実施例では２次元集積回路として半導体集積回路である２次元集積回路を例示したが、本発明の集積回路としてハイブリッド集積回路等の他の集積回路であってもよい。   In the above embodiment, the two-dimensional integrated circuit, which is a semiconductor integrated circuit, is exemplified as the two-dimensional integrated circuit. However, the integrated circuit of the present invention may be another integrated circuit such as a hybrid integrated circuit.

回転対称な位置に貫通電極を配置した部分回路をさらにチップ上で回転対称な位置に配置した２次元集積回路の例Example of a two-dimensional integrated circuit in which a partial circuit in which through electrodes are arranged at rotationally symmetric positions is further arranged at rotationally symmetric positions on the chip. 同一の回路を配列上に並べた２次元集積回路の貫通電極レイアウトTwo-dimensional integrated circuit through-electrode layout with identical circuits arranged in an array （ａ）は、図７の３次元集積回路上面の貫通電極レイアウト、（ｂ）は３次元集積回路下面の貫通電極レイアウト7A shows a through electrode layout on the top surface of the three-dimensional integrated circuit in FIG. 7, and FIG. 7B shows a through electrode layout on the bottom surface of the three-dimensional integrated circuit. 従来の３次元集積回路の断面図Sectional view of a conventional three-dimensional integrated circuit 従来の２次元集積回路の断面図Sectional view of a conventional two-dimensional integrated circuit （ａ）は図５の上面の貫通電極レイアウト、（ｂ）は下面の貫通電極レイアウト5A is a through electrode layout on the upper surface of FIG. 5, and FIG. 5B is a through electrode layout on the lower surface. 図５の２次元集積回路を交互にπ(rad)回転して積層してできた３次元集積回路の断面図FIG. 5 is a cross-sectional view of a three-dimensional integrated circuit obtained by alternately stacking the two-dimensional integrated circuit of FIG. 5 by rotating π (rad). （ａ）は、π/２(rad)回転して積層する場合の２次元集積回路下面の貫通電極レイアウト、（ｂ）は、π/２(rad)回転して積層する場合の２次元集積回路上面の貫通電極レイアウト(A) is a through electrode layout on the lower surface of a two-dimensional integrated circuit when stacked by rotating by π / 2 (rad), and (b) is a two-dimensional integrated circuit by stacking by rotating by π / 2 (rad). Top through-hole electrode layout

Claims (5)

複数の２次元集積回路が積層された３次元集積回路であって、
前記複数の２次元集積回路のそれぞれは、少なくとも２つの同一の部分回路が該２次元集積回路の平面の所定位置を積層方向の第１の回転軸として所定角度の回転対称な位置に配置され、該部分回路は上層へ接続する第１の信号伝送路と下層へ接続する第２の信号伝送路とが該部分回路の平面の中心位置を積層方向の第２の回転軸として前記所定角度の回転対称な位置に配置され、
前記複数の２次元集積回路が各々の前記第１の回転軸をその軸方向に同一位置に配置されて積層され、上下に隣接する２つの前記２次元集積回路の一方が前記第１の回転軸を中心に前記所定角度回転されたとき、前記一方の２次元集積回路の前記部分回路が前記所定角度回転されて、上下に隣接する２つの前記２次元集積回路上の前記部分回路同士が対向するようにされて、２つの前記２次元集積回路のうち上層の２次元集積回路の前記第１の信号伝送路と下層の２次元集積回路の前記第２の信号伝送路とが対向接続され、かつ、前記上層の２次元集積回路の前記第２の信号伝送路と前記下層の２次元集積回路の前記第１の信号伝送路とが対向接続されて張り合わされていることを特徴とする３次元集積回路。 A three-dimensional integrated circuit in which a plurality of two-dimensional integrated circuits are stacked,
Disposed respectively two identical subcircuits rotation symmetry of the predetermined angular predetermined position of the plane of the two-dimensional integrated circuit as a first rotation axis in the stacking direction even without least positions of the plurality of 2-dimensional integrated circuits is, the predetermined angle the partial circuits center position of the plane of the second signal transmission path and the partial circuit connected to the first signal transmission path and a lower layer to connect to the upper layer as a second rotation axis in the stacking direction disposed rotationally symmetric positions,
The plurality of two-dimensional integrated circuits are stacked with the first rotation shafts arranged in the same position in the axial direction, and one of the two adjacent two-dimensional integrated circuits is the first rotation shaft. When the predetermined circuit is rotated about the predetermined angle, the partial circuit of the one two-dimensional integrated circuit is rotated by the predetermined angle, and the partial circuits on the two adjacent two-dimensional integrated circuits are opposed to each other. And the first signal transmission path of the upper two-dimensional integrated circuit of the two two-dimensional integrated circuits and the second signal transmission path of the lower two-dimensional integrated circuit are oppositely connected, and The three- dimensional integrated circuit characterized in that the second signal transmission path of the upper two-dimensional integrated circuit and the first signal transmission path of the lower two-dimensional integrated circuit are connected to be opposed to each other. circuit. 前記２次元集積回路上で回転対称な位置に配置された少なくとも２つの前記部分回路の配置回転の中心である前記第１の回転軸は、前記２次元集積回路の平面の中央位置にあることを特徴とする請求項１に記載の３次元集積回路。 Said first rotation axis which is the center of the arrangement the rotation of at least two of said partial circuits are arranged in rotational symmetrical positions in the two-dimensional integrated circuit is that the center position of the plane of the two-dimensional integrated circuits The three-dimensional integrated circuit according to claim 1, wherein: 前記２次元集積回路上の少なくとも２つの前記部分回路は、前記第１の回転軸を中心としてπｎ／２ラジアン（ただし、ｎは自然数）回転対称な位置に配置されていることを特徴とする請求項１に記載の３次元集積回路。 At least two of said partial circuits on the two-dimensional integrated circuit, said Paienu / 2 radians (where, n is a natural number) the first rotary shaft as the center claims, characterized in that it is arranged in rotationally symmetrical positions 3D integrated circuits according to claim 1. 前記２次元集積回路は、前記部分回路が複数、２次元配列状に並べて構成されていることを特徴とする請求項１乃至３のうちいずれか一項に記載の３次元集積回路。 The three-dimensional integrated circuit according to any one of claims 1 to 3, wherein the two-dimensional integrated circuit includes a plurality of partial circuits arranged in a two-dimensional array . 前記第１及び第２の信号伝送路は、少なくとも導電体、コンデンサ、コイル及び光配線のいずれかであることを特徴とする請求項１に記載の３次元集積回路。 2. The three-dimensional integrated circuit according to claim 1, wherein the first and second signal transmission paths are at least one of a conductor, a capacitor, a coil, and an optical wiring.
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