JP5094274B2 - Image processing apparatus and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems in which conversion processing of a rectangular image to raster image data is complicated, and when such addressing method is attained only by hardware, operation verification therefor also requires much time. <P>SOLUTION: Based on a first write-address generation method, image data are read line by line from a line memory capable of storing pixel data for n lines in which one line is composed of n&times;n&times;m pixels. Further, after writing of a rectangular image to the line memory is performed based on a second write-address generation method, line-by-line reading of image data from the line memory is performed based on a second read-out-address generation method. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to an image processing apparatus and method for inputting a plurality of rectangular images and converting them into dot sequential raster image data.

  Consider a case where page unit image data composed of a plurality of rectangular images is converted into line unit image data and output using a buffer memory for image data. In this case, it is necessary to convert page unit image data input in units of rectangular images into line unit image data. The most common conversion method is a double buffer method using a buffer memory twice the amount of data corresponding to (number of lines of image data contained in a rectangular image) × (number of pixels for one line). There is a method to convert by.

  As another method, from a rectangular image to raster image data by a single buffer method using a buffer memory having a capacity corresponding to (number of lines of image data included in a rectangular image) × (number of pixels for one line). There is a way to convert. In this method, after the image data for one line is read from the buffer memory, the next rectangular image is written to the read address (see Patent Documents 1 and 2).

  Next, as a conventional example 1, a conversion process from a rectangular image to line-based image data by the former double buffer method will be described.

  In the rectangular image in this example, the number of lines of image data included in the rectangular image is four, and each line is composed of four pixels. Then, the rectangular image is composed of pixel data of 16 pixels in total of 4 pixels × 4 pixels.

  2A and 2B are diagrams illustrating a rectangular image composed of n × n pixels. FIG. 2A illustrates a rectangular image that is first input to the buffer memory. FIG. The rectangular image input next to the buffer memory is shown.

  The order of the pixel data input to the buffer memory is the same as the numerical order in the figure. That is, when pixel data of one line (n × n × m pixels) is input in one rectangular image, the pixel data of the next line is input. That is, in the example of FIG. 2A, when the pixel data of the pixels 1 to 4 in the first line is input, the pixel data of the pixels 5 to 8 in the second line is input next. When pixels 16 and so on are input to the buffer memory, the input of the rectangular image shown in FIG. Next, when the rectangular image shown in FIG. 2B is input, the pixel data of the pixels 17 to 32 are also input in the same order. In FIG. 2, only two rectangular images are shown. Similarly, in the third rectangular image, the pixel data of the pixels 33 to 48 are arranged in the order of the pixels of the rectangular image shown in FIG. . The same applies to the subsequent rectangular pixels.

  FIG. 3 is a block diagram showing the configuration of a double buffer memory circuit.

  Reference numerals 420 and 430 denote line buffer memories each having a capacity of (number of lines of image data included in a rectangular image) × (number of pixels for one line (x)) shown in FIG. The memory control unit 410 controls writing of rectangular images to the line buffers 420 and 430 and reading of image data from the line buffer memory. Here, when x = 32, eight rectangular images corresponding to 32 pixels included in one line of image data in page units are expressed as “one rectangular image array”. In this case, the total number of pixels that can be stored in the line buffer memory is 32 × 8 = 256 pixels. In this case, when image data of 256 pixels (eight rectangular images) is written in the line buffer 420, the writing control unit switches to the line buffer 430 and stores the next input rectangular image in the line buffer 430. On the other hand, the read control unit operates so as to read the image data line by line from the line buffer 420 that has been written by the write control unit.

  FIG. 4 is a diagram for explaining the order in which rectangular images are written to the line buffer memory by the write control unit, and FIG. 5 is a diagram for explaining the order in which image data is read from the line buffer memory by the read control unit. . As described above, when writing image data, the image data is written to the line buffer memory in units of rectangular images, and when reading, the image data is read in units of lines. However, in the case of such a double buffer system, two line buffers for four lines, each having 32 pixels as one line, are necessary. As the size of the rectangular image increases, a larger capacity line buffer memory is required. This is necessary and is a cause of cost increase.

  Next, a conversion process from a rectangular image to line-based image data by a single buffer (for example, only the line buffer 420) will be described as Conventional Example 2.

  The order of writing the image data of the first rectangular image array is the same as that in FIG. The order of reading the image data of the first one rectangular image array is as shown in FIG. However, since it is a single buffer here, the address for storing the next input rectangular image when the image data is read from the line buffer memory in units of lines differs.

  FIG. 6 is a diagram illustrating a state in which the next input two rectangular images are stored for the read address after the image data for one line is read from the line buffer memory.

  Here, the line 600 stores pixels 1 to 16 and pixels 17 to 32 of two rectangular images (shown in FIG. 2). Similarly, after the reading of the image data for one main scan is completed and the reading of the first one rectangular image array is completed, each of the lines 601 to 603 includes pixel 33 to pixel 64, pixel The pixel data of 65-pixel 96 and pixel 97-pixel 128 are stored.

  FIG. 7 is a diagram for explaining reading of image data of the second one rectangular image array.

  When reading out the image data of the first row, the pixels 1 to 4 of the first rectangular image, the pixels 17 to 20 of the second rectangular image, the pixels 33 to 36 of the third rectangular image, and so on. The pixels 113 to 116 of the eighth rectangular image are read out. This reading order is as shown by the dotted line in FIG. The image data in the second row, that is, the pixels 5 to 8 and the pixels 21 to 24 are similarly addressed and read out.

  FIG. 8 is a diagram illustrating a state in which each pixel of the next input rectangular image is written at the pixel position read in the order shown in FIG. FIG. 8 shows a state in which the first and second rectangular images (FIG. 2) of the third one rectangular image array are input and stored when the image data of the second one rectangular image array is read.

  FIG. 9 shows that after the third rectangular image array is stored in the line buffer in this way, the first rectangular image (FIG. 2A) of the fourth input rectangular image array to be input next is read out. It is a figure which shows the state stored in the position of image data. That is, after the third one rectangular image array is stored in the line buffer, reading of the image data of one main scan is started, and the first rectangle of the fourth one rectangular image array is read along with the reading of the data. An image is stored at the position of the read image data.

  Although not described in detail below, when reading the image data of the fifth rectangular image array, that is, when writing the image data of the sixth rectangular image array, the same as when writing the image data of the first rectangular image array The addressing method will be adopted.

As described above, this method requires such six kinds of addressing even in a small image of 4 pixels × 4 lines and a main scan of 32 pixels. Accordingly, the size of the rectangular image to be converted is increased, and address control in writing and reading of data becomes more complicated when an actually used image size is assumed.
JP 2004-40181 A JP 2001-285644 A

  As described above, in the above-described prior art, the conversion process from the rectangular image to the raster image data is complicated. That is, the former method requires a memory capacity twice as large as the number of sub-scanning lines, so that the memory capacity becomes very large in order to incorporate the memory in the IC in order to perform high-speed operation.

  In the latter method, as described above, it is necessary to write a rectangular image next to the address from which the image data is read, and to read the written image data in the main scanning direction. The processing becomes more complicated as the number increases. In particular, when such an addressing method is to be realized only by hardware, it takes time to verify these operations. In addition, since all addressing methods could be hardwareized without being verified, the risk of bugs was high.

  An object of the present invention is to solve the above-mentioned problems of the prior art.

  According to an aspect of the present invention, there is provided an image processing apparatus and method for simplifying addressing at the time of memory access while avoiding an increase in memory capacity in a conversion process from a rectangular image to raster image data. There is to do.

In order to achieve the above object, an image processing apparatus according to an aspect of the present invention has the following arrangement. That is,
An image processing device for inputting a plurality of rectangular images composed of n × n pixels and outputting image data in units of lines with n × m pixels as one line,
Storage means capable of storing pixel data for n lines in which one line is n × m pixels;
Address generation means for generating a write address for writing the rectangular image in the storage means, and a read address for reading line-unit image data from the storage means;
Each time m rectangular images are written to the storage means, the write address generation method is switched between the first write address generation method and the second write address generation method, and image data for n lines is stored in the storage unit. Switching means for switching the read address generation method between the first read address generation method and the second read address generation method each time reading from the means;
After writing the rectangular image to the storage unit based on the first write address generation method, the image data is read in line units from the storage unit based on the first read address generation method. After writing the rectangular image to the storage unit based on the second write address generation method, the image data is read in line units from the storage unit based on the second read address generation method. and control means for controlling said storage means,
The control unit reads the image data of one line or more and less than n lines from the storage unit based on the first read address generation method, and the control unit reads the image data into the area where the image data is read. In response to starting to write a rectangular image based on the second write address generation method and reading image data of one line or more and less than n lines from the storage unit based on the second read address generation method, Start writing a rectangular image based on the first write address generation method to the area from which the image data has been read,
The first write address generation method is a method of generating addresses so that n pixels are written n times every n × m addresses in writing each rectangular image, and the write start address of the kth rectangular image is set as the write start address. The address obtained by adding n × n is the write start address of the (k + 1) th rectangular image, and the address obtained by adding n to the write start address of the kth rectangular image is the write start address of the (k + 2) th rectangular image. So that the address is generated
The first read address generation method is a method of generating an address so that n pixels are read m times in reading of each line, and an address obtained by adding n × n to the kth read start address is (k + 1). This is a method for generating an address so that an address obtained by adding n to the k-th read start address becomes the (k + 2) -th read start address.
The second write address generation method is a method of generating an address so that n × n pixels are written once in writing of each rectangular image, and n × n is set as a write start address of the kth rectangular image. In this method, the address is generated so that the added address becomes the write start address of the (k + 1) th rectangular image.
The second read address generation method is a method of generating an address so that n pixels are read m times in reading of each line, and an address obtained by adding n × n to the kth read start address is (k + 1). This is a method of generating an address so that an address obtained by adding n × m to the kth read start address becomes the (k + 2) th read start address .

In order to achieve the above object, an image processing method according to an aspect of the present invention includes the following steps. That is,
It has a storage means capable of storing pixel data for n lines where one line is n × m pixels, and inputs a plurality of rectangular images composed of n × n pixels to make n × m pixels one line. An image processing method in an image processing apparatus for outputting line-unit image data,
A generation step of generating a write address for writing the rectangular image to the memory and a read address for reading line-unit image data from the storage unit;
Each time m rectangular images are written to the memory, the write address generation method is switched between the first write address generation method and the second write address generation method, and image data for n lines is read from the memory. A switching step of switching the read address generation method between a first read address generation method and a second read address generation method each time;
After writing the rectangular image to the memory based on the first write address generation method, the image data is read from the memory in units of lines based on the first read address generation method, and After writing a rectangular image to the memory based on a second write address generation method, the memory is configured to read line-by-line image data from the memory based on the second read address generation method. and a control step of controlling,
In response to reading out image data of one line or more and less than n lines from the storage unit based on the first read address generation method, the control step reads the image data into the area from which the image data was read. In response to starting to write a rectangular image based on the second write address generation method and reading image data of one line or more and less than n lines from the storage unit based on the second read address generation method, Start writing a rectangular image based on the first write address generation method to the area from which the image data has been read,
The first write address generation method is a method of generating addresses so that n pixels are written n times every n × m addresses in writing each rectangular image, and the write start address of the kth rectangular image is set as the write start address. The address obtained by adding n × n is the write start address of the (k + 1) th rectangular image, and the address obtained by adding n to the write start address of the kth rectangular image is the write start address of the (k + 2) th rectangular image. So that the address is generated
The first read address generation method is a method of generating an address so that n pixels are read m times in reading of each line, and an address obtained by adding n × n to the kth read start address is (k + 1). This is a method for generating an address so that an address obtained by adding n to the k-th read start address becomes the (k + 2) -th read start address.
The second write address generation method is a method of generating an address so that n × n pixels are written once in writing of each rectangular image, and n × n is set as a write start address of the kth rectangular image. In this method, the address is generated so that the added address becomes the write start address of the (k + 1) th rectangular image.
The second read address generation method is a method of generating an address so that n pixels are read m times in reading of each line, and an address obtained by adding n × n to the kth read start address is (k + 1). This is a method of generating an address so that an address obtained by adding n × m to the kth read start address becomes the (k + 2) th read start address .

  According to the present invention, in the conversion processing from rectangular images to raster image data, it is possible to simplify the addressing at the time of memory access while avoiding an increase in memory capacity.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments do not limit the present invention according to the claims, and all combinations of features described in the present embodiments are essential to the solution means of the present invention. Not exclusively.

  First, the concept of addressing according to the present embodiment will be described with reference to FIGS.

  FIG. 10 is a diagram for explaining the address order when the image data of the first m (m = 8) rectangular image arrays (8 rectangular images) is written into the line buffer. Here, as in the above description of the prior art, one line is 32 pixels, and one rectangular image is 4 × 4 pixels. In the figure, the ◯ numbers indicate the order in which rectangular images are written.

  Here, the first rectangular image (FIG. 2A) is written at addresses 1 to 4, 33 to 36, 65 to 68, and 97 to 100 as indicated by 1001. Next, the second rectangular image (FIG. 2B) is written to addresses 17 to 20, 49 to 52, 81 to 84, and 113 to 116 as indicated by 1002. Similarly, the third rectangular image is written at addresses 5 to 8, 37 to 40, 69 to 72, 101 to 104, as indicated by 1003. The fourth rectangular image is written at addresses 21 to 24, 53 to 56, 85 to 88, and 117 to 120 as indicated by 1004.

  This means that data in one rectangular image is written with an offset of 32 addresses per line, and the next rectangular image is written with an offset of 16 addresses. However, after the second, fourth, and sixth rectangular images, if the address is advanced by 16 addresses, the capacity of the line buffer shown in FIG. 10 is exceeded, so that it is folded and advanced by a total of 16 addresses.

  FIG. 11 is a diagram for explaining the reading order of image data in the first row of one rectangular image array stored as shown in FIG.

  Here, in the order of data in the first row of the original rectangular image, data 1111 at addresses 1 to 7, next data 1112 at addresses 17 to 20, next data 1113 at addresses 5 to 8, and data 1114 at addresses 21 to 24 are used. Are read in this order.

  In the above-described conventional example 2, the next input rectangular image is written at the address from which the image data is read. In this embodiment, the reading of the image data in the first row of the rectangular image array is completed. Until the next rectangular image data is not written.

  FIG. 12 shows the lines of the first and second rectangular images among the image data of the second rectangular image array inputted next after the reading of the first row of image data of the first rectangular image array of FIG. It is a figure which shows the state written in the buffer. Here, the pixel data of the first and second rectangular images are stored in the order of addresses.

  In this way, the rectangular image data of the second rectangular image array need only be written in the order of the pixels shown in FIG. However, even if image data of the first line of the first rectangular image array is read out, only image data for two rectangular images (32 pixels in the example of FIG. 12) can be written. For this reason, when the input of data is faster than the reading speed, it is necessary to wait for the end of the reading of the data of the second line and control to write the image data of the subsequent two rectangular images.

  FIG. 13 is a diagram showing a state in which the image data of the second rectangular image array is thus written in the line buffer. Here, the pixel data of the first and second rectangular images are stored in the order of addresses in the first row of the line buffer, and the pixel data of the third and fourth rectangular images are stored in the order of addresses in the next row. . Similarly, pixel data of the fifth and sixth rectangular images are stored in the third row, and pixel data of the seventh and eighth rectangular images are stored in the fourth row in the order of addresses.

  FIG. 14 is a diagram illustrating a process of reading the image data of the second rectangular image array shown in FIG. 13 from the line buffer in the order of the main scanning lines.

  Here, at the time of reading data on the first line of the main scanning, addresses 1 to 4, addresses 17 to 20, addresses 33 to 36, addresses 49 to 52, addresses 65 to 68, addresses 81 to 84, addresses 97 to 100, and addresses Data are read in the order of 113 to 116.

  In this case, as in the case of accessing the image data of the first rectangular image array, the image data of the third rectangular image array cannot be written until the first line of data of the second rectangular image array is read. And When the reading of the image data of the first line of the second rectangular image array is completed, the first two rectangular images of the third rectangular image array are written. The writing order at this time is the same as the addressing method at the time of writing the image data of the first rectangular image array shown in FIG.

  According to such an addressing method, it becomes easy to input one page of image data divided into rectangular images and convert it into a raster image. In other words, depending on whether the input image data is an odd-numbered rectangular image array or an even-numbered rectangular image array, the address for writing the image data of each rectangular image array and the reading address may be changed. .

  Based on this addressing concept, an application example to an actually assumed system will be described.

  FIG. 1 is a block diagram showing a schematic configuration of an image processing apparatus for converting a rectangular image into a dot-sequential raster image according to the present embodiment.

  A large capacity main memory 105 is connected to the CPU 100. Further, image processing units (processors) 200 and 300 are connected via interchip buses 110 and 130. It is assumed that the main memory 105 stores page-unit image data input from an image input unit (not shown). When image processing is performed on page-unit image data stored in the main memory 105, if image processing is to be performed with the page-unit image data as it is, a buffer memory for storing image data for one page is stored in the image memory. It is necessary to provide the unit 300. However, providing the image processing unit 300 with a large-capacity buffer memory that can store image data for one page increases the cost.

  Therefore, in the present embodiment, it is assumed that the image processing unit 300 performs image processing in units of images (rectangular images) obtained by dividing the page-unit image data stored in the main memory 105 into a plurality of rectangular areas. . In this case, if the image processing unit 300 has a buffer memory that can store a rectangular image, image processing can be executed. However, in the present embodiment, the image data output from the image processing unit 200 is output as image data in line units corresponding to one line of image data in page units. In order to output image data as line-by-line image data, it is necessary to convert a rectangular image into line-by-line image data, and the conversion mechanism is incorporated in the image processing unit 200.

  In FIG. 1, it is determined whether or not the image data input from the main memory 105 to the image processing unit 200 via the inter-chip bus 110 is image data to be processed by the image processing unit 200. The If it is determined that the image data is processed by the image processing unit 200, the image data is sent to the internal data bus 240. On the other hand, when it is determined that the image data is not processed by the image processing unit 200, the image data is sent to the image processing unit 300 via the inter-chip bus 120.

  The control unit 220 executes a conversion process from rectangular images to raster image data, and is connected to the line memory 210 via the internal memory bus 230. The control unit 220 converts the rectangular image into dot sequential raster image data and outputs the result to the internal data bus 250. Then, the processed image data is output from the image processing unit 200 to the bus 280 under the control of the data output control unit 270.

  FIG. 15 is a block diagram showing a configuration of control unit 220 according to the present embodiment.

  The image data 1600 of the rectangular image that is input under the control of the input signal 1601 is divided into lines by the data dividing unit 1611. When a certain amount of data accumulates in the data dividing unit 1611, the write control unit 1620 outputs a write request 1606 and a write address 1603 to the access arbitration unit 1630. When this write request is permitted by the access arbitration unit 1630, the write control unit 1620 writes the image data stored in the buffer of the data dividing unit 1611 to the line memory 210 via the memory bus 230.

  On the other hand, the access arbitration unit 1630 monitors the state of data writing to and reading from the line memory 210. Status management such as the above-described one-line read end timing and a mode giving priority to write or read access is performed.

  When the access arbitration unit 1630 permits reading of data from the line memory 210, the read control unit 1640 reads image data from the line memory 210 via the memory bus 230. When the data transmission unit 1650 is notified by the control signal 1608, the data transmission unit 1650 takes in the data of the memory bus 230 and stores it in a buffer (not shown) of the data transmission unit 1650.

  One pixel is composed of data of each color component of C (cyan), M (magenta), Y (yellow), and K (black), and 48 bits (12 bits × 4) in order to express each color with 12 bits (4096 gradations). Color) data. The size of one rectangular image is 32 pixels × 32 lines. A system example in which the maximum number of pixels in the line direction is 8192 pixels (for 256 rectangular images) will be described.

  FIG. 16 is a diagram showing a data array of rectangular images in the line memory 210.

  The numbers in the vertical direction (1 to 32) indicate lines (line numbers) in the line memory, where 1 is the first line, 2 is the second line, etc. It shall be.

  Here, since the number of pixels for one line of one rectangular image is 32 (pixels), the amount of data for one line of the rectangular image is 1536 bits of 48 bits × 32 (pixels). If the line memory 210 has a 256-bit width per address, six addresses are required for one line of one rectangular image. Further, in the above-described number of pixels in the line direction (8192 pixels), 1536 addresses are required. Therefore, if the line memory 210 is cut in units of one line (8192 pixels), the head address of the second line is the address “1536”. Thereafter, the head address of each line is incremented by “1536”.

  FIG. 16 shows the address offset number (upper part) and the line number (left part) of the head part of each line, and shows the head part of each line in an enlarged manner.

  Next, the actual addressing order will be described.

  First, an addressing sequence (first write address generation method) when writing an odd-numbered rectangular image array to the line memory 210 will be described.

  When the image data of the odd-numbered rectangular image array is input, the writing control unit 1620 writes the first rectangular image in accordance with the positions of the address offset numbers 0 to 5 (vertical 0 to 5 in FIG. direction). The write control unit 1620 writes the second rectangular image to addresses 192 to 197 indicated by 1602 with an address offset (32 × 6 addresses = 192 addresses) for 32 lines in one rectangular image. .

  If these steps are repeated, eight rectangular images are written as indicated by 1700 to 1707 in FIG. Then, when the ninth rectangular image is written next, the address is folded. When this address is folded, the block is shifted by one, and the ninth rectangular image is written in the line memory 210 in the area corresponding to addresses 6 to 11 indicated by 1603 in FIG.

  By writing 256 rectangular images to the line memory 210 using the above method (first write address generation method), the odd-numbered rectangular image array is written to the entire area of the line memory 210. .

  When the line-unit image data is read from the line memory 210 in which the rectangular image array is written by the first write address generation method, it is written in the 1604 area, 1605 area,... Shown in FIG. Read out pixel data. As a result, the read control unit 1640 reads image data in units of lines in which 32 pixels × 256 = 8192 pixels are used as the number of pixels in one line. Then, the read control unit 1640 reads out the odd-numbered rectangular image array from the line memory 210 by repeating the reading of the image data in units of lines as the second line, the third line,. A method of reading out line-unit image data stored in a specific line from the line memory 210 in which the rectangular image array is written by the first write address generation method is referred to as a first read address generation method. .

  Next, the addressing sequence (second write address generation method) when writing the even-numbered rectangular image array into the line memory 210 will be described.

  In the case of an even-numbered rectangular image array, the writing control unit 1620 writes the first rectangular image in the area 1604 shown in FIG. Each rectangular image is written in the line memory 210 as one block (for six addresses) for one line (32 pixels = 1536 bits). Then, the writing control unit 1620 writes the second rectangular image in the area 1605 shown in FIG. Then, the writing control unit 1620 repeats the operation of writing the third and subsequent rectangular images in the area corresponding to the first line on the line memory 210. Then, the writing control unit 1620 writes eight rectangular images so that the first line on the line memory 210 is in a state where the rectangular images are written in all areas. The ninth to sixteenth rectangular images are written in an area corresponding to the second line on the line memory 210. Similarly, the 17th to 24th rectangular images are written on the 3rd line, and the 25th to 32nd rectangular images are written on the 4th line. Eventually, the 249th to 256th rectangular images are written in the 32nd line, and the even-numbered rectangular image array is written in the entire area of the line memory 210.

  On the other hand, when the even-numbered rectangular image array is read from the line memory 210, the read control unit 1640 reads while skipping addresses by 192 addresses, such as addresses 0 to 5, addresses 192 to 197, and addresses 384 to 389. . When the line is folded back to the end, an offset of 6 addresses is given, and data is read out such as addresses 6 to 11, addresses 198 to 203, and addresses 390 to 395. When the reading of the image data for one line is thus completed, the data area for eight rectangular images is released. As described above, a method of reading out image data in units of lines from the line memory 210 in which the rectangular image array is written in the second write address generation method is referred to as a second read address generation method.

  The offset address generation method for realizing the first write address generation method, the second write address generation method, the first read address generation method, and the second read address generation method is a method of using the line memory 210. Depending on the formula, it is possible to formulate it.

  This time, four offsets of line_offset, rect_offset, return_offset, and in_block_offset are used, and the contents of the offset are switched according to the odd-numbered rectangular image array and the even-numbered rectangular image array to generate an address.

  An arithmetic expression for generating this address can be shown below.

address = line_offset + rect_offset + return_offset + in_block_offset
FIG. 18 is a diagram for explaining the meaning of the offset depending on the type and mode of each offset.

In this example,
(1) Write mode:
(Odd-numbered rectangular image array) odd line Address = (current_line−1) × 1536 + ((current_rect−1)% 8) × 192 + Int ((current_rect−1) / 8) × 6 + current_beat (1)
(Even-numbered rectangular image array) odd line Address = (current_line−1) × 6 + (current_rect−1) × 192 + 0 + current_beat Equation (2)
In the case of FIG. 10 described above, the above formula is as follows.

(Odd-numbered rectangular image array) odd line Address = (current_line−1) × 32 + ((current_rect−1)% 2) × 16 + Int ((current_rect−1) / 2) × 4 + current_beat
(Even-numbered rectangular image array) odd line Address = (current_line−1) × 4 + (current_rect−1) × 16 + 0 + current_beat
(2) Read mode:
(Odd-numbered rectangular image array) odd line Address = (rcurrent_line−1) × 1536 + ((current_block−1)% 8) × 192 + Int ((current_block−1) / 8) × 6 + current_beat (3)
(Even-numbered rectangular image array) even line Address = (rcurrent_line−1) × 6 + ((current_block−1) × 192 + 0 + current_beat... (4)
And so on. In the above formula, “(current_rect−1)% 8” represents the remainder when (current_rect−1) is divided by “8”. Further, (current_block-1) is the number of lines constituting one rectangular image. Furthermore, Int ((current_block-1) / 8) represents the integer part of the quotient obtained by dividing (current_block-1) by 8.

  Current_rect in the writing mode indicates the order of the rectangular images in one rectangular image array (initially 1), and current_block at the time of reading indicates the number of blocks with 32 pixels as one block. The current_beat has the number of memory addresses on the line memory 210 necessary to input 32 pixels as an offset. Rcurrent_line indicates the line position (any one of 1 to 32) at the time of reading.

  Also, “8”, which is the number of rectangular images written in one line, is the number of rectangular images when each rectangular image is stored in the line buffer as shown in FIG. 12, from 8192/1024 (32 pixels × 32 lines). Seeking.

  As described above, if the line of the current rectangular image and the position of the rectangular image in one rectangular image array are known, an address can be generated.

  Next, the operation of the access arbitration unit 1630 will be described with reference to FIG.

  FIG. 19 is a diagram for explaining state transition controlled by the access arbitration unit 1630 according to the present embodiment.

  Here, eight states (S0 to S7) are defined for processing a certain page. Here, the three states of write access priority high (S2), read priority high (S4), and final rectangular image array read (S6) are the main states. State S0 indicates a reset state, and state S1 indicates an idle (standby) state. A state S3 indicates a state where writing of predetermined rectangular image data is completed, and a state S5 indicates a state where reading of image data for one main scanning line is completed.

  In the state S2, if there is a write request (write access), the write is preferentially executed. Note that the read request (read access) may be permitted or may not be permitted depending on the number of rectangular images written so far.

  In the state S4, the read request has priority. For example, in the example of FIG. 17, when the writing request reads out one line of data in the main scanning direction, writing of eight rectangular images is permitted. However, until this one line of data is read, the data write request remains unpermitted.

  In the final state S6, only the read request is executed. In this case, the data for the last two rectangular image arrays of the page is already stored in the line memory 210 and is read. At this time, even if there is a write request for the next page, writing of the image data of the next page is not permitted until the image data of the current page is completely read and output. When all the image data of the current page is read in this way, the process proceeds to state S7.

  According to these control methods, the capacity of the line memory may be a capacity of (the number of lines constituting the rectangular image) × (the number of pixels of one line). Then, image data in page units can be converted into image data in line units and output by two types of addressing methods for writing and reading.

  In this example, the line memory is provided in the IC as in the system shown in FIG. 1, but it is also possible to use a part of a large capacity memory such as a DRAM. Further, these controls can be implemented not only by hardware but also by software.

  20 to 22 are flowcharts for explaining data conversion processing by the control unit 220 of FIG.

  Steps S100 to S112 in FIG. 20 show processing for inputting a plurality of rectangular images and storing the image data of one rectangular image array in the line memory 210.

  First, in step S100, current_line and current_rect are both initialized to “1”. In step S101, the first rectangular image is input. In step S102, an address for storing the pixel data of the first line of the rectangular image is generated. In step S103, the control unit 220 writes the pixel data for one line of the rectangular image to the address. In this case, the address is generated based on the above-described equation (1). When the pixel data for one line of the rectangular image is written in the line memory 210 in this way, the current_line is incremented by 1 in step S104, and steps S102 to S105 are repeated until one rectangular image is written in the line memory 210 in step S105. When the first rectangular image is thus written in the line memory 210, the process proceeds to step S106, current_line is returned to "1", and the next rectangular image is input in step S108. In step S108, current_rect indicating the order of the rectangular images is incremented by one. In step S109, the control unit 220 executes the processes in steps S102 to S105 described above (step S140) and writes the rectangular image in the line memory 210. When the writing of the second rectangular image to the line memory 210 is thus completed, the process proceeds to step S110, the current_line is returned to “1”, and the process proceeds to step S111. In step S <b> 111, the control unit 220 determines whether the image data of one rectangular image array is stored in the line memory 210. If the storage is completed, the process proceeds to step S112. If not, the process returns to step S106. The state in which the image data of one rectangular image array is stored in the line memory 210 is as shown in FIG. 10, for example.

  Next, proceeding to FIG. 21, in steps S113 to S119, the image data of the one rectangular image array is read from the line memory 210. That is, in step S113, the address at which the first line (current_block = 1) of the first rectangular image is stored is calculated. This can be obtained, for example, by the above-described equation (3). Next, in step S114, the control unit 220 reads the image data for one line. Next, in step S115, current_block is incremented by 1, and in step S116, steps S113 to S116 are repeated until image data for one line (8192 pixels) of image data in page units is read. When the image data for one line of the page-unit image data is read out in this way, the next rectangular image can be written. In step S117, it is checked whether the next rectangular image is input. The process proceeds to S118. In step S118, each line of the plurality of lines constituting the inputted rectangular image is stored in an area for one line of the line memory 210 that has been read. In this case, the write address is calculated based on the above-described equation (2), for example. Thus, the state in which the subsequent two rectangular images are written is as shown in FIG. 12, for example.

  In step S117, when the next rectangular image is not input, or when step S118 ends, the process proceeds to step S119 to check whether the reading of the image data of one rectangular image array is completed. If not completed, the process proceeds to step S120, current_block is returned to “1”, rcurrent_line is incremented by 1, and the process proceeds to step S113. In this way, the reading of one rectangular image array is completed and the image data of the next one rectangular image array is stored, for example, as shown in FIG.

  Next, in step S121, it is checked whether image data of the next one rectangular image array is stored. Here, when there is no image data of the next rectangular image array, it is determined that no rectangular image is input thereafter, and the process is terminated. This end determination is not limited to this. When the number of rectangular images input in advance is known, it may be determined by the number, or when there is no input after a predetermined time has elapsed. It may be determined that this process is finished.

  In step S122 and subsequent steps, the second rectangular image array data is read. In step S122, both current_block and current_line are initialized to “1”. In step S123, for example, a read address is calculated according to the above-described equation (4), and the first row of the rectangular image of current_block is read. Next, in step S124, current_block is incremented by 1 and preparation for reading the first row of the rectangular image of the next current_block is made. When it is determined in step S125 that the image data of the first row of the rectangular image has been read out for one line of image data in page units, the process proceeds to step S126. In step S126, current_block is set to “1”, current_line is incremented by 1, and then the process proceeds to reading image data on the second line of the rectangular image.

  In step S127, since reading of one line of image data in units of pages is completed and writing of the next rectangular image is possible, it is determined whether the next rectangular image is input. If it has been input, the process proceeds to step S128, and the rectangular image is stored in the image area of the first row that has already been read, as in step S140. In step S129, it is checked whether reading of image data of one rectangular image array stored as shown in FIG. 13, for example, is completed. When the reading is not completed, the process returns to step S123. When the reading is completed, the process proceeds to step S130, and it is determined whether the image data of the next one rectangular image array has been stored. Here, when the storage is completed, the image data is stored as shown in FIG. 10, for example. In that case, the process proceeds to step S113, and the image data of the rectangular image array is read. If not, the process proceeds to step S131. Next, if no image data of the rectangular image array is stored, it is determined to end. This is the same as in step S121. On the other hand, if any image data is stored, it is determined that the image data of the next rectangular image array is input, and the process proceeds to step S127.

  Here, in order to make the explanation easy to understand, the description has been made with one flowchart. However, it may be executed by so-called multitask processing in which rectangular image input, writing to the line buffer, and reading processing of image data stored in the line buffer are executed in separate tasks. In addition, the address calculation formula shown above is changed according to the size of the rectangular image and the number of pixels for one line of image data in page units, and thus is described only as an example, and the present invention is limited. Of course, it is not a thing. For example, if the size of the rectangular image is n × n pixels, n may be an arbitrary value as long as it is an integer of 2 or more. Further, when the size of the rectangular image is n × n pixels, it is desirable that the number of pixels of line-by-line image data is n × n × m pixels. At this time, n and m may be arbitrary values as long as they are integers of 2 or more.

  In the above description, the writing of the rectangular image is started in response to the reading of the image data for one line from the line memory 210. However, other modes may be used. For example, when the size of the rectangular image is n × n pixels (n is an integer equal to or larger than 2), when image data of one line or more and less than n lines is read from the line memory 210, writing of the rectangular image is started. May be. Even in this case, the time required to read and write the image data can be shortened compared to the case where writing of the rectangular image is started after reading the image data for n lines from the line memory 210.

(Other embodiments)
Although the embodiments of the present invention have been described in detail above, the present invention may be applied to a system constituted by a plurality of devices or may be applied to an apparatus constituted by one device.

  In the present invention, a software program that implements the functions of the above-described embodiments is supplied directly or remotely to a system or apparatus, and the computer of the system or apparatus reads and executes the supplied program. Can also be achieved. In that case, as long as it has the function of a program, the form does not need to be a program.

  Accordingly, since the functions of the present invention are implemented by computer, the program code installed in the computer also implements the present invention. That is, the claims of the present invention include the computer program itself for realizing the functional processing of the present invention. In this case, the program may be in any form as long as it has a program function, such as an object code, a program executed by an interpreter, or script data supplied to the OS.

  Various recording media for supplying the program can be used. For example, floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, MO, CD-ROM, CD-R, CD-RW, magnetic tape, nonvolatile memory card, ROM, DVD (DVD-ROM, DVD- R).

  As another program supply method, the program can be supplied by connecting to a home page on the Internet using a browser of a client computer and downloading the program from the home page to a recording medium such as a hard disk. In this case, the computer program itself of the present invention or a compressed file including an automatic installation function may be downloaded. It can also be realized by dividing the program code constituting the program of the present invention into a plurality of files and downloading each file from a different homepage. That is, a WWW server that allows a plurality of users to download a program file for realizing the functional processing of the present invention on a computer is also included in the claims of the present invention.

  Further, the program of the present invention may be encrypted, stored in a storage medium such as a CD-ROM, and distributed to users. In that case, a user who has cleared a predetermined condition is allowed to download key information to be decrypted from a homepage via the Internet, and using the key information, the encrypted program can be executed on a computer in a format that can be executed. To be installed.

  Further, the present invention can be realized in a form other than the form in which the functions of the above-described embodiments are realized by the computer executing the read program. For example, based on the instructions of the program, an OS or the like running on the computer performs part or all of the actual processing, and the functions of the above-described embodiments can also be realized by the processing.

  Furthermore, the program read from the recording medium may be written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. In this case, thereafter, based on the instructions of the program, the CPU or the like provided in the function expansion board or function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing. .

1 is a block diagram illustrating a schematic configuration of an image processing apparatus that converts rectangular images into dot-sequential raster image data according to the present embodiment. FIGS. 2A and 2B are diagrams illustrating a configuration example of a rectangular image. FIG. 2A illustrates a first rectangular image, and FIG. 2B illustrates a rectangular image to be input next. It is a block diagram showing a memory circuit configuration of a double buffer system. It is a figure explaining the writing order of the image data to the line buffer by a writing control part. It is a figure explaining the read-out order of the image data from the line buffer by a read-out control part. FIG. 6 is a diagram illustrating a state in which two rectangular images input next are stored in the read memory area after data reading for one main scanning line is completed. It is a figure explaining reading of the image data of the 2nd rectangular image array. It is a figure which shows a mode that each pixel of the rectangular image input next is written in the position of the pixel read in the order shown in FIG. After the third rectangular image array is stored in the line buffer, reading of the image data of one main scan is started, and the first rectangle of the fourth rectangular image array to be input next with the reading of the data is started. It is a figure which shows the state in which the image was stored in the position of the read image data. In this embodiment, it is a figure explaining the address order at the time of writing the image data of the first rectangular image array in a line buffer. In this Embodiment, it is a figure explaining the read-out order of the image data of the 1st line for the rectangular image array stored as shown in FIG. In the present embodiment, after reading out the first row of image data for the first rectangular image array in FIG. 11, the first and second of the image data for the second rectangular image array that is input next. It is a figure which shows the state which wrote the rectangular image in the line buffer. In this Embodiment, it is a figure which shows the state by which the image data for the 2nd rectangular image array was written in the line buffer. FIG. 14 is a diagram illustrating a process of reading image data for the second rectangular image array shown in FIG. 13 from the line buffer in the present embodiment. It is a block diagram which shows the structure of the control part which concerns on this Embodiment. It is a figure which shows the data arrangement | sequence of the rectangular image in the line memory which concerns on this Embodiment. It is a figure which shows the relationship between the address and data of the line memory which concerns on this Embodiment. It is a figure explaining the meaning of the offset by the kind and mode of each offset in this Embodiment. It is a figure explaining the state transition controlled by the access arbitration part which concerns on this Embodiment. , , It is a flowchart explaining the data conversion process by the control part which concerns on this Embodiment.

Claims (8)

An image processing device for inputting a plurality of rectangular images composed of n × n pixels and outputting image data in units of lines with n × m pixels as one line,
Storage means capable of storing pixel data for n lines in which one line is n × m pixels;
Address generation means for generating a write address for writing the rectangular image in the storage means, and a read address for reading line-unit image data from the storage means;
Each time m rectangular images are written to the storage means, the write address generation method is switched between the first write address generation method and the second write address generation method, and image data for n lines is stored in the storage unit. Switching means for switching the read address generation method between the first read address generation method and the second read address generation method each time reading from the means;
After writing the rectangular image to the storage unit based on the first write address generation method, the image data is read in line units from the storage unit based on the first read address generation method. After writing the rectangular image to the storage unit based on the second write address generation method, the image data is read in line units from the storage unit based on the second read address generation method. and control means for controlling said storage means,
The control unit reads the image data of one line or more and less than n lines from the storage unit based on the first read address generation method, and the control unit reads the image data into the area where the image data is read. In response to starting to write a rectangular image based on the second write address generation method and reading image data of one line or more and less than n lines from the storage unit based on the second read address generation method, Start writing a rectangular image based on the first write address generation method to the area from which the image data has been read,
The first write address generation method is a method of generating addresses so that n pixels are written n times every n × m addresses in writing each rectangular image, and the write start address of the kth rectangular image is set as the write start address. The address obtained by adding n × n is the write start address of the (k + 1) th rectangular image, and the address obtained by adding n to the write start address of the kth rectangular image is the write start address of the (k + 2) th rectangular image. So that the address is generated
The first read address generation method is a method of generating an address so that n pixels are read m times in reading of each line, and an address obtained by adding n × n to the kth read start address is (k + 1). This is a method for generating an address so that an address obtained by adding n to the k-th read start address becomes the (k + 2) -th read start address.
The second write address generation method is a method of generating an address so that n × n pixels are written once in writing of each rectangular image, and n × n is set as a write start address of the kth rectangular image. In this method, the address is generated so that the added address becomes the write start address of the (k + 1) th rectangular image.
The second read address generation method is a method of generating an address so that n pixels are read m times in reading of each line, and an address obtained by adding n × n to the kth read start address is (k + 1). An image processing apparatus that generates an address so that an address obtained by adding n × m to a k-th read start address becomes a (k + 2) -th read start address . In response to reading one line of image data from the storage means based on the first read address generation method, the control means writes the second write to the area from which the image data has been read. The writing of the rectangular image based on the address generation method is started, and the image data is read in response to reading the image data for one line from the storage unit based on the second read address generation method. The image processing apparatus according to claim 1 , wherein writing of a rectangular image based on the first write address generation method is started to an area. The first write address generation method is a method of generating an address for writing the rectangular image to different lines by n pixels,
It said first read address generating method is a method for generating an address for reading the image data of n × m pixels that will be stored in a specific line as image data in line units,
The second write address generation method is a method of generating an address for writing the rectangular image on the same line,
The second read address generation method is a method of generating an address for reading n × m pixel image data as image data in units of lines from each line included in the n lines. The image processing apparatus according to 1 or 2 . Wherein, after reading the image data of the one line, in the region of the image data thus read out, then any one of claims 1 to 3, characterized in that storing a rectangular image that is input 1 The image processing apparatus according to item. It has a storage means capable of storing pixel data for n lines where one line is n × m pixels, and inputs a plurality of rectangular images composed of n × n pixels to make n × m pixels one line. An image processing method in an image processing apparatus for outputting line-unit image data,
A generation step of generating a write address for writing the rectangular image to the memory and a read address for reading line-unit image data from the storage unit;
Each time m rectangular images are written to the memory, the write address generation method is switched between the first write address generation method and the second write address generation method, and image data for n lines is read from the memory. A switching step of switching the read address generation method between a first read address generation method and a second read address generation method each time;
After writing the rectangular image to the memory based on the first write address generation method, the image data is read from the memory in units of lines based on the first read address generation method, and After writing a rectangular image to the memory based on a second write address generation method, the memory is configured to read line-by-line image data from the memory based on the second read address generation method. and a control step of controlling,
In response to reading out image data of one line or more and less than n lines from the storage unit based on the first read address generation method, the control step reads the image data into the area from which the image data was read. In response to starting to write a rectangular image based on the second write address generation method and reading image data of one line or more and less than n lines from the storage unit based on the second read address generation method, Start writing a rectangular image based on the first write address generation method to the area from which the image data has been read,
The first write address generation method is a method of generating addresses so that n pixels are written n times every n × m addresses in writing each rectangular image, and the write start address of the kth rectangular image is set as the write start address. The address obtained by adding n × n is the write start address of the (k + 1) th rectangular image, and the address obtained by adding n to the write start address of the kth rectangular image is the write start address of the (k + 2) th rectangular image. So that the address is generated
The first read address generation method is a method of generating an address so that n pixels are read m times in reading of each line, and an address obtained by adding n × n to the kth read start address is (k + 1). This is a method for generating an address so that an address obtained by adding n to the k-th read start address becomes the (k + 2) -th read start address.
The second write address generation method is a method of generating an address so that n × n pixels are written once in writing of each rectangular image, and n × n is set as a write start address of the kth rectangular image. In this method, the address is generated so that the added address becomes the write start address of the (k + 1) th rectangular image.
The second read address generation method is a method of generating an address so that n pixels are read m times in reading of each line, and an address obtained by adding n × n to the kth read start address is (k + 1). An image processing method characterized in that an address is generated so that an address obtained by adding n × m to a kth read start address becomes a (k + 2) th read start address. . In response to reading out image data for one line from the memory based on the first read address generation method, the control step includes the second write address to the area from which the image data has been read out. The writing of the rectangular image based on the generation method is started, and the image data for one line is read from the memory based on the second read address generation method. 6. The image processing method according to claim 5 , wherein writing of a rectangular image based on the first write address generation method is started. The first write address generation method is a method of generating an address for writing the rectangular image to different lines by n pixels,
It said first read address generating method is a method for generating an address for reading the image data of n × m pixels that will be stored in a specific line as image data in line units,
The second write address generation method is a method of generating an address for writing the rectangular image on the same line,
The second read address generation method is a method of generating an address for reading n × m pixel image data as image data in units of lines from each line included in the n lines. The image processing method according to 5 or 6 . Wherein the control step, after reading the image data of the one line, in the region of the image data thus read out, then any one of claims 5 to 7, characterized in that storing a rectangular image that is input 1 The image processing method according to item.

Images