JP5093171B2 - Data compression device, data decompression device, and display device equipped with the same - Google Patents

Description

  The present invention relates to a data compression apparatus that compresses or expands digital data, a data expansion apparatus, and a display device equipped with them.

  Currently, the transition from analog broadcasting to digital broadcasting is promoted in television broadcasting, and the transition from DVD to BD (Blu-ray Disc) is promoted in recording media. Along with these transitions, the transition from SD (Standard Definition) images to HD (High Definition) images is also accelerating.

  An HD image has an increased data amount and processing load as compared to an SD image, and causes an increase in memory capacity in a device (for example, a display device or a recording device) and an increase in bus transmission amount. High-efficiency compression techniques for image data include compression methods such as MPEG and JPEG, but the processing load is high, and dedicated hardware must be installed in the equipment for high-speed processing, which increases costs . In view of this, there has been proposed a method capable of reducing the memory capacity and the transmission amount by a relatively simple process, although the compression rate does not reach that of a compression method such as MPEG or JPEG (for example, see Patent Documents 1 and 2). ).

Japanese Patent Laid-Open No. 7-15347 Japanese Patent Laid-Open No. 3-14587

  The simplest method for compressing digital data such as image data is a method of discarding the lower bits of the digital data. The lower bit corresponds to the high-frequency component of the image, and even if the component is discarded, the effect on the image quality is less than when the upper bit is discarded. It is certain that etc. will decline.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a technique capable of compressing or decompressing digital data by a simple process while suppressing deterioration in quality.

  A data compression device according to an aspect of the present invention is the most significant bit having a common bit value among a plurality of digital values by comparing the plurality of digital values constituting the digital data bit by bit from the most significant bit. A common bit number detection unit that detects the number of bits from a bit as a common bit number, and discards bit data corresponding to the common bit number detected by the common bit number detection unit from the most significant bit of the digital value, and the digital value A compression unit that compresses the digital value by discarding bit data corresponding to the lower-order discard bit number obtained by subtracting the common bit number from the preset total discard bit number from the least significant bit.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, a system, a recording medium, a computer program, and the like are also effective as an aspect of the present invention.

  Digital data can be compressed or expanded by a simple process while suppressing deterioration in quality.

It is a block diagram which shows the structure of the display apparatus which mounts the data compression apparatus and data expansion apparatus based on Embodiment 1 of this invention. It is a figure which shows the structure of the data compression apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the structural example of a common bit number detection part. It is a figure which shows the structural example of the common bit number detection part for detecting the common bit number of six digital values. It is a figure which shows the structural example of a compression part. It is a figure which shows the data structure example of a bit stream. It is a figure which shows the structure of the data expansion | extension apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the structural example of an expansion | extension part. It is a figure which shows the structure of the data compression apparatus which concerns on Embodiment 2 of this invention. It is a figure which shows the example of a data structure of the bit stream produced | generated by the differential compression system.

  Before describing details of the data compression apparatus and the data expansion apparatus according to the embodiment of the present invention, application examples of the data compression apparatus and the data expansion apparatus will be described.

Embodiment 1.
FIG. 1 is a block diagram showing a configuration of a display device 500 equipped with a data compression device and a data decompression device according to Embodiment 1 of the present invention. The display device 500 may be a thin television such as a liquid crystal television or a plasma television, or may be a video camera display system.

  The display device 500 includes a decoding unit 510, a first compression unit 100a, a frame memory 520, a second expansion unit 200b, an intermediate frame generation unit 530, a second compression unit 100b, a first expansion unit 200a, and a display unit 540. . As the first compression unit 100a and the second compression unit 100b, a data compression device described later can be employed. As the first decompression unit 200a and the second decompression unit 200b, a data decompression device described later can be employed.

  The decoding unit 510 decodes input encoded image data. The encoded image data includes MPEG-2, MPEG-4, H.264. The data is compression-encoded by a method such as H.264 / AVC and is input to the decoding unit 510 via a broadcast wave or a recording medium.

  The intermediate frame generation unit 530 is mounted to realize a function of increasing the frame rate. A typical moving image file is often composed of 60 frames per second. The intermediate frame generation unit 530 generates a moving image of 120 frames per second by generating intermediate frame images (that is, interpolation images) between adjacent frame images included in the moving image file of 60 frames per second. Image data can be generated. This technique of doubling the frame rate is used as a technique for reducing image blur. In particular, it is effective as a measure against image blurring of a liquid crystal television. Note that an existing general technique can be adopted as a method for generating the intermediate frame image.

  However, when the frame rate is increased, the amount of image data to be held in the frame memory 520 increases, and the amount of traffic on the internal bus 550 increases. That is, the load in the apparatus and the cost increase. On the other hand, a method of reducing the image data amount and the traffic amount by compressing and holding or transmitting the image data in the display device 500 is conceivable. In order to realize this, the display device 500 includes the first compression unit 100a, the second expansion unit 200b, the second compression unit 100b, and the first expansion unit 200.

  The first compression unit 100a compresses the image data decoded by the decoding unit 510. Image data is described by a digital value of a plurality of bits. The first compression unit 100a compresses the digital data by discarding the bit data of a predetermined number of bits from the digital data of the plurality of bits. For example, if 5 bits of bit data are discarded from 10 bits of digital data, the amount of data can be compressed in half. In this case, even if the frame rate is doubled by the intermediate frame generation unit 530, the original data amount is substantially maintained.

  The image data compressed by the first compression unit 100a is temporarily stored in the frame memory 520 via the internal bus 550. The second decompressing unit 200 b decompresses the image data in units of frames held in the frame memory 520 and outputs the decompressed image data to the intermediate frame generating unit 530. The intermediate frame generation unit 530 generates interpolated image data from the frame-unit image data expanded by the second expansion unit 200b and outputs the interpolated image data to the second compression unit 100b. The second compression unit 100b compresses the generated interpolated image data. The image data compressed by the second compression unit 100b is temporarily stored in the frame memory 520 via the internal bus 550.

  The first decompressing unit 200a decompresses the compressed image data (including the compressed interpolated image data) held in the frame memory 520 and outputs the decompressed image data to the display unit 540. The display unit 540 displays the image data expanded by the first expansion unit 200a.

  Note that the data compression device and the data decompression device according to Embodiment 1 of the present invention can also be applied to the display device 500 configured not to include the intermediate frame generation unit 530, the second compression unit 100b, and the second decompression unit 200b. It is. The display device 500 includes the first compression unit 100a and the first decompression unit 200a, so that the amount of image data to be held in the frame memory 520 and the internal bus 550 can be reduced. The amount of traffic can be reduced.

  Further, the application example of the data compression device and the data decompression device according to the first embodiment of the present invention is not limited to the display device 500 shown in FIG. For example, you may apply to an image recording / reproducing apparatus. Further, the data compression device and the data decompression device may be mounted on different devices. For example, the former may be mounted on a transmission device and the latter may be mounted on a reception device.

  Details of the data compression device and the data decompression device according to Embodiment 1 of the present invention will be described below. It is assumed that the size of the image processed by the data compression device and the data expansion device (more specifically, the number of vertical and horizontal pixels) is known between the two. Further, the data compression apparatus converts the digital data into a bit stream in a format to be described later. It is assumed that the data decompressor already knows the structure of the bit stream. Further, it is assumed that the data decompression apparatus can decompress only a bit stream conforming to the format.

  FIG. 2 is a diagram showing a configuration of the data compression apparatus 100 according to Embodiment 1 of the present invention. The data compression apparatus 100 discards bit data having a predetermined total number of discarded bits from R (R is an integer of 2 or more) bits of digital data, thereby converting the digital data to r (1 ≦ r <R) bits. Compress and convert. In the following description, an example in which compression conversion is performed on 4-bit digital data by discarding 4-bit bit data from 8-bit digital data will be described. In this case, the total discard bit number is 4 bits.

  The data compression apparatus 100 includes a holding unit 110, a common bit number detection unit 120, a compression unit 130, and an assembly unit 140. The holding unit 110 can hold N (N is a natural number) digital values. Here, an example in which digital values each representing a unit pixel are continuously input to the holding unit 110 will be described. These digital values may be input in the order of raster scanning from the upper left to the lower right of the image, or may be input in the scanning order with the main scanning direction as the horizontal direction and the sub-scanning direction as the vertical direction. They may be input in the scanning order in which the scanning direction is the vertical direction and the sub-scanning direction is the horizontal direction.

  Hereinafter, an example will be described in which N = 6, that is, digital values for 6 pixels are stored in the holding unit 110 and the digital values for 6 pixels are compressed as one unit. If the number of pixels of one image is not divisible by 6, the last number of pixel data input to the holding unit 110 is less than 6, but in that case, there are blank spaces for less than 6. Zero is stored in the data area, and processing is performed in the same manner as when the digital values for six pixels are satisfied.

  The digital values for six pixels stored in the holding unit 110 are input to the common bit number detection unit 120. Here, the digital values for the six pixels are expressed as x0, x1, x2, x3, x4, and x5 in the order of input. An example of the digital value xi (i = 0,..., 5) for the six pixels is given below.

x0: 10111101
x1: 10101111
x2: 10100011
x3: 1001000
x4: 10011011
x5: 1000110

  The common bit number detection unit 120 compares a plurality of digital values continuously input from the holding unit 110 in bit units from the most significant bit, so that the bit values are common among the plurality of digital values. The number of bits from the most significant bit is detected as a common bit number p (p is an integer (excluding negative)).

  In the example described above, the common bit number detection unit 120 detects the common bit number p from the most significant bit of the digital value for six pixels input from the holding unit 110. More specifically, the digital values for six pixels are compared bit by bit from the most significant bit, and the number of bits from the most significant bit until a different bit value first appears is obtained. For example, when the most significant bit value is the same value and the next bit value is different, the common bit number p is 1. In the digital value xi (i = 0,..., 5) in the above-described example, the upper 7th bit and the 6th bit are “10” and the common bit number p is 2.

  FIG. 3 is a diagram illustrating a configuration example of the common bit number detection unit 120. The common bit number detection unit 120 includes an upper bit extractor 121, a switch 122, a signal register 123, a determination register 124, an OR circuit (hereinafter referred to as an OR circuit) 125, an exclusive OR circuit (hereinafter referred to as an XOR circuit). 126), an OR circuit 127, a switch 128, and a counter 129.

  The digital values stored in the holding unit 110 are sequentially input to the upper bit extractor 121. The upper bit extractor 121 extracts the upper (R−r) bits of the input digital value. In the above-described example, upper (8-4) bits, that is, upper 4 bits are extracted. The extracted upper bits are input to the switch 122.

  When the upper bit input from the upper bit extractor 121 is the first digital value of the N digital values, the switch 122 outputs the upper bit to the signal register 123 and outputs a predetermined reset signal. Is sent to the decision register 124. The signal register 123 temporarily holds the upper bit.

  The determination register 124 can handle a digital value of (R−r) bits (here, 4 bits), and whether or not the upper bits of one digital value and the upper bits of another digital value are the same. judge. If they are the same, “0” is output, and if they are different, “1” is output. The determination register 124 is reset to an initial value when the reset signal is input. That is, all bit values are reset to “0”. In this case, since a 4-bit digital value is handled, “0000” is set.

  The switch 122 switches the output destination and outputs the upper bits to the OR circuit 125 and the XOR circuit 126 when the input upper bits are those of digital values other than the head of the N digital values. .

  The OR circuit 125 takes a logical sum of the upper bits temporarily stored in the signal register 123 and the upper bits input from the switch 122 and stores the logical sum result in the signal register 123. The XOR circuit 126 performs an exclusive OR of the upper bits temporarily stored in the signal register 123 and the upper bits input from the switch 122 and outputs the exclusive OR result to the OR circuit 127. The exclusive OR result indicates a bit unit match between the upper bits. The matching bit is “0”, and the non-matching bit is “1”.

  The OR circuit 127 calculates the logical sum of the value stored in the determination register 124 and the value input from the XOR circuit 126 and stores the logical sum result in the determination register 124 via the switch 128. When the above processing is repeated N times, the output destination of the switch 128 is switched, and the digital value output from the OR circuit 127 is input to the counter 129 via the switch 128. The counter 129 counts the number of “0” s consecutive from the most significant bit of the digital value input from the OR circuit 127. The count value is output to the compression unit 130 and the assembly unit 140 as the common bit number p.

  FIG. 4 is a diagram illustrating a configuration example of the common bit number detection unit 120 for detecting the common bit number of six digital values. 4 corresponds to the functions of the OR circuit 125 and the signal register 123 shown in FIG. The XOR circuit 1261 to XOR circuit 1265 shown in FIG. 4 corresponds to the function of the XOR circuit 126 shown in FIG. 4 corresponds to the functions of the OR circuit 127 and the determination register 124 shown in FIG.

  Here, consider an example in which the digital value xi (i = 0,..., 5) of the above-described example is input to the upper bit extractor 121. The upper bit extractor 121 is provided with the upper 4 bits (“1011”, “1010”, “1010”, “1001”, “1001”, “1000” of each digital value xi (i = 0,..., 5). ”) Is extracted and output to the OR circuit 1251 to the OR circuit 1255. When these upper 4 bits are input to the OR circuit 1251 to the OR circuit 1255, the digital value output from the OR circuit 1275 is “0011”. The counter 129 counts the number of “0” s consecutive from the most significant bit of “0011”. Here it is 2. That is, the common bit number p is 2.

  Returning to FIG. 2, the compression unit 130 discards bit data for the common bit number p detected by the common bit number detection unit 120 from the most significant bit of the digital value stored in the holding unit 110, and Bit data corresponding to the number of lower-order discard bits obtained by subtracting the common bit number p from the total discard bit number is discarded from the least significant bit of the digital value. In the following example, the compression unit 130 discards bit data corresponding to the common bit number p from the most significant bit of all digital values except for one of a plurality of digital values stored in the holding unit 110. In addition, the bit data corresponding to the number of lower-order discard bits is discarded from the least significant bit of all the digital values. That is, the compression process is skipped for one digital value (for example, the first digital value) among the plurality of digital values.

  FIG. 5 is a diagram illustrating a configuration example of the compression unit 130. The compression unit 130 includes a switch 131 and a discard unit 132. When the digital value input from the holding unit 110 is the first digital value among the N digital values, the switch 131 outputs the digital value to the assembling unit 140 as it is. When the digital value input from the holding unit 110 is a digital value other than the head of the N digital values, the switch 131 outputs the digital value to the discard unit 132.

  The discard unit 132 refers to the common bit number p and converts the R-bit digital value into an r-bit digital value. Here, an 8-bit digital value is converted into a 4-bit digital value. For example, the discarding unit 132 performs conversion by the following process. First, a bit shift amount s for shifting the digital value of R bits is calculated. This bit shift amount s is calculated by (R−rp). Here, the bit shift amount s is (8-4-2) = 2.

  Next, the discarding unit 132 right-bit shifts the digital value of R bits by the calculated bit shift amount s. As a result, lower-order bit data for s bits is discarded. Next, in order to extract bit data of lower r bits from the digital value after the right bit shift, the discarding unit 132 performs a masking process on the digital value after the right bit shift. For example, a logical sum of the digital value after the right bit shift and “00001111” is calculated. Thereby, a 4-bit digital value can be extracted. By repeating the above processing, the compressed digital values yi (i = 0,..., 5) corresponding to the digital values xi (i = 0,. It becomes the value of.

y0: 10111101
y1: 1011
y2: 1000
y3: 0110
y4: 0110
y5: 0011

  Returning to FIG. 2, the assembling unit 140 assembles the data compressed by the compressing unit 130. More specifically, the assembling unit 140 uses the common bit number p, one uncompressed digital value not compressed by the compressing unit 130, and all the compressed digital values compressed by the compressing unit 130 as one unit bit. Assemble as a stream. The assembly unit 140 preferably formats the bit stream so that it can be processed in units of bytes so that it can be easily handled by an internal bus of a digital device. That is, when the number of bits of the bit stream is not a multiple of a predetermined value, for example, a multiple of 8, adjustment bits are inserted into the bit stream so as to be a multiple of 8. Of course, the predetermined value may be other than 8.

More specific description will be given below. First, bit data indicating the common bit number p is arranged, and then the compressed digital values yi (i = 0,..., 5) are arranged in order. Here, the bit number q of the digital value representing the common bit number p needs to satisfy the relational expression (R−r <2 ^q ). In the example described above, since R = 8 and r = 4, the minimum ^q that satisfies 4 <2q is 3.

The total bit number B of the bit stream is defined by the following equation 1.
B = R + r × (N−1) + q (Formula 1)

  In the example described above, since N = 6, the total number of bits B is 31. In order to make the total bit number B a multiple of 8 which is a byte unit, it is necessary to insert one adjustment bit. Here, one bit is added to the bit data expressing the common bit number p. That is, the bit number q of the digital value expressing the common bit number p is set to 4, the common bit number p is assigned to the lower 3 bits of the digital value, and “0” is inserted as the adjustment bit into the 1 bit. Thereby, it is possible to format in units of bytes.

  FIG. 6 is a diagram illustrating a data structure example of a bit stream. The data structure is obtained by converting the 8-bit digital value for 6 pixels into the 8-bit digital value for 1 pixel and the 4-bit digital value for 5 pixels in the above example and formatting. . The bit shift amount s may be added instead of the common bit number p. When generating one bit stream, the assembling unit 140 generates a bit stream corresponding to digital values for the next six pixels. By repeating this process, one entire image can be compressed.

  FIG. 7 is a diagram showing a configuration of the data decompression apparatus 200 according to Embodiment 1 of the present invention. The data decompression device 200 is a device that decompresses the data compressed by the data compression device 100 described above. The data decompression apparatus 200 includes a holding unit 210, a decomposition unit 220, and a decompression unit 230. The bit stream generated by the data compression apparatus 100 is input to the holding unit 210, and the holding unit 210 temporarily holds the bit stream.

  The decomposition unit 220 decomposes the bitstream input from the holding unit 210 into the common bit number p, the uncompressed digital value, and the compressed digital value, and outputs the result to the decompression unit 230. In the case of the bit stream shown in FIG. 6, the leading common bit number p is first extracted, then the leading 8-bit digital value y0 is extracted, and then the 4-bit digital value yi (i = 1,. .., 5) are taken out sequentially.

  The decompressing unit 230 adds upper bit data common to the uncompressed digital value to the upper bit side of the compressed digital value, and the lower bit side of the compressed digital value is obtained from the common bit number p. Add bit data for the number of lower bits discarded. When adding the bit data, an intermediate value in a numerical range that can be expressed by the lower-order discard bit number may be added as a correction term.

  FIG. 8 is a diagram illustrating a configuration example of the decompression unit 230. The decompression unit 230 includes an intermediate value calculator 231, a switch 232, an upper bit extractor 233, a shifter 234, an OR circuit 235, and an OR circuit 236.

  Digital values yi (i = 0,..., 5) are sequentially input to the switch 232. When the head digital value y0 is input, the switch 232 outputs the same as it is to the outside and also outputs it to the upper bit extractor 233. When a digital value yi (i = 0,..., 5) other than the head is input, the switch 232 outputs the digital value yi (i = 0,..., 5) to the shifter 234.

  When the leading digital value y0 is input to the decompression unit 230, the common bit number q is also input to the decompression unit 230. The common bit number q is input to the intermediate value calculator 231, the upper bit extractor 233, and the shifter 234, respectively.

The upper bit extractor 233 generates a common mask value m defined by the following equation 2 from the head digital value y0.
m = (y0 >> (Rp)) << (Rp) (Formula 2)
Here, the operator “>>” represents a right bit shift, and the operator “<<” represents a left bit shift.

  The upper bit extractor 233 right-bit shifts the head digital value y0 by the number of bits obtained by subtracting the common bit number q (= 2) from the number of bits (= 8) of the head digital value y0. Then, the left bit is shifted by the same number of bits. Thereby, the lower 6 bits of the head digital value y0 can be masked. In the example described above, since the top digital value y0 is “10111101”, the common mask value m is “10000000”. The common mask value m is held in the upper bit extractor 233 until the common bit number q of the next bit stream is input.

The shifter 234 shifts the digital values yi (i = 0,..., 5) other than the above by a bit shift amount t defined by the following equation 3 to the left. The digital value yi (i = 0,..., 5) after the left bit shift is output to the OR circuit 235.
t = R−r−p (Formula 3)

  Here, the bit shift amount t is 8-4-2 = 2. In the example described above, since the digital value y1 is “1011”, the digital value y1 ′ after the left bit shift is “101100”.

  The OR circuit 236 performs a logical OR between the digital value yi ′ (i = 1,..., 5) after the left bit shift by the shifter 234 and the common mask value m stored in the upper bit extractor 233. Take. In the example described above, the digital value y1 ′ after the left bit shift is “101100”, and thus the digital value y1 ″ after the logical sum is “10101100”.

The intermediate value calculator 231 calculates a correction term for suppressing an error between the original digital value and the restored digital value that occurs through the compression and expansion processes. More specifically, since an R (= 8) bit digital value is converted into an r (= 4) bit digital value during compression, the original digital value is converted into the bit shift amount s (= R−r−). The bit was shifted to the right by p = 8-4-2 = 2). Thus, an error of the lower s bits, ie a maximum of 2 ^s −1, can occur with respect to the original digital value.

In order to suppress this error, the intermediate value calculator 231 obtains the bit shift amount s using the input common bit number q, and calculates 2 ^s−1 as a correction term. When s = 0, the correction term is 0. In the example described above, s = 2 and the correction term is 2.

  The OR circuit 236 calculates the logical sum of the digital value yi ″ (i = 1,..., 5) after the logical sum input from the OR circuit 235 and the correction term input from the intermediate value calculator 231. The restored digital value xi ′ (i = 1,..., 5) is output. In the above-described example, the digital value y1 ″ after the logical sum is “10101100”, and thus the restored digital value x1 ′ is “10101110”. The original digital value x1 is “10101111”, and the error can be suppressed to 1.

  As described above, according to the first embodiment, the number of discarded bits on the lower bit side can be suppressed as much as possible, so that digital data can be compressed or expanded by a simple process while suppressing a decrease in quality. In addition, compression and decompression can be realized only by basic logical operations, and hardware implementation is easy. When implemented in hardware, compression and decompression can be made faster and more stable. Further, since the conversion table is not referred to when compressing and expanding, the memory capacity does not increase. Further, the error between the original data and the restored data generated by the compression and expansion can be kept to a slight level.

  Further, when the compression / decompression technique according to Embodiment 1 is applied to continuous pixel data, the number of common bits of a plurality of digital values tends to increase. This is because the adjacent pixel data is highly likely to be approximated. In particular, the tendency becomes strong in background parts such as the sky. In this case, the number of discarded bits on the lower bit side can be suppressed, and both quality maintenance and a high compression rate can be achieved.

Embodiment 2. FIG.
In the second embodiment, a compression apparatus and method that appropriately use the compression method according to the first embodiment and the differential compression method will be described.

  FIG. 9 is a diagram showing a configuration of a data compression device 100m according to Embodiment 2 of the present invention. The configuration of the data compression device 100m is a configuration in which a difference generation unit 150 and a determination unit 160 are added between the holding unit 110 and the common bit number detection unit 120 of the data compression device 100 illustrated in FIG.

  The difference generation unit 150 obtains difference values between successive digital values of a plurality of digital values continuously input from the holding unit 110. In the example described above, {digital value Xi−digital value X (i + 1)} (i = 0,..., 5) is calculated. Here, since there are six digital values, five difference values are calculated. The sign of the difference value is not discarded and is maintained.

  The determination unit 160 determines whether all the difference values obtained by the difference generation unit 150 are values within a range that can be expressed by the total number of discarded bits. In the example described above, since the total number of discarded bits is 4, the value within the range that can be expressed by the total number of discarded bits is −7 to +7. The most significant bit of the total discard bit number is assigned to the sign bit. When all the difference values are values within a range that can be expressed by the total number of discarded bits, the determination unit 160 generates the bit stream using a differential compression method, which will be described later, and the assembly unit 140 and the difference generation unit 150. To instruct. If even one of all the difference values is out of the range that can be represented by the total number of discarded bits, the common bit number detection is performed so that the bit stream is generated by the compression method according to the first embodiment. The unit 120 and the assembly unit 140 are instructed.

  The assembling unit 140, when all the difference values by the determination unit 160 are values within the range that can be expressed by the total number of discarded bits, identification information indicating that the compression method is the difference method, the plurality of digital values The first or last digital value and all the difference values are assembled as a unit bit stream. For example, the identification information indicating that the compression method is a differential method takes a value in the range of 0 to 4 common bits in the method of converting 8 bits into 4 bits in the above description of the second embodiment. Therefore, a value other than the value of the common bit number, for example, 7 can be assigned to distinguish it from the common bit number.

  FIG. 10 is a diagram illustrating a data structure example of a bitstream generated by the differential compression method. In the bitstream, identification information indicating that the compression method is a differential method is inserted instead of the common bit number of the bitstream shown in FIG. Following the identification information, the leading digital value X0, the difference Δ1 between the leading digital value X0 and the second digital value X1, the differences Δ2,... Between the second digital value X1 and the third digital value X2,. . . A difference from the previous adjacent pixel such as a difference Δ5 between the fifth digital value X4 and the sixth digital value X5 is described.

  Therefore, in the data decompression apparatus corresponding to the second embodiment, referring to the identification information of the first few bits in the bitstream, if the compression method is the compression method of the first embodiment, the decompression method of the first embodiment On the other hand, if the identification information indicates that the compression method is the differential method, the decompression process, that is, the difference Δ1 and the difference Δ2 are sequentially performed from the leading digital value X0, in contrast to the compression difference method of the second embodiment. ,. . . The second digital value X1 to the sixth digital value X5 are restored by adding or subtracting the difference values of the difference Δ5.

  As described above, according to the second embodiment, it is possible to further suppress the occurrence of an error between the original digital value and the restored digital value. Although the difference compression method basically does not cause an error, there is a possibility that the difference value is likely to vary, so that the compression rate is likely to vary. Therefore, it is not suitable for hardware. However, when all the difference values can be expressed by a predetermined number of bits, it can be compressed with higher quality than the compression method according to the first embodiment. Therefore, when all the difference values can be expressed by a predetermined number of bits, the differential compression method is adopted. When the difference value cannot be adopted, the compression method according to the first embodiment is adopted, so that the compression rate is kept constant and higher. Can be compressed to quality.

  In other words, for example, when the pixel value gradually changes as in gradation or the like, the lower-order bits of the predetermined number of bits are discarded in the compression method of the first embodiment. Depending on the number of low-order bits to be discarded, when the bit is close to the MSB, a difference between adjacent signals becomes larger than the original signal value when decoding, resulting in a step-like gradation, resulting in a reduction in image quality May lead to However, according to the differential compression method of the second embodiment, if the difference between all adjacent pixels within the predetermined pixel range is within the predetermined value, it can be regarded as a gradation image. By switching to the differential compression method of mode 2, even a minute image change such as gradation can be compressed with high quality.

  The present invention has been described based on some embodiments. It is understood by those skilled in the art that these embodiments are exemplifications, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. By the way.

  For example, the above-described parameters (for example, N, r) may be adaptively variably controlled according to the image content, instead of being fixed. For example, the data compression device 100 acquires the luminance distribution in the image to be compressed from another component in the display device 500. When compressing pixel data in an area where the acquired luminance distribution is leveled from a predetermined reference pattern, a control unit (not shown) in the data compression apparatus 100 controls the value of N to be larger than the current value. Also, the value of r is controlled to be smaller than the current value. When the acquired luminance distribution varies from a predetermined reference pattern, control is performed in reverse.

  In the above-described embodiment, the size of the image to be processed is known between the data compression apparatus 100 and the data expansion apparatus 200. If the size is not known, the common bit number of the bit stream is set. The size may be described in the area to be described. Of course, you may describe in the other area | region of the said bit stream.

  In addition, 4 bits are reserved as an area for describing the number of common bits, the number of common bits is described by 3 bits, and the remaining 1 bit describes the position information on the screen of the pixel data included in the bit stream. May be. On the premise of a scanning method in which the main scanning direction is the horizontal direction and the sub-scanning direction is the vertical direction, in the bit stream including the top pixel data of the horizontal line of the screen, “1” is described in the remaining 1 bit, and the top pixel In a bit stream not including data, “0” is described in the remaining 1 bit. This information makes it easy to count the number of lines and synchronize.

  In the above-described embodiment, image data has been described as an example of digital data to be compressed. However, audio data may be used. The common bit number detection unit 120 can similarly process the audio data continuously input from the holding unit 110.

  100 data compression device, 100a first compression unit, 100b second compression unit, 110 holding unit, 120 common bit number detection unit, 130 compression unit, 140 assembly unit, 150 difference generation unit, 160 determination unit, 200a first decompression unit 200b second decompression unit, 200 data decompression device, 210 holding unit, 220 decomposing unit, 230 decompression unit, 500 display device, 510 decoding unit, 520 frame memory, 530 intermediate frame generation unit, 540 display unit, 550 internal bus.

Claims (7)

By comparing multiple digital values that make up digital data bit by bit from the most significant bit, the bit number from the most significant bit, where the bit value is common among the multiple digital values, is the common bit number A common bit number detection unit to detect;
From the most significant bit of the digital value, the bit data corresponding to the number of common bits detected by the common bit number detection unit is discarded, and from the least significant bit of the digital value, from the preset total number of discarded bits A compression unit that compresses the digital value by discarding bit data corresponding to the number of lower-order discard bits obtained by subtracting the common bit number;
A data compression apparatus comprising: An assembly unit for assembling the data compressed by the compression unit;
The compression unit skips compression processing for one digital value of the plurality of digital values;
The assembly unit assembles the number of common bits, one uncompressed digital value not compressed by the compression unit, and a compressed digital value compressed by the compression unit as a unit bit stream. Item 2. The data compression device according to Item 1.   The data compression apparatus according to claim 2, wherein the assembling unit inserts adjustment bits so that the number of bits of the bit stream is a multiple of a predetermined value. A difference generation unit that obtains a difference value between successive digital values of a plurality of digital values that are continuously input; and
A determination unit that determines whether or not all the difference values obtained by the difference generation unit are values within a range that can be expressed by the total number of discarded bits,
The assembly unit, when all the difference values are values that can be expressed by the total number of discarded bits by the determination unit, identification information indicating that the compression method is a difference method, the plurality of digital values 4. The data compression apparatus according to claim 2, wherein the first or last digital value and all the difference values are assembled as a unit bit stream. A data decompression device for decompressing data compressed by the data compression device according to claim 2 or 3,
A decomposing unit that decomposes the bitstream into the common bit number, the uncompressed digital value, and the compressed digital value;
The upper bit side common to the uncompressed digital value is added to the upper bit side of the compressed digital value, and the lower-order discard bit number obtained from the common bit number is added to the lower bit side of the compressed digital value. A decompression unit for adding bit data of
A data decompression apparatus comprising:   6. The data decompression apparatus according to claim 5, wherein the decompression unit adds an intermediate value in a numerical range that can be expressed by the number of lower-order discard bits to the lower-order bits of the compressed digital value. A decoding unit for decoding the encoded image data;
The data compression device according to claim 2 or 3, wherein the image data decoded by the decoding unit is compressed.
The data expansion device according to claim 5 or 6, wherein the image data compressed by the data compression device is expanded.
A display unit for displaying the image data expanded by the data expansion device;
A display device comprising:

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