JP5090010B2 - Encoder - Google Patents

Description

  The present invention relates to an error correction encoding / decoding technique, and more particularly to an encoding device, a decoding device, and a recorded information reading device that perform error correction encoding / decoding on data stored in a storage medium.

  In recent years, storage devices using hard disks are becoming essential devices in various fields such as personal computers, hard disk recorders, video cameras, and mobile phones. Storage devices using a hard disk have various specifications required depending on the field to which they are applied. For example, a hard disk mounted on a personal computer is required to have high speed and large capacity. In order to improve high speed and large capacity, it is necessary to perform error correction coding with high correction capability. However, since the amount of data handled per unit time increases as the speed increases, errors per unit time also increase proportionally. Then, when an error correction method with low error correction capability is used, the hard disk is re-read, so that the time required to access the hard disk increases and becomes a bottleneck for speeding up.

  In general, a signal sequence in which a DC component is reduced or removed (hereinafter referred to as “DC-free” or “DC-free”) is desired as a signal sequence to be subjected to error correction coding. . DC free means that the frequency is 0, that is, the spectrum in the DC component is 0. In other words, it means that the ratio of 0 and 1 is equal in a plurality of bits included in the signal sequence before modulation. By providing the signal sequence with the DC-free property, the average level of the reproduction signal obtained from the recording pattern of the modulation data stored in the storage medium is a predetermined signal sequence length regardless of the pattern of the signal sequence before modulation. The noise resistance is improved by having a constant property within the range of. That is, in a signal sequence having a low DC-free property, the detection probability decreases in data detection using the Viterbi algorithm. As a result, the correction capability in low density parity check decoding and Reed-Solomon decoding is also reduced. In general, a run-length limit code is used to ensure synchronization between sampling timing and data. The run length limited code is a coding that limits the maximum continuous length of 0 or the maximum continuous length of 1.

Conventionally, as a method for performing run-length limited encoding while satisfying DC-freeness of a signal sequence, a plurality of encoded sequences are obtained by executing run-length limited encoding on signal sequences to which different redundant bits are added. Among them, a method for selecting a sequence having characteristics close to DC-free has been proposed (see, for example, Patent Document 1). In addition, a method has been proposed in which run-length limited encoding having a plurality of different properties is performed, and a sequence having characteristics close to DC-free is selected from the plurality of encoded sequences (for example, Patent Document 2). reference.).
JP 2002-100125 A JP 2004-213863 A

  Under such circumstances, the present inventor has come to recognize the following problems. When realizing DC-free coding by selecting a sequence having good DC-free characteristics from among a plurality of coded sequences, there is no coded sequence having good DC-free characteristics among the plurality of coded sequences to be selected. There is a case. That is, it is necessary to have a configuration capable of generating at least one sequence having good DC-free characteristics among the encoded sequences to be selected, which affects the circuit scale and the storage capacity.

  The present invention has been made in view of such a situation, and a general purpose thereof is an encoding device, a decoding device, and a signal processing device capable of improving DC-free characteristics while satisfying a run length restriction with a smaller circuit scale. An encoding method and a storage system are provided.

  In order to solve the above problems, an encoding device according to an aspect of the present invention includes a first run-length limited encoding unit, a signal processing unit, a second run-length limited encoding unit, and a DC component removal encoding unit. And comprising. The first run length limited encoding unit generates a first encoded sequence by subjecting the digital signal sequence to run length limited encoding. The signal processing unit performs predetermined signal processing on the digital signal sequence without changing the number of bits included in the digital signal sequence. The second run-length limited encoding unit generates a second encoded sequence by performing run-length limited encoding on the digital signal sequence that has been subjected to predetermined signal processing by the signal processing unit. The direct current component removal coding unit is one of the first coded sequence generated by the first run length limited coding unit and the second coded sequence generated by the second run length limited coding unit. Select one to output.

  Here, the “DC component removal coding unit” includes a circuit that removes or reduces a DC component of an input sequence, and a circuit that outputs a sequence having a high DC-free property. Further, the “first run length limited encoding unit” and the “second run length limited encoding unit” may be run length limited encoding circuits having the same properties. Further, in the case of run-length limited encoding circuits having the same properties, the “first run-length limited encoding unit” and the “second run-length limited encoding unit” are each provided with one run-length limited encoding circuit. You may implement | achieve by performing by division | segmentation.

  According to this aspect, since run-length limited encoding is performed on two different sequences, two completely different encoded sequences can be obtained. By executing predetermined signal processing so as not to increase the number of bits included in a sequence to be subjected to run-length limited encoding, an encoded sequence can be obtained without reducing the overall coding rate. Since the two encoded sequences are completely different, it is a more preferable option in selecting an encoded sequence having a high DC-free property. By selecting an encoded sequence having a high DC-free property from more preferable options, the possibility of selecting an encoded sequence having a higher DC-free property can be improved. Further, by using the same run length limited encoding circuit, the circuit configuration can be simplified and the scale can be reduced.

  The signal processing unit may perform bit inversion processing on each of a plurality of bits included in the digital signal sequence. The signal processing unit may rearrange the order of a plurality of bits included in the digital signal sequence. Further, the signal processing unit may perform a bit order rearrangement process after performing a bit inversion process on each of a plurality of bits included in the digital signal sequence. According to this aspect, different sequences can be generated without increasing the number of bits included in a sequence to be run-length limited encoding by rearranging the bit inversion process and / or the bit order. Further, since the number of bits included in the sequence does not increase, an encoded sequence can be obtained without reducing the overall encoding rate. Further, the predetermined process executed to generate the different series is a bit inversion process and / or a process of rearranging the order of the bits, whereby the predetermined process can be realized with a simple circuit configuration.

  The direct current component removal encoding unit includes an encoded sequence selection unit that selects one of the first encoded sequence and the second encoded sequence, and an encoding selected by the encoded sequence selection unit. The selection identification information generated by the selection identification information generation unit is added to any part of the selection identification information generation unit that generates selection identification information indicating a sequence and the encoded sequence selected by the encoding sequence selection unit. And an identification information adding unit. Further, the encoded sequence selection unit is already selected by the encoded sequence selection unit and a first connection unit that connects the encoded sequence already selected by the encoded sequence selection unit and the first encoded sequence. A second connecting unit that connects the encoded sequence and the second encoded sequence. The encoded sequence selection unit sets the sequence concatenated by the first concatenation unit as a new first encoded sequence, sets the sequence concatenated by the second concatenation unit as a new second encoded sequence, and selects one of the codes A conversion sequence may be selected. A first addition unit for adding a first determination bit to any part of the first encoded sequence output from the first run-length limited encoding unit, and a second output from the second run-length limited encoding unit A second adding unit that adds a second determination bit obtained by inverting the first determination bit to any part of the encoded sequence may be further provided.

  Here, “addition” includes addition, multiplication, insertion, and the like. In addition, “connecting an already selected encoded sequence and the first encoded sequence” means connecting an encoded sequence selected in the past and a sequence that is currently a candidate for selection, etc. including. According to this aspect, by adding information indicating that any of the encoded sequences has been selected to the encoded sequence, the selected encoded sequence can be easily determined on the decoding side.

  The encoded sequence selection unit may include a first ratio calculation unit, a second ratio calculation unit, and a selection output unit. The first ratio calculation unit includes a bit indicating 0 and 1 among a plurality of bits generated by the first run length limited encoding unit or included in the first encoded sequence concatenated by the first concatenation unit The ratio with the bit indicating is calculated. The second ratio calculation unit calculates a bit indicating 0 and 1 out of a plurality of bits included in the second encoded sequence generated by the second run length limited encoding unit or concatenated by the second concatenation unit. Calculate the ratio to the indicated bit. The selection output unit selects and outputs an encoded sequence corresponding to a ratio closer to 50% of the ratio calculated by the first ratio calculation unit and the ratio calculated by the second ratio calculation unit. . According to this aspect, an encoded sequence having a high DC-free property can be selected by selecting the one where the ratio between the bit indicating 0 and the bit indicating 1 is close to 50%.

  The encoded sequence selection unit may include a first summation unit, a second summation unit, an encoded sequence detection unit, and a selection output unit. The first summation unit generates a first summation value by summing a plurality of bits included in the first encoded sequence generated by the first run length limited encoding unit or concatenated by the first concatenation unit. To do. The second summation unit generates a second summation value by summing a plurality of bits included in the second encoded sequence generated by the second run length limited encoding unit or concatenated by the second concatenation unit. To do. The coded sequence detection unit compares the absolute value of the first sum value generated by the first summation unit with the absolute value of the second sum value generated by the second summation unit, and compares the absolute value of the first summation value with the first summation sequence. And an encoded sequence corresponding to the smaller sum of the second encoded sequences is detected. The selection output unit selects and outputs the encoded sequence detected by the sequence detection unit from the first encoded sequence and the second encoded sequence.

  Here, the “summed value” includes adding bits included in the series. In addition, “a plurality of bits included in a sequence” includes a bit indicating 0 or 1 and the like, and a bit when a bit indicating 0 is replaced with +1 and a bit indicating 1 is replaced with −1. Including. According to this aspect, a plurality of bits included in the encoded sequence are added together, and a sequence corresponding to a smaller combined value is selected, so that an encoded sequence having a high DC-free property can be selected.

  The encoded sequence selection unit includes a first mobile addition unit, a first maximum value detection unit, a second mobile addition unit, a second maximum value detection unit, an encoded sequence detection unit, and a selection output unit. You may have. The first mobile adder is configured to move and add a plurality of bits included in the first encoded sequence generated by the first run length limited encoding unit or concatenated by the first concatenation unit. The same number of first moving addition values as bits are generated. The first maximum value detection unit detects a maximum value among the plurality of first movement addition values generated by the first movement addition unit. The second moving addition unit moves and adds a plurality of bits included in the second encoded sequence generated by the second run length limited encoding unit or concatenated by the second concatenating unit. As many second moving addition values as the number of bits are generated. The second maximum value detection unit detects a maximum value among the plurality of second movement addition values generated by the second movement addition unit. The encoded sequence detection unit compares the maximum value detected by the first maximum value detection unit with the maximum value detected by the second maximum value detection unit, and compares the first encoded sequence and the second encoded sequence. The encoded sequence corresponding to the smaller maximum value is detected. The selection output unit selects and outputs the encoded sequence detected by the sequence detection unit from the first encoded sequence and the second encoded sequence.

  Here, “moving and adding” includes moving and adding, and calculating an absolute value. According to this aspect, by selecting a sequence using the maximum value among the results of moving and adding a plurality of bits included in the encoded sequence, an encoded sequence having a high DC-free property can be selected.

  Another aspect of the present invention is a decoding device. The apparatus includes an input unit, a determination bit acquisition unit, a run length limited decoding unit, and a signal processing unit. The input unit inputs an encoded sequence to which a predetermined determination bit is added. The determination bit acquisition unit acquires a predetermined determination bit added to the encoded sequence input by the input unit. The run length limited decoding unit generates a digital signal sequence by performing run length limited decoding on the encoded sequence input by the input unit. The signal processing unit performs bit inversion on each of a plurality of bits included in the digital signal sequence in accordance with the determination bit acquired by the determination bit acquisition unit with respect to the digital signal sequence generated by the run length limited decoding unit. Either the process of outputting or the process of outputting a plurality of bits included in the digital signal series as they are is executed. Further, the signal processing unit may execute a process of changing the order of the plurality of bits included in the digital signal sequence, instead of the process of performing bit inversion on each of the plurality of bits included in the digital signal sequence. . According to this aspect, the original digital signal sequence can be decoded by executing a process corresponding to the DC-free encoding executed on the encoding side.

  Yet another embodiment of the present invention is a signal processing device. This apparatus is a signal processing apparatus including an encoding unit and a decoding unit. The encoding unit includes a first run length limited encoding unit, a first signal processing unit, a second run length limited encoding unit, a first addition unit, a second addition unit, and a DC component removal encoding unit. And having. The first run length limited encoding unit generates a first encoded sequence by subjecting the digital signal sequence to run length limited encoding. The first signal processing unit performs bit inversion processing on each of the plurality of bits included in the digital signal sequence without changing the number of the plurality of bits included in the digital signal sequence. The second run-length limited encoding unit generates a second encoded sequence by performing run-length limited encoding on the digital signal sequence that has been subjected to bit inversion processing by the signal processing unit. The first addition unit adds a first determination bit to any part of the first encoded sequence output from the first run length limited encoding unit. The second adding unit adds a second determination bit obtained by inverting the first determination bit to any location of the second encoded sequence output from the second run length limited encoding unit. The direct current component removal encoding unit includes a first encoded sequence to which the first determination bit is added by the first addition unit and a second encoded sequence to which the second determination bit is added by the second addition unit, Either one is selected and output. The decoding unit includes an input unit, a determination bit acquisition unit, a run length limited decoding unit, and a second signal processing unit. The input unit inputs an encoded sequence to which either the first determination bit or the second determination bit is added. The determination bit acquisition unit acquires a determination bit of either the first determination bit or the second determination bit added to the encoded sequence input by the input unit. The run-length limited decoding unit generates a decoded signal sequence by performing run-length limited decoding on the encoded sequence input by the input unit. When the determination bit acquired by the determination bit acquisition unit is the first determination bit, the second signal processing unit outputs the digital signal sequence generated by the run length limited decoding unit as it is. In addition, when the determination bit acquired by the determination bit acquisition unit is the second determination bit, the second signal processing unit performs bit processing on a plurality of bits included in the decoded signal sequence generated by the run-length limited decoding unit. A signal sequence generated by executing the inversion process is output.

  According to this aspect, since run-length limited encoding is performed on two different sequences, two completely different encoded sequences can be obtained. By executing predetermined signal processing so as not to increase the number of bits included in a sequence to be subjected to run-length limited encoding, an encoded sequence can be obtained without reducing the overall coding rate. Since the two encoded sequences are completely different, it is a more preferable option in selecting an encoded sequence having a high DC-free property. By selecting an encoded sequence having a high DC-free property from more preferable options, the possibility of selecting an encoded sequence having a higher DC-free property can be improved. In addition, on the decoding side, the original digital signal sequence can be decoded by executing processing corresponding to the DC-free encoding executed on the encoding side.

  Yet another embodiment of the present invention is a storage system. This storage system is a signal storage system including a write channel for writing data to the storage device and a read channel for reading data stored in the storage device. The write channel includes a first encoding unit that performs run-length encoding of data, and a second encoding that encodes the data encoded by the first encoding unit using a low-density parity check code And a writing unit for writing the data encoded by the second encoding unit to the storage device. The read channel includes an input unit that inputs an analog signal output from the storage device, an analog-digital conversion unit that converts the analog signal input from the input unit into a digital signal, and an analog-digital conversion unit. A soft output detector that calculates the likelihood of a digital signal and outputs a soft decision value; a first decoder corresponding to a second encoder that decodes data output from the soft output detector; A second decoding unit corresponding to the first encoding unit, which decodes the data decoded by the first decoding unit. The first encoding unit includes: a first run-length limited encoding unit that generates a first encoded sequence by performing run-length limited encoding on the digital signal sequence; and a number of bits included in the digital signal sequence The signal processing unit that executes predetermined signal processing on the digital signal sequence without changing the signal, and the run-length limited encoding of the digital signal sequence that has been subjected to predetermined signal processing by the signal processing unit A second run-length limited encoding unit that generates an encoded sequence; a first encoded sequence generated by the first run-length limited encoding unit; and a second code generated by the second run-length limited encoding unit A direct-current component removal coding unit that selects and outputs one of the coded sequences. The second decoding unit includes a run-length limited decoding unit that generates a digital signal sequence by performing run-length limited decoding on the data decoded by the first decoding unit, and a digital signal sequence generated by the run-length limited decoding unit On the other hand, according to the selection in the DC component removal coding unit, the process of outputting each bit of the plurality of bits included in the digital signal sequence by bit inversion, or outputting the plurality of bits included in the digital signal sequence as they are A signal processing unit that executes any one of the processes. According to this aspect, the storage system can be accessed at higher speed by executing the encoding process with high DC-free property.

  Yet another embodiment of the present invention is also a storage system. The storage system further includes a storage device that stores data, and a control unit that controls writing to the storage device and reading from the storage device. The read channel reads data stored in the storage device in accordance with an instruction from the control unit, and the write channel writes encoded data in the storage device in accordance with an instruction from the control unit. According to this aspect, the storage system can be accessed at higher speed by executing the encoding process with high DC-free property.

  Yet another embodiment of the present invention is an encoding device. This device may be an integrated device, and the device may be integrated on a single semiconductor substrate. According to this aspect, encoding processing with high DC-free characteristics can be executed efficiently, and it is not necessary to install extra hardware, so that a low-scale semiconductor integrated circuit can be realized.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  According to the present invention, the DC-free characteristic can be improved with a smaller circuit scale while satisfying the run length limitation.

(First embodiment)
Before specifically describing the first embodiment, first, an outline of the storage system 100 according to the first embodiment will be described. The storage system 100 according to the first embodiment includes a hard disk controller, a magnetic disk device, and a read / write channel including a read channel and a write channel. In the light channel, run-length limited coding, DC-free coding, and LDPC coding are executed as coding. In the read channel, data detection using a Viterbi algorithm or the like and LDPC decoding are performed. In this data detection, it is known that detection accuracy deteriorates due to the presence of a DC component. Furthermore, the correction capability of LDPC decoding decreases due to the deterioration of detection accuracy. Therefore, in the first embodiment of the present invention, the configuration is such that DC-free encoding for reducing the DC component is performed before the LDPC encoding. Note that the storage system 100 according to the first embodiment is not limited to LDPC encoding, and may be configured to execute other error correction encoding schemes, for example, turbo encoding or convolutional encoding. .

  DC-free coding is realized by selecting a sequence having higher DC-free property from two different sequences. When RLL encoding having two different properties is performed in order to generate two different sequences, the circuit scale increases as the second RLL encoding circuit is required. Even in the case of an application that does not pose a problem in circuit scale, as a result of executing RLL coding having two different properties, both sequences are not always good in DC-freeness. Therefore, in the first embodiment of the present invention, the same RLL encoding is executed.

  Here, when executing the same RLL encoding, it is necessary to avoid that the sequences to be selected are the same. It is also necessary to avoid the case where there is no restricted coding sequence with good DC-free characteristics. Therefore, in the first embodiment of the present invention, an arbitrary signal sequence and two sequences after performing predetermined signal processing on an arbitrary signal sequence are targeted before RLL encoding. . Thereby, since the generated sequences are completely different, a sequence having a statistically good DC-free property can be generated. Further, by executing this predetermined signal processing without changing the number of bits of the signal sequence, a reduction in coding gain is avoided. Furthermore, since various sequences can be generated by arbitrarily changing the processing content of signal processing, the range of selection can be expanded. Therefore, it is possible to generate a sequence with better DC-free characteristics. Therefore, the first embodiment of the present invention is suitable for an application such as a hard disk where the coding rate cannot be set low. Details will be described later.

  Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of a storage system 100 according to the first embodiment of the present invention. 1 is roughly divided into a hard disk controller 1 (hereinafter abbreviated as “HDC1”), a central processing unit 2 (hereinafter abbreviated as “CPU2”), and a read / write channel 3 (hereinafter abbreviated as “CPU2”). , Abbreviated as “R / W channel 3”), voice coil motor / spindle motor control unit 4 (hereinafter abbreviated as “VCM / SPM control unit 4”), and disk enclosure 5 (hereinafter referred to as “DE5”). Abbreviated as)). In general, the HDC 1, CPU 2, R / W channel 3, and VCM / SPM control unit 4 are configured on the same substrate.

  The HDC 1 includes a main control unit 11 that controls the entire HDC 1, a data format control unit 12, an error correction coding control unit 13 (hereinafter abbreviated as “ECC control unit 13”), and a buffer RAM 14. The HDC 1 is connected to the host system via an interface unit (not shown). Further, it is connected to the DE 5 via the R / W channel 3, and transfers data between the host and the DE 5 under the control of the main control unit 11. A read reference clock (RRCK) generated by the R / W channel 3 is input to the HDC 1. The data format control unit 12 converts the data transferred from the host into a format suitable for recording on the disk medium 50, and conversely, suitable for transferring the data reproduced from the disk medium 50 to the host. Convert to format. The disk medium 50 includes, for example, a magnetic disk. The ECC control unit 13 adds redundant symbols using data to be recorded as information symbols in order to enable correction and detection of errors contained in data reproduced from the disk medium 50. The ECC control unit 13 determines whether or not an error has occurred in the reproduced data. If there is an error, the ECC control unit 13 corrects the error or detects the error. However, the number of symbols that can correct errors is limited, and is related to the length of redundant data. That is, if a large amount of redundant data is added, the format efficiency deteriorates, so that there is a trade-off with the number of error correctable symbols. When error correction is performed using Reed-Solomon (RS) code as ECC, up to (number of redundant symbols / 2) errors can be corrected. The buffer RAM 14 temporarily stores data transferred from the host and transfers it to the R / W channel 3 at an appropriate timing. On the contrary, the read data transferred from the R / W channel 3 is temporarily stored and transferred to the host at an appropriate timing after the ECC decoding process or the like is completed.

  The CPU 2 includes a flash ROM 21 (hereinafter abbreviated as “FROM 21”) and a RAM 22, and is connected to the HDC 1, the R / W channel 3, the VCM / SPM control unit 4, and the DE 5. The FROM 21 stores an operation program for the CPU 2.

  The R / W channel 3 is roughly divided into a write channel 31 and a read channel 32, and transfers data to be recorded and reproduced data to and from the HDC 1. The R / W channel 3 is connected to the DE 5 and executes transmission of a recording signal and reception of a reproduction signal. Details will be described later.

  The VCM / SPM control unit 4 controls a voice coil motor 52 (hereinafter abbreviated as “VCM52”) and a spindle motor 53 (hereinafter abbreviated as “SPM53”) in the DE 5.

  The DE 5 is connected to the R / W channel 3 and executes recording signal reception and reproduction signal transmission. The DE 5 is connected to the VCM / SPM control unit 4. The DE 5 includes a disk medium 50, a head 51, a VCM 52, an SPM 53, a preamplifier 54, and the like. In the storage system 100 of FIG. 1, it is assumed that there is one disk medium 50 and the head 51 is disposed only on one surface side of the disk medium 50. A stacked arrangement may be used. The head 51 is generally provided corresponding to each surface of the disk medium 50. The recording signal transmitted by the R / W channel 3 is supplied to the head 51 via the preamplifier 54 in the DE 5 and is recorded on the disk medium 50 by the head 51. Conversely, a signal reproduced from the disk medium 50 by the head 51 is transmitted to the R / W channel 3 via the preamplifier 54. The VCM 52 in the DE 5 moves the head 51 in the radial direction of the disk medium 50 in order to position the head 51 at a target position on the disk medium 50. The SPM 53 rotates the disk medium 50.

  Here, the R / W channel 3 will be described with reference to FIG. FIG. 2 is a diagram showing a configuration of the R / W channel 3 of FIG. The R / W channel 3 is roughly composed of a write channel 31 and a read channel 32.

  The write channel 31 includes a byte interface unit 301, a scrambler 302, a run length restriction and DC free encoding unit 303 (hereinafter abbreviated as “RLL / DC free encoding unit 303”), a low density parity check encoding unit. 304 (hereinafter abbreviated as “LDPC encoding unit 304”), a write compensation unit 305 (hereinafter abbreviated as “write pre-con unit 305”), and a driver 306.

  In the byte interface unit 301, data transferred from the HDC 1 is processed as input data. Data to be written on the medium is input from the HDC 1 in units of one sector. At this time, not only user data (512 bytes) for one sector but also ECC bytes added by the HDC 1 are input simultaneously. The data bus is normally 1 byte (8 bits) and is processed as input data by the byte interface unit 301. The scrambler 302 converts the write data into a random series. This is because the repetition of data with the same rule adversely affects the detection performance at the time of reading and prevents the error rate from deteriorating.

  The RLL / DC free encoding unit 303 is for limiting the maximum continuous length of 0. By limiting the maximum continuous length of 0, a data series suitable for the automatic gain control unit 317 (hereinafter abbreviated as “AGC317”) or the like is obtained. Furthermore, the direct current component is reduced, the data detection capability is improved, and the error correction capability is improved. Details will be described later.

  The LDPC encoding unit 304 has a role of generating a sequence including parity bits, which are redundant bits, by LDPC encoding the data sequence. LDPC encoding is performed by multiplying a k × n matrix called a generator matrix by a data sequence of length k from the left. Each element included in the parity check matrix H corresponding to this generator matrix is 0 or 1, and since the number of 1 is smaller than the number of 0, it is called a low density parity check code (Low Density Parity Check Codes). It is. By using this arrangement of 1 and 0, the LDPC iterative decoding unit can efficiently correct errors.

  The write pre-con unit 305 is a circuit that compensates for non-linear distortion due to continuous magnetization transitions on the medium. A rule necessary for compensation is detected from the write data, and the write current waveform is adjusted in advance so that the magnetization transition occurs at the correct position. The driver 306 is a driver that outputs a signal corresponding to the pseudo ECL level. The output from the driver 306 is sent to the DE 5 (not shown), sent to the head 51 through the preamplifier 54, and the write data is recorded on the disk medium 50.

  The read channel 32 includes a variable gain amplifier 311 (hereinafter abbreviated as “VGA 311”), a low-pass filter 312 (hereinafter abbreviated as “LPF 312”), an AGC 317, and an analog / digital converter 313 (hereinafter “ADC 313”). A frequency synthesizer 314, a filter 315, a soft output detection unit 320, an LDPC iterative decoding unit 322, a synchronization signal detection unit 321, a run length limited / DC free decoding unit 323 (hereinafter referred to as “RLL / DC free decoding”). Abbreviated as “portion 323”) and a descrambler 324.

  The VGA 311 and AGC 317 adjust the amplitude of the read waveform of data sent from the preamplifier 54 (not shown). The AGC 317 compares the ideal amplitude with the actual amplitude, and determines the gain to be set in the VGA 311. The LPF 312 can adjust the cutoff frequency and the boost amount, and is responsible for part of the reduction to high frequency noise and equalization to a partial response (hereinafter referred to as “PR”) waveform. The LPF 312 equalizes the PR waveform, but it is difficult to completely equalize with the analog LPF due to many factors such as fluctuations in the flying height of the head, non-uniformity of the medium, and fluctuations in the rotation of the motor. Then, equalization to the PR waveform is performed again using the filter 315 having more flexibility. The filter 315 may have a function of adaptively adjusting the tap coefficient. The frequency synthesizer 314 generates a sampling clock for the ADC 313.

  The ADC 313 is configured to directly obtain synchronous samples by AD conversion. In addition to this configuration, an asynchronous sample may be obtained by AD conversion. In this case, a zero-phase restart unit, a timing control unit, and an interpolation filter may be further provided after the ADC 313. Synchronous samples need to be obtained from asynchronous samples, and these blocks play that role. The zero phase restart unit is a block for determining an initial phase, and is used to obtain a synchronization sample as soon as possible. After determining the initial phase, the timing controller compares the ideal sample value with the actual sample value to detect a phase shift. A synchronous sample can be obtained by determining parameters of the interpolation filter using this.

  The soft output detection unit 320 is a soft output Viterbi algorithm (Soft-Output Viterbi Algorithm; hereinafter abbreviated as “SOVA”), which is a kind of Viterbi algorithm in order to avoid degradation of decoding characteristics due to intersymbol interference. Used. That is, in order to solve the problem that the interference between recorded codes increases and the decoding characteristics deteriorate as the recording density of magnetic disk devices increases in recent years, a partial response due to intersymbol interference is a method for overcoming this problem. The most likely decoding (Partial Response Maximum Like Like) (hereinafter abbreviated as “PRML”) method is used. PRML is a method for obtaining a signal sequence that maximizes the likelihood of a partial response of a reproduction signal.

  When the SOVA method is used as the soft output detection unit 320, a soft decision value is output. For example, assume that a soft decision value (−0.71, +0.18, +0.45, −0.45, −0.9) is output as the SOVA output. These values represent numerical values as to whether the possibility of being 0 or 1 is high. For example, the first “−0.71” indicates that the possibility of 1 is large, and the second “+0.18” is likely to be 0, but the possibility of 1 is small. Means no. The output of the conventional Viterbi detector is a hard value, and the output of SOVA is hard-decided. In the case of the above example, it is (1, 0, 0, 1, 1). The hard value represents only whether it is 0 or 1, and information on which is more likely is lost. For this reason, decoding performance is improved by inputting a soft decision value to the LDPC iterative decoding unit 322.

  The LDPC iterative decoding unit 322 has a role of restoring an LDPC encoded data sequence to a sequence before LDPC encoding. As a decoding method, there are mainly a sum-product decoding method and a min-sum decoding method. The sum-product decoding method is advantageous in terms of decoding performance, but the min-sum decoding method is realized by hardware. With the feature that is easy. In an actual decoding operation using an LDPC code, very good decoding performance can be obtained by repeatedly decoding between the soft output detector 320 and the LDPC iterative decoder 322. For this reason, a configuration is actually required in which a plurality of stages of software output detection units 320 and LDPC iterative decoding units 322 are arranged. The synchronization signal detection unit 321 has a role of detecting a synchronization signal (Sync Mark) added to the head of data and recognizing the head position of the data.

  The RLL / DC free decoding unit 323 performs the reverse operation of the RLL / DC free encoding unit 303 of the write channel 31 on the data output from the LDPC iterative decoding unit 322, and restores the original data series. Details will be described later.

  The descrambler 324 performs the reverse operation of the scrambler 302 of the write channel 31 to restore the original data series. The data generated here is transferred to the HDC 1.

  Here, “DC free” will be described. FIGS. 3A to 3B are diagrams showing examples of DC-free characteristics according to the first embodiment of the present invention. FIG. 3A is a diagram illustrating an example of the distribution of soft decision values when DC is free and when DC is not. The horizontal axis represents the number, and the vertical axis represents the soft decision value. The vertical axis is an axis including ± 0 on the center and including both positive and negative soft decision values. A first characteristic 200 indicated by a solid line indicates a distribution in the case of DC free. A second characteristic 300 indicated by a broken line shows an example of distribution when DC is not free. As described above, “DC free” indicates that the ratio of the number of 0 and 1 bits included in the sequence is 50%. In other words, as shown in the first characteristic 200 of FIG. 3A, in the distribution of soft decision values in the LDPC iterative decoding unit 322 of FIG. It means that the amount is small. On the other hand, when not DC-free, for example, as shown in the second characteristic 300 of FIG. 3A, in the distribution of the soft decision value, the distribution amount near ± 0 is increased.

  FIG. 3B is a diagram showing an example of bit error rate characteristics when the DC is free and when it is not. The horizontal axis represents a signal-to-noise ratio (Signal to Noise Ratio), and the vertical axis represents a bit error rate (Bit Error Rate). A third characteristic 210 indicated by a solid line indicates a bit error rate characteristic in the case of DC free. A fourth characteristic 310 indicated by a broken line indicates a bit error rate characteristic when the DC is not free. As shown in the figure, the bit error rate is worse in the case where DC is not free than in the case where DC is free.

  FIG. 4 is a diagram illustrating a configuration example of the RLL / DC free encoding unit 303 in FIG. The RLL / DC free encoding unit 303 includes a first RLL encoding unit 60, a first signal processing unit 62, a second RLL encoding unit 64, and a DC component removal encoding unit 66.

  The first RLL encoding unit 60 generates a first encoded sequence by subjecting the digital signal sequence output from the scrambler 302 to run-length limited encoding. The first signal processing unit 62 performs predetermined signal processing on the digital signal sequence without changing the number of bits included in the digital signal sequence output from the scrambler 302. The predetermined signal processing may be any processing as long as the number of bits included in the digital signal sequence is not changed. For example, a process of executing a bit inversion process for each of a plurality of bits included in the digital signal sequence may be used. Further, the order of a plurality of bits included in the digital signal sequence may be rearranged. Also, both bit inversion processing and bit order rearrangement processing may be performed. The second RLL encoding unit 64 generates a second encoded sequence by subjecting the digital signal sequence, which has been subjected to predetermined signal processing by the signal processing unit output from the first signal processing unit 62, to run-length limited encoding. To do. The DC component removal encoding unit 66 has a high DC-free property among the first encoded sequence generated by the first RLL encoding unit 60 and the second encoded sequence generated by the second RLL encoding unit 64. , Select either one and output.

  This will be described using a specific example. When the digital signal sequence to be processed is composed of 300 bits, the RLL / DC-free encoding unit 303 processes 30 bits as one set and is divided into 10 times. Here, when the encoding rate of the first RLL encoding unit 60 and the second RLL encoding unit 64 is 30/31, the output per one time output from the first RLL encoding unit 60 and the second RLL encoding unit 64, respectively. The number of bits in the series is 31 bits.

  FIG. 5 is a diagram illustrating a configuration example of the DC component removal coding unit 66 of FIG. The DC component removal encoding unit 66 includes an encoded sequence selection unit 74, a selection identification information generation unit 76, and an identification information addition unit 78. The encoded sequence selection unit 74 is one of the first encoded sequence generated by the first RLL encoding unit 60 and the second encoded sequence generated by the second RLL encoding unit 64. Select. The selection identification information generation unit 76 generates selection identification information indicating the encoded sequence selected by the encoded sequence selection unit 74. The identification information adding unit 78 adds the selection identification information generated by the selection identification information generating unit 76 to any part of the encoded sequence selected by the encoded sequence selecting unit 74.

  This will be specifically described. When the first encoded sequence is selected by the encoded sequence selection unit 74, the selection identification information added to the first encoded sequence by the identification information adding unit 78 is “0”. On the other hand, when the second encoded sequence is selected by the encoded sequence selection unit 74, the selection identification information added to the first encoded sequence by the identification information adding unit 78 is “1”. In other words, the first encoded sequence to which selection identification information “0” is added or the second encoded sequence to which selection identification information “1” is added is output to LDPC encoding section 304. The part to which the selection identification information is added by the identification information adding unit 78 may be an arbitrary fixed part in the encoded sequence, and may be added to the end of the encoded sequence, for example. Although details will be described later, the selection identification information added here is a determination bit, and an appropriate decoding process is realized by analyzing the position of the determination bit added on the decoding side and the content of the determination bit. The Rukoto. In the specific example described above, 1-bit selection identification information is added to a 31-bit encoded sequence at a time, and a total of 32-bit sequences are output. That is, the coding rate in the entire RLL / DC free coding unit 303 is 30/32.

  The encoded sequence selection unit 74 may include a first connection unit and a second connection unit (not shown). The first concatenation unit concatenates the encoded sequence already selected by the encoded sequence selection unit 74 and the first encoded sequence. The second concatenation unit concatenates the encoded sequence already selected by the encoded sequence selection unit 74 and the second encoded sequence. In this case, the encoded sequence selection unit 74 sets the sequence connected by the first connecting unit as a new first encoded sequence, sets the sequence connected by the second connecting unit as a new second encoded sequence, Either one of the encoded sequences may be selected. In other words, the encoded sequence selection unit 74 makes a selection determination for a combination of the encoded sequence selected in the past and the encoded sequence that is currently selected as a candidate for selection in the long section. DC-free characteristics can be improved.

  6A to 6C are diagrams illustrating first to third configuration examples of the encoded sequence selection unit 74 in FIG. FIG. 6A is a diagram illustrating a first configuration example of the encoded sequence selection unit 74 in FIG. The encoded sequence selection unit 74 in the first configuration includes a first ratio calculation unit 80, a second ratio calculation unit 82, and a selection output unit 84.

  The first ratio calculation unit 80 calculates a ratio between a bit indicating 0 and a bit indicating 1 among a plurality of bits included in the first encoded sequence. The second ratio calculation unit 82 calculates a ratio between a bit indicating 0 and a bit indicating 1 among a plurality of bits included in the second encoded sequence. The selection output unit 84 selects an encoded sequence corresponding to a ratio closer to 50% of the ratio calculated by the first ratio calculation unit 80 and the ratio calculated by the second ratio calculation unit 82. Output.

This will be described using a specific example. First, it is assumed that 31-bit encoded sequences are output from the first RLL encoding unit 60 and the second RLL encoding unit 64 at time t = 1. In this case, the first ratio calculator 80 and the second ratio calculator 82 analyze the bits included in the respective encoded sequences and calculate the ratio. Here, among the bits included in the encoded sequence input to the first ratio calculation unit 80, when the bit indicating 0 is 14 bits and the bit indicating 1 is 17 bits, the ratio is the first ratio calculation unit 80 is calculated as follows.
Ratio _{t = 1} = (number of bits indicating 0 + 1) / (number of bits of coded sequence + 1) = (14 + 1) / (31 + 1) ≈46.9%

In addition, among the bits included in the encoded sequence input to the second ratio calculation unit 82, when the bit indicating 0 is 12 bits and the bit indicating 1 is 19 bits, the ratio is the second ratio calculation unit 82. Is calculated as follows. In this case, since the ratio of the first encoded sequence is closer to 50%, the first encoded sequence is selected by the selection output unit 84 at t = 1. In addition, the number of bits “14” indicating 0 according to the selected first encoded sequence is stored. In the numerators on the right side of the above formula and the following formula, “1” and “0” are added because the selection identification information is assumed to be “0” and “1”, respectively. . In addition, in the denominator on the right side of the above formula and the formula below, “1” is added in order to calculate the ratio of the number of 0s in the series including the selection identification information.
Ratio _{t = 1} = (number of bits indicating 0 + 0) / (number of bits of coded sequence + 1) = 12 / (31 + 1) = 37.5%

Next, it is assumed that a 31-bit encoded sequence is output from the first RLL encoding unit 60 and the second RLL encoding unit 64 at t = 2 as in the case of t = 1. Here, among the bits included in the encoded sequence input to the first ratio calculation unit 80, when the bit indicating 0 is 11 bits and the bit indicating 1 is 20 bits, the ratio is calculated as follows. Is done.
Ratio _{t = 2} = (number of bits indicating 0 + 1) / ((number of bits of coded sequence + 1) × t) = (14 + 1 + 111 + 1) / ((31 + 1) × 2) ≈42.2%

  Unlike the case of t = 1, the first ratio calculation unit 80 is a sequence in which the encoded sequence selected at t = 1 and the first encoded sequence at t = 2 are connected by the first connecting unit. Calculate the ratio for. That is, the number “14 + 1” of bits indicating 0 in the first encoded sequence selected at t = 1, and the number “11 + 1” of bits indicating 0 in the first encoded sequence at t = 2. It will be added in the numerator of the formula. The denominator is the number of bits for two sets of encoded sequences.

In addition, among the bits included in the encoded sequence input to the second ratio calculation unit 82, when the bit indicating 0 is 17 bits and the bit indicating 1 is 14 bits, the second ratio calculation unit 82 The ratio is calculated as follows. In this case, since the ratio of the second encoded sequence is closer to 50%, the second encoded sequence is selected by the selection output unit 84 at t = 2.
Ratio _{t = 2} = (number of bits indicating 0 + 0) / ((number of bits of coded sequence + 1) × t) = (14 + 1 + 17 + 0) / ((31 + 1) × 2) = 50.0%

Similarly, the ratio is calculated after t = 3. Here, the ratio at t = k is expressed as follows. However, k is an integer of 1 or more. Nbit (m) indicates the number of bits indicating 0 among the bits included in the encoded sequence selected at t = m. Here, Nbit (k) indicates the number of bits indicating 0 among the bits included in the encoded sequence for which the ratio is calculated. It is assumed that selection identification information is also included in the encoded sequence for which the ratio is calculated.
Ratio ^{_{t = k = Σ k m =}} 1 Nbit (m) / (32 × k)

  FIG. 6B is a diagram illustrating a second configuration example of the encoded sequence selection unit 74 in FIG. The encoded sequence selection unit 74 in the second configuration includes a first summation unit 86, a second summation unit 88, and a selection output unit 84. The first summation unit 86 sums a plurality of bits included in the first encoded sequence to generate a first sum value. The second summing unit 88 sums a plurality of bits included in the second encoded sequence to generate a second summed value. The encoded sequence detection unit compares the first added value generated by the first adder 86 with the second added value generated by the second adder 88, and compares the first encoded sequence and the second code. An encoded sequence corresponding to the smaller sum of the converted sequences is detected. The selection output unit 84 selects and outputs the encoded sequence detected by the sequence detection unit from the first encoded sequence and the second encoded sequence.

  This will be described using a specific example. First, it is assumed that a 31-bit encoded sequence is output from each of the first RLL encoding unit 60 and the second RLL encoding unit 64 at t = 1. In this case, the first summing unit 86 and the second summing unit 88 sum the bits included in the respective encoded sequences. In the summation, 0 may be replaced with “+1” and 1 may be replaced with “−1” for total. By summing in this way, when the number of bits indicating 0 and 1 is equal, the sum is 0. Therefore, the selection output unit 84 may select an encoded sequence having a sum value close to 0, for example, an encoded sequence having a small absolute value of the sum value. This method is also called continuous digital summation (hereinafter abbreviated as “RDS”).

Here, at t = 1, out of 31 bits included in the encoded sequence input to the first summing unit 86, the bit indicating 0 is 14 bits, and the bit indicating 1 is 17 bits. Is calculated as follows. Note that “1” is added in the first term on the right side because the selection identification information is assumed to be zero.
RDS _abs = | (14 + 1) × (+1) + 17 × (−1) | = 2

Further, among the bits included in the encoded sequence input to the second summing unit 88, when the bit indicating 0 is 12 bits and the bit indicating 1 is 19 bits, the ratio is calculated as follows: . In this case, since the RDS of the first encoded sequence is smaller, the first encoded sequence is selected by the selection output unit 84 at t = 1. Here, the RDS for the first coded sequence before calculating the absolute value is stored as “RDS ₁ = −2”. Note that “1” is added in the second term on the right side because the selection identification information is assumed to be 1.
RDS _abs = | 12 × (+1) + (19 + 1) × (−1) | = 6

Next, at t = 2, as in the case of t = 1, it is assumed that 31-bit encoded sequences are output from the first RLL encoding unit 60 and the second RLL encoding unit 64, respectively. Here, among the bits included in the encoded sequence input to the first summing unit 86, when the bit indicating 0 is 11 bits and the bit indicating 1 is 20 bits, the RDS is calculated as follows. The Unlike t = 1, at t = 2, the number of bits related to the encoded sequence selected at t = 1 is taken into consideration.
RDS _abs = | RDS ₁ + (11 + 1) × (+1) + 20 × (−1) | = | −2 + (− 8) | = 10

In addition, among the bits included in the encoded sequence input to the second summing unit 88, when the bit indicating 0 is 17 bits and the bit indicating 1 is 14 bits, the ratio is calculated as follows. . In this case, since the RDS of the second encoded sequence is smaller, the first encoded sequence is selected by the selection output unit 84 at t = 2. Further, RDS ₂ = 0 is stored.
RDS _abs = | RDS ₁ + 17 × (+1) + (14 + 1) × (−1) | = | −2 + (+ 2) | = 0

Similarly, RDS _abs is calculated after t = 3. Here, RDS _abs (k) at t = k is expressed as follows. However, t is an integer of 1 or more. Nbit0 (m) indicates the number of bits indicating 0 among the bits included in the encoded sequence selected at t = m and the selection identification information. Nbit1 (m) indicates the number of bits indicating 1 out of the bits included in the encoded sequence selected at t = m and the selection identification information. However, Nbit0 (k) and Nbit1 (k) indicate the number of bits indicating 0 and the number of bits indicating 1 respectively, among the bits included in the encoded sequence for which the sum is calculated.
RDS _abs (k) = | RDS (k−1) + Nbit0 (k) × (+1) + Nbit1 (k) × (−1) | = | Σ ^k _{m = 1} (Nbit0 (m) × (+1) + Nbit1 (m) ) × (-1)) |

  The operation of the coded sequence selection unit 74 described above is characterized in that the movement calculation process is performed between past successive times while the interval calculation process is performed at a certain time. Thus, by combining the section process and the movement process, the DC-free property is improved in the long section, for example, the entire 300-bit sequence.

  In addition, the summation process in the first summation unit 86 and the second summation unit 88 may add up the bits indicating 0 or 1 included in the encoded sequence as they are. In this case, in the selection output unit 84, the encoded sequence corresponding to the sum closer to the half of the number of encoded sequences is selected.

  FIG. 6C is a diagram illustrating a third configuration example of the encoded sequence selection unit 74 in FIG. The encoded sequence selection unit 74 in the third configuration includes a first mobile addition unit 90, a first maximum value detection unit 92, a second mobile addition unit 94, a second maximum value detection unit 96, and a selection output unit. 84. The first moving addition unit 90 generates the same number of first moving addition values as the plurality of bits by calculating the moving addition of the plurality of bits included in the first encoded sequence. The first maximum value detection unit 92 detects the maximum value among the plurality of first movement addition values generated by the first movement addition unit 90. The second moving addition unit 94 generates the same number of second moving addition values as the plurality of bits by moving and adding the plurality of bits included in the second encoded sequence. The second maximum value detector 96 detects the maximum value among the plurality of second movement addition values generated by the second movement addition unit 94. The encoded sequence detection unit compares the maximum value detected by the first maximum value detection unit 92 with the maximum value detected by the second maximum value detection unit 96, and compares the first encoded sequence and the second code. An encoded sequence corresponding to the smaller maximum value is detected from the encoded sequences. The selection output unit 84 selects and outputs the encoded sequence detected by the sequence detection unit from the first encoded sequence and the second encoded sequence.

  As in the second configuration example, the third configuration example of the encoded sequence selection unit 74 is obtained by calculating the RDS of each encoded sequence in the first mobile addition unit 90 and the second mobile addition unit 94. The selection output unit 84 selects an encoded sequence. In the third configuration example, an encoded sequence that is close to 0 in consideration of only the final calculated value of the 32-bit RDS calculation is selected in that the encoded sequence having the smaller maximum value during the calculation of the 32-bit RDS is selected. This is different from the second configuration example in which is selected. In other words, in the third configuration example, the selection process is performed by the movement calculation in both the predetermined section and the plurality of sections. By taking such an aspect, it is possible to select a sequence having good DC-free properties even in the middle of the section.

Here, the “maximum value during calculation of RDS” is derived as follows for each time t. However, Min {y (0), y (1)} indicates a function that selects a smaller value and outputs the number of the selected sequence. For example, when y (0)> y (1), S (t) is 1. Further, max {x} indicates a function for detecting the maximum value of x. K represents a value in the range of 32 × (t−1) +1 to 32 × t. Bit (m, j) indicates +1 when the m-th bit is 0 in the j-th encoded sequence, and indicates -1 when it is 1.
S (t) = Min {MaxRDS (1), MaxRDS (2)}
MaxRDS (1) = max {RDS (k, 1)}
MaxRDS (2) = max {RDS (k, 2)}
RDS (k, 1) = | Σ k m = 1 Bit (m, 1) |
RDS (k, 2) = | Σ k m = 1 Bit (m, 2) |

Bit (m, 1) and Bit (m, 2) are calculated by rewriting the bits related to the selected sequence as follows each time t increases, and then calculating the above formulas and the like. Become.
Bit (m, 1) = Bit (m, 2) = Bit (m, S (t−1)): m = (t−1) × 32 + 1 to t × 32, t ≠ 1

Here, the operation of the third configuration example of the encoded sequence selection unit 74 illustrated in FIG. 6C is compared with the operation of the second configuration example of the encoded sequence selection unit 74 illustrated in FIG. . FIG. 7 is a diagram illustrating a difference in operation of the coded sequence selection unit 74 illustrated in FIG. 6B and FIG. 6C, respectively. The horizontal axis represents time, and the vertical axis represents RDS. Here, 400A indicates the transition of RDS in the first encoded sequence. 400B indicates the transition of RDS in the second encoded sequence. In the second configuration example of the encoded sequence selection unit 74 shown in FIG. 6B, RDS _A and RDS _B which are final values of the RDS interval calculation are compared, and the smaller encoded sequence is selected. . In FIG. 7, since RDS _A <RDS _B , the selection output unit 84 selects the first encoded sequence. On the other hand, in the third configuration example of the encoded sequence selection unit 74 shown in FIG. 6C, the RDS in each bit, that is, the maximum value among the absolute values after the 32 bits are sequentially subjected to the movement calculation process. Compare the values and select the smaller encoded sequence. In FIG. 7, MaxA is the maximum value for the first encoded sequence, and MaxB is the maximum value for the second encoded sequence. Here, since MaxA> MaxB, the selection output unit 84 selects the second encoded sequence. Even when any configuration example is applied to the encoded sequence selection unit 74, an encoded sequence having a high DC-free property can be selected.

  FIG. 8 is a diagram illustrating a configuration example of the RLL / DC free decoding unit 323 of FIG. The RLL / DC free decoding unit 323 includes a determination bit acquisition unit 68, an RLL decoding unit 70, and a second signal processing unit 72. The determination bit acquisition unit 68 acquires a predetermined determination bit added to the encoded sequence input by the LDPC iterative decoding unit 322. The RLL decoding unit 70 generates a digital signal sequence by subjecting the encoded sequence input by the LDPC iterative decoding unit 322 to run-length limited decoding. The second signal processing unit 72 performs a predetermined signal executed by the first signal processing unit 62 on the digital signal sequence generated by the RLL decoding unit 70 according to the determination bit acquired by the determination bit acquisition unit 68. The signal processing that is the reverse of the processing is executed and output. For example, in the first signal processing unit 62 of FIG. 4, when the bit inversion process and / or the process of changing the order of bits is performed, the bit inversion process and / or the exchanged series is changed back to the original. Process. Or according to the determination bit acquired by the determination bit acquisition part 68, the 2nd signal processing part 72 performs the process which outputs the some bit contained in a digital signal series as it is.

  These configurations described above can be realized in hardware by a CPU, memory, or other LSI of an arbitrary computer, and in software by a program having a communication function loaded in the memory. Here, functional blocks realized by the cooperation are depicted. Accordingly, those skilled in the art will understand that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof.

  According to the first embodiment, by executing the same RLL encoding, it is possible to generate a sequence having a good DC-free property without increasing the circuit scale. Since an arbitrary signal sequence and two sequences after performing predetermined signal processing on an arbitrary signal sequence before RLL encoding are processed, the generated sequences are completely different. A sequence having good DC-free property can be generated. Further, by executing this predetermined signal processing without changing the number of bits of the signal sequence, a decrease in coding gain can be avoided. Furthermore, since various sequences can be generated by arbitrarily changing the processing content of signal processing, the range of selection can be expanded. Therefore, it is possible to generate a sequence with better DC-free characteristics. Therefore, it is suitable for an application such as a hard disk where the coding rate cannot be set low. Further, by using the same RLL encoding circuit, the circuit configuration can be simplified and the scale can be reduced.

  In addition, different sequences can be generated without increasing the number of bits included in the sequence to be run-length limited encoding by rearranging the bit order and / or rearranging the bit order. Further, since the number of bits included in the sequence does not increase, an encoded sequence can be obtained without reducing the overall encoding rate. Further, the predetermined process executed to generate the different series is a bit inversion process and / or a process of rearranging the order of the bits, whereby the predetermined process can be realized with a simple circuit configuration. Further, by adding information indicating that any of the encoded sequences has been selected to the encoded sequence, the selected encoded sequence can be easily discriminated on the decoding side.

  The encoded sequence selection unit 74 performs a selection determination on a concatenation of an encoded sequence selected in the past and an encoded sequence that is a candidate for current selection. The characteristics can be improved. In the encoded sequence selection unit 74, the RDS is calculated by combining the interval process and the movement process, whereby the DC-free property can be improved in the long interval, for example, the entire 300-bit sequence. Also, by selecting the one where the ratio of the bit indicating 0 and the bit indicating 1 is close to 50%, it is possible to select an encoded sequence having a high DC-free property. In addition, by adding a plurality of bits included in the encoded sequence and selecting a sequence corresponding to a smaller combined value, an encoded sequence having a high DC-free property can be selected. Further, by selecting a sequence using the maximum value among the results obtained by moving and adding a plurality of bits included in the encoded sequence, an encoded sequence having a high DC-free property can be selected. The original digital signal sequence can be decoded by executing a process corresponding to the DC-free encoding executed on the encoding side. By executing the encoding process with high DC-free property, the storage system can be accessed at higher speed. Moreover, since it is not necessary to install extra hardware, a low-scale semiconductor integrated circuit can be realized.

  In the first embodiment, the R / W channel 3 may be integrated on a single semiconductor substrate. Further, the coding sequence selection unit 74 of the first embodiment has been described as the interval calculation process or the movement calculation process. However, the present invention is not limited to this, and an encoded sequence having a high DC-free property may be selected by performing section average processing or moving average processing. Even in this case, the same effect can be obtained. In the configuration of the RLL / DC free encoding unit 303, the first signal processing unit 62 that performs predetermined signal processing is used to generate two different signal sequences. However, the present invention is not limited to this, and a plurality of signal sequences may be generated using a plurality of signal processing units. For example, a signal processing device that executes a bit inversion process, a process for changing the order of bits, a bit inversion process, and a process for changing the order of bits may be provided. In this case, an appropriate decoding process can be realized on the decoding side by setting the determination bit indicating that any of the four sequences has been selected to 2 bits. Also, four different sequences can be generated, including sequences that are not subjected to signal processing. In addition, since the number of options can be increased, the possibility that a sequence having a high DC-free property is generated can be improved.

(Second Embodiment)
The second embodiment relates to an error correction encoding / decoding technique, and in particular, a signal encoding device, a signal decoding device, a signal processing device, and an error correction encoding or error correction for data stored in a storage medium, and It relates to a storage system.

  First, the background art regarding the second embodiment will be described.

  In recent years, storage devices using hard disks are becoming essential devices in various fields such as personal computers, hard disk recorders, video cameras, and mobile phones. Storage devices using a hard disk have various specifications required depending on the field to which they are applied. For example, a hard disk mounted on a personal computer is required to have high speed and large capacity. In order to improve high speed and large capacity, it is necessary to perform error correction coding with high correction capability. However, since the amount of data handled per unit time increases as the speed increases, errors per unit time also increase proportionally. Then, unless a correction method having a high error correction capability is used, the hard disk is re-read, so that the time required to access the hard disk increases and becomes a bottleneck for speeding up.

  In general, a signal sequence in which a DC component is reduced or removed (hereinafter referred to as “DC-free” or “DC-free”) is desired as a signal sequence to be subjected to error correction coding. . DC free means that the frequency is 0, that is, the spectrum in the DC component is 0. In other words, it means that the ratio of 0 and 1 is equal in a plurality of bits included in the signal sequence before modulation. By providing the signal sequence with the DC-free property, the average level of the reproduction signal obtained from the recording pattern of the modulation data stored in the storage medium is a predetermined signal sequence length regardless of the pattern of the signal sequence before modulation. The noise resistance is improved by having a constant property within the range of. That is, in a signal sequence having a low DC-free property, the detection probability decreases in data detection using the Viterbi algorithm. As a result, the correction capability in low density parity check decoding and Reed-Solomon decoding is also reduced. In general, a run-length limit code is used to ensure synchronization between sampling timing and data. The run length limited code is a coding that limits the maximum continuous length of 0 or the maximum continuous length of 1.

  Conventionally, as a method for performing run-length limited encoding while satisfying DC-freeness of a signal sequence, a plurality of encoded sequences are obtained by executing run-length limited encoding on signal sequences to which different redundant bits are added. Among them, a method for selecting a sequence having characteristics close to DC free has been proposed (for example, see Japanese Patent Application Laid-Open No. 2002-100125). In addition, a method has been proposed in which run-length limited encoding having a plurality of different properties is performed, and a sequence having characteristics close to DC-free is selected from the plurality of encoded sequences (for example, Japanese Patent Application Laid-Open No. 2004-2004). -213863).

  A problem to be solved by the second embodiment will be described.

  Under such circumstances, the present inventor has come to recognize the following problems. That is, on the encoding side, when realizing DC-free encoding by selecting a sequence having good DC-free characteristics from among a plurality of encoded sequences, the DC-free characteristics of a plurality of encoded sequences to be selected are selected. There are cases where a good coded sequence does not exist. Further, when determining the encoded sequence selected on the encoding side on the decoding side, there is a problem that errors increase due to an erroneous determination.

  The second embodiment of the present invention has been made in view of such a situation, and the general purpose thereof is a signal encoding device capable of improving the DC-free characteristic while satisfying the run length limitation with a smaller circuit scale, The object is to provide a signal decoding device, a signal processing device, and a storage system.

  Means for solving the problems in the second embodiment will be described.

  In order to solve the above-described problem, a signal encoding apparatus according to an aspect of the second embodiment includes a run-length limited encoding unit that generates a run-length encoded sequence by performing run-length limited encoding on a predetermined signal sequence. And a Reed-Solomon encoding unit that performs Reed-Solomon encoding on the run-length encoded sequence generated by the run-length limited encoding unit. The Reed-Solomon encoding unit generates a redundant sequence for generating a redundant sequence for performing Reed-Solomon encoding of the run-length encoded sequence, and adds the redundant sequence generated by the redundant sequence generating unit to the run-length encoded sequence A redundant sequence adding unit.

  Here, “addition” includes addition, multiplication, insertion, and the like. According to this aspect, by performing Reed-Solomon coding after performing run-length limited coding, the decoding side performs run-length limited decoding on the signal sequence after performing Reed-Solomon decoding. Therefore, the error correction capability can be improved.

  Another aspect of the second embodiment of the present invention is also a signal encoding device. This apparatus changes the number of bits included in a first run-length limited encoding unit that generates a first run-length encoded sequence by performing run-length limited encoding on the digital signal sequence, and a digital signal sequence. The second run length is obtained by subjecting the digital signal sequence to a signal processing unit that performs predetermined signal processing and a run length limited encoding of the digital signal sequence that has been subjected to predetermined signal processing by the signal processing unit. A second run-length limited encoding unit that generates an encoded sequence; a first run-length encoded sequence generated by the first run-length limited encoding unit; and a second run-length limited encoding unit that is generated by the second run-length limited encoding unit. A direct-current component removal coding unit that selects and outputs either one of the two-run length coded sequences and a direct-current component removal coding unit; The Reed-Solomon encoding unit that generates a redundant sequence by performing Reed-Solomon encoding on the run-length encoded sequence that has been applied, and the redundant sequence generated by the Reed-Solomon encoding unit are output by the DC component removal encoding unit. And a redundant sequence addition unit for adding to the run-length encoded sequence.

  Here, the “DC component removal coding unit” includes a circuit that removes or reduces a DC component of an input sequence, and a circuit that outputs a sequence having a high DC-free property. Further, the “first run length limited encoding unit” and the “second run length limited encoding unit” may be run length limited encoding circuits having the same properties. Further, in the case of run-length limited encoding circuits having the same properties, the “first run-length limited encoding unit” and the “second run-length limited encoding unit” are each provided with one run-length limited encoding circuit. You may implement | achieve by performing by division | segmentation.

  According to this aspect, since run-length limited encoding is performed on two different sequences, two completely different encoded sequences can be obtained. By executing predetermined signal processing so as not to increase the number of bits included in a sequence to be subjected to run-length limited encoding, an encoded sequence can be obtained without reducing the overall coding rate. Since the two encoded sequences are completely different, it is a more preferable option in selecting an encoded sequence having a high DC-free property. By selecting an encoded sequence having a high DC-free property from more preferable options, the possibility of selecting an encoded sequence having a higher DC-free property can be improved. Further, by using the same run length limited encoding circuit, the circuit configuration can be simplified and the scale can be reduced. Further, by performing Reed-Solomon coding after performing run-length limited coding, the decoding side performs run-length limited decoding on the signal sequence after performing Reed-Solomon decoding. In other words, run-length limited decoding is performed on a sequence that has been error-corrected by Reed-Solomon decoding. If it does so, the encoding sequence selected in the encoding side can be discriminate | determined correctly, and the error correction capability as a whole can be improved.

  The signal processing unit may perform bit inversion processing on each of a plurality of bits included in the digital signal sequence. The signal processing unit may rearrange the order of a plurality of bits included in the digital signal sequence. Further, the signal processing unit may perform a bit order rearrangement process after performing a bit inversion process on each of a plurality of bits included in the digital signal sequence. According to this aspect, different sequences can be generated without increasing the number of bits included in a sequence to be run-length limited encoding by rearranging the bit inversion process and / or the bit order. Further, since the number of bits included in the sequence does not increase, an encoded sequence can be obtained without reducing the overall encoding rate. Further, the predetermined process executed to generate the different series is a bit inversion process and / or a process of rearranging the order of the bits, whereby the predetermined process can be realized with a simple circuit configuration.

  The direct current component removal encoding unit includes an encoded sequence selection unit that selects one of the first encoded sequence and the second encoded sequence, and an encoding selected by the encoded sequence selection unit. The selection identification information generated by the selection identification information generation unit is added to any part of the selection identification information generation unit that generates selection identification information indicating a sequence and the encoded sequence selected by the encoding sequence selection unit. And an identification information adding unit. Further, the encoded sequence selection unit is already selected by the encoded sequence selection unit and a first connection unit that connects the encoded sequence already selected by the encoded sequence selection unit and the first encoded sequence. A second connecting unit that connects the encoded sequence and the second encoded sequence. The encoded sequence selection unit sets the sequence concatenated by the first concatenation unit as a new first encoded sequence, sets the sequence concatenated by the second concatenation unit as a new second encoded sequence, and selects one of the codes A conversion sequence may be selected. A first addition unit for adding a first determination bit to any part of the first encoded sequence output from the first run-length limited encoding unit, and a second output from the second run-length limited encoding unit A second adding unit that adds a second determination bit obtained by inverting the first determination bit to any part of the encoded sequence may be further provided.

  Here, “concatenating the already selected encoded sequence and the first encoded sequence” means connecting the encoded sequence selected in the past and the sequence currently selected as a candidate. Etc. According to this aspect, by adding information indicating that any of the encoded sequences has been selected to the encoded sequence, the selected encoded sequence can be easily determined on the decoding side.

  The encoded sequence selection unit may include a first ratio calculation unit, a second ratio calculation unit, and a selection output unit. The first ratio calculation unit includes a bit indicating 0 and 1 among a plurality of bits generated by the first run length limited encoding unit or included in the first encoded sequence concatenated by the first concatenation unit The ratio with the bit indicating is calculated. The second ratio calculation unit calculates a bit indicating 0 and 1 out of a plurality of bits included in the second encoded sequence generated by the second run length limited encoding unit or concatenated by the second concatenation unit. Calculate the ratio to the indicated bit. The selection output unit selects and outputs an encoded sequence corresponding to a ratio closer to 50% of the ratio calculated by the first ratio calculation unit and the ratio calculated by the second ratio calculation unit. . According to this aspect, an encoded sequence having a high DC-free property can be selected by selecting the one where the ratio between the bit indicating 0 and the bit indicating 1 is close to 50%.

  The encoded sequence selection unit may include a first summation unit, a second summation unit, an encoded sequence detection unit, and a selection output unit. The first summation unit generates a first summation value by summing a plurality of bits included in the first encoded sequence generated by the first run length limited encoding unit or concatenated by the first concatenation unit. To do. The second summation unit generates a second summation value by summing a plurality of bits included in the second encoded sequence generated by the second run length limited encoding unit or concatenated by the second concatenation unit. To do. The coded sequence detection unit compares the absolute value of the first sum value generated by the first summation unit with the absolute value of the second sum value generated by the second summation unit, and compares the absolute value of the first summation value with the first summation sequence. And an encoded sequence corresponding to the smaller sum of the second encoded sequences is detected. The selection output unit selects and outputs the encoded sequence detected by the sequence detection unit from the first encoded sequence and the second encoded sequence.

  Here, the “summed value” includes adding bits included in the series. In addition, “a plurality of bits included in a sequence” includes a bit indicating 0 or 1 and the like, and a bit when a bit indicating 0 is replaced with +1 and a bit indicating 1 is replaced with −1. Including. According to this aspect, a plurality of bits included in the encoded sequence are added together, and a sequence corresponding to a smaller combined value is selected, so that an encoded sequence having a high DC-free property can be selected.

  The encoded sequence selection unit includes a first mobile addition unit, a first maximum value detection unit, a second mobile addition unit, a second maximum value detection unit, an encoded sequence detection unit, and a selection output unit. You may have. The first mobile adder is configured to move and add a plurality of bits included in the first encoded sequence generated by the first run length limited encoding unit or concatenated by the first concatenation unit. The same number of first moving addition values as bits are generated. The first maximum value detection unit detects a maximum value among the plurality of first movement addition values generated by the first movement addition unit. The second moving addition unit moves and adds a plurality of bits included in the second encoded sequence generated by the second run length limited encoding unit or concatenated by the second concatenating unit. As many second moving addition values as the number of bits are generated. The second maximum value detection unit detects a maximum value among the plurality of second movement addition values generated by the second movement addition unit. The encoded sequence detection unit compares the maximum value detected by the first maximum value detection unit with the maximum value detected by the second maximum value detection unit, and compares the first encoded sequence and the second encoded sequence. The encoded sequence corresponding to the smaller maximum value is detected. The selection output unit selects and outputs the encoded sequence detected by the sequence detection unit from the first encoded sequence and the second encoded sequence.

  Here, “moving and adding” includes moving and adding, and calculating an absolute value. According to this aspect, by selecting a sequence using the maximum value among the results of moving and adding a plurality of bits included in the encoded sequence, an encoded sequence having a high DC-free property can be selected.

  The redundant sequence adding unit may include a dividing unit that divides the redundant sequence generated by the Reed-Solomon encoding unit into a plurality of sets. The group divided by the dividing unit may be added to any part of the run-length encoded sequence and to a different part for each group. The redundant sequence adding unit may add the run length encoded sequence at equal intervals for each group divided by the dividing unit. According to this aspect, the RLL of the sequence after the redundant sequence is added by distributing the redundant sequence divided into a plurality of sets to different locations at any location in the run-length encoded sequence. And DC-free characteristics can be improved. Further, by adding each group at equal intervals, it is possible to further improve the RLL property and DC-free characteristics of the sequence after the redundant sequence is added.

  The dividing unit may divide one of two or more bits included in the redundant sequence generated by the Reed-Solomon encoding unit as one set. The dividing unit may divide 2N (N is an integer of 1 or more) bits as a set among a plurality of bits included in the redundant sequence generated by the Reed-Solomon encoding unit. According to this aspect, by adding an even number of redundant sequences to the run-length encoded sequence, it is possible to further improve the RLL property of the sequence after the redundant sequence is added.

  Yet another aspect of the second embodiment of the present invention is a signal decoding apparatus. The apparatus includes: an input unit that inputs a first signal sequence into which a predetermined redundant sequence is inserted; a redundant sequence detection unit that detects an insertion position of a redundant sequence out of the first signal sequence input by the input unit; According to the insertion location detected by the redundant sequence detection unit, the redundant sequence is separated from the first signal sequence input by the input unit, and the second sequence is separated by the redundant sequence acquisition unit and the redundant sequence acquisition unit. The Reed-Solomon decoding unit that corrects the error of the second signal sequence acquired by the redundant sequence acquisition unit using the redundant bits, and the run-length limit for the second signal sequence that has been checked for errors by the Reed-Solomon decoding unit A run-length limited decoding unit that performs decoding. According to this aspect, error correction capability can be improved by performing run-length limited decoding on the signal sequence after performing Reed-Solomon decoding.

  Another aspect of the second embodiment of the present invention is also a signal decoding device. The apparatus includes an input unit, a determination bit acquisition unit, a run length limited decoding unit, and a signal processing unit. The input unit inputs an encoded sequence to which a predetermined determination bit is added. The determination bit acquisition unit acquires a predetermined determination bit added to the encoded sequence input by the input unit. The run length limited decoding unit generates a digital signal sequence by performing run length limited decoding on the encoded sequence input by the input unit. The signal processing unit performs bit inversion on each of a plurality of bits included in the digital signal sequence in accordance with the determination bit acquired by the determination bit acquisition unit with respect to the digital signal sequence generated by the run length limited decoding unit. Either the process of outputting or the process of outputting a plurality of bits included in the digital signal series as they are is executed. Further, the signal processing unit may execute a process of changing the order of the plurality of bits included in the digital signal sequence, instead of the process of performing bit inversion on each of the plurality of bits included in the digital signal sequence. . According to this aspect, the original digital signal sequence can be decoded by executing a process corresponding to the DC-free encoding executed on the encoding side.

  Yet another aspect of the second embodiment of the present invention is a signal processing device. This apparatus includes a signal encoding device and a signal decoding device. According to this aspect, by performing Reed-Solomon coding after performing run-length limited coding, the decoding side performs run-length limited decoding on the signal sequence after performing Reed-Solomon decoding. Therefore, the error correction capability can be improved.

  Yet another aspect of the second embodiment of the present invention is a storage system. The storage system is a signal storage system including a write channel for writing data to the storage device and a read channel for reading data stored in the storage device, and the write channel performs run-length limited encoding on the data. In addition, a first encoding unit that performs Reed-Solomon encoding on the data that has been run-length limited encoded, and a low-density parity for the data encoded by the first encoding unit A second encoding unit that encodes using the check code; and a writing unit that writes the data encoded by the second encoding unit to the storage device, and the read channel is output from the storage device An input unit for inputting an analog signal, an analog-to-digital conversion unit for converting the analog signal input from the input unit into a digital signal and outputting the digital signal, and an analog digital signal Corresponding to a soft output detection unit that calculates the likelihood of the digital signal output from the digital conversion unit and outputs a soft decision value, and a second encoding unit that decodes the data output from the soft output detection unit , A first decoding unit, and a second decoding unit corresponding to the first encoding unit, which decodes the data decoded by the first decoding unit. The first encoding unit includes a run-length limited encoding unit that generates a run-length encoded sequence by performing run-length limited encoding on the data, and a run-length encoded sequence generated by the run-length limited encoded unit Reed-Solomon encoding unit that generates a redundant sequence by adding Reed-Solomon encoding and a redundant sequence generated by the Reed-Solomon encoding unit to the run-length encoded sequence generated by the run-length limited encoding unit A redundant sequence adding unit. The second decoding unit includes: an input unit that inputs data decoded by the first decoding unit; a redundant sequence detection unit that detects an insertion point of a redundant sequence from the first signal sequence input by the input unit; In accordance with the insertion location detected by the redundant sequence detection unit, the redundant sequence is separated from the first signal sequence input by the input unit, and is separated by the redundant sequence acquisition unit that acquires the second signal sequence A Reed-Solomon decoding unit that corrects an error in the second signal sequence acquired by the redundant sequence acquisition unit using the redundant bits, and a run length for the second signal sequence in which the error is corrected by the Reed-Solomon decoding unit. A run-length limited decoding unit that performs limited decoding.

  According to this aspect, by performing Reed-Solomon coding after performing run-length limited coding, the decoding side performs run-length limited decoding on the signal sequence after performing Reed-Solomon decoding. Therefore, the error correction capability can be improved. Further, since the error correction capability can be improved, the storage system can be accessed at higher speed.

  Yet another aspect of the second embodiment of the present invention is also a storage system. The storage system further includes a storage device that stores data, and a control unit that controls writing to the storage device and reading from the storage device. The read channel reads data stored in the storage device in accordance with an instruction from the control unit, and the write channel writes encoded data in the storage device in accordance with an instruction from the control unit. According to this aspect, by performing Reed-Solomon coding after performing run-length limited coding, the decoding side performs run-length limited decoding on the signal sequence after performing Reed-Solomon decoding. Therefore, the error correction capability can be improved. Further, since the error correction capability can be improved, the storage system can be accessed at higher speed.

  Yet another aspect of the second embodiment of the present invention is a signal encoding apparatus. This device may be an integrated device, and the device may be integrated on a single semiconductor substrate. According to this aspect, encoding processing with high DC-free characteristics and high run-length characteristics can be efficiently performed, and it is not necessary to install extra hardware, so that a low-scale semiconductor integrated circuit can be realized.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  Before specifically describing the second embodiment of the present invention, an outline of the storage system 1100 according to the second embodiment will be described first. The storage system 1100 according to the second embodiment includes a hard disk controller, a magnetic disk device, and a read / write channel including a read channel and a write channel. In the write channel, Reed-Solomon coding, run-length limited coding, DC-free coding, and LDPC coding are executed as error correction coding. This Reed-Solomon encoding (hereinafter abbreviated as “RS encoding”) may be mounted integrally with a semiconductor on which a lead channel is mounted, or may be mounted on another semiconductor. In the read channel, data detection using a Viterbi algorithm or the like and LDPC decoding are performed. In this data detection, it is known that detection accuracy deteriorates due to the presence of a DC component. Furthermore, the correction capability of LDPC decoding decreases due to the deterioration of detection accuracy. Therefore, in the second embodiment of the present invention, the configuration is such that DC-free encoding for reducing the DC component is performed before the LDPC encoding. Note that the storage system 1100 according to the second embodiment is not limited to LDPC encoding, and may be configured to execute other error correction encoding schemes, for example, turbo encoding or convolutional encoding. .

  DC-free coding is realized by selecting a sequence having higher DC-free property from two different sequences. When RLL encoding having two different properties is performed in order to generate two different sequences, the circuit scale increases as the second RLL encoding circuit is required. Even in the case of an application that does not pose a problem in circuit scale, as a result of executing RLL coding having two different properties, both sequences are not always good in DC-freeness. Therefore, in the second embodiment of the present invention, the same RLL encoding is executed.

  Here, when executing the same RLL encoding, it is necessary to avoid that the sequences to be selected are the same. It is also necessary to avoid the case where there is no restricted coding sequence with good DC-free characteristics. Therefore, in the second embodiment of the present invention, an arbitrary signal sequence and two sequences after executing predetermined signal processing on an arbitrary signal sequence are subjected to RLL encoding. . As a result, the generated sequences are completely different, so that a sequence having a statistically good DC-free property can be generated. Further, by executing this predetermined signal processing without changing the number of bits of the signal sequence, a reduction in coding gain is avoided. Furthermore, since various sequences can be generated by arbitrarily changing the processing content of signal processing, the range of selection can be expanded. Therefore, the possibility of generating a sequence with better DC-free characteristics is improved. Therefore, the second embodiment of the present invention is suitable for an application such as a hard disk where the coding rate cannot be set low.

  When selecting any one of a plurality of RLL-encoded sequences, there is a possibility that the decoding side erroneously targets a sequence different from the sequence selected on the encoding side. In this case, errors increase. In general, Reed-Solomon encoding has been performed before RLL encoding. In this case, on the decoding side, RLL decoding is performed before Reed-Solomon decoding (hereinafter abbreviated as “RS decoding”), and the possibility of erroneous determination of the selected sequence is not low. Therefore, in the second embodiment of the present invention, on the encoding side, error correction encoding is performed in the order of RLL encoding and / or DC-free encoding and RS encoding. On the decoding side, error correction decoding is performed in the order of RS decoding and RLL decoding.

  However, on the encoding side, when error correction coding is performed in the order of RLL coding and / or DC-free coding and RS coding, redundant bits added in RS coding are RLL and / or DC. The free characteristics will not be satisfied. In general, the number of redundant bits generated in RS encoding and added to an RLL encoded sequence is about 1/10 of the added sequence, so that the RLL property and / or the DC-free characteristic is not satisfied. The harmful effect of this is great. Therefore, in the second embodiment of the present invention, the redundant sequence generated in the RS encoding is divided and added in a distributed manner to the RLL encoded sequence. As a result, the encoded sequence after the redundant sequence is added satisfies the RLL property and the DC-free characteristic. Details will be described later.

  Hereinafter, a second embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 9 is a diagram showing a configuration of a storage system 1100 according to the second embodiment of the present invention. The storage system 1100 of FIG. 9 is broadly divided into a hard disk controller 1001 (hereinafter abbreviated as “HDC 1001”), a central processing unit 1002 (hereinafter abbreviated as “CPU 1002”), and a read / write channel 1003 (hereinafter abbreviated as “CPU 1002”). , Abbreviated as “R / W channel 1003”), voice coil motor / spindle motor controller 1004 (hereinafter abbreviated as “VCM / SPM controller 1004”), and disk enclosure 1005 (hereinafter “DE1005”). Abbreviated as)). In general, the HDC 1001, the CPU 1002, the R / W channel 1003, and the VCM / SPM control unit 1004 are configured on the same substrate.

  The HDC 1001 includes a main control unit 1011 that controls the entire HDC 1001, a data format control unit 1012, and a buffer RAM 1014. The HDC 1001 is connected to the host system via an interface unit (not shown). Further, it is connected to the DE 1005 via the R / W channel 1003, and executes data transfer between the host and the DE 1005 under the control of the main control unit 1011. The HDC 1001 receives a read reference clock (RRCK) generated by the R / W channel 1003. The data format control unit 1012 converts the data transferred from the host into a format suitable for recording on the disk medium 1050 and, conversely, suitable for transferring the data reproduced from the disk medium 1050 to the host. Convert to format. The disk medium 1050 includes, for example, a magnetic disk. The buffer RAM 1014 temporarily stores the data transferred from the host and transfers it to the R / W channel 1003 at an appropriate timing. Conversely, the read data transferred from the R / W channel 1003 is temporarily stored and transferred to the host at an appropriate timing.

  The CPU 1002 includes a flash ROM 1021 (hereinafter abbreviated as “FROM 1021”) and a RAM 1022, and is connected to the HDC 1001, the R / W channel 1003, the VCM / SPM control unit 1004, and the DE 1005. The FROM 1021 stores an operation program for the CPU 1002.

  The R / W channel 1003 is roughly divided into a write channel 1031 and a read channel 1032, and executes transfer of data to be recorded and reproduced data to and from the HDC 1001. Further, the R / W channel 1003 is connected to the DE 1005 and executes transmission of a recording signal and reception of a reproduction signal. Details will be described later.

  The VCM / SPM control unit 1004 controls a voice coil motor 1052 (hereinafter abbreviated as “VCM1052”) and a spindle motor 1053 (hereinafter abbreviated as “SPM1053”) in the DE 1005.

  The DE 1005 is connected to the R / W channel 1003 and executes reception of a recording signal and transmission of a reproduction signal. The DE 1005 is connected to the VCM / SPM control unit 1004. The DE 1005 includes a disk medium 1050, a head 1051, a VCM 1052, an SPM 1053, a preamplifier 1054, and the like. In the storage system 1100 of FIG. 9, it is assumed that there is one disk medium 1050 and the head 1051 is disposed only on one side of the disk medium 1050. A stacked arrangement may be used. The head 1051 is generally provided corresponding to each surface of the disk medium 1050. The recording signal transmitted through the R / W channel 1003 is supplied to the head 1051 via the preamplifier 1054 in the DE 1005 and is recorded on the disk medium 1050 by the head 1051. Conversely, a signal reproduced from the disk medium 1050 by the head 1051 is transmitted to the R / W channel 1003 via the preamplifier 1054. The VCM 1052 in the DE 1005 moves the head 1051 in the radial direction of the disk medium 1050 in order to position the head 1051 at a target position on the disk medium 1050. Further, the SPM 1053 rotates the disk medium 1050.

  Here, the R / W channel 1003 will be described with reference to FIG. FIG. 10 is a diagram showing the configuration of the R / W channel 1003 of FIG. The R / W channel 1003 is roughly composed of a write channel 1031 and a read channel 1032.

  The write channel 1031 includes a byte interface unit 1301, a scrambler 1302, a run length limited / DC free / RS encoding unit 1303 (hereinafter abbreviated as “RLL / DC free / RS encoding unit 1303”), and a low density parity. A check encoding unit 1304 (hereinafter abbreviated as “LDPC encoding unit 1304”), a write compensation unit 1305 (hereinafter abbreviated as “write precon unit 1305”), and a driver 1306 are included.

  The byte interface unit 1301 processes the data transferred from the HDC 1001 as input data. Data to be written on the medium is input from the HDC 1001 in units of one sector. The data bus is normally 1 byte (8 bits), and is processed as input data by the byte interface unit 1301. The scrambler 1302 converts the write data into a random series. This is because the repetition of data with the same rule adversely affects the detection performance at the time of reading and prevents the error rate from deteriorating.

  The RLL / DC free / RS encoding unit 1303 adds redundant symbols using data to be recorded as information symbols in order to enable correction and detection of errors included in data reproduced from the disk medium 1050. The RS code determines whether or not an error has occurred in the reproduced data, and corrects or detects if there is an error. However, the number of symbols that can correct errors is limited, and is related to the length of redundant data. That is, if a large amount of redundant data is added, the format efficiency deteriorates, so that there is a trade-off with the number of error correctable symbols. When error correction is performed using an RS code as ECC, up to (number of redundant symbols / 2) errors can be corrected. Also, the RLL / DC free / RS encoding unit 1303 limits the maximum continuous length of 0. By limiting the maximum continuous length of 0, a data series suitable for an automatic gain control unit 1317 (hereinafter abbreviated as “AGC1317”) or the like is obtained. Furthermore, the direct current component is reduced to improve the error correction capability. Details will be described later.

  The LDPC encoding unit 1304 has a role of generating a sequence including parity bits, which are redundant bits, by LDPC encoding the data sequence. LDPC encoding is performed by multiplying a k × n matrix called a generator matrix by a data sequence of length k from the left. Each element included in the parity check matrix H corresponding to this generator matrix is 0 or 1, and since the number of 1 is smaller than the number of 0, it is called a low density parity check code (Low Density Parity Check Codes). It is. By using this arrangement of 1 and 0, the LDPC iterative decoding unit can efficiently correct errors.

  The write pre-con unit 1305 is a circuit that compensates for non-linear distortion due to continuous magnetization transitions on the medium. A rule necessary for compensation is detected from the write data, and the write current waveform is adjusted in advance so that the magnetization transition occurs at the correct position. The driver 1306 is a driver that outputs a signal corresponding to the pseudo ECL level. The output from the driver 1306 is sent to the DE 1005 (not shown), sent to the head 1051 through the preamplifier 1054, and the write data is recorded on the disk medium 1050.

  The read channel 1032 includes a variable gain amplifier 1311 (hereinafter abbreviated as “VGA 1311”), a low-pass filter 1312 (hereinafter abbreviated as “LPF 1312”), an AGC 1317, and an analog / digital converter 1313 (hereinafter “ADC 1313”). A frequency synthesizer 1314, a filter 1315, a soft output detector 1320, an LDPC iterative decoder 1322, a synchronization signal detector 1321, a run length limited / DC free / RS decoder 1323 (hereinafter referred to as “RLL / DC”). Abbreviated as “free / RS decoder 1323”) and a descrambler 1324.

  The VGA 1311 and AGC 1317 adjust the amplitude of the read waveform of data sent from the preamplifier 1054 (not shown). The AGC 1317 compares the ideal amplitude with the actual amplitude, and determines the gain to be set in the VGA 1311. The LPF 1312 can adjust the cutoff frequency and the boost amount, and is responsible for part of the reduction to high-frequency noise and equalization to a partial response (hereinafter referred to as “PR”) waveform. Although the LPF 1312 equalizes the PR waveform, it is difficult to completely equalize with the analog LPF due to many factors such as fluctuations in the flying height of the head, non-uniformity of the medium, and fluctuations in the rotation of the motor. Then, equalization to the PR waveform is performed again using the filter 1315 having more flexibility. The filter 1315 may have a function of adaptively adjusting the tap coefficient. The frequency synthesizer 1314 generates a sampling clock for the ADC 1313.

  The ADC 1313 is configured to obtain a synchronous sample directly by AD conversion. In addition to this configuration, an asynchronous sample may be obtained by AD conversion. In this case, a zero-phase restart unit, a timing control unit, and an interpolation filter may be further provided after the ADC 1313. Synchronous samples need to be obtained from asynchronous samples, and these blocks play that role. The zero phase restart unit is a block for determining an initial phase, and is used to obtain a synchronization sample as soon as possible. After determining the initial phase, the timing controller compares the ideal sample value with the actual sample value to detect a phase shift. A synchronous sample can be obtained by determining parameters of the interpolation filter using this.

  The soft output detection unit 1320 is a soft output Viterbi algorithm (Soft-Output Viterbi Algorithm; hereinafter abbreviated as “SOVA”), which is a type of Viterbi algorithm, in order to avoid degradation of decoding characteristics due to intersymbol interference. Used. That is, in order to solve the problem that the interference between recorded codes increases and the decoding characteristics deteriorate as the recording density of magnetic disk devices increases in recent years, a partial response due to intersymbol interference is a method for overcoming this problem. The most likely decoding (Partial Response Maximum Like Like) (hereinafter abbreviated as “PRML”) method is used. PRML is a method for obtaining a signal sequence that maximizes the likelihood of a partial response of a reproduction signal.

  When the SOVA method is used as the soft output detection unit 1320, a soft decision value is output. For example, assume that a soft decision value (−0.71, +0.18, +0.45, −0.45, −0.9) is output as the SOVA output. These values represent numerical values as to whether the possibility of being 0 or 1 is high. For example, the first “−0.71” indicates that the possibility of 1 is large, and the second “+0.18” is likely to be 0, but the possibility of 1 is small. Means no. The output of the conventional Viterbi detector is a hard value, and the output of SOVA is hard-decided. In the case of the above example, it is (1, 0, 0, 1, 1). The hard value represents only whether it is 0 or 1, and information on which is more likely is lost. For this reason, decoding performance is improved by inputting a soft decision value to the LDPC iterative decoding unit 1322.

  The LDPC iterative decoding unit 1322 has a role of restoring an LDPC encoded data sequence to a sequence before LDPC encoding. As a decoding method, there are mainly a sum-product decoding method and a min-sum decoding method. The sum-product decoding method is advantageous in terms of decoding performance, but the min-sum decoding method is realized by hardware. With the feature that is easy. In an actual decoding operation using an LDPC code, very good decoding performance can be obtained by repeatedly decoding between the soft output detection unit 1320 and the LDPC iterative decoding unit 1322. For this reason, a configuration in which a plurality of stages of software output detection units 1320 and LDPC iterative decoding units 1322 are arranged is actually required. The synchronization signal detection unit 1321 has a role of detecting a synchronization signal (Sync Mark) added to the head of data and recognizing the head position of the data.

  The RLL / DC free / RS decoding unit 1323 performs the reverse operation of the RLL / DC free / RS encoding unit 1303 of the write channel 1031 on the data output from the LDPC iterative decoding unit 1322, and the original data sequence Return to. Details will be described later.

  The descrambler 1324 performs the reverse operation of the scrambler 1302 of the write channel 1031 to restore the original data series. The data generated here is transferred to the HDC 1001.

  Here, “DC free” will be described. FIGS. 11A to 11B are diagrams illustrating examples of DC-free characteristics according to the second embodiment of the present invention. FIG. 11A is a diagram illustrating an example of the distribution of soft decision values when DC is free and when DC is not. The horizontal axis represents the number, and the vertical axis represents the soft decision value. The vertical axis is an axis including ± 0 on the center and including both positive and negative soft decision values. A first characteristic 1200 indicated by a solid line indicates a distribution in the case of DC free. A second characteristic 1300 indicated by a broken line indicates an example of distribution when DC free. As described above, “DC free” indicates that the ratio of the number of 0 and 1 bits included in the sequence is 50%. In other words, as illustrated in the first characteristic 1200 of FIG. 11A, in the distribution of soft decision values in the LDPC iterative decoding unit 1322 of FIG. It means that the amount is small. On the other hand, when not DC-free, for example, as illustrated in the second characteristic 1300 of FIG. 11A, in the distribution of the soft decision value, the distribution amount near ± 0 is increased.

  FIG. 11B is a diagram illustrating an example of bit error rate characteristics when the DC is free and when it is not DC free. The horizontal axis represents a signal-to-noise ratio (Signal to Noise Ratio), and the vertical axis represents a bit error rate (Bit Error Rate). A third characteristic 1210 indicated by a solid line indicates a bit error rate characteristic when DC is free. A fourth characteristic 1310 indicated by a broken line indicates a bit error rate characteristic when the DC is not free. As shown in the figure, the bit error rate is worse in the case where DC is not free than in the case where DC is free.

  FIG. 12 is a diagram illustrating a configuration example of the RLL / DC free / RS encoding unit 1303 of FIG. The RLL / DC free / RS encoding unit 1303 includes an RLL / DC free encoding unit 1040, an RS encoding unit 1042, and a redundant sequence addition unit 1044. The RLL / DC free coding unit 1040 performs a run length limited coding and a DC free coding on a predetermined signal sequence, thereby abbreviated to a run length limited coded sequence (hereinafter, referred to as an “RLL sequence”) having DC freeness. ) Is generated. The RS encoder 1042 generates a redundant sequence by performing RS encoding on the RLL sequence generated by the RLL / DC free encoder 1040. The redundant sequence addition unit 1044 adds the redundant sequence generated by the RS encoding unit 1042 in a distributed manner to the RLL encoded sequence generated by the RLL / DC free encoding unit 1040.

  FIG. 13 is a diagram illustrating a configuration example of the RLL / DC free encoding unit 1040 of FIG. The RLL / DC free encoding unit 1403 includes a first RLL encoding unit 1060, a first signal processing unit 1062, a second RLL encoding unit 1064, and a direct current component removal encoding unit 1066.

  The first RLL encoding unit 1060 generates a first encoded sequence by subjecting the digital signal sequence output from the scrambler 1302 to run-length limited encoding. The first signal processing unit 1062 performs predetermined signal processing on the digital signal sequence without changing the number of bits included in the digital signal sequence output from the scrambler 1302. The predetermined signal processing may be any processing as long as the number of bits included in the digital signal sequence is not changed. For example, a process of executing a bit inversion process for each of a plurality of bits included in the digital signal sequence may be used. Further, the order of a plurality of bits included in the digital signal sequence may be rearranged. Also, both bit inversion processing and bit order rearrangement processing may be performed. The second RLL encoding unit 1064 generates a second encoded sequence by performing run-length limited encoding on the digital signal sequence that has been subjected to predetermined signal processing by the signal processing unit output from the first signal processing unit 1062 To do. The DC component removal encoding unit 1066 has a high DC-free property among the first encoded sequence generated by the first RLL encoding unit 1060 and the second encoded sequence generated by the second RLL encoding unit 1064. , Select either one and output.

  This will be described using a specific example. When the digital signal sequence to be processed is composed of 300 bits, the RLL / DC free encoding unit 1040 processes 30 bits as one set and divides it into 10 times. Here, when the encoding rate of the first RLL encoding unit 1060 and the second RLL encoding unit 1064 is 30/31, the output per one time output from the first RLL encoding unit 1060 and the second RLL encoding unit 1064, respectively. The number of bits in the series is 31 bits.

  FIG. 14 is a diagram illustrating a configuration example of the DC component removal coding unit 1066 of FIG. DC component removal encoding section 1066 includes an encoded sequence selection section 1074, a selection identification information generation section 1076, and an identification information addition section 1078. The encoded sequence selection unit 1074 is one of the first encoded sequence generated by the first RLL encoding unit 1060 and the second encoded sequence generated by the second RLL encoding unit 1064. Select. The selection identification information generation unit 1076 generates selection identification information indicating the encoded sequence selected by the encoded sequence selection unit 1074. The identification information adding unit 1078 adds the selection identification information generated by the selection identification information generation unit 1076 to any location of the encoded sequence selected by the encoded sequence selection unit 1074.

  This will be specifically described. When the first encoded sequence is selected by the encoded sequence selection unit 1074, the selection identification information added to the first encoded sequence by the identification information addition unit 1078 is “0”. On the other hand, when the second encoded sequence is selected by the encoded sequence selection unit 1074, the selection identification information added to the first encoded sequence by the identification information addition unit 1078 is “1”. In other words, the first encoded sequence to which selection identification information “0” is added or the second encoded sequence to which selection identification information “1” is added is output to LDPC encoding section 1304. It should be noted that the part to which the selection identification information is added by the identification information adding unit 1078 may be an arbitrary fixed part in the encoded sequence, and may be added to the end of the encoded sequence, for example. Although details will be described later, the selection identification information added here is a determination bit, and an appropriate decoding process is realized by analyzing the position of the determination bit added on the decoding side and the content of the determination bit. The Rukoto. In the specific example described above, 1-bit selection identification information is added to a 31-bit encoded sequence at a time, and a total of 32-bit sequences are output. That is, the coding rate in the RLL / DC free coding unit 1040 is 30/32.

  Also, the encoded sequence selection unit 1074 may include a first connection unit and a second connection unit (not shown). The first concatenation unit concatenates the encoded sequence already selected by the encoded sequence selection unit 1074 and the first encoded sequence. The second concatenation unit concatenates the encoded sequence already selected by the encoded sequence selection unit 1074 and the second encoded sequence. In this case, the encoded sequence selection unit 1074 sets the sequence concatenated by the first concatenation unit as a new first encoded sequence, and the sequence concatenated by the second concatenation unit as a new second encoded sequence, Either one of the encoded sequences may be selected. In other words, the encoded sequence selection unit 1074 performs selection determination on a combination of the encoded sequence selected in the past and the encoded sequence that is currently selected as a candidate for selection in the long section. DC-free characteristics can be improved.

  FIGS. 15A to 15C are diagrams illustrating first to third configuration examples of the encoded sequence selection unit 1074 of FIG. FIG. 15 (a) is a diagram illustrating a first configuration example of the encoded sequence selection unit 1074 of FIG. The encoded sequence selection unit 1074 in the first configuration includes a first ratio calculation unit 1080, a second ratio calculation unit 1082, and a selection output unit 1084.

  First ratio calculation section 1080 calculates a ratio between a bit indicating 0 and a bit indicating 1 among a plurality of bits included in the first encoded sequence. Second ratio calculation section 1082 calculates a ratio between a bit indicating 0 and a bit indicating 1 among a plurality of bits included in the second encoded sequence. The selection output unit 1084 selects an encoded sequence corresponding to a ratio closer to 50% of the ratio calculated by the first ratio calculation unit 1080 and the ratio calculated by the second ratio calculation unit 1082. Output.

This will be described using a specific example. First, it is assumed that a 31-bit encoded sequence is output from each of the first RLL encoding unit 1060 and the second RLL encoding unit 1064 at time t = 1. In this case, the first ratio calculator 1080 and the second ratio calculator 1082 analyze the bits included in the respective encoded sequences and calculate the ratio. Here, among the bits included in the encoded sequence input to the first ratio calculation unit 1080, when the bit indicating 0 is 14 bits and the bit indicating 1 is 17 bits, the ratio is the first ratio calculation unit 1080 is calculated as follows.
Ratio _{t = 1} = (number of bits indicating 0 + 1) / (number of bits of coded sequence + 1) = (14 + 1) / (31 + 1) ≈46.9%

In addition, among the bits included in the encoded sequence input to the second ratio calculation unit 1082, when the bit indicating 0 is 12 bits and the bit indicating 1 is 19 bits, the ratio is the second ratio calculation unit 1082. Is calculated as follows. In this case, since the ratio of the first encoded sequence is closer to 50%, the first encoded sequence is selected by the selection output unit 1084 at t = 1. In addition, the number of bits “14” indicating 0 according to the selected first encoded sequence is stored. In the numerator on the right side of the above equation and the following equation, “1” and “0” are added because the selection identification information is assumed to be “0” and “1”. It is. In the above expression and the denominator on the right side of the following expression, “1” is added in order to calculate the ratio of the number of 0s in the series including the selection identification information.
Ratio _{t = 1} = (number of bits indicating 0 + 0) / (number of bits of coded sequence + 1) = 12 / (31 + 1) = 37.5%

Next, it is assumed that a 31-bit encoded sequence is output from the first RLL encoding unit 1060 and the second RLL encoding unit 1064 at t = 2 as in the case of t = 1. Here, among the bits included in the encoded sequence input to the first ratio calculation unit 1080, when the bit indicating 0 is 11 bits and the bit indicating 1 is 20 bits, the ratio is calculated as follows: Is done.
Ratio _{t = 2} = (number of bits indicating 0 + 1) / ((number of bits of coded sequence + 1) × t) = (14 + 1 + 111 + 1) / ((31 + 1) × 2) ≈42.2%

  Unlike the case of t = 1, the first ratio calculation unit 1080 has a sequence in which the encoded sequence selected at t = 1 and the first encoded sequence at t = 2 are concatenated by the first concatenating unit. Calculate the ratio for. That is, the number “14 + 1” of bits indicating 0 in the first encoded sequence selected at t = 1 and the number “11 + 1” of bits indicating 0 in the first encoded sequence at t = 2. It will be added in the numerator of the previous formula. The denominator in the previous equation is the number of bits for two sets of encoded sequences.

In addition, among the bits included in the encoded sequence input to the second ratio calculation unit 1082, when the bit indicating 0 is 17 bits and the bit indicating 1 is 14 bits, the second ratio calculation unit 1082 The ratio is calculated as follows. In this case, since the ratio of the second encoded sequence is closer to 50%, the second encoded sequence is selected by the selection output unit 1084 at t = 2.
Ratio _{t = 2} = (number of bits indicating 0 + 0) / ((number of bits of coded sequence + 1) × t) = (14 + 1 + 17 + 0) / ((31 + 1) × 2) = 50.0%

Similarly, the ratio is calculated after t = 3. Here, the ratio at t = k is expressed as follows. However, k is an integer of 1 or more. Nbit (m) indicates the number of bits indicating 0 among the bits included in the encoded sequence selected at t = m. Here, Nbit (k) indicates the number of bits indicating 0 among the bits included in the encoded sequence for which the ratio is calculated. It is assumed that selection identification information is also included in the encoded sequence for which the ratio is calculated.

  FIG.15 (b) is a figure which shows the 2nd structural example of the encoding sequence selection part 1074 of FIG. The encoded sequence selection unit 1074 in the second configuration includes a first summation unit 1086, a second summation unit 1088, and a selection output unit 1084. The first summation unit 1086 sums a plurality of bits included in the first encoded sequence to generate a first sum value. The second summation unit 1088 sums a plurality of bits included in the second encoded sequence to generate a second sum value. The coded sequence detection unit compares the first sum value generated by the first summation unit 1086 with the second sum value generated by the second summation unit 1088, and compares the first coded sequence and the second code. An encoded sequence corresponding to the smaller sum of the converted sequences is detected. The selection output unit 1084 selects and outputs the encoded sequence detected by the sequence detection unit from the first encoded sequence and the second encoded sequence.

  This will be described using a specific example. First, it is assumed that a 31-bit encoded sequence is output from the first RLL encoding unit 1060 and the second RLL encoding unit 1064 at t = 1. In this case, the first summation unit 1086 and the second summation unit 1088 sum the bits included in the respective encoded sequences. In the summation, 0 may be replaced with “+1” and 1 may be replaced with “−1” for total. By summing in this way, when the number of bits indicating 0 and 1 is equal, the sum is 0. Therefore, the selection output unit 1084 may select an encoded sequence with a combined value close to 0, for example, an encoded sequence with a small absolute value of the combined value. This method is also called continuous digital summation (hereinafter abbreviated as “RDS”).

Here, at t = 1, out of 31 bits included in the encoded sequence input to the first summation unit 1086, the bit indicating 0 is 14 bits, and the bit indicating 1 is 17 bits. Is calculated as follows. Note that “1” is added in the first term on the right side because the selection identification information is assumed to be zero.
RDS _abs = | (14 + 1) × (+1) + 17 × (−1) | = 2

Further, among the bits included in the encoded sequence input to the second summation unit 1088, when the bit indicating 0 is 12 bits and the bit indicating 1 is 19 bits, the ratio is calculated as follows: . In this case, since the RDS of the first encoded sequence is smaller, the first encoded sequence is selected by the selection output unit 1084 at t = 1. Here, the RDS for the first coded sequence before calculating the absolute value is stored as “RDS ₁ = −2”. Note that “1” is added in the second term on the right side because the selection identification information is assumed to be 1.
RDS _abs = | 12 × (+1) + (19 + 1) × (−1) | = 6

Next, at t = 2, as in the case of t = 1, it is assumed that a 31-bit encoded sequence is output from each of the first RLL encoding unit 1060 and the second RLL encoding unit 1064. Here, of the bits included in the encoded sequence input to the first summation unit 1086, when the bit indicating 0 is 11 bits and the bit indicating 1 is 20 bits, the RDS is calculated as follows. The Unlike t = 1, at t = 2, the number of bits related to the encoded sequence selected at t = 1 is taken into consideration.
RDS _abs = | RDS ₁ + (11 + 1) × (+1) + 20 × (−1) | = | −2 + (− 8) | = 10

In addition, among the bits included in the encoded sequence input to the second summation unit 1088, when the bit indicating 0 is 17 bits and the bit indicating 1 is 14 bits, the ratio is calculated as follows: . In this case, since the RDS of the second encoded sequence is smaller, the first encoded sequence is selected by the selection output unit 1084 at t = 2. Further, RDS ₂ = 0 is stored.
RDS _abs = | RDS ₁ + 17 × (+1) + (14 + 1) × (−1) | = | −2 + (+ 2) | = 0

Similarly, RDS _abs is calculated after t = 3. Here, RDS _abs (k) at t = k is expressed as follows. However, t is an integer of 1 or more. Nbit0 (m) indicates the number of bits indicating 0 among the bits included in the encoded sequence selected at t = m and the selection identification information. Nbit1 (m) indicates the number of bits indicating 1 out of the bits included in the encoded sequence selected at t = m and the selection identification information. However, Nbit0 (k) and Nbit1 (k) indicate the number of bits indicating 0 and the number of bits indicating 1 respectively, among the bits included in the encoded sequence for which the sum is calculated.

  The operation of the coded sequence selection unit 1074 described above is characterized in that the movement calculation process is performed between successive past times while performing the interval calculation process at a certain time. Thus, by combining the section process and the movement process, the DC-free property is improved in the long section, for example, the entire 300-bit sequence.

  In addition, the summation processing in the first summation unit 1086 and the second summation unit 1088 may add up the bits indicating 0 or 1 included in the encoded sequence as they are. In this case, in the selection output unit 1084, the encoded sequence corresponding to the sum closer to the half of the number of encoded sequences is selected.

  FIG.15 (c) is a figure which shows the 3rd structural example of the encoding sequence selection part 1074 of FIG. The encoded sequence selection unit 1074 in the third configuration includes a first mobile addition unit 1090, a first maximum value detection unit 1092, a second mobile addition unit 1094, a second maximum value detection unit 1096, and a selection output unit. 1084. The first moving addition unit 1090 generates the same number of first moving addition values as the plurality of bits by calculating the moving addition of the plurality of bits included in the first encoded sequence. The first maximum value detection unit 1092 detects the maximum value among the plurality of first movement addition values generated by the first movement addition unit 1090. Second moving addition section 1094 generates the same number of second moving addition values as the plurality of bits by moving and adding the plurality of bits included in the second encoded sequence. The second maximum value detection unit 1096 detects the maximum value among the plurality of second movement addition values generated by the second movement addition unit 1094. The encoded sequence detection unit compares the maximum value detected by the first maximum value detection unit 1092 with the maximum value detected by the second maximum value detection unit 1096, and compares the first encoded sequence and the second code. An encoded sequence corresponding to the smaller maximum value is detected from the encoded sequences. The selection output unit 1084 selects and outputs the encoded sequence detected by the sequence detection unit from the first encoded sequence and the second encoded sequence.

  The third configuration example of the encoded sequence selection unit 1074 is similar to the second configuration example in that the first mobile adder 1090 and the second mobile adder 1094 calculate the RDS of each encoded sequence. The selection output unit 1084 selects an encoded sequence. In the third configuration example, an encoded sequence that is close to 0 in consideration of only the final calculated value of the 32-bit RDS calculation is selected in that the encoded sequence having the smaller maximum value during the calculation of the 32-bit RDS is selected. This is different from the second configuration example in which is selected. In other words, in the third configuration example, the selection process is performed by the movement calculation in both the predetermined section and the plurality of sections. By taking such an aspect, it is possible to select a sequence having good DC-free properties even in the middle of the section.

Here, the “maximum value during calculation of RDS” is derived as follows for each time t. However, Min {y (0), y (1)} indicates a function that selects a smaller value and outputs the number of the selected sequence. For example, when y (0)> y (1), S (t) is 1. Further, max {x} indicates a function for detecting the maximum value of x. K represents a value in the range of 32 × (t−1) +1 to 32 × t. Bit (m, j) indicates +1 when the m-th bit is 0 in the j-th encoded sequence, and indicates -1 when it is 1.
S (t) = Min {MaxRDS (1), MaxRDS (2)}
MaxRDS (1) = max {RDS (k, 1)}
MaxRDS (2) = max {RDS (k, 2)}

Bit (m, 1) and Bit (m, 2) are calculated after rewriting the bits related to the selected sequence as follows each time t increases.
Bit (m, 1) = Bit (m, 2) = Bit (m, S (t−1)): m = (t−1) × 32 + 1 to t × 32, t ≠ 1

Here, the operation of the third configuration example of the encoded sequence selection unit 1074 shown in FIG. 15C is compared with the operation of the second configuration example of the encoded sequence selection unit 1074 shown in FIG. . FIG. 16 is a diagram illustrating a difference in operation of the coded sequence selection unit 1074 illustrated in FIG. 15B and FIG. 15C, respectively. The horizontal axis represents time, and the vertical axis represents RDS. Here, 1400A indicates the transition of RDS in the first encoded sequence. 1400B indicates the transition of RDS in the second encoded sequence. In the second configuration example of the coded sequence selection unit 1074 shown in FIG. 15B, RDS _A and RDS _B , which are final values of the RDS interval calculation, are compared and the smaller coded sequence is selected. . In FIG. 16, since RDS _A <RDS _B , the selection output unit 1084 selects the first encoded sequence. On the other hand, in the third configuration example of the encoded sequence selection unit 1074 shown in FIG. 15 (c), the RDS in each bit, that is, the maximum value among the absolute values after the 32 bits are sequentially subjected to the movement calculation process Compare the values and select the smaller encoded sequence. In FIG. 16, MaxA is the maximum value for the first encoded sequence, and MaxB is the maximum value for the second encoded sequence. Here, since MaxA> MaxB, the selection output unit 1084 selects the second encoded sequence. Even when any configuration example is applied to the encoded sequence selection unit 1074, it is possible to select an encoded sequence having a high DC-free property.

  Returning to FIG. Redundant sequence adding section 1044 includes a dividing section (not shown). The dividing unit divides the redundant sequence generated by the RS encoding unit 1042 into a plurality of sets. The group divided by the dividing unit is added to any part of the RLL / DC-free encoded sequence and to a different part for each group. Redundant sequence adding section 1044 adds to the RLL / DC-free encoded sequence at equal intervals, for example, every L, for each group divided by the dividing section. The dividing unit divides one of two or more bits included in the redundant sequence generated by the RS encoding unit 1042 as one set. The dividing unit divides 2N (N is a positive integer) bits as one set among a plurality of bits included in the redundant sequence generated by the RS encoding unit 1042.

  The operation of the RLL / DC free / RS encoding unit 1303 illustrated in FIG. 12 will be specifically described. FIG. 17 is a diagram illustrating an operation example of the RLL / DC free / RS encoding unit 1303 of FIG. First, the RLL / DC free encoding unit 1040 generates an RLL / DC free encoding sequence 1400. Next, RS encoding section 1042 performs RS encoding on RLL / DC free encoded sequence 1400 to generate redundant sequence 1500. Next, the dividing unit of the redundant sequence adding unit 1044 divides the redundant sequence 1500 into M partial redundant sequences 1510. The partial redundancy sequence 1510 represents the first partial information sequence 1510a, the second partial information sequence 1510b,..., The Mth partial information sequence 1510c. Each partially redundant sequence 1510 includes 2N bits. Redundant sequence adding section 1044 adds to RLL / DC-free encoded sequence 1400 for each partial redundant sequence 1510 in a distributed manner at different positions. Redundant sequence adding section 1044 adds partial redundant sequence 1510 to RLL / DC-free encoded sequence 1400 at regular intervals. As a result, all bits included in the redundant sequence 1500 are added to the RLL / DC free encoded sequence 1400, and an RLL / DC free / RS encoded sequence 1600 is generated.

Here, the lengths of the RLL / DC free encoded sequence 1400, the redundant sequence 1500, and the RLL / DC free / RS encoded sequence 1600 are expressed as follows. Here, L indicates an interval at which the partial redundancy sequence 1510 is added. N, s, α, and β are positive integers.
Length of RLL / DC-free coded sequence 1400 = sL + α
Redundant sequence 1500 length = 2 NM + β
Length of RLL / DC free / RS coded sequence 1600 = length of RLL / DC free coded sequence 1400 + length of redundant sequence 1500

  Next, a specific operation process of the RLL / DC free / RS encoding unit 1303 will be described. FIG. 18 is a flowchart illustrating an operation example of the RLL / DC free / RS encoding unit 1303 of FIG. First, the RLL / DC free encoding unit 1040 generates an RLL / DC free encoding sequence 1400 (S1010). Next, the RS encoding unit 1042 performs RS encoding on the RLL / DC free encoded sequence 1400 to generate a redundant sequence 1500 (S1012). Next, the dividing unit of the redundant sequence adding unit 1044 divides the redundant sequence 1500 into M partial redundant sequences 1510 and adds the partial redundant sequences 1510 to different positions at equal intervals (S1014 to S1020).

  In S14 to S20, first, the counter i related to the RLL / DC free coded sequence 1400 is set to L, and the counter j related to the redundant sequence 1500 is set to 1 (S1014). Next, the jth to (j + 2N) th bits of the redundant sequence 1500 are added after the ith bit from the beginning of the RLL / DC free coded sequence 1400 (S1016). However, if any of the (j + 1) th to (j + 2N) th bits does not exist in the redundant sequence 1500, after adding all the existing bits, the process proceeds to step S1018. Next, the counter i is incremented by L and the counter j is incremented by 2N (S1018). Here, if j is 2NM or less (N in S1020), it is determined that the RLL / DC-free encoded sequence 1400 to be added remains, and the processes in S1016 to S1020 are repeated. On the other hand, if j is a value greater than 2NM (Y in S1020), that is, it is determined that all redundant sequences 1500 have been added, and the process ends.

This will be described using a specific example. The RLL / DC free encoding unit 1040 has a continuity of bits indicating 0 in a bit sequence y0 (m) indicating a plurality of even-numbered bits in x (n) indicating the RLL / DC free encoding sequence 1400. Are encoded as restricted. Also, the RLL / DC-free encoding unit 1040 is configured such that the continuity of bits indicating 0 is limited in each of the bit sequences y1 (m) indicating a plurality of odd-numbered bits in x (n). Encode. For example, x (n), y0 (m), and y1 (m) are expressed as follows. Here, the maximum continuous length of 0 was assumed to be 3.
x (n) = {011100101001100010001}
y0 (m) = x (2n) = {0101101000}
y1 (m) = x (2n + 1) = {1100010101}

  Also, DC-free coding generally refers to coding such that the ratio of bits indicating 0 or 1 is close to 50% in a predetermined section of the RLL / DC-free coded sequence 1400. In other words, it is not necessary to be DC-free in a section shorter than the predetermined section. In the above x (n), the number of bits indicating 0 is 11, whereas the number of bits indicating 1 is 9, so it can be said that the DC-free property is substantially satisfied.

  Here, when adding redundant sequence 1500 to RLL / DC free encoded sequence 1400 in redundant sequence adding section 1044, x ′ (n) indicating first RLL / DC free / RS encoded sequence 1610 added in series And the RLL property and DC free property of x ″ (n) indicating the second RLL / DC free / RS encoded sequence 1620 added in a distributed manner. The redundant sequence 1500 to be added is 4 bits, and is A, B, C, and D, respectively. Further, y0 ′ (m) and y1 ′ (m) are bit sequences indicating a plurality of even-numbered bits and odd-numbered bits in x ′ (n) indicating the first RLL / DC-free / RS encoded sequence 1610, respectively. Indicates. Also, y0 ″ (m) and y1 ″ (m) are bit sequences existing in even and odd numbers in x ″ (n) indicating the second RLL / DC free / RS encoded sequence 1620, respectively. Show.

Redundant sequence 1500 = {A, B, C, D}
x ′ (n) = {0111001010011000010001ABCD}
y0 ′ (m) = {0101101000AC}
y1 ′ (m) = {1100010101BD}

x ″ (n) = {01110AB0101001100CD10001}
y0 ″ (m) = {010B11010D00}
y1 ″ (m) = {11A00010C101}

  According to the above formulas x ′ (n), y0 ′ (m), and y1 ′ (m), A indicates 0 in y0 ′ (m) and y1 ′ (m) when added in series. If it is a bit, the maximum continuous length of 0 is 4. If both A and C are bits indicating 0, the maximum continuous length of 0 is 5. Since the redundant sequence added in series is not subjected to RLL encoding, such a result is obtained. On the other hand, according to the above-described formulas x ″ (n), y0 ″ (m), and y1 ″ (m), in the case of y0 ″ (m) and y1 ″ (m) when added in a distributed manner. The maximum continuous length of 0 remains 3 except when A or D is 0. Even if A and D are bits indicating 0, the maximum continuous length of 0 is only 4 at most. In other words, even when an even number of bits are added to the RLL / DC-free encoded sequence as a set, it can be said that the RLL property does not deteriorate greatly. In other words, it can be said that an effect equivalent to the RLL encoding of the redundant sequence can be obtained by adding the redundant sequence to the RLL / DC free encoded sequence in a distributed manner.

  Further, considering the DC-free property, when all of A, B, C, and D are bits indicating 0, x ″ (n) has 15 bits indicating 0 and 9 bits indicating 1 As a result, the DC-free property is slightly deteriorated. Further, when all of A, B, C, and D are bits indicating 1, x ″ (n) has 11 bits indicating 0 and 13 bits indicating 1 and is somewhat DC-free. Deteriorates. However, it is rare that all redundant bits indicate the same bit. In addition, the length of the redundant bit is about 1/10 as compared with the length of the run-length encoded sequence. The entire encoded sequence 1600 is hardly degraded.

  Therefore, by adding 2N redundant bits as a set to the RLL sequence at equal intervals, the RLL sequence after the redundant sequence is added, that is, the RLL / DC free / RS encoded sequence 1600 has RLL property, DC-free characteristics can be satisfied. Although it is not always necessary to add them at equal intervals, the equal intervals have the effect of simplifying the processing. In addition, the RLL property of the redundant sequence portion can be greatly improved as compared with the case where it is not distributed and added.

  FIG. 19 is a diagram illustrating a configuration example of the RLL / DC free / RS decoding unit 1323 of FIG. The RLL / DC free / RS decoding unit 1323 includes a redundant sequence detection unit 1034, a redundant sequence acquisition unit 1036, an RS decoding unit 1038, and an RLL / DC free decoding unit 1046. The redundant sequence detection unit 1034 detects the insertion point of the redundant sequence from the first signal sequence input by the LDPC iterative decoding unit 1322. Specifically, the insertion position is detected in consideration of the insertion interval of the redundant sequence and the number of bits per set.

  The redundant sequence acquisition unit 1036 acquires the second signal sequence by separating the redundant sequence from the first signal sequence input by the LDPC iterative decoding unit 1322 according to the insertion location detected by the redundant sequence detection unit 1034. The RS decoding unit 1038 corrects the error of the second signal sequence acquired by the redundant sequence acquisition unit 1036 using the redundant bits separated by the redundant sequence acquisition unit 1036. The RLL / DC free decoding unit 1046 performs run-length limited decoding on the second signal sequence whose error is corrected by the RS decoding unit 1038. Specifically, processing is performed in the reverse order to the operation of RLL / DC free / RS encoding section 1303 shown in FIG.

  20 is a diagram illustrating a configuration example of the RLL / DC free decoding unit 1046 of FIG. The RLL / DC free decoding unit 1046 includes a determination bit acquisition unit 1068, an RLL decoding unit 1070, and a second signal processing unit 1072. Determination bit acquisition unit 1068 acquires a predetermined determination bit added to the second signal sequence in which the error is corrected by RS decoding unit 1038. The RLL decoding unit 1070 generates a digital signal sequence by performing run-length limited decoding on the second signal sequence (excluding the determination bit) whose error has been corrected by the RS decoding unit 1038. The second signal processing unit 1072 performs a predetermined signal executed by the first signal processing unit 1062 on the digital signal sequence generated by the RLL decoding unit 1070 according to the determination bit acquired by the determination bit acquisition unit 1068. The signal processing that is the reverse of the processing is executed and output. For example, if the first signal processing unit 1062 in FIG. 13 performs a bit inversion process and / or a process of changing the order of bits, the bit inversion process and / or the exchanged sequence is replaced to restore the original. Process. Or according to the determination bit acquired by the determination bit acquisition part 1068, the 2nd signal processing part 1072 performs the process which outputs the some bit contained in a digital signal series as it is.

  These configurations described above can be realized in hardware by a CPU, memory, or other LSI of an arbitrary computer, and in software by a program having a communication function loaded in the memory. Here, functional blocks realized by the cooperation are depicted. Accordingly, those skilled in the art will understand that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof.

  According to the second embodiment, by performing the RS encoding after the run length limited encoding, the decoding side performs the run length limited decoding on the signal sequence after the RS decoding. become. In other words, run-length limited decoding is performed on a sequence that has been error-corrected by RS decoding. If it does so, the encoding sequence selected in the encoding side can be discriminate | determined correctly, and the error correction capability as a whole can be improved. Further, by adding the redundant sequence divided into a plurality of sets to different locations at any location of the run-length limited encoded sequence, the RLL property of the sequence after the redundant sequence is added, and the DC Free characteristics can be improved. Further, by adding each group at equal intervals, it is possible to further improve the RLL property and DC-free characteristics of the sequence after the redundant sequence is added. By adding an even number of redundant sequences to the run-length limited encoded sequence, the RLL property of the sequence after the redundant sequence is added can be further improved. Even if an even number of bits are added to a RLL / DC-free encoded sequence as a set, it can be said that the RLL property does not deteriorate greatly. In other words, an effect equivalent to RLL encoding of a redundant sequence can be obtained by distributing and loading redundant sequences into RLL / DC free encoded sequences. Since the length of the redundant bit is about 1/10 of the length of the run-length limited encoded sequence, the DC-free property is hardly deteriorated, and the redundant sequence portion is compared with the case where it is not distributed and added. The RLL property can be greatly improved.

  Also, by executing the same RLL encoding, it is possible to generate a sequence having a good DC-free property without increasing the circuit scale. Since an arbitrary signal sequence and two sequences after performing predetermined signal processing on an arbitrary signal sequence before RLL encoding are processed, the generated sequences are completely different. A sequence having good DC-free property can be generated. Further, by executing this predetermined signal processing without changing the number of bits of the signal sequence, a decrease in coding gain can be avoided. Furthermore, since various sequences can be generated by arbitrarily changing the processing content of signal processing, the range of selection can be expanded. Therefore, it is possible to generate a sequence with better DC-free characteristics. Therefore, it is suitable for an application such as a hard disk where the coding rate cannot be set low. Further, by using the same RLL encoding circuit, the circuit configuration can be simplified and the scale can be reduced.

  In addition, different sequences can be generated without increasing the number of bits included in the sequence to be run-length limited encoding by rearranging the bit order and / or rearranging the bit order. Further, since the number of bits included in the sequence does not increase, an encoded sequence can be obtained without reducing the overall encoding rate. Further, the predetermined process executed to generate the different series is a bit inversion process and / or a process of rearranging the order of the bits, whereby the predetermined process can be realized with a simple circuit configuration. Further, by adding information indicating that any of the encoded sequences has been selected to the encoded sequence, the selected encoded sequence can be easily discriminated on the decoding side.

  In addition, the encoded sequence selection unit 1074 performs selection determination on a combination of an encoded sequence selected in the past and an encoded sequence that is a candidate for current selection. DC-free characteristics can be improved. In the encoded sequence selection unit 1074, the RDS is calculated by combining the interval process and the movement process, thereby improving the DC-free property in the long interval, for example, the entire 300-bit sequence. Also, by selecting the one where the ratio of the bit indicating 0 and the bit indicating 1 is close to 50%, it is possible to select an encoded sequence having a high DC-free property. In addition, by adding a plurality of bits included in the encoded sequence and selecting a sequence corresponding to a smaller combined value, an encoded sequence having a high DC-free property can be selected. Further, by selecting a sequence using the maximum value among the results obtained by moving and adding a plurality of bits included in the encoded sequence, an encoded sequence having a high DC-free property can be selected. The original digital signal sequence can be decoded by executing a process corresponding to the DC-free encoding executed on the encoding side. By executing the encoding process with high DC-free property, the storage system can be accessed at higher speed. Moreover, since it is not necessary to install extra hardware, a low-scale semiconductor integrated circuit can be realized.

  In the second embodiment, the R / W channel 1003 may be integrated on a single semiconductor substrate. Further, the coding sequence selection unit 1074 of the second embodiment has been described as the interval calculation process or the movement calculation process. However, the present invention is not limited to this, and an encoded sequence having a high DC-free property may be selected by performing section average processing or moving average processing. Even in this case, the same effect can be obtained. In addition, in the configuration of the RLL / DC free / RS encoding unit 1303, the description has been given assuming that two different signal sequences are generated using the first signal processing unit 1062 that executes predetermined signal processing. However, the present invention is not limited to this, and a plurality of signal sequences may be generated using a plurality of signal processing units. For example, a signal processing device that executes a bit inversion process, a process for changing the order of bits, a bit inversion process, and a process for changing the order of bits may be provided. In this case, an appropriate decoding process can be realized on the decoding side by setting the determination bit indicating that any of the four sequences has been selected to 2 bits. Also, four different sequences can be generated, including sequences that are not subjected to signal processing. In addition, since the number of options can be increased, the possibility that a sequence having a high DC-free property is generated can be improved.

  Moreover, although the case where RS code was used as an error correction system was demonstrated, not only this but another system code, for example, LDPC code and turbo code, may be sufficient. Even in these cases, it goes without saying that the same effects as described above can be obtained.

  12 and FIG. 12, the RS encoding unit 1042 and the redundant sequence adding unit 1044 are separate blocks. However, the RS encoding unit 1042 is not limited to this, and the redundant sequence adding unit 1044 is not limited thereto. The structure containing these may be sufficient. In FIG. 17 and FIG. 18, the description has been made assuming that the partial redundancy sequence 1510 is added to the RLL / DC-free encoded sequence 1400 after L intervals are initially set. However, the present invention is not limited to this, and these processes may be executed in place of any value, for example, α or 0. In S20, it has been described that the end determination is performed based on whether j is larger than 2NM. However, this is not restrictive, and the termination determination may be performed on the condition that i is larger than sL. Even in these cases, it goes without saying that the same effects as described above can be obtained.

(Third embodiment)
The third embodiment of the present invention relates to an error correction encoding / decoding technique, and in particular, an encoding device, a decoding device, a signal processing device, and a storage that perform error correction encoding / decoding on data stored in a storage medium. About the system.

  The background art regarding the third embodiment will be described.

  In recent years, storage devices using hard disks are becoming essential devices in various fields such as personal computers, hard disk recorders, video cameras, and mobile phones. Storage devices using a hard disk have various specifications required depending on the field to which they are applied. For example, a hard disk mounted on a personal computer is required to have high speed and large capacity. In order to improve high speed and large capacity, it is necessary to perform error correction coding with high correction capability. However, since the amount of data handled per unit time increases as the speed increases, errors per unit time also increase proportionally. Then, when an error correction method with low error correction capability is used, the hard disk is re-read, so that the time required to access the hard disk increases and becomes a bottleneck for speeding up.

  In general, a signal sequence in which a DC component is reduced or removed (hereinafter referred to as “DC-free” or “DC-free”) is desired as a signal sequence to be subjected to error correction coding. . DC free means that the frequency is 0, that is, the spectrum in the DC component is 0. In other words, it means that the ratio of 0 and 1 is equal in a plurality of bits included in the signal sequence before modulation. By providing the signal sequence with the DC-free property, the average level of the reproduction signal obtained from the recording pattern of the modulation data stored in the storage medium is a predetermined signal sequence length regardless of the pattern of the signal sequence before modulation. The noise resistance is improved by having a constant property within the range of. That is, in a signal sequence having a low DC-free property, the detection probability decreases in data detection using the Viterbi algorithm. As a result, the correction capability in low density parity check decoding and Reed-Solomon decoding is also reduced. In general, a run-length limit code is used to ensure synchronization between sampling timing and data. The run length limited code is a coding that limits the maximum continuous length of 0 or the maximum continuous length of 1.

  Conventionally, as a method for performing run-length limited encoding while satisfying DC-freeness of a signal sequence, a plurality of encoded sequences are obtained by executing run-length limited encoding on signal sequences to which different redundant bits are added. Among them, a method for selecting a sequence having characteristics close to DC free has been proposed (for example, see Japanese Patent Application Laid-Open No. 2002-100125). In addition, a method has been proposed in which run-length limited encoding having a plurality of different properties is performed, and a sequence having characteristics close to DC-free is selected from the plurality of encoded sequences (for example, Japanese Patent Application Laid-Open No. 2004-2004). -213863).

  A problem to be solved by the third embodiment will be described.

  Under such circumstances, the present inventor has come to recognize the following problems. When realizing DC-free coding by selecting a sequence having good DC-free characteristics from among a plurality of coded sequences, there is no coded sequence having good DC-free characteristics among the plurality of coded sequences to be selected. There is a case. That is, it is necessary to have a configuration capable of generating at least one sequence having good DC-free characteristics among the encoded sequences to be selected, which affects the circuit scale and the storage capacity.

  The third embodiment of the present invention has been made in view of such a situation, and the general purpose thereof is an encoding device and a decoding that can improve DC-free characteristics while satisfying run-length restrictions with a smaller circuit scale. An object is to provide a device, a signal processing device, and a storage system.

  In order to solve the above-described problem, an encoding apparatus according to an aspect of the third embodiment of the present invention performs run-length limited encoding that generates a first encoded sequence by performing run-length limited encoding on a digital signal sequence. A signal processing unit that performs predetermined signal processing on the first encoded sequence without changing the number of bits included in the first encoded sequence to generate a second encoded sequence; A DC component removal encoding unit that selects and outputs one of the first encoded sequence generated by the run-length limited encoding unit and the second encoded sequence generated by the signal processing unit; Is provided. Here, the “DC component removal coding unit” includes a circuit that removes or reduces a DC component of an input sequence, and a circuit that outputs a sequence having a high DC-free property.

  According to this aspect, two completely different sequences can be generated by generating a sequence generated by run-length limited encoding and a sequence obtained by signal processing of the sequence. Further, by executing predetermined signal processing so as not to increase the number of bits included in the sequence, an encoded sequence can be obtained without reducing the overall coding rate. Since the two encoded sequences are phase-inverted, it is a more preferable option for selecting an encoded sequence having a high DC-free property. By selecting an encoded sequence having a high DC-free property from more preferable options, the possibility of selecting an encoded sequence having a higher DC-free property can be improved. Further, by using a single run-length limited encoding circuit, the circuit configuration can be simplified and the scale can be reduced.

  The run-length limited encoding unit is at least one or more 0 consecutive sections in which bits indicating 0 among a plurality of bits included in the first encoded sequence are continuously present, and has a maximum length. At least one or more bits in which a length of 0 continuous section is not less than 0 and not more than the first allowable continuous length and a bit indicating 1 among a plurality of bits included in the first encoded sequence exists continuously The first encoded sequence may be generated such that the length of one continuous section having the maximum length is 0 or more and the second allowable continuous length or less. According to this aspect, by limiting both the continuous length of 0 and the continuous length of 1 included in the first encoded sequence by the run-length limited encoding unit, the limitation is also maintained in the second encoded sequence. .

  The run length limited encoding unit may generate the first encoded sequence with the first allowable continuous length and the second allowable continuous length as the same length. According to this aspect, even if bit inversion processing is performed on an encoded sequence in which the continuous length of 1 and the continuous length of 0 are limited in the subsequent stage of the run-length limited encoding unit, the restriction on the continuous length is maintained. it can. The signal processing unit may perform bit inversion processing on each of a plurality of bits included in the digital signal sequence. According to this aspect, by performing bit inversion processing, different sequences can be generated without increasing the number of bits included in the sequence. Further, since the number of bits included in the sequence does not increase, an encoded sequence can be obtained without reducing the overall encoding rate. Further, the predetermined process executed to generate the different series is a bit inversion process, whereby the predetermined process can be realized with a simple circuit configuration.

  The direct current component removal encoding unit includes an encoded sequence selection unit that selects one of the first encoded sequence and the second encoded sequence, and an encoding selected by the encoded sequence selection unit. The selection identification information generated by the selection identification information generation unit is added to any part of the selection identification information generation unit that generates selection identification information indicating a sequence and the encoded sequence selected by the encoding sequence selection unit. And an identification information adding unit. The encoded sequence selection unit includes a first concatenation unit that connects the encoded sequence already selected by the encoded sequence selection unit and the first encoded sequence, and the encoding already selected by the encoded sequence selection unit. A second concatenation unit that concatenates the sequence and the second encoded sequence. The encoded sequence selection unit sets the sequence concatenated by the first concatenation unit as a new first encoded sequence, sets the sequence concatenated by the second concatenation unit as a new second encoded sequence, and either one of the new sequence An encoded sequence may be selected. A first addition unit for adding a first determination bit to any part of the first encoded sequence output from the run-length limited encoding unit; and any of the second encoded sequence output from the signal processing unit. And a second adding unit that adds a second determination bit obtained by inverting the first determination bit at a location.

  Here, “addition” includes addition, multiplication, insertion, and the like. In addition, “connecting an already selected encoded sequence and the first encoded sequence” means connecting an encoded sequence selected in the past and a sequence that is currently a candidate for selection, etc. including. According to this aspect, by adding information indicating that any of the encoded sequences has been selected to the encoded sequence, the selected encoded sequence can be easily determined on the decoding side.

  The encoded sequence selection unit includes a first ratio calculation unit that calculates a ratio between a bit indicating 0 and a bit indicating 1 among a plurality of bits included in the first encoded sequence, and included in the second encoded sequence A second ratio calculating unit that calculates a ratio between a bit indicating 0 and a bit indicating 1 among the plurality of bits, a ratio calculated by the first ratio calculating unit, and a ratio calculated by the second ratio calculating unit A selection output unit that selects and outputs an encoded sequence corresponding to a ratio closer to 50% of the ratio. According to this aspect, an encoded sequence having a high DC-free property can be selected by selecting the one where the ratio between the bit indicating 0 and the bit indicating 1 is close to 50%.

  The encoded sequence selection unit adds a plurality of bits included in the first encoded sequence to generate a first combined value, and adds a plurality of bits included in the second encoded sequence. The second summation unit that generates the second summation value, the absolute value of the first summation value generated by the first summation portion, and the absolute value of the second summation value generated by the second summation portion are compared. Among the first encoded sequence and the second encoded sequence, the encoded sequence detection unit that detects the encoded sequence corresponding to the smaller sum value, the first encoded sequence, and the second encoded sequence A selection output unit that selects and outputs the encoded sequence detected by the sequence detection unit. Here, the “summed value” includes adding bits included in the series. In addition, “a plurality of bits included in a sequence” includes a bit indicating 0 or 1 and the like, and a bit when a bit indicating 0 is replaced with +1 and a bit indicating 1 is replaced with −1. Including. According to this aspect, a plurality of bits included in the encoded sequence are added together, and a sequence corresponding to a smaller combined value is selected, so that an encoded sequence having a high DC-free property can be selected.

  An encoded sequence selection unit includes a first mobile addition unit that generates the same number of first mobile addition values as a plurality of bits by moving and adding a plurality of bits included in the first encoded sequence; A first maximum value detection unit that detects a maximum value among the plurality of first movement addition values generated by the unit, and a plurality of bits by moving and adding a plurality of bits included in the second encoded sequence, A second movement addition unit that generates the same number of second movement addition values; a second maximum value detection unit that detects a maximum value among a plurality of second movement addition values generated by the second movement addition unit; Comparing the maximum value detected by the 1 maximum value detection unit with the maximum value detected by the second maximum value detection unit, the smaller maximum value of the first encoded sequence and the second encoded sequence An encoded sequence detection unit for detecting an encoded sequence corresponding to A first encoding sequence, of a second coding sequence, and a selection output section for selectively outputting the detected coded sequence by sequence detector may have. Here, “moving and adding” includes moving and adding, and calculating an absolute value. According to this aspect, by selecting a sequence using the maximum value among the results of moving and adding a plurality of bits included in the encoded sequence, an encoded sequence having a high DC-free property can be selected.

  Another aspect of the third embodiment of the present invention is a decoding device. The apparatus includes an input unit that inputs an encoded sequence to which a predetermined determination bit is added, a determination bit acquisition unit that acquires a predetermined determination bit added to the encoded sequence input by the input unit, and an input The bit sequence inverts each of a plurality of bits included in the encoded sequence according to the determination bit acquired by the determination bit acquisition unit and outputs the signal sequence to be decoded. Or a signal processing unit that executes any one of the process of outputting the encoded sequence as a signal sequence to be decoded as it is and the run length of the signal sequence to be decoded output by the signal processing unit. A run-length limited decoding unit that generates a digital signal sequence by performing limited decoding. According to this aspect, the original digital signal sequence can be decoded by executing a process corresponding to the DC-free encoding executed on the encoding side.

  Yet another aspect of the third embodiment of the present invention is a signal processing device. This apparatus is a signal processing apparatus including an encoding unit and a decoding unit, and the encoding unit performs a run-length limited code that generates a first encoded sequence by performing a run-length limited encoding on a digital signal sequence. Output from the encoding unit, the signal processing unit that generates the second encoded sequence by performing bit inversion processing on each of the plurality of bits included in the first encoded sequence, and the run-length limited encoding unit A first addition unit that adds a first determination bit to any part of the first encoded sequence, and a first determination bit is bit-inverted to any part of the second encoded sequence output from the signal processing unit A second addition unit for adding the second determination bit, a first encoded sequence to which the first determination bit is added by the first addition unit, and a second code to which the second determination bit is added by the second addition unit. Izu A DC component removal encoding unit that selects and outputs either of them, and a decoding unit, an input unit that inputs an encoded sequence to which either the first determination bit or the second determination bit is added, A determination bit acquisition unit that acquires a determination bit added to the encoded sequence input by the input unit, and a determination bit acquired by the determination bit acquisition unit for the encoded sequence input by the input unit Either a process of outputting a signal sequence to be decoded by bit-inverting each of a plurality of bits included in the digital signal sequence, or a process of outputting an encoded sequence as a signal sequence to be decoded as it is A digital signal sequence is generated by run-length limited decoding of the signal sequence to be decoded and output from the signal processing unit. A runlength limited decoding unit which may have a.

  According to this aspect, by performing the inversion process so as not to increase the number of bits included in the sequence, the encoded sequence can be obtained without reducing the overall coding rate. Since the two encoded sequences are in a logically inverted relationship, it is a more preferable option for selecting an encoded sequence having a high DC-free property. By selecting an encoded sequence having a high DC-free property from more preferable options, the possibility of selecting an encoded sequence having a higher DC-free property can be improved. In addition, on the decoding side, the original digital signal sequence can be decoded by executing processing corresponding to the DC-free encoding executed on the encoding side.

  Yet another aspect of the third embodiment of the present invention is a storage system. This storage system is a signal storage system including a write channel for writing data to the storage device and a read channel for reading data stored in the storage device, and the write channel is a first that performs run-length encoding of data. The data encoded by the first encoding unit, the second encoding unit that encodes the data encoded by the first encoding unit using the low-density parity check code, and the second encoding unit The read channel writes an analog signal output from the storage device, and converts the analog signal input from the input unit into a digital signal and outputs the digital signal. An analog-digital converter, a software output detector that calculates the likelihood of the digital signal output from the analog-digital converter, and outputs a soft decision value; A first decoding unit corresponding to a second encoding unit that decodes data output from the force detection unit, and a first encoding unit that decodes data decoded by the first decoding unit. A corresponding second decoding unit. The first encoding unit includes a run-length limited encoding unit that generates a first encoded sequence by performing run-length limited encoding on the digital signal sequence, and a plurality of bits included in the first encoded sequence. On the other hand, a first determination bit is added to one of the signal processing unit that performs bit inversion processing to generate the second encoded sequence and the first encoded sequence output from the run-length limited encoding unit. A first adding unit that adds a second determination bit obtained by inverting the first determination bit to any part of the second encoded sequence output from the signal processing unit, and a first addition DC component for selecting and outputting one of the first encoded sequence to which the first determination bit is added by the unit and the second encoded sequence to which the second determination bit is added by the second addition unit And a removal coding unit. That. The second decoding unit includes an input unit that inputs an encoded sequence to which either the first determination bit or the second determination bit is added, and a determination bit that is added to the encoded sequence input by the input unit. A determination bit acquisition unit to be acquired, and a bit sequence obtained by inverting each of a plurality of bits included in the digital signal sequence in accordance with the determination bit acquired by the determination bit acquisition unit for the encoded sequence input by the input unit A signal processing unit that performs either of a process of outputting a signal sequence to be decoded or a process of outputting an encoded sequence as a signal sequence to be decoded as it is and a signal processing unit A run-length limited decoding unit that generates a digital signal sequence by subjecting the signal sequence to be decoded to run-length limited decoding. According to this aspect, the storage system can be accessed at higher speed by executing the encoding process with high DC-free property.

  Yet another aspect of the third embodiment of the present invention is also a storage system. The storage system further includes a storage device that stores data, and a control unit that controls writing to the storage device and reading from the storage device. The read channel reads data stored in the storage device in accordance with an instruction from the control unit, and the write channel writes encoded data in the storage device in accordance with an instruction from the control unit. According to this aspect, the storage system can be accessed at higher speed by executing the encoding process with high DC-free property.

  Yet another aspect of the third embodiment of the present invention is an encoding device. This device may be an integrated device, and the device may be integrated on a single semiconductor substrate. According to this aspect, encoding processing with high DC-free characteristics can be executed efficiently, and it is not necessary to install extra hardware, so that a low-scale semiconductor integrated circuit can be realized.

  Yet another aspect of the third embodiment of the present invention is a run-length limited encoding method. This method is a run-length limited encoding method for generating an encoded sequence by performing run-length limited encoding on a digital signal sequence, and a bit indicating 0 among a plurality of bits included in the encoded sequence is It is at least one or more consecutive 0 continuous sections that exist continuously, and the length of the continuous zero section having the maximum length is not less than 0 and not more than the first allowable continuous length, and is included in the encoded sequence At least one continuous section in which a bit indicating one of a plurality of bits continuously exists, and the length of one continuous section having the maximum length is shorter than the second allowable continuous length. Thus, the first encoded sequence is generated. The run-length limited encoding method may generate an encoded sequence with the first allowable continuous length and the second allowable continuous length as the same length. According to this aspect, by limiting both the continuous length of 0 and the continuous length of 1 included in the encoded sequence by the run-length limited encoding unit, an encoded sequence having a better restriction on the continuous length is generated. it can.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  Before specifically describing the third embodiment of the present invention, an outline of a storage system according to the third embodiment will be described first. The storage system according to the third embodiment includes a hard disk controller, a magnetic disk device, and a read / write channel including a read channel and a write channel. In the light channel, run-length limited coding, DC-free coding, and LDPC coding are executed as coding. In the read channel, data detection using a Viterbi algorithm or the like and LDPC decoding are performed. In this data detection, it is known that detection accuracy deteriorates due to the presence of a DC component. Furthermore, the correction capability of LDPC decoding decreases due to the deterioration of detection accuracy. Therefore, in the third embodiment of the present invention, the configuration is such that DC-free encoding for reducing the DC component is performed before the LDPC encoding. Note that the storage system according to the third embodiment is not limited to LDPC encoding, and may be configured to execute another error correction encoding scheme, for example, turbo encoding or convolutional encoding.

  DC-free coding is realized by selecting a sequence having higher DC-free property from two different sequences. When RLL encoding having two different properties is performed in order to generate two different sequences, the circuit scale increases as the second RLL encoding circuit is required. Even in the case of an application that does not pose a problem in circuit scale, as a result of executing RLL coding having two different properties, both sequences are not always good in DC-freeness. Therefore, in the third embodiment, the same RLL encoding is executed.

  Here, when executing the same RLL encoding, it is necessary to avoid that the sequences to be selected are the same. It is also necessary to avoid the case where there is no restricted coding sequence with good DC-free characteristics. Therefore, in the third embodiment, a sequence obtained by RLL encoding and two sequences obtained by inverting the sequence are selected. In RLL encoding, not only 0 but also the continuous length of 1 is limited. As a result, the RLL characteristics can be guaranteed not only in the sequence obtained by RLL coding but also in the inverted sequence. The two sequences to be generated have substantially the same DC-free property, but by averaging over several intervals, a sequence having a statistically good DC-free property can be generated. Therefore, the encoding device according to the third embodiment can improve both the RLL characteristic and the DC-free property. In addition, since the encoding apparatus according to the third embodiment is realized with a simple configuration such as a single RLL encoding unit and an inverting unit, the circuit scale can be reduced. Furthermore, since the encoding apparatus according to the third embodiment can generate an encoded sequence having a high DC-free property without setting the encoding rate low, the encoding rate such as a hard disk cannot be set low. Suitable for applications. Details will be described later.

  Hereinafter, the third embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 21 is a diagram showing a configuration of a storage system 2100 according to the third embodiment of the present invention. The storage system 2100 of FIG. 21 is broadly divided into a hard disk controller 2001 (hereinafter abbreviated as “HDC 2001”), a central processing unit 2002 (hereinafter abbreviated as “CPU 2002”), and a read / write channel 2003 (hereinafter abbreviated as “CPU 2002”). , Abbreviated as “R / W channel 2003”), voice coil motor / spindle motor control unit 2004 (hereinafter abbreviated as “VCM / SPM control unit 2004”), and disk enclosure 2005 (hereinafter “DE2005”). Abbreviated as)). In general, the HDC 2001, the CPU 2002, the R / W channel 2003, and the VCM / SPM control unit 2004 are configured on the same substrate.

  The HDC 2001 includes a main control unit 2011 that controls the entire HDC 2001, a data format control unit 2012, an error correction coding control unit 2013 (hereinafter abbreviated as “ECC control unit 2013”), and a buffer RAM 2014. The HDC 2001 is connected to the host system via an interface unit (not shown). Further, it is connected to the DE 2005 via the R / W channel 2003, and executes data transfer between the host and the DE 2005 under the control of the main control unit 2011. A read reference clock (RRCK) generated by the R / W channel 2003 is input to the HDC 2001. The data format control unit 2012 converts data transferred from the host into a format suitable for recording on the disk medium 2050, and conversely, suitable for transferring data reproduced from the disk medium 2050 to the host. Convert to format. The disk medium 2050 includes, for example, a magnetic disk. The ECC control unit 2013 adds redundant symbols using data to be recorded as information symbols in order to enable correction and detection of errors included in data reproduced from the disk medium 2050. The ECC control unit 2013 determines whether or not an error has occurred in the reproduced data, and corrects or detects when there is an error. However, the number of symbols that can correct errors is limited, and is related to the length of redundant data. That is, if a large amount of redundant data is added, the format efficiency deteriorates, so that there is a trade-off with the number of error correctable symbols. When error correction is performed using Reed-Solomon (RS) code as ECC, up to (number of redundant symbols / 2) errors can be corrected. The buffer RAM 2014 temporarily stores data transferred from the host and transfers the data to the R / W channel 2003 at an appropriate timing. Conversely, the read data transferred from the R / W channel 2003 is temporarily stored, and transferred to the host at an appropriate timing after the ECC decoding process or the like is completed.

  The CPU 2002 includes a flash ROM 2021 (hereinafter abbreviated as “FROM 2021”) and a RAM 2022, and is connected to the HDC 2001, the R / W channel 2003, the VCM / SPM control unit 2004, and the DE 2005. The FROM 2021 stores an operation program for the CPU 2002.

  The R / W channel 2003 is roughly divided into a write channel 2031 and a read channel 2032, and transfers data to be recorded and reproduced data to and from the HDC 2001. The R / W channel 2003 is connected to the DE 2005, and executes a recording signal transmission process and a reproduction signal reception process. Details will be described later.

  A VCM / SPM control unit 2004 controls a voice coil motor 2052 (hereinafter abbreviated as “VCM2052”) and a spindle motor 2053 (hereinafter abbreviated as “SPM2053”) in DE 2005.

  The DE 2005 is connected to the R / W channel 2003 and executes reception of a recording signal and transmission of a reproduction signal. The DE 2005 is connected to the VCM / SPM control unit 2004. The DE 2005 includes a disk medium 2050, a head 2051, a VCM 2052, an SPM 2053, a preamplifier 2054, and the like. In the storage system 2100 of FIG. 21, it is assumed that there is one disk medium 2050 and the head 2051 is disposed only on one surface side of the disk medium 2050. A stacked arrangement may be used. The head 2051 is generally provided corresponding to each surface of the disk medium 2050. The recording signal transmitted by the R / W channel 2003 is supplied to the head 2051 via the preamplifier 2054 in the DE 2005 and is recorded on the disk medium 2050 by the head 2051. Conversely, a signal reproduced from the disk medium 2050 by the head 2051 is transmitted to the R / W channel 2003 via the preamplifier 2054. The VCM 2052 in the DE 2005 moves the head 2051 in the radial direction of the disk medium 2050 in order to position the head 2051 at a target position on the disk medium 2050. Further, the SPM 2053 rotates the disk medium 2050.

  Here, the R / W channel 2003 will be described with reference to FIG. FIG. 22 is a diagram showing a configuration of the R / W channel 2003 of FIG. The R / W channel 2003 is roughly composed of a write channel 2031 and a read channel 2032.

  The write channel 2031 includes a byte interface unit 2301, a scrambler 2302, a run length restriction and DC free encoding unit 2303 (hereinafter abbreviated as “RLL / DC free encoding unit 2303”), and a low density parity check encoding unit. 2304 (hereinafter abbreviated as “LDPC encoding unit 2304”), write compensation unit 2305 (hereinafter abbreviated as “write pre-con unit 2305”), and driver 2306.

  The byte interface unit 2301 processes the data transferred from the HDC 2001 as input data. Data to be written on the medium is input from the HDC 2001 in units of one sector. At this time, not only user data (512 bytes) for one sector but also ECC bytes added by the HDC 2001 are input simultaneously. The data bus is normally 1 byte (8 bits), and is processed as input data by the byte interface unit 2301. The scrambler 2302 converts the write data into a random series. This is because the repetition of data with the same rule adversely affects the detection performance at the time of reading and prevents the error rate from deteriorating.

  The RLL / DC free encoding unit 2303 is for limiting the maximum continuous length of 0 and 1. By limiting the maximum continuous length of 0 and the maximum continuous length of 1, a data series suitable for the automatic gain control unit 2317 (hereinafter abbreviated as “AGC2317”) or the like is obtained. Furthermore, the direct current component is reduced, the data detection capability is improved, and the error correction capability is improved. Details will be described later.

  The LDPC encoding unit 2304 has a role of generating a sequence including parity bits, which are redundant bits, by LDPC encoding the data sequence. LDPC encoding is performed by multiplying a k × n matrix called a generator matrix by a data sequence of length k from the left. Each element included in the parity check matrix H corresponding to this generator matrix is 0 or 1, and since the number of 1 is smaller than the number of 0, it is called a low density parity check code (Low Density Parity Check Codes). It is. By using this arrangement of 1 and 0, the LDPC iterative decoding unit can efficiently correct errors.

  The write pre-con unit 2305 is a circuit that compensates for non-linear distortion caused by a continuous magnetization transition on the medium. A rule necessary for compensation is detected from the write data, and the write current waveform is adjusted in advance so that the magnetization transition occurs at the correct position. The driver 2306 is a driver that outputs a signal corresponding to the pseudo ECL level. The output from the driver 2306 is sent to the DE 2005 (not shown), sent to the head 2051 through the preamplifier 2054, and the write data is recorded on the disk medium 2050.

  The read channel 2032 includes a variable gain amplifier 2311 (hereinafter abbreviated as “VGA 2311”), a low-pass filter 2312 (hereinafter abbreviated as “LPF 2312”), an AGC 2317, an analog / digital converter 2313 (hereinafter “ADC 2313”). A frequency synthesizer 2314, a filter 2315, a soft output detection unit 2320, an LDPC iterative decoding unit 2322, a synchronization signal detection unit 2321, a run length limited / DC free decoding unit 2323 (hereinafter referred to as “RLL / DC free decoding”). Abbreviated as “part 2323”) and a descrambler 2324.

  The VGA 2311 and the AGC 2317 adjust the amplitude of the read waveform of data sent from the preamplifier 2054 (not shown). The AGC 2317 compares the ideal amplitude with the actual amplitude, and determines the gain to be set in the VGA 2311. The LPF 2312 can adjust the cut-off frequency and the boost amount, and is responsible for part of the reduction to high frequency noise and equalization to a partial response (hereinafter referred to as “PR”) waveform. The LPF 2312 performs equalization to the PR waveform, but it is difficult to completely equalize with the analog LPF due to many factors such as head flying height fluctuation, medium non-uniformity, and motor rotation fluctuation. Then, equalization to the PR waveform is performed again using the filter 2315 having more flexibility. The filter 2315 may have a function of adaptively adjusting the tap coefficient. The frequency synthesizer 2314 generates a sampling clock for the ADC 2313.

  The ADC 2313 is configured to obtain a synchronous sample directly by AD conversion. In addition to this configuration, an asynchronous sample may be obtained by AD conversion. In this case, a zero-phase restart unit, a timing control unit, and an interpolation filter may be further provided after the ADC 2313. Synchronous samples need to be obtained from asynchronous samples, and these blocks play that role. The zero phase restart unit is a block for determining an initial phase, and is used to obtain a synchronization sample as soon as possible. After determining the initial phase, the timing controller compares the ideal sample value with the actual sample value to detect a phase shift. A synchronous sample can be obtained by determining parameters of the interpolation filter using this.

  The soft output detection unit 2320 is a soft output Viterbi algorithm (Soft-Output Viterbi Algorithm; hereinafter abbreviated as “SOVA”), which is a type of Viterbi algorithm, in order to avoid degradation of decoding characteristics due to intersymbol interference. Used. That is, in order to solve the problem that the interference between recorded codes increases and the decoding characteristics deteriorate as the recording density of magnetic disk devices increases in recent years, a partial response due to intersymbol interference is a method for overcoming this problem. The most likely decoding (Partial Response Maximum Like Like) (hereinafter abbreviated as “PRML”) method is used. PRML is a method for obtaining a signal sequence that maximizes the likelihood of a partial response of a reproduction signal.

  When the SOVA method is used as the soft output detection unit 2320, a soft decision value is output. For example, assume that a soft decision value (−0.71, +0.18, +0.45, −0.45, −0.9) is output as the SOVA output. These values represent numerical values as to whether the possibility of being 0 or 1 is high. For example, the first “−0.71” indicates that the possibility of 1 is large, and the second “+0.18” is likely to be 0, but the possibility of 1 is small. Means no. The output of the conventional Viterbi detector is a hard value, and the output of SOVA is hard-decided. In the case of the above example, it is (1, 0, 0, 1, 1). The hard value represents only whether it is 0 or 1, and information on which is more likely is lost. For this reason, decoding performance is improved by inputting a soft decision value to the LDPC iterative decoding unit 2322.

  The LDPC iterative decoding unit 2322 has a role of restoring an LDPC encoded data sequence to a sequence before LDPC encoding. As a decoding method, there are mainly a sum-product decoding method and a min-sum decoding method. The sum-product decoding method is advantageous in terms of decoding performance, but the min-sum decoding method is realized by hardware. With the feature that is easy. In an actual decoding operation using an LDPC code, very good decoding performance can be obtained by repeatedly decoding between the soft output detection unit 2320 and the LDPC iterative decoding unit 2322. For this reason, a configuration in which a plurality of stages of software output detection units 2320 and LDPC iterative decoding units 2322 are arranged is actually required. The synchronization signal detection unit 2321 has a role of detecting a synchronization signal (Sync Mark) added to the head of data and recognizing the head position of the data.

  The RLL / DC free decoding unit 2323 performs the reverse operation of the RLL / DC free encoding unit 2303 of the write channel 2031 on the data output from the LDPC iterative decoding unit 2322 to restore the original data series. Details will be described later.

  The descrambler 2324 performs the reverse operation of the scrambler 2302 of the write channel 2031 to restore the original data series. The data generated here is transferred to the HDC 2001.

  Here, “DC free” will be described. FIGS. 23A to 23B are diagrams illustrating examples of DC-free characteristics according to the third embodiment of the present invention. FIG. 23A is a diagram showing an example of the distribution of soft decision values when DC is free and when it is not. The horizontal axis represents the number, and the vertical axis represents the soft decision value. The vertical axis is an axis including ± 0 on the center and including both positive and negative soft decision values. A first characteristic 2200 indicated by a solid line indicates a distribution in the case of DC free. A second characteristic 2300 indicated by a broken line indicates an example of distribution when DC free. As described above, “DC free” indicates that the ratio of the number of 0 and 1 bits included in the sequence is 50%. In other words, as shown in the first characteristic 2200 of FIG. 23A, in the distribution of the soft decision values in the LDPC iterative decoding unit 2322 of FIG. 22, ± 1/2 is the central value, and the distribution around ± 0. It means that the amount is small. On the other hand, when not DC-free, for example, as illustrated in the second characteristic 2300 of FIG. 23A, in the distribution of the soft decision value, the distribution amount near ± 0 is increased.

  FIG. 23B is a diagram illustrating an example of bit error rate characteristics when the DC is free and when it is not. The horizontal axis represents a signal-to-noise ratio (Signal to Noise Ratio), and the vertical axis represents a bit error rate (Bit Error Rate). A third characteristic 2210 indicated by a solid line indicates a bit error rate characteristic when DC is free. A fourth characteristic 2310 indicated by a broken line indicates a bit error rate characteristic when the DC is not free. As shown in the figure, the bit error rate is worse in the case where DC is not free than in the case where DC is free.

  FIG. 24 is a diagram illustrating a configuration example of the RLL / DC free encoding unit 2303 in FIG. The RLL / DC free encoding unit 2303 includes an RLL encoding unit 2060, a first signal processing unit 2062, and a direct current component removal encoding unit 2066.

  The RLL encoding unit 2060 generates a first encoded sequence by subjecting the digital signal sequence output from the scrambler 2302 to run-length limited encoding. The first signal processing unit 2062 performs predetermined signal processing on the first encoded sequence without changing the number of bits included in the first encoded sequence output from the RLL encoding unit 2060. Thus, a second encoded sequence is generated. The predetermined signal processing may be any processing as long as the number of bits included in the digital signal sequence is not changed. For example, a process of executing a bit inversion process for each of a plurality of bits included in the digital signal sequence may be used. The DC component removal encoding unit 2066 has a high DC-free property among the first encoded sequence generated by the RLL encoding unit 2060 and the second encoded sequence generated by the first signal processing unit 2062. Either one of the encoded sequences is selected and output. Here, when the digital signal sequence to be processed is composed of 300 bits, the RLL / DC free encoding unit 2303 processes 30 bits as one set and is divided into 10 times. Here, when the coding rate of the RLL coding unit 2060 is 30/31, the number of bits per sequence output from the RLL coding unit 2060 and the first signal processing unit 2062 is 31 bits. Become.

  In general, RLL encoding is performed according to the rule (d, k) so that the continuous length of “0” existing in the signal sequence is limited. The rule (d, k) is that a signal sequence generated as a result of RLL encoding is such that the number of “0” existing between two “1” s in the signal sequence is not less than d and not more than k. It is a rule that requires to be. Here, “two“ 1 ”s” in a signal sequence means two adjacent “1” s when all “0” s are removed from the signal sequence. For example, if the rule (d, k) is (0, 3), it can be said that the signal sequence “0110100010” satisfies the rule. On the other hand, when the rule (d, k) is (1, 3), it cannot be said that the signal sequence “0110100010” satisfies the rule. This is because the number of “0” s between “1” of the second bit in the signal sequence and “1” of the third bit adjacent thereto is 0, and the condition of 1 to 3 is not satisfied. . In other words, if d is not 0 in the rule (d, k), it can be said that the condition is severe. Note that d and k in the rule (d, k) are both integers of 0 or more.

  In the RLL encoding unit 2060 of the third embodiment, the rule (d, k) is applied not only to “0” but also to “1” as described above. “Apply rule (d, k) for“ 1 ”” indicates that the number of “1” existing between two “0” s in the signal sequence is not less than d and not more than k. That is, the RLL encoding unit 2060 applies the rule (d0, k0) for the continuous length of “0” and applies the rule (d1, k1) for the continuous length of “1”. And the continuous length of both “1” are simultaneously limited. Furthermore, the RLL encoding unit 2060 outputs the first encoded sequence in which the continuous lengths of both “0” and “1” are simultaneously limited to the DC component removal encoding unit 2066 and also the first signal processing unit 2062 Then, the second encoded sequence obtained by inverting the encoded sequence is output to DC component removal encoding section 2066. By taking such an aspect, both of the two encoded sequences input to the DC component removal encoding unit 2066 can satisfy the RLL characteristic. In other words, the first encoded sequence satisfies the rule (d0, k0) for “0”, the rule (d1, k1) for 1, and the second encoded sequence satisfies the rule (0 for “0”). d1, k1) and the rule (d0, k0) is satisfied for 1.

In the two rules (d0, k0) and (d1, k1) in the third embodiment, d0 and d1 are preferably set to values of 0 for both. As described above, in the rule (d, k), when d is not 0, the condition is severe, and the coding rate is significantly reduced. Further, k0 and k1 are preferably set as a value of k1 or more. This is because in the storage system 2100 according to the third embodiment, priority is given to limiting the continuous length of “0”. More preferably, it may be set as k0 = k1. This is because if the number of “1” s included in the signal sequence is too small, the performance of the AGC 2317 and the timing control unit (not shown) in FIG. 22 may deteriorate or may not operate normally. Needless to say, k0 and k1 are non-zero integers, and values larger than d0 and d1 must be set, respectively. In summary, d0, k0, d1, and k1 in the two rules (d0, k0) and (d1, k1) are preferably set so as to have the relationship shown below. When set as follows, the first encoded sequence generated by the RLL encoding unit 2060 and the first signal processing unit 2062 and the second encoded sequence obtained by inverting the first encoded sequence are the same The RLL characteristics are as follows.
d0 = d1 = 0
k0 = k1> 0

  FIG. 25 is a diagram illustrating a configuration example of the DC component removal coding unit 2066 of FIG. The DC component removal encoding unit 2066 includes an encoded sequence selection unit 2074, a selection identification information generation unit 2076, and an identification information addition unit 2078. The encoded sequence selection unit 2074 selects either one of the first encoded sequence generated by the RLL encoding unit 2060 and the second encoded sequence generated by the first signal processing unit 2062. select. The selection identification information generation unit 2076 generates selection identification information indicating the encoded sequence selected by the encoded sequence selection unit 2074. The identification information adding unit 2078 adds the selection identification information generated by the selection identification information generation unit 2076 to any location of the encoded sequence selected by the encoded sequence selection unit 2074.

  This will be specifically described. When the first encoded sequence is selected by the encoded sequence selection unit 2074, the selection identification information added to the first encoded sequence by the identification information addition unit 2078 is “0”. On the other hand, when the second encoded sequence is selected by the encoded sequence selection unit 2074, the selection identification information added to the first encoded sequence by the identification information adding unit 2078 is “1”. In other words, the first encoded sequence to which selection identification information “0” is added or the second encoded sequence to which selection identification information “1” is added is output to LDPC encoding section 2304. It should be noted that the part to which the selection identification information is added by the identification information adding unit 2078 may be an arbitrary fixed part in the encoded sequence, and may be added to the end of the encoded sequence, for example. Although details will be described later, the selection identification information added here is a determination bit, and an appropriate decoding process is realized by analyzing the position of the determination bit added on the decoding side and the content of the determination bit. The Rukoto. In the specific example described above, 1-bit selection identification information is added to a 31-bit encoded sequence at a time, and a total of 32-bit sequences are output. That is, the coding rate in the entire RLL / DC free coding unit 2303 is 30/32.

  The encoded sequence selection unit 2074 may include a first connection unit and a second connection unit (not shown). The first concatenation unit concatenates the encoded sequence already selected by the encoded sequence selection unit 2074 and the first encoded sequence. The second concatenation unit concatenates the encoded sequence already selected by the encoded sequence selection unit 2074 and the second encoded sequence. In this case, the encoded sequence selection unit 2074 sets the sequence connected by the first connecting unit as a new first encoded sequence, sets the sequence connected by the second connecting unit as a new second encoded sequence, Either one of the encoded sequences may be selected. In other words, the encoded sequence selection unit 2074 performs selection determination on a concatenation of an encoded sequence selected in the past and an encoded sequence that is a candidate for current selection. DC-free characteristics can be improved.

  FIGS. 26A to 26C are diagrams illustrating first to third configuration examples of the encoded sequence selection unit 2074 in FIG. FIG. 26 (a) is a diagram illustrating a first configuration example of the coded sequence selection unit 2074 in FIG. The encoded sequence selection unit 2074 in the first configuration includes a first ratio calculation unit 2080, a second ratio calculation unit 2082, and a selection output unit 2084.

  The first ratio calculation unit 2080 calculates a ratio between a bit indicating 0 and a bit indicating 1 among a plurality of bits included in the first encoded sequence. Second ratio calculation section 2082 calculates a ratio between a bit indicating 0 and a bit indicating 1 among a plurality of bits included in the second encoded sequence. The selection output unit 2084 selects an encoded sequence corresponding to a ratio closer to 50% from the ratio calculated by the first ratio calculation unit 2080 and the ratio calculated by the second ratio calculation unit 2082. Output.

This will be described using a specific example. First, it is assumed that 31-bit encoded sequences are output from the RLL encoding unit 2060 and the first signal processing unit 2062 at time t = 1. In this case, the first ratio calculator 2080 and the second ratio calculator 2082 analyze the bits included in the respective encoded sequences and calculate the ratio. Here, among the bits included in the encoded sequence input to the first ratio calculation unit 2080, when the bit indicating 0 is 14 bits and the bit indicating 1 is 17 bits, the ratio is the first ratio calculation unit It is calculated by 2080 as follows.
Ratio _{t = 1} = (number of bits indicating 0 + 1) / (number of bits of coded sequence + 1) = (14 + 1) / (31 + 1) ≈46.9%

Of the bits included in the encoded sequence input to the second ratio calculation unit 2082, the bits indicating 0 are 17 bits and the bits indicating 1 are 14 bits. This is because the encoded sequence input to the second ratio calculator 2082 is a logical inversion of the encoded sequence input to the first ratio calculator 2080. Therefore, the ratio _{t = 1} is calculated by the second ratio calculator 2082 as follows. In the numerators on the right side of the previous equation and the following equation, “1” and “0” are added because the selection identification information is assumed to be “0” and “1”, respectively. is there. Further, the reason why “1” is added in the denominator of the right side of the previous equation and the following equation is to calculate the ratio of the number of 0s in the sequence including the selection identification information.
Ratio _{t = 1} = (number of bits indicating 0 + 0) / (number of bits of coded sequence + 1) = (17 + 0) / (31 + 1) ≈53.1%

  Here, if the ratio of the first encoded sequence and the second encoded sequence is expressed as “(50 ± α)%”, both are α = 3.1. Therefore, since any ratio can be said to be close to 50%, it is possible to select any encoded sequence. In such a case, the first encoded sequence is preferably selected. The first encoded sequence does not pass through the first signal processing unit 2062, and it is not necessary to execute processing corresponding to the first signal processing unit 2062 in the RLL / DC free decoding unit 2323 described later. Therefore, when the first encoded sequence is selected, the processing power in the storage system 2100 can be reduced. In the following description, it is assumed that the first encoded sequence is selected when α is the same at t = 0.

As described above, at t = 1, the selection output unit 2084 selects the first encoded sequence. In addition, the number of bits “14” indicating 0 according to the selected first encoded sequence is stored. Next, it is assumed that a 31-bit encoded sequence is output from the RLL encoding unit 2060 and the first signal processing unit 2062 at t = 2 as in the case of t = 1. Here, among the bits included in the encoded sequence input to the first ratio calculation unit 2080, when the bit indicating 0 is 11 bits and the bit indicating 1 is 20 bits, the ratio is calculated as follows: Is done.
Ratio _{t = 2} = (number of bits indicating 0 + 1) / ((number of bits of coded sequence + 1) × t) = (14 + 1 + 111 + 1) / ((31 + 1) × 2) ≈42.2%

  Unlike the case of t = 1, the first ratio calculation unit 2080 is a sequence in which the encoded sequence selected at t = 1 and the first encoded sequence at t = 2 are connected by the first connecting unit. Calculate the ratio for. That is, the number “14 + 1” of bits indicating 0 in the first encoded sequence selected at t = 1 and the number “11 + 1” of bits indicating 0 in the first encoded sequence at t = 2. It will be added in the numerator of the above formula. Further, the denominator in the above equation is the number of bits for two sets of encoded sequences.

Of the bits included in the encoded sequence input to the second ratio calculator 2082, the bits indicating 0 are 20 bits and the bits indicating 1 are 11 bits. Then, the ratio is calculated by the second ratio calculation unit 2082 as follows. In this case, since the ratio of the second encoded sequence is closer to 50%, the second encoded sequence is selected by the selection output unit 2084 at t = 2.
Ratio _{t = 2} = (number of bits indicating 0 + 0) / ((number of bits of coded sequence + 1) × t) = (14 + 1 + 20 + 0) / ((31 + 1) × 2) = 54.7%

Similarly, the ratio is calculated after t = 3. Here, the ratio at t = n is expressed as follows. However, n is an integer of 1 or more. Nbit (m) indicates the number of bits indicating 0 among the bits included in the encoded sequence selected at t = m. Nbit (n) indicates the number of bits indicating 0 among the bits included in the encoded sequence whose ratio is to be calculated. It is assumed that selection identification information is also included in the encoded sequence for which the ratio is calculated.

  FIG. 26B is a diagram illustrating a second configuration example of the encoded sequence selection unit 2074 in FIG. The encoded sequence selection unit 2074 in the second configuration includes a first summation unit 2086, a second summation unit 2088, and a selection output unit 2084. The first summation unit 2086 sums a plurality of bits included in the first encoded sequence to generate a first sum value. Second summation section 2088 sums a plurality of bits included in the second encoded sequence to generate a second sum value. The coded sequence detection unit compares the first sum value generated by the first summation unit 2086 with the second sum value generated by the second summation unit 2088, and compares the first coded sequence and the second code. An encoded sequence corresponding to the smaller sum of the converted sequences is detected. The selection output unit 2084 selects and outputs the encoded sequence detected by the sequence detection unit from the first encoded sequence and the second encoded sequence.

  This will be described using a specific example. First, it is assumed that a 31-bit encoded sequence is output from the RLL encoding unit 2060 and the first signal processing unit 2062 at t = 1. In this case, the first summation unit 2086 and the second summation unit 2088 sum the bits included in the respective encoded sequences. In the summation, 0 may be replaced with “+1” and 1 may be replaced with “−1” for total. By summing in this way, when the number of bits indicating 0 and 1 is equal, the sum is 0. Therefore, the selection output unit 2084 may select an encoded sequence having a combined value close to 0, for example, an encoded sequence having a small absolute value of the combined value. This method is also called continuous digital summation (hereinafter abbreviated as “RDS”).

Here, at t = 1, out of 31 bits included in the encoded sequence input to the first summing unit 2086, the bit indicating 0 is 14 bits, and the bit indicating 1 is 17 bits. Is calculated as follows. Note that “1” is added to the multiplicand of the first term on the right side because the selection identification information is assumed to be zero.
RDS _abs = | (14 + 1) × (+1) + 17 × (−1) | = 2

Of the bits included in the encoded sequence input to the second summing unit 2088, the bits indicating 0 are 17 bits, and the bits indicating 1 are 14. Therefore, the ratio is calculated as follows: Note that “1” is added in the second term on the right side because the selection identification information is assumed to be 1.
RDS _abs = | 17 × (+1) + (14 + 1) × (−1) | = 2

Here, at t = 1, since any RDS _abs has the same value for the first encoded sequence and the second encoded sequence, any encoded sequence may be selected. In other words, since the first encoded sequence and the second encoded sequence are in a logically inverted relationship, the RDS _abs are always the same. Here, “always the same” includes that the RDS at that time is the same. That is, even if the RDS _{abs at} t = 1 are the same, the RDS _{abs at} t = 2, which will be described later, are calculated after reflecting the RDS _abs selected at t = 1. Do not mean. Note that when the two RDS _abs are the same, the first coded sequence is preferably selected. The first encoded sequence does not pass through the first signal processing unit 2062, and it is not necessary to execute processing corresponding to the first signal processing unit 2062 in the RLL / DC free decoding unit 2323 described later. Therefore, when the first encoded sequence is selected, the processing power in the storage system 2100 can be reduced. In the following description, it is assumed that the first encoded sequence is selected at t = 1. Further, it is assumed that the RDS for the first coded sequence before calculating the absolute value is stored as “RDS ₁ = −2”.

Next, at t = 2, as in the case of t = 1, it is assumed that 31-bit encoded sequences are output from the RLL encoding unit 2060 and the first signal processing unit 2062, respectively. Here, among the bits included in the encoded sequence input to the first summation unit 2086, when the bit indicating 0 is 11 bits and the bit indicating 1 is 20 bits, the RDS is calculated as follows. The Unlike t = 1, at t = 2, the RDS for the encoded sequence selected at t = 1 is also taken into consideration.
RDS _abs = | RDS ₁ + (11 + 1) × (+1) + 20 × (−1) | = | −2 + (− 8) | = 10

Of the bits included in the encoded sequence input to the second summing unit 2088, the bits indicating 0 are 20 bits, and the bits indicating 1 are 11 bits. Therefore, the ratio is calculated as follows: In this case, since the RDS of the second encoded sequence is smaller, the second encoded sequence is selected by the selection output unit 2084 at t = 2. Also, RDS ₂ = 6 is stored.
RDS _abs = | RDS ₁ + 20 × (+1) + (11 + 1) × (−1) | = | −2 + (+ 8) | = 6

Similarly, RDS _abs is calculated after t = 3. Here, RDS _abs (n) at t = n is expressed as follows. However, t is an integer of 1 or more. Nbit0 (m) indicates the number of bits indicating 0 among the bits included in the encoded sequence selected at t = m and the selection identification information. Nbit1 (m) indicates the number of bits indicating 1 out of the bits included in the encoded sequence selected at t = m and the selection identification information. Here, Nbit0 (n) and Nbit1 (n) indicate the number of bits indicating 0 and the number of bits indicating 1 among the bits included in the encoded sequence for which the sum value is calculated, respectively.

Here, the convergence of RDS (n) in the third embodiment will be described. Here, RDS (n) indicates a value before calculating an absolute value in RDS _abs (n). Further, “convergence of RDS (n)” includes that n is infinite and RDS (n) is 0, RDS (n) does not diverge at least, and an arbitrary time t In this case, it includes vibrating around ± 0. By generating RDS (n) having such properties, good DC-free characteristics can always be maintained.

This will be described using a specific example. Here, it is assumed that RDS in each encoded sequence at time n = 1 to 5 is calculated as follows. Note that RDS1 (n) indicates RDS in the first encoded sequence, and RDS2 (n) indicates RDS in the second encoded sequence.
RDS1 (n) = {+ 5, +7, −1, −6, −4}
RDS2 (n) = {− 5, −7, +1, +6, +4}

Here, for n = 1, it is assumed that the RDS _abs are the same as described above and RDS1 (1) is selected. Then, RDS (n) calculated at n = 1 to 5 is expressed as follows.
RDS (n) = {5, -2, -1, 5, 1}

  The above equation indicates that when RDS (n) at an arbitrary time n is 0 or more, an encoded sequence having a negative RDS is selected and approaches 0 at the next time (n + 1). In addition, when RDS (n) at an arbitrary time n is 0 or less, an encoded sequence having a positive RDS is selected at the next time (n + 1) and approaches 0. Here, in the third embodiment, as described above, since the first encoded sequence and the second encoded sequence are sequences that are logically inverted from each other, RDS1 (n) and RDS2 (n) Is a value obtained by inverting the sign. Then, at any n, one RDS always has the sign of the other RDS inverted. Therefore, as shown in the above equation, RDS (n) does not diverge at any n, and has a property of oscillating around ± 0. In other words, by making the first encoded sequence and the second encoded sequence invert each other, RDS (n) can have good convergence, so that high DC-free characteristics are guaranteed, and Can be maintained. Furthermore, as described above, the first encoded sequence and the second encoded sequence have the same RLL characteristics. Therefore, by taking the mode shown in the third embodiment, the storage system 2100 can simultaneously improve the RLL characteristic and the DC free characteristic. Needless to say, the same effect can be obtained in the embodiment shown in FIG.

  The operation of the coded sequence selection unit 2074 described above is characterized in that the movement calculation process is performed between successive past times while performing the interval calculation process at a certain time. Thus, by combining the section process and the movement process, the DC-free property is improved in the long section, for example, the entire 300-bit sequence.

  In addition, the summation processing in the first summation unit 2086 and the second summation unit 2088 may add up the bits indicating 0 or 1 included in the encoded sequence as they are. In this case, in the selection output unit 2084, the encoded sequence corresponding to the sum closer to the half of the number of encoded sequences is selected.

  FIG. 26C is a diagram illustrating a third configuration example of the coded sequence selection unit 2074 in FIG. The encoded sequence selection unit 2074 in the third configuration includes a first mobile addition unit 2090, a first maximum value detection unit 2092, a second mobile addition unit 2094, a second maximum value detection unit 2096, and a selection output unit. 2084. The first moving addition unit 2090 generates the same number of first moving addition values as the plurality of bits by calculating the moving addition of the plurality of bits included in the first encoded sequence. The first maximum value detection unit 2092 detects the maximum value among the plurality of first movement addition values generated by the first movement addition unit 2090. The second moving addition unit 2094 generates the same number of second moving addition values as the plurality of bits by moving and adding the plurality of bits included in the second encoded sequence. The second maximum value detection unit 2096 detects the maximum value among the plurality of second movement addition values generated by the second movement addition unit 2094. The encoded sequence detection unit compares the maximum value detected by the first maximum value detection unit 2092 with the maximum value detected by the second maximum value detection unit 2096, and compares the first encoded sequence and the second code. An encoded sequence corresponding to the smaller maximum value is detected from the encoded sequences. The selection output unit 2084 selects and outputs the encoded sequence detected by the sequence detection unit from the first encoded sequence and the second encoded sequence.

  As in the second configuration example, the third configuration example of the encoded sequence selection unit 2074 is obtained by calculating the RDS of each encoded sequence in the first mobile addition unit 2090 and the second mobile addition unit 2094. The selection output unit 2084 selects an encoded sequence. In the third configuration example, an encoded sequence that is close to 0 in consideration of only the final calculated value of the 32-bit RDS calculation is selected in that the encoded sequence having the smaller maximum value during the calculation of the 32-bit RDS is selected. This is different from the second configuration example in which is selected. In other words, in the third configuration example, the selection process is performed by the movement calculation in both the predetermined section and the plurality of sections. By taking such an aspect, it is possible to select a sequence having good DC-free properties even in the middle of the section.

Here, the “maximum value during calculation of RDS” is derived as follows for each time t. However, Min {y (0), y (1)} indicates a function that selects a smaller value and outputs the number of the selected sequence. For example, when y (0)> y (1), S (t) is 1. Further, max {x} indicates a function for detecting the maximum value of x. N represents a value in the range of (t−1) × 32 + 1 to 32 × t. Bit (m, j) indicates +1 when the m-th bit is 0 in the j-th encoded sequence, and indicates -1 when it is 1.
S (t) = Min {MaxRDS (1), MaxRDS (2)}
MaxRDS (1) = max {RDS (n, 1)}
MaxRDS (2) = max {RDS (n, 2)}

Bit (m, 1) and Bit (m, 2) are calculated after rewriting the bits related to the selected sequence as follows each time t increases.
Bit (m, 1) = Bit (m, 2) = Bit (m, S (t−1)): m = (t−1) × 32 + 1 to t × 32, t ≠ 1

Here, the operation of the third configuration example of the encoded sequence selection unit 2074 shown in FIG. 26C is compared with the operation of the second configuration example of the encoded sequence selection unit 2074 shown in FIG. . FIG. 27 is a diagram illustrating a difference in operation of the coded sequence selection unit 2074 illustrated in FIG. 26B and FIG. 26C, respectively. The horizontal axis represents time, and the vertical axis represents RDS. Here, 2400A indicates transition of RDS in the first encoded sequence. 2400B indicates transition of RDS in the second encoded sequence. In the second configuration example of the encoded sequence selection unit 2074 shown in FIG. 26B, RDS _A and RDS _B which are final values of the RDS interval calculation are compared, and the smaller encoded sequence is selected. . In FIG. 27, since RDS _A <RDS _B , the selection output unit 2084 selects the first encoded sequence. On the other hand, in the third configuration example of the encoded sequence selection unit 2074 shown in FIG. 26 (c), the RDS in each bit, that is, the maximum value among the absolute values after the 32 bits are sequentially subjected to the movement calculation process. Compare the values and select the smaller encoded sequence. In FIG. 27, MaxA is the maximum value for the first encoded sequence, and MaxB is the maximum value for the second encoded sequence. Here, since MaxA> MaxB, the selection output unit 2084 selects the second encoded sequence. Even when any configuration example is applied to the encoded sequence selection unit 2074, it is possible to select an encoded sequence having a high DC-free property.

  FIG. 28 is a diagram illustrating a configuration example of the RLL / DC free decoding unit 2323 of FIG. The RLL / DC free decoding unit 2323 includes a determination bit acquisition unit 2068, an RLL decoding unit 2070, and a second signal processing unit 2072. Determination bit acquisition unit 2068 acquires a predetermined determination bit added to the encoded sequence input by LDPC iterative decoding unit 2322. The second signal processing unit 2072 performs signal processing opposite to the predetermined signal processing executed by the first signal processing unit 2062 on the encoded sequence according to the determination bit acquired by the determination bit acquisition unit 2068. The process to output is executed. For example, when the bit inversion process is performed in the first signal processing unit 2062 of FIG. Or according to the determination bit acquired by the determination bit acquisition part 2068, the 2nd signal processing part 2072 performs the process which outputs the some bit contained in an encoding series as it is. The RLL decoding unit 2070 generates a digital signal sequence by performing run-length limited decoding on the encoded sequence output by the second signal processing unit 2072.

  These configurations described above can be realized in hardware by a CPU, memory, or other LSI of an arbitrary computer, and in software by a program having a communication function loaded in the memory. Here, functional blocks realized by the cooperation are depicted. Accordingly, those skilled in the art will understand that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof.

  According to the third embodiment, a relationship in which a generated sequence is logically inverted by targeting an RLL-encoded signal sequence and a signal sequence that has undergone bit inversion processing on the signal sequence. Therefore, since the calculated RDS (n) can have good convergence by making the first encoded sequence and the second encoded sequence invert each other, high DC-free characteristics can be obtained. Guaranteed and maintainable. Furthermore, as described above, the first encoded sequence and the second encoded sequence have the same RLL characteristics. Therefore, by taking the mode shown in the third embodiment, the storage system 2100 can simultaneously improve the RLL characteristic and the DC free characteristic. Further, by performing bit inversion processing, different sequences can be generated without increasing the number of bits included in the sequence.

  Further, since the number of bits included in the sequence does not increase, an encoded sequence can be obtained without reducing the overall encoding rate. Further, by adding information indicating that any of the encoded sequences has been selected to the encoded sequence, the selected encoded sequence can be easily discriminated on the decoding side. In addition, the encoded sequence selection unit 2074 performs selection determination on a combination of the encoded sequence selected in the past and the encoded sequence that is currently selected as a candidate, so that in the long section DC-free characteristics can be improved. In the encoded sequence selection unit 2074, the RDS is calculated by combining the interval process and the movement process, whereby the DC-free property can be improved in the long interval, for example, the entire 300-bit sequence. Also, by selecting the one where the ratio of the bit indicating 0 and the bit indicating 1 is close to 50%, it is possible to select an encoded sequence having a high DC-free property. In addition, by adding a plurality of bits included in the encoded sequence and selecting a sequence corresponding to a smaller combined value, an encoded sequence having a high DC-free property can be selected. Further, by selecting a sequence using the maximum value among the results obtained by moving and adding a plurality of bits included in the encoded sequence, an encoded sequence having a high DC-free property can be selected. The original digital signal sequence can be decoded by executing a process corresponding to the DC-free encoding executed on the encoding side. By executing the encoding process with high DC-free property, the storage system can be accessed at higher speed. Moreover, since it is not necessary to install extra hardware, a low-scale semiconductor integrated circuit can be realized.

  In the third embodiment, the R / W channel 2003 may be integrated on a single semiconductor substrate. Further, the coding sequence selection unit 2074 of the third embodiment has been described as the interval calculation process or the movement calculation process. However, the present invention is not limited to this, and an encoded sequence having a high DC-free property may be selected by performing section average processing or moving average processing. Even in this case, the same effect can be obtained.

(Fourth embodiment)
The fourth embodiment relates to a technology for accessing a storage medium, and more particularly, to an amplitude adjustment device, an amplitude adjustment method, and a storage system that adjust the amplitude of a signal read from the storage medium.

  The background art of the fourth embodiment will be described.

  In recent years, storage devices using hard disks are becoming essential devices in various fields such as personal computers, hard disk recorders, video cameras, and mobile phones. Storage devices using a hard disk have various specifications required depending on the field to which they are applied. For example, a hard disk mounted on a personal computer is required to have high speed and large capacity. However, since the amount of data handled per unit time increases as the speed increases, errors per unit time also increase proportionally. Then, it becomes difficult to correct all errors, and as a result, the time required to access the hard disk may increase, which becomes a bottleneck for speeding up.

  Generally, a magnetoresistive element (MagnetoResitive) has been used as an element for reading a signal stored in a storage device. However, the reproduced signal waveform read from the storage device via the magnetoresistive element has a problem that the output amplitude of the positive pulse and the output amplitude of the negative pulse are asymmetric (hereinafter referred to as “amplitude asymmetry”). (For example, see Non-Patent Document 1). The problem of amplitude asymmetry (Amplitude Asymmetry) occurs when the output amplitude of either the positive pulse or the negative pulse is reduced by the magnetoresistive element, and the dynamic range of both pulses is different. . When the asymmetry of the amplitude appears remarkably, the detection accuracy of the data detection process executed in the subsequent stage of the magnetoresistive element deteriorates. If it does so, the correction capability of the error correction decoding performed after data detection will reduce. In such a case, it is necessary to access the storage device again in order to correctly reproduce the data stored in the storage device, so that it is difficult to increase the speed of the storage device. As a technique for eliminating this asymmetry, conventionally, a bias magnetic field applied to the magnetoresistive element has been controlled (see, for example, Japanese Patent Laid-Open No. 4-205903). Further, the asymmetry is corrected by adjusting the zero level of the analog / digital converter (see, for example, Japanese Patent Application Laid-Open No. 5-205205). Further, the asymmetry is corrected by feeding back the result after the error correction processing (see, for example, JP-A-11-238205).

Akihiko Takeo, et. al. , “Characterization of GMR Nonlinear Response and the Impact on BER in Permendicular Magnetic Recording”, IEEE Transactions on Magnetics, July, 2004. 40, no. 4

  A problem to be solved by the fourth embodiment will be described.

  Under such circumstances, the present inventor has come to recognize the following problems. That is, depending on the analog circuit, the operation becomes unstable, so that it is difficult to correct nonlinearity accurately, and the circuit scale increases. On the other hand, when nonlinearity is corrected by digital processing, there are problems such as generation of a delay associated with a feedback loop or increase in circuit scale accompanying an increase in the number of bits in an analog / digital converter.

  The fourth embodiment of the present invention has been made in view of such circumstances, and a general purpose thereof is to provide a storage device that can reduce amplitude asymmetry with a smaller circuit scale.

  In order to solve the above-described problem, an amplitude adjustment device according to an aspect of a fourth embodiment of the present invention includes an input unit and an analog-digital conversion unit. The input unit is an analog signal output via a magnetoresistive element, and the dynamic range in the positive section and the dynamic range in the negative section are asymmetric, and an analog signal including a non-linear section in one of the sections is input. . When the amplitude of the analog signal input from the input unit is present in the nonlinear section, the analog-to-digital conversion unit converts the analog signal into a digital signal while adjusting the amplitude, and outputs the digital signal. The analog-to-digital conversion unit includes a pre-adjustment unit that adjusts the amplitude of the analog signal so as to cancel the non-linearity in the non-linear period before converting the analog signal into the digital signal.

  Here, the “nonlinear section” includes a section in which the amplitude of an analog signal input to the magnetoresistive element is distorted and output in the input / output characteristics of the magnetoresistive element. In addition, “the pre-adjustment unit that adjusts the amplitude of the analog signal so as to cancel the non-linearity in the non-linear section” means that the input / output characteristics are the reverse of the input / output characteristics in the non-linear section or approximate to the reverse characteristics Including a precorrector having the above characteristics.

  According to this aspect, the non-linearity of the amplitude generated in the magnetoresistive element can be canceled by adjusting the amplitude of the analog signal in the analog-to-digital converter. Further, by canceling the non-linearity of the amplitude generated in the magnetoresistive element, it is possible to improve the detection accuracy of data detection executed in the subsequent stage. Further, it is possible to improve error characteristics after error correction decoding executed in the subsequent stage.

  The pre-adjusting unit may adjust the amplitude of the analog signal in the nonlinear interval by setting the input / output characteristics in the nonlinear interval to a value corresponding to the inverse of the hyperbolic tangent function. In the plurality of partial sections included in the non-linear section, the pre-adjustment unit is set with a linear function having a first slope greater than at least 1 as input / output characteristics of the first partial section of the plurality of partial sections. Also, a linear function having a slope different from the first slope may be set as the input / output characteristics of the second partial section that is continuous with the first partial section among the plurality of partial sections. Here, the “value corresponding to the reciprocal of the hyperbolic tangent function” includes at least a value approximating the input / output characteristics of the hyperbolic tangent function, for example, the input / output characteristics of the hyperbolic tangent function and the n-order function (n is 1 A plurality of values obtained by adding, subtracting, multiplying, or dividing the above input / output characteristics. Further, “continuous” includes that the end point of the first partial section and the start point of the second partial section match, and the start point of the first partial section and the end point of the second partial section match. Including.

  The pre-adjustment unit may include a plurality of resistance elements and a comparison unit. The plurality of resistance elements are a plurality of resistance elements installed in series, and each receives a reference signal having a constant voltage and sequentially outputs a reference signal whose amplitude is adjusted to the subsequent resistance element. The comparison unit adjusts the amplitude of the analog signal by comparing the reference signal output from each of the plurality of resistance elements with the amplitude of the analog signal input from the input unit. Further, the width of the amplitude adjustment of the plurality of resistance elements may be changed by making the resistance values of the respective resistance elements non-uniform. Moreover, the resistance element corresponding to the non-linear section among the plurality of resistance elements is set to a resistance value different from the resistance value of the resistance element corresponding to the section other than the non-linear section, thereby adjusting the non-linearity in the non-linear section. Also good. Here, “to make the resistance value of each resistance element non-uniform” means that the resistance value of at least one or more of the resistance elements is different from the resistance value of other resistance elements. In addition, in a plurality of resistance elements, a plurality of resistance elements having the same resistance value may exist. According to this aspect, the analog signal amplitude asymmetry can be reduced with a small circuit by simply setting the resistance values of the plurality of resistance elements included in the analog-digital conversion unit.

  The pre-adjusting unit is connected to an input terminal of at least one of the plurality of resistance elements, and applies a corresponding reference voltage to each of the input terminals, so that each of the plurality of resistance elements And a reference voltage control unit that adjusts the amplitude of the output reference signal. In this case, the plurality of resistance elements may have the same resistance value. Further, the reference voltage control unit applies a reference voltage different from the input end of the resistance element corresponding to the section other than the non-linear section to the input end of the resistance element corresponding to the non-linear section among the plurality of resistance elements. The nonlinearity in the nonlinear section may be adjusted. Here, the “corresponding reference voltage” includes a reference voltage determined in association with each resistive element, may be set in advance, and dynamically changes according to the quality of the magnetoresistive element. May be. According to this aspect, the reference voltage controller can flexibly control the amplitude of the reference signal. Further, since the resistance values of the plurality of resistance elements included in the analog-digital conversion unit can be made the same, the circuit cost can be reduced. In addition, the amplitude asymmetry of the analog signal can be reduced with a small circuit.

  Another aspect of the fourth embodiment of the present invention is an amplitude adjustment method. The method includes an input step and an output step. The input step is an analog signal output via the magnetoresistive element, and the dynamic range in the positive section and the dynamic range in the negative section are asymmetric, and an analog signal including a non-linear section is input in one of the sections. To do. In the outputting step, the analog signal existing in the non-linear section is converted into a digital signal and output while adjusting the amplitude so as to cancel the non-linearity in the non-linear section. According to this aspect, the amplitude nonlinearity generated in the magnetoresistive element can be canceled by adjusting the amplitude of the analog signal in the outputting step. Further, by canceling the non-linearity of the amplitude generated in the magnetoresistive element, it is possible to improve the detection accuracy of data detection executed in the subsequent stage. Further, it is possible to improve error characteristics after error correction decoding executed in the subsequent stage.

  Yet another aspect of the fourth embodiment of the present invention is a storage system. This storage system is a signal storage system including a write channel for writing data to the storage device and a read channel for reading data stored in the storage device. The write channel includes a first encoding unit that performs run-length encoding of data, and a second encoding that encodes the data encoded by the first encoding unit using a low-density parity check code And a writing unit that writes the data encoded by the second encoding unit to the storage device. The read channel includes an input unit, an analog / digital conversion unit, a soft output detection unit, a first decoding unit, and a second decoding unit. The input unit is an analog signal output from the storage device via the magnetoresistive element, and the dynamic range in the positive section and the dynamic range in the negative section are asymmetric, and one of the sections includes a nonlinear section Enter. The analog-digital conversion unit converts the analog signal input from the input unit into a digital signal and outputs the digital signal. The soft output detection unit calculates the likelihood of the digital signal output from the analog-digital conversion unit and outputs a soft decision value. The first decoding unit decodes the data output from the soft output detection unit and corresponds to the second encoding unit. The second decoding unit decodes the data decoded by the first decoding unit and corresponds to the first encoding unit. The analog-to-digital conversion unit cancels the non-linearity in the non-linear section with respect to the analog signal before converting the analog signal to the digital signal when the amplitude of the analog signal input from the input unit exists in the non-linear section. A pre-adjustment unit for adjusting the amplitude; According to this aspect, it is possible to reduce the influence caused by the amplitude asymmetry generated in the magnetoresistive element, and to access the storage system at a higher speed.

  Yet another aspect of the fourth embodiment of the present invention is also a storage system. The storage system further includes a storage device that stores data, and a control unit that controls writing to the storage device and reading from the storage device. The read channel reads data stored in the storage device via the magnetoresistive element in accordance with an instruction from the control unit, and the write channel writes encoded data to the storage device in accordance with the instruction from the control unit. According to this aspect, it is possible to reduce the influence caused by the amplitude asymmetry generated in the magnetoresistive element, and to access the storage system at a higher speed.

  Yet another aspect of the fourth embodiment of the present invention is an amplitude adjusting device. This apparatus is integrated on a single semiconductor substrate. According to this aspect, a low-scale semiconductor integrated circuit can be realized by being integrated.

  Yet another aspect of the fourth embodiment of the present invention is a recorded information reading apparatus. The recorded information reading device inputs an analog signal input from an analog signal output from a reading unit that reads recorded information recorded on a disk, and inputs an analog signal from the analog signal input unit, and converts this into a digital signal. When the analog signal input level is either positive or negative, the relationship between the analog signal and the digital signal in the input / output characteristics is low and the analog signal input level is high. An analog-to-digital converter that differs depending on the case. The analog-to-digital conversion unit is a plurality of resistance elements installed in series, and receives a reference signal having a constant voltage as input and sequentially outputs a plurality of reference signals whose amplitudes are adjusted to the subsequent resistance elements. A comparison unit that adjusts an input level of the analog signal by comparing a resistance element, a reference signal output from each of the plurality of resistance elements, and an input level of the analog signal input from the input unit; You may have. The plurality of resistance elements may change the range of adjustment of the input level by making the resistance values of the respective resistance elements non-uniform.

  Yet another aspect of the fourth embodiment of the present invention is a recorded information reading apparatus. This device inputs an analog signal input from an analog signal output from a reading unit that reads recorded information recorded on a disc, and inputs an analog signal from the analog signal input unit and converts it into a digital signal. The analog-digital conversion unit in which the relationship between the analog signal and the digital signal in the input / output characteristics is variable, and the relationship between the analog signal and the digital signal in the input-output characteristics of the analog-digital conversion unit is determined according to the output of the analog-digital conversion unit A control unit. The analog-digital conversion unit may have a variable resistor to which an analog signal is input, and the control unit may determine a resistance value of the variable resistor.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  Before specifically describing the fourth embodiment of the present invention, an outline of a storage device according to the fourth embodiment will be described first. The storage device according to the fourth embodiment includes a hard disk controller, a magnetic disk device, and a read / write channel including a read channel and a write channel. In a magnetic disk device, data stored in a hard disk is usually read through a head including a magnetoresistive element (hereinafter referred to as “MR element”). Here, in the waveform of the signal read from the hard disk, the output amplitude of the positive pulse and the output amplitude of the negative pulse may be asymmetric, which has become a bottleneck for speeding up. Therefore, in the fourth embodiment of the present invention, amplitude asymmetry is improved when an analog signal read in the read channel is converted into a digital signal. Although details will be described later, the asymmetry of the amplitude is reduced by setting the input / output characteristics of the analog-digital converter so as to cancel the asymmetry of the amplitude.

  Hereinafter, the fourth embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 29 is a diagram showing a configuration of a magnetic disk device 3100 according to the fourth embodiment of the present invention. 29 is broadly divided into a hard disk controller 3001 (hereinafter abbreviated as “HDC 3001”), a central processing unit 3002 (hereinafter abbreviated as “CPU 3002”), and a read / write channel 3003 (hereinafter abbreviated as “CPU 3002”). Hereinafter, abbreviated as “R / W channel 3003”), voice coil motor / spindle motor control unit 3004 (hereinafter abbreviated as “VCM / SPM control unit 3004”), and disk enclosure 3005 (hereinafter “DE3005”). Is abbreviated as “.”). In general, the HDC 3001, the CPU 3002, the R / W channel 3003, and the VCM / SPM control unit 3004 are configured on the same substrate.

  The HDC 3001 includes a main control unit 3011 that controls the entire HDC 3001, a data format control unit 3012, an error correction coding control unit 3013 (hereinafter abbreviated as “ECC control unit 3013”), and a buffer RAM 3014. The HDC 3001 is connected to the host system via an interface unit (not shown). Further, it is connected to the DE 3005 via the R / W channel 3003, and executes data transfer processing between the host and the DE 3005 under the control of the main control unit 3011. The HDC 3001 receives a read reference clock (RRCK) generated by the R / W channel 3003. The data format control unit 3012 converts the data transferred from the host into a format suitable for recording on the disk medium 3050, and conversely, suitable for transferring the data reproduced from the disk medium 3050 to the host. Convert to format. The disk medium 3050 includes, for example, a magnetic disk. The ECC control unit 3013 adds redundant symbols using data to be recorded as information symbols in order to enable correction and detection of errors included in data reproduced from the disk medium 3050. The ECC control unit 3013 determines whether or not an error has occurred in the reproduced data, and corrects or detects if there is an error. However, the number of symbols that can correct errors is limited, and is related to the length of redundant data. That is, if a large amount of redundant data is added, the format efficiency deteriorates, so that there is a trade-off with the number of error correctable symbols. When error correction is performed using Reed-Solomon (RS) code as ECC, up to (number of redundant symbols / 2) errors can be corrected. The buffer RAM 3014 temporarily stores data transferred from the host and transfers the data to the R / W channel 3003 at an appropriate timing. Conversely, the read data transferred from the R / W channel 3003 is temporarily stored, and transferred to the host at an appropriate timing after the ECC decoding process or the like is completed.

  The CPU 3002 includes a flash ROM 3021 (hereinafter abbreviated as “FROM 3021”) and a RAM 3022, and is connected to the HDC 3001, the R / W channel 3003, the VCM / SPM control unit 3004, and the DE 3005. In the FROM 3021, an operation program for the CPU 3002 is stored.

  The R / W channel 3003 is roughly divided into a write channel 3031 and a read channel 3032, and executes transfer processing of data to be recorded and reproduced from the HDC 3001. Further, the R / W channel 3003 is connected to the DE 3005 and executes transmission of a recording signal and reception of a reproduction signal. Details will be described later.

  The VCM / SPM control unit 3004 controls a voice coil motor 3052 (hereinafter abbreviated as “VCM 3052”) and a spindle motor 3053 (hereinafter abbreviated as “SPM 3053”) in the DE 3005.

  The DE 3005 is connected to the R / W channel 3003 and executes a recording signal reception process and a reproduction signal transmission process. The DE 3005 is connected to the VCM / SPM control unit 3004. The DE 3005 includes a disk medium 3050, a head 3051, a VCM 3052, an SPM 3053, a preamplifier 3054, and the like. In the magnetic disk device 3100 of FIG. 29, it is assumed that there is one disk medium 3050 and the head 3051 is disposed only on one surface side of the disk medium 3050. May be arranged in a stacked manner. The head 3051 is generally provided corresponding to each surface of the disk medium 3050. The recording signal transmitted through the R / W channel 3003 is supplied to the head 3051 via the preamplifier 3054 in the DE 3005 and is recorded on the disk medium 3050 by the head 3051. Conversely, a signal reproduced from the disk medium 3050 by the head 3051 is transmitted to the R / W channel 3003 via the preamplifier 3054. The VCM 3052 in the DE 3005 moves the head 3051 in the radial direction of the disk medium 3050 in order to position the head 3051 at a target position on the disk medium 3050. The SPM 3053 rotates the disk medium 3050. Note that the output amplitude of the head 3051 is asymmetric due to the MR element as described above. Details will be described later.

  Here, the R / W channel 3003 will be described with reference to FIG. FIG. 30 is a diagram showing the configuration of the R / W channel 3003 of FIG. The R / W channel 3003 is roughly composed of a write channel 3031 and a read channel 3032.

  The write channel 3031 includes a byte interface unit 3301, a scrambler 3302, a run length limited encoding unit 3303 (hereinafter abbreviated as “RLL encoding unit 3303”), and a low density parity check encoding unit 3304 (hereinafter “LDPC”). A writing compensator 3305 (hereinafter abbreviated as “write pre-con unit 3305”), and a driver 3306.

  The byte interface unit 3301 processes the data transferred from the HDC 3001 as input data. Data to be written on the medium is input from the HDC 3001 in units of one sector. At this time, not only user data (512 bytes) for one sector but also ECC bytes added by the HDC 3001 are input simultaneously. The data bus is normally 1 byte (8 bits) and is processed as input data by the byte interface unit 3301. The scrambler 3302 converts the write data into a random series. This is because the repetition of data with the same rule adversely affects the detection performance at the time of reading and prevents the error rate from deteriorating. The RLL encoding unit 3303 is for limiting the maximum continuous length of 0. By limiting the maximum continuous length of 0, a data series suitable for an automatic gain control unit 3317 (hereinafter abbreviated as “AGC3317”) or the like is obtained.

  The LDPC encoding unit 3304 has a role of generating a sequence including parity bits that are redundant bits by LDPC encoding the data sequence. LDPC encoding is performed by multiplying a k × n matrix called a generator matrix by a data sequence of length k from the left. Each element included in the parity check matrix H corresponding to this generator matrix is 0 or 1, and since the number of 1 is smaller than the number of 0, it is called a low density parity check code (Low Density Parity Check Codes). It is. By using this arrangement of 1 and 0, the LDPC iterative decoding unit can efficiently correct errors.

  The write pre-con unit 3305 is a circuit that compensates for non-linear distortion due to continuous magnetization transition on the medium. A rule necessary for compensation is detected from the write data, and the write current waveform is adjusted in advance so that the magnetization transition occurs at the correct position. A driver 3306 is a driver that outputs a signal corresponding to the pseudo ECL level. The output from the driver 3306 is sent to a DE 3005 (not shown), sent to the head 3051 through the preamplifier 3054, and the write data is recorded on the disk medium 3050.

  The read channel 3032 includes a variable gain amplifier 3311 (hereinafter abbreviated as “VGA 3311”), a low-pass filter 3312 (hereinafter abbreviated as “LPF 3312”), an AGC 3317, an analog / digital converter 3313 (hereinafter “ADC 3313”). Abbreviated as a frequency synthesizer 3314, a filter 3315, a soft output detector 3320, an LDPC iterative decoder 3322, a synchronization signal detector 3321, and a run length limited decoder 3323 (hereinafter abbreviated as "RLL decoder 3323"). ), A descrambler 3324.

  The VGA 3311 and AGC 3317 adjust the amplitude of the read waveform of data sent from the preamplifier 3054 (not shown). The AGC 3317 compares the ideal amplitude with the actual amplitude, and determines the gain to be set in the VGA 3311. The LPF 3312 can adjust the cut-off frequency and the boost amount, and is responsible for part of the reduction to high-frequency noise and the equalization to a partial response (hereinafter referred to as “PR”) waveform. Although the LPF 3312 equalizes the PR waveform, it is difficult to completely equalize with the analog LPF due to many factors such as head flying height fluctuation, medium non-uniformity, and motor rotation fluctuation. Then, equalization to the PR waveform is performed again using the filter 3315 having more flexibility. The filter 3315 may have a function of adaptively adjusting the tap coefficient. The frequency synthesizer 3314 generates a sampling clock for the ADC 3313.

  The ADC 3313 is configured to obtain a synchronous sample directly by AD conversion. In addition to this configuration, an asynchronous sample may be obtained by AD conversion. In this case, a zero-phase restart unit, a timing control unit, and an interpolation filter may be further provided in the subsequent stage of the ADC 3313. Synchronous samples need to be obtained from asynchronous samples, and these blocks play that role. The zero phase restart unit is a block for determining an initial phase, and is used to obtain a synchronization sample as soon as possible. After determining the initial phase, the timing controller compares the ideal sample value with the actual sample value to detect a phase shift. A synchronous sample can be obtained by determining parameters of the interpolation filter using this. The ADC 3313 is configured to have an input / output characteristic opposite to the asymmetry, and improves the amplitude asymmetry generated in the head 3051. Details will be described later.

  The soft output detection unit 3320 is a soft output Viterbi algorithm (Soft-Output Viterbi Algorithm; hereinafter abbreviated as “SOVA”), which is a type of Viterbi algorithm, in order to avoid degradation of decoding characteristics due to intersymbol interference. Used. That is, in order to solve the problem that the interference between recorded codes increases and the decoding characteristics deteriorate as the recording density of magnetic disk devices increases in recent years, a partial response due to intersymbol interference is a method for overcoming this problem. The most likely decoding (Partial Response Maximum Like Like) (hereinafter abbreviated as “PRML”) method is used. PRML is a method for obtaining a signal sequence that maximizes the likelihood of a partial response of a reproduction signal.

  When the SOVA method is used as the soft output detection unit 3320, a soft decision value is output. For example, assume that a soft decision value (−0.71, +0.18, +0.45, −0.45, −0.9) is output as the SOVA output. These values represent numerical values as to whether the possibility of being 0 or 1 is high. For example, the first “−0.71” indicates that the possibility of 1 is large, and the second “+0.18” is likely to be 0, but the possibility of 1 is small. Means no. The output of the conventional Viterbi detector is a hard value, and the output of SOVA is hard-decided. In the case of the above example, it is (1, 0, 0, 1, 1). The hard value represents only whether it is 0 or 1, and information on which is more likely is lost. For this reason, decoding performance is improved by inputting a soft decision value to the LDPC iterative decoding unit 3322.

  The LDPC iterative decoding unit 3322 has a role of restoring an LDPC encoded data sequence to a sequence before LDPC encoding. As a decoding method, there are mainly a sum-product decoding method and a min-sum decoding method. The sum-product decoding method is advantageous in terms of decoding performance, but the min-sum decoding method is realized by hardware. With the feature that is easy. In an actual decoding operation using an LDPC code, very good decoding performance can be obtained by repeatedly decoding between the soft output detection unit 3320 and the LDPC iterative decoding unit 3322. For this purpose, a configuration in which a plurality of stages of software output detection units 3320 and LDPC iterative decoding units 3322 are arranged is actually required.

  The synchronization signal detection unit 3321 has a role of detecting a synchronization signal (Sync Mark) added to the head of data and recognizing the head position of the data. The RLL decoding unit 3323 performs the reverse operation of the RLL encoding unit 3303 of the write channel 3031 on the data output from the LDPC iterative decoding unit 3322 to restore the original data series. The descrambler 3324 performs the reverse operation of the scrambler 3302 of the write channel 3031 to restore the original data series. The data generated here is transferred to the HDC 3001.

  These configurations can be realized in terms of hardware by a CPU, memory, or other LSI of an arbitrary computer, and in terms of software, they are realized by a program having a communication function loaded in the memory. The functional block realized by those cooperation is drawn. Accordingly, those skilled in the art will understand that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof.

Here, the input / output characteristics of the head 3051 in FIG. 29 and the input / output characteristics desired for the ADC 3313 in FIG. 30 will be described. FIG. 31A is a diagram showing an example of input / output characteristics of the head 3051 of FIG. The horizontal axis represents the input magnetic field Hin, and the vertical axis represents the output voltage Vout. The input magnetic field takes a value in the range of Hin0_min to Hin0_max. When there is no non-linearity due to the MR element of the head 3051, the output voltage takes a value in the range of Vout0_min to Vout0_max as illustrated by a broken line. However, if the non-linearity due to the MR elements of the head 3051 is present, as shown by the solid line, the output voltage is a value in the range of Vout0_min~V ^'out0_max. That is, the input / output characteristics are asymmetric with respect to the origin. FIG. 31A shows that the input / output characteristics are nonlinear in the non-linear section 3200 in the positive section. Therefore, the output voltage when the input voltage is Vin0_max becomes V ^'out0_max to not become Vout0_max. FIG. 31B is a diagram illustrating an example of output characteristics of the LPF 3312 in FIG. FIG. 31B is a diagram showing that the dynamic range of the output voltage of the head 3051 shown in FIG. 31A is further distorted by the LPF 3312. The horizontal axis represents the input magnetic field Hin, and the vertical axis represents the output voltage Vout. The input magnetic field takes a value in the range of Hin0_min to Hin0_max.

FIG. 31C shows an example of an output waveform of the head 3051 in FIG. The horizontal axis represents time, and the vertical axis represents output voltage. FIG. 31C illustrates that the positive section and the negative section are asymmetric with respect to 0V. That is, the head 3051, indicating that the amplitude energy is reduced by (Vout0_max-V ^'out0_max). As a result, the detection accuracy of data detection (not shown) existing in the subsequent stage deteriorates. Further, the error correction capability of an error correction circuit (not shown) existing in the subsequent stage is deteriorated. Note that the non-linearity caused by the MR element means that the dynamic range in the positive section and the dynamic range in the negative section become asymmetric as shown in FIG.

32A and 32B are diagrams showing examples of input / output characteristics of the ADC 3313 in FIG. The horizontal axis represents the input voltage Vin, and the vertical axis represents the output voltage Vout. The output voltage shown in FIGS. 32A and 32B is not the digital signal output in the ADC 3313 but the output voltage of the analog signal whose amplitude is adjusted in the ADC 3313. The input voltage takes a value in the range of Vin1_min to Vin1_max. When nonlinearity due to the MR element of the head 3051 exists, the output voltage has a value in the range of Vout1_min to Vout1_max as illustrated by the solid line. FIG. 32A shows a case where the ADC 3313 is provided with a characteristic corresponding to the reverse characteristic in order to eliminate the non-linearity caused by the MR element of the head 3051 shown in FIG. FIG. 32B also shows that the ADC 3313 has a characteristic corresponding to the reverse characteristic in order to eliminate the nonlinearity caused by the MR element of the head 3051 shown in FIG. 31B and the distortion caused by the LPF 3312. Indicates the case. Here, assuming that there is no voltage fluctuation between the head 3051 and the ADC 3313, the voltages illustrated in FIGS. 31A to 31B and FIGS. 32A to 32B are as follows. It becomes a relationship.
Vin1_max = V ^'out0_max
Vout1_max = Vout0_max

したがって、ＡＤＣ３３１３の入出力特性としては、たとえば次式で示すような、双曲線正接関数の逆特性に相当する特性とすればよい。ここで、ａは実数であり、ヘッド３０５１の特性により決定されてもよい。

These mean that non-linearity due to the MR element included in the head 3051 has been eliminated. In other words, the ADC 3313 is provided with a characteristic that is an inverse characteristic of the input / output characteristics in each nonlinear section 3200 of FIGS. 31A to 31B, that is, a characteristic in the nonlinear section 3300 in FIGS. By doing so, the nonlinearity caused by the MR element can be eliminated. It is known that the input / output characteristics in the nonlinear section 3200 of FIG. 31A are generally hyperbolic tangent functions as shown in the following equation.

Therefore, the input / output characteristic of the ADC 3313 may be a characteristic corresponding to the inverse characteristic of the hyperbolic tangent function, as shown by the following equation, for example. Here, a is a real number, and may be determined by the characteristics of the head 3051.

  FIG. 32C is a diagram illustrating an example of input / output characteristics of the ADC 3313 when the input / output characteristics in the nonlinear section 3300 of FIG. 32B are approximated by two linear functions. In FIG. 32C, the horizontal axis indicates the input voltage and the vertical axis indicates the output voltage, as in FIG. The input voltage takes a value in the range of Vin1_min to Vin1_max. Further, the output voltage has a value in the range of Vout1_min to Vout1_max. As described above, in order to eliminate the non-linearity caused by the MR element, the input / output characteristic of the ADC 3313 may be set to a characteristic opposite to the hyperbolic tangent function. However, it is generally difficult to achieve this characteristic. Therefore, in the fourth embodiment of the present invention, approximation is made with two linear functions as shown in FIG. Specifically, when the input voltage is in the range of Vin1a to Vin1b, the input / output characteristics represented by the first linear function 3330 are used. When the input voltage is in the range of Vin1b to Vin1_max, the input / output characteristics represented by the second linear function 3340 may be used.

  Here, a specific configuration of the ADC 3313 that realizes the input / output characteristics shown in FIG. FIG. 33 is a diagram illustrating a configuration example of the ADC 3313 in FIG. 30. The ADC 3313 includes a pre-adjustment unit 3060 indicated by a broken line and a discretization unit 3062. Although the case where an analog signal is converted into a digital signal consisting of 3 bits is shown here, the present invention is not limited to this.

  When the amplitude of the analog signal input from the input unit exists in the nonlinear section, the ADC 3313 converts the analog signal into a digital signal while adjusting the amplitude, and outputs the digital signal. That is, the pre-adjustment unit 3060 adjusts the amplitude of the analog signal so as to cancel the nonlinearity in the nonlinear section before converting the analog signal into a digital signal. Specifically, the pre-adjusting unit 3060 adjusts the amplitude of the analog signal in the non-linear section by setting the input / output characteristics in the non-linear section as an approximate value of the inverse of the hyperbolic tangent function. Next, the discretization unit 3062 converts the analog signal whose amplitude has been adjusted by the pre-adjustment unit 3060 into a 3-bit digital signal and outputs it.

  The pre-adjusting unit 3060 has a first primary having a first slope greater than at least 1 as input / output characteristics of the first partial section of the plurality of partial sections in the plurality of partial sections included in the nonlinear section. Function 3330 is set. In addition, a second linear function 3340 having a slope different from the first slope is set as the input / output characteristic of the second partial section that is continuous with the first partial section among the plurality of partial sections. Here, the first partial section refers to, for example, the section from Vin1a to Vin1b illustrated in FIG. Further, the second partial section that is continuous with the first partial section is, for example, a section from Vin1b to Vin1_max illustrated in FIG. When the input / output characteristics of the second partial section are the input / output characteristics shown in FIG. 32C, the slope of the second linear function 3340 is set to be smaller than the first slope.

  This will be specifically described. The pre-adjustment unit 3060 includes a first resistance element 3064, a second resistance element 3066, a third resistance element 3068, a fourth resistance element 3070, a fifth resistance element 3072, and a sixth resistance element 3074, represented by a resistance element 3400. A seventh resistance element 3076, an eighth resistance element 3078, a ninth resistance element 3080, and a comparison unit 3082 are included. Each of the resistance elements 3400 is installed in series, and receives a reference signal Vref having a constant voltage as input, and sequentially outputs reference signals whose amplitudes are adjusted to the subsequent resistance elements. Next, the comparison unit 3082 adjusts the amplitude of the analog signal by comparing the reference signal output from each of the plurality of resistance elements 3400 with the amplitude of the analog signal input from the LPF 3312. That is, an analog signal having a temporally continuous value is compared with a reference signal output from each resistance element 3400, and eight discrete signals are output according to the magnitude relationship. The eight signals here are analog signals, but each has a constant amplitude indicating either plus or minus.

  The plurality of resistance elements 3400 change the amount of decrease in the voltage output from each resistance element by making each resistance value non-uniform. Specifically, the voltage Vref of the reference signal applied to each resistance element is reduced and output according to the resistance value at the output of each resistance element. That is, the voltage is reduced as the resistance value is increased, and the degree of reduction is decreased as the resistance value is decreased. In other words, in each of the plurality of resistance elements 3400, by making each resistance value a non-uniform value for each section, the voltage adjustment width in each resistance element 3400 is different. Can be changed. In the fourth embodiment of the present invention, in each of the first partial section and the second partial section, which are nonlinear sections, the resistance values of the corresponding resistance elements 3400 are made different from the resistance values of the other resistive elements. The slope of the input / output characteristics is adjusted.

  For example, resistance elements corresponding to sections other than the first partial section or the second partial section are assumed to be a fifth resistance element 3072, a sixth resistance element 3074, a seventh resistance element 3076, and an eighth resistance element 3078. These resistance values are assumed to be R. Further, it is assumed that the resistance elements corresponding to the first partial section are the third resistance element 3068 and the fourth resistance element 3070. Further, it is assumed that the resistance element corresponding to the second partial section is the second resistance element 3066. In this case, the resistance values of the third resistance element 3068 and the fourth resistance element 3070 corresponding to the first partial section are smaller than the resistance value R of the resistance element corresponding to a section other than the first partial section or the second partial section. A value, for example, R / 3 may be set. Further, the resistance value of the second resistance element 3066 corresponding to the second partial section may be set to a value larger than the resistance value R, for example, 2R. In general, the first resistance element 3064 and the ninth resistance element 3080, which are resistance elements at both ends, are set to a value R / 2 that is half of the resistance value R of a normal resistance element.

34A to 34C are diagrams showing examples of the characteristics of the output signal of the soft output detection unit 3320 in FIG. In each figure, the vertical axis represents the bit error rate, and the horizontal axis represents the signal-to-noise ratio (Signal to Noise Ratio). FIG. 34 (a) shows the first bit error rate characteristic 3350 of the soft output detector 3320 when the input / output characteristic of the head 3051 of FIG. 29 is 5%, and the fourth embodiment of the present invention. It is a figure which shows the 2nd bit error rate characteristic 3360 at the time of applying. FIG. 34A further shows the third bit error rate characteristic when the above-described asymmetry can be ideally eliminated, or when the input / output characteristic does not exist in the head 3051 of FIG. FIG. The asymmetry of 5% means that the dynamic range V1 in the positive interval is about 90% of the dynamic range V2 in the negative interval (V1 = V2 × (1−0.05) / (1 + 0.05) ≈0.9 × V2). It means that. As illustrated in the second bit error rate characteristic 3360 of FIG. 34A, the bit error rate characteristic can be improved by applying the fourth embodiment of the present invention. For example, as shown in the second bit error rate characteristic 3360, the desired SNR when the bit error rate is 10 ⁻⁵ is 0.1 dB compared to the first bit error rate characteristic 3350 to which the fourth embodiment of the present invention is not applied. The degree has been improved.

  In general, in the field of storage devices such as hard disks, it is generally known that about one generation of technological innovation is necessary to improve the bit error rate by about 0.1 dB. Therefore, it goes without saying that the improvement of the bit error rate of 0.1 dB according to the fourth embodiment of the present invention is a remarkable effect for those skilled in the art.

  FIG. 34B is a diagram showing the bit error rate characteristics when 10% asymmetry exists in the input / output characteristics in the head 3051 of FIG. FIG. 34C is a diagram showing the bit error rate characteristics in the case where there is 15% asymmetry in the input / output characteristics in the head 3051 of FIG. As illustrated in the second bit error rate characteristic 3360 of FIGS. 34 (b) and 34 (c), as in the case of FIG. 34 (a), the asymmetry of the amplitude is reduced by the fourth embodiment of the present invention. In addition, the bit error rate can be remarkably improved.

  The present invention has been described based on the fourth embodiment. The fourth embodiment is an exemplification, and various modifications can be made to combinations of the embodiments or combinations of their constituent elements and processing processes, and such modifications are also within the scope of the present invention. This will be understood by those skilled in the art.

  According to the fourth embodiment, by adjusting the amplitude of the analog signal in the analog-to-digital converter, the nonlinearity of the amplitude generated in the magnetoresistive element can be reduced. Further, by reducing the nonlinearity of the amplitude generated in the magnetoresistive element, the error characteristics after error correction decoding can be remarkably improved. In addition, by simply setting the resistance values of a plurality of resistance elements included in the analog-digital conversion unit, it is possible to reduce the amplitude asymmetry of the analog signal with a small-scale and highly stable circuit. Further, the storage system can be accessed at a higher speed by reducing the influence of the asymmetry of the amplitude generated in the magnetoresistive element. Moreover, since it is not necessary to install extra hardware, a low-scale semiconductor integrated circuit can be realized.

  Next, the modification of 4th Embodiment of this invention is shown. First, an overview. The present modification relates to a storage system that reduces amplitude asymmetry caused by an MR element included in a head. In this modification, the magnetic disk device 3100 has the same configuration as that shown in FIG. The R / W channel 3003 has the same configuration as that in FIG. The difference between the fourth embodiment of the present invention is that the ADC 3313 of FIG. 30 has the configuration of FIG. That is, this modification is characterized in that the resistance value in the analog-digital converter included in the storage system is variable. In addition, about the part which is common in 4th Embodiment mentioned above, the same code | symbol is attached | subjected and description is simplified.

  FIG. 35 is a diagram illustrating a modification of the configuration of the ADC 3313 in FIG. 30. The ADC 3313 includes a pre-adjustment unit 3060, a discretization unit 3062, and a resistance value control unit 3086. The resistance value control unit 3086 controls the resistance value of the resistance element 3400 included in the pre-adjustment unit 3060 in accordance with an instruction from the outside. “External instruction” includes an instruction from a circuit other than ADC 3313, and may be an instruction from LDPC iterative decoding unit 3322, for example. In this case, the error correction result in the LDPC iterative decoding unit 3322 is notified, and if the result is good, the resistance value of the pre-adjustment unit 3060 is not changed. Good. In addition, the resistance value control unit 3086 instructs the pre-adjustment unit 3060 regarding the resistance element whose resistance value should be changed and the resistance value after the change in response to a user instruction via an interface (not shown). Also good. In this case, the resistance value control unit 3086 controls the pre-adjustment unit 3060 so that the designated resistance element 3400 has the designated resistance value.

  FIG. 36 is a diagram showing a modification of the configuration of the resistance element 3400 of FIG. The resistance element 3400 includes a first adjustment resistance element 3084a typified by the adjustment resistance element 3084, a second adjustment resistance element 3084b, an nth adjustment resistance element 3084n, and a first switching section 3088a typified by the switching section 3088. , M-th switching unit 3088m. n is an integer of 2 or more, and m is an integer of 1 or more. Each switching unit 3088 turns the switch ON or OFF based on an instruction from the resistance value control unit 3086. A specific example will be described. For example, it is assumed that the resistance values of all the adjustment resistance elements 3084 are 2R. In this case, when any of the switching units 3088 is OFF, the resistance value in the resistance element 3400 is 2R. When only one of the switching units 3088 is ON, the resistance value in the resistance element 3400 is R. When the k switching units 3088 are ON, the resistance value in the resistance element 3400 is 2R / k. In other words, for the resistance element 3400 corresponding to a section other than the non-linear section, the resistance value control unit 3086 turns on one of the switching units 3088 and sets its resistance value to R. Further, for the resistance element 3400 corresponding to the non-linear section, the resistance value control unit 3086 may set 0 or two or more switching units 3088 to ON and set the resistance value to a value other than R. Note that only one or more of the resistance elements included in the pre-adjustment unit 3060 may be configured as shown in FIG. Further, the resistance values of the adjustment resistor elements 3084 may not be the same. Even in these cases, it goes without saying that the same effect can be obtained by appropriately changing the control of the switching unit 3088 by the resistance value control unit 3086.

  FIG. 37 is a diagram showing a modification of the configuration of the front adjustment unit 3060 in FIG. The pre-adjustment unit 3060 shown in FIG. 37 has a configuration in which a reference voltage control unit 3090 is added to the pre-adjustment unit 3060 shown in FIG. Note that portions common to the pre-adjustment unit 3060 illustrated in FIG. 33 described above are denoted by the same reference numerals, and description thereof is simplified. The reference voltage control unit 3090 is connected to the input terminals of at least one of the plurality of resistance elements, and applies a corresponding reference voltage to each of the input terminals, thereby each of the plurality of resistance elements. The amplitude of the reference signal output from is adjusted. In the present modification, the plurality of resistance elements may have the same resistance value. Also, the reference voltage control unit 3090 applies a reference voltage different from the input ends of the resistance elements corresponding to the sections other than the nonlinear section to the input ends of the resistance elements corresponding to the nonlinear section among the plurality of resistance elements. May adjust the non-linearity in the non-linear section. Here, the “corresponding reference voltage” includes a reference voltage determined in association with each resistive element, may be set in advance, and dynamically changes according to the quality of the magnetoresistive element. May be. According to this aspect, the reference voltage controller can flexibly control the amplitude of the reference signal. Further, since the resistance values of the plurality of resistance elements included in the analog-digital conversion unit can be made the same, the circuit cost can be reduced. In addition, the amplitude asymmetry of the analog signal can be reduced with a small circuit.

  In the above, the modification of this invention was demonstrated based on 4th Embodiment. This modification is an exemplification, and various other modifications are possible in the combination of the embodiments, or in the combination of each component and each process, and such a modification is also within the scope of the present invention. This is understood by those skilled in the art.

  According to the modification of the fourth embodiment, the same effect as that of the fourth embodiment described above can be obtained. Further, by making the resistance value of the resistance element variable, it is possible to flexibly improve the nonlinearity of the amplitude.

  In the fourth embodiment, the input / output characteristics of the head 3051 have been described as having a non-linear section in the positive section. However, the present invention is not limited to this, and nonlinearity may exist in the negative interval. Even in this case, the same effect can be obtained by making the resistance value of the resistance element 3400 corresponding to the non-linear section different from the resistance value of other sections. Further, the R / W channel 3003 may be integrated on one semiconductor substrate.

(Fifth embodiment)
The fifth embodiment relates to a digital signal decoding technique, and more particularly, to a decoding device, a decoding method, and a storage system that correct / decode errors in data stored in a storage medium.

  The background art regarding the fifth embodiment will be described.

  In recent years, storage devices using hard disks are becoming essential devices in various fields such as personal computers, hard disk recorders, video cameras, and mobile phones. Storage devices using a hard disk have various specifications required depending on the field to which they are applied. For example, a hard disk mounted on a personal computer is required to have high speed and large capacity. In order to improve high speed and large capacity, it is necessary to perform error correction coding with high correction capability. However, since the amount of data handled per unit time increases as the speed increases, errors per unit time also increase proportionally. Then, when an error correction method with low error correction capability is used, the hard disk is re-read, so that the time required to access the hard disk increases and becomes a bottleneck for speeding up.

  In general, there is intersymbol interference in a data series read from a hard disk. Conventionally, a data sequence from which intersymbol interference has been removed has been detected by using a soft decision Viterbi algorithm (hereinafter referred to as “SOVA”) that can accurately detect a data sequence including white noise (for example, (See JP 2003-228923 A and JP 2004-139664 A). However, the data series read from the hard disk may include colored noise. In such a case, even if data detection is performed by SOVA, the intersymbol interference is not correctly removed, and even if decoding is performed at a later stage, accurate decoding cannot be expected. Conventionally, in order to solve such a problem, DDNP (Data Dependent Noise Predictive) -SOVA that detects a data series by predicting colored noise, that is, colored noise, is used as a data detection algorithm. (See, eg, “Aleksandar Kavic, et al.,“ The Viterbi Algorithm and Markov Noise Memory ”, IEEE Transactions on Information Theory. .

  Under such circumstances, the present inventor has come to recognize the following problems. That is, at the stage where the data series is read from the hard disk, it is difficult to determine whether the noise included in the data series is colored noise, white noise, or both noises. is there. For this reason, even if it decodes after performing data detection using any detection algorithm, it is a subject that the decoding characteristic will become unstable.

  The fifth embodiment of the present invention has been made in view of such circumstances, and a general purpose thereof is to provide a decoding device, a decoding method, and a storage system capable of improving the decoding characteristics regardless of the noise characteristics. It is in.

  In order to solve the above problems, a decoding device according to an aspect of a fifth embodiment of the present invention includes an input unit that inputs a data sequence, and a generation that generates a plurality of different signal sequences from the data sequence input by the input unit A selection unit that selects one signal sequence among a plurality of signal sequences generated by the generation unit, a decoding unit that decodes the signal sequence selected by the selection unit, and a signal sequence decoded by the decoding unit A detection unit that detects the degree of decoding error; and a determination unit that determines whether the error detected by the detection unit is within a predetermined tolerance. When the determination unit determines that the degree of error is within a predetermined tolerance, an instruction to output the signal sequence decoded by the decoding unit is given. When the determination unit determines that the degree of error exceeds a predetermined tolerance, the selection unit instructs the selection of another signal sequence different from the one signal sequence, and the selection unit The processing by the decoding unit and below is re-executed on the selected signal sequence.

  Here, “a plurality of different signal sequences” include a plurality of signal sequences generated by different data detection methods for a predetermined signal sequence. Further, “detecting the degree of decoding error” includes checking whether or not the error has been corrected and determining the presence or absence of an error by detecting an error such as CRC. In addition, “the degree of error is within a predetermined tolerance” includes that a correct decoding result has been obtained. To be done. “The degree of error exceeds a predetermined tolerance” includes that a correct decoding result has not been obtained. For example, the error is not corrected, and an error remains due to error detection such as CRC. It is determined that it is. “Selecting a different signal sequence” includes selecting a signal sequence different from the already selected signal sequence. In addition, the “processing by the decoding unit and below” includes processing by the decoding unit, the detection unit, and the determination unit. According to this aspect, it is possible to improve the decoding performance in the decoding unit by repeating the decoding process until the error becomes a decoding sequence within a predetermined tolerance. Also, the decoding performance can be stabilized.

  The selection unit may preferentially select a signal sequence that has a high probability that the determination unit determines that the degree of error is within tolerance. In addition, the selection unit prioritizes a signal sequence corresponding to a data sequence detected using a Viterbi algorithm having a function of predicting noise generated depending on a signal among a plurality of signal sequences generated by the generation unit. You may choose. Here, “noise generated depending on a signal” includes noise generated depending on past signals and noise. According to this aspect, it is possible to reduce the number of times that it is necessary to repeatedly execute the predetermined processing below the decoding unit by preferentially selecting a signal sequence having a high probability of being determined that the error level is within the tolerance. .

  The input unit may include a first input unit and a second input unit that generate different data series. The generation unit may generate one or more signal sequences from either one of the data sequences input from the first input unit and the second input unit, or both data sequences. The generation unit is a data sequence of a plurality of data sequences respectively input by the first input unit and the second input unit, and is based on a first Viterbi algorithm having a function of predicting noise generated depending on a signal A signal sequence may be generated based on the detected data sequence and / or the data sequence detected by the second Viterbi algorithm having a function different from that of the first Viterbi algorithm. According to this aspect, a plurality of candidates to be decoded can be generated. By generating a plurality of candidates, the certainty of decoding can be improved.

  The input unit may input a data sequence that has been converted to a soft decision value, and the generation unit may generate a signal sequence by converting the data sequence input by the input unit into a hard decision value. According to this aspect, a decoded sequence can be generated with a simple configuration. The generation unit is a case where soft decision data having an absolute value smaller than a predetermined threshold is continuous in a section having a predetermined length or more in the data series input by the input unit, When the number of continuous soft decision data in a section is larger than a predetermined number, the sign of the continuous soft decision data is inverted and then converted into a hard decision value, or the continuous soft decision data The signal sequence may be generated by logically inverting the data subjected to the hard decision after converting the data into a hard decision value. Further, the generation unit corresponds to a section when the codes of adjacent soft decision data are different in a section having a predetermined length or more among the plurality of soft decision data included in the data series input by the input section. Generate a signal sequence by inverting the sign of the soft decision data and then converting it to a hard decision value or by logically inverting the hard decision data after converting the soft decision data corresponding to the section to a hard decision value To do. In addition, the generation unit reverses the sign of the soft decision data having an absolute value smaller than a predetermined threshold among the plurality of soft decision data included in the data series input by the input unit, and then converts the decision value into a hard decision value Alternatively, the signal sequence may be generated by logically inverting the hard-decided data after converting the soft-decision data having an absolute value smaller than a predetermined threshold to a hard-decision value.

  Here, the “soft decision value” includes a value represented by multiple values greater than two values, and also includes a reliability. The reliability indicates the certainty of data and may be expressed by an absolute value of a soft decision value. “Reversing the sign of the soft decision data” includes multiplying the soft decision data by (−1) and the like, and logically inverting the hard decision value of the soft decision data. In addition, “when the signs of adjacent soft decision data are different” includes that the plurality of soft decision data are soft decision data alternately indicating positive and negative, and the sign bit indicating positive and the negative are set to negative. This includes that the sign bit shown is alternately included in the soft decision data. According to this aspect, the decoding characteristic can be improved by causing the hard decision value corresponding to the soft decision value with low reliability to be determined in the reverse direction.

  Further, the generation unit corrects the hard decision value of the other data series based on the hard decision value of one of the plurality of data series input from the input unit. By doing so, a signal sequence may be generated. The generation unit has a function of predicting noise generated depending on a signal, which is two data sequences out of a plurality of data sequences input by the first input unit and the second input unit. Based on the hard decision value of one of the data series detected by the 1 Viterbi algorithm and the data series detected by the second Viterbi algorithm having a function different from the first Viterbi algorithm, the hardness of the other data series is determined. The signal sequence may be generated by correcting the determination value. Further, the generation unit is two data series of the plurality of data series input by the first input unit and the second input unit, and the hard decision value of the first data included in one data series If the hard decision value of the second data existing in the position corresponding to the first data is different from the data included in the other data series, the first data included in the one data series is changed to the second data. The hard decision value of one data series may be corrected by replacing with. Further, the generation unit is two data series of the plurality of data series input by the first input unit and the second input unit, and the hard decision value of the first data included in one data series The absolute value of the soft decision value of the second data when the data is included in the other data series and is different from the hard decision value of the second data existing at the position corresponding to the first data. When the difference between the absolute value of the soft decision value of the first data and the first data is larger than a predetermined threshold value, the first data included in one data series is replaced with the second data, whereby one data series The hard decision value may be corrected. According to this aspect, by correcting a plurality of hard decision sequences with each other, it is possible to generate a signal sequence that is strong in both noise characteristics. Decoding characteristics can be improved. Also, the decoding characteristic can be improved by making the hard decision value corresponding to the soft decision value with low reliability in the reverse direction.

  Another aspect of the fifth embodiment of the present invention is a decoding method. The method includes a step of inputting a data sequence, a step of generating a plurality of different signal sequences from the input data sequence, a step of selecting one signal sequence among the generated plurality of signal sequences, Decoding the signal sequence, and the step of selecting sequentially differs from the already selected signal sequence until the degree of error of the signal sequence decoded in the decoding step becomes smaller than a predetermined threshold value. The process after the step of selecting and decoding the signal series is repeatedly executed. Here, “the degree of error is smaller than a predetermined threshold” includes that a correct decoding result has been obtained. For example, an error is corrected and an error is detected by error detection such as CRC. It is determined that there is no. According to this aspect, according to this aspect, it is possible to improve the decoding performance in the decoding unit by repeating the decoding process until the decoding sequence is such that the error is within a predetermined tolerance. Also, the decoding performance can be stabilized.

  Yet another aspect of the fifth embodiment of the present invention is a storage system. This storage system is a signal storage system comprising a write channel for writing data to the storage device and a read channel for reading data stored in the storage device, wherein the write channel encodes the data for Reed-Solomon encoding And a writing unit that writes the data encoded by the encoding unit to the storage device, the read channel includes an input unit that inputs an analog signal output from the storage device, and an analog input from the input unit An analog-to-digital conversion unit that converts a signal into a digital signal and outputs it, a soft output detection unit that calculates the likelihood of the digital signal output from the analog-to-digital conversion unit and outputs a soft decision value, and a soft output detection unit A decoding unit corresponding to the encoding unit that decodes the output data. The decoding unit includes an input unit that inputs data output from the software output detection unit, a generation unit that generates a plurality of different signal sequences from the data input by the input unit, and a plurality of signal sequences generated by the generation unit A selection unit that selects one signal sequence, a decoding unit that decodes the signal sequence selected by the selection unit, a detection unit that detects the degree of decoding error of the signal sequence decoded by the decoding unit, and a detection unit And a determination unit that determines whether or not the degree of error detected by the method is within a predetermined tolerance. When the determination unit determines that the error level is within a predetermined tolerance, the decoding unit is instructed to output the decoded signal sequence, and the determination unit causes the error level to exceed a predetermined tolerance. Is selected, the selection unit instructs the selection of another signal sequence different from the one signal sequence, and the processing below the detection unit is re-executed for the signal sequence newly selected by the selection unit. Is done. Yet another embodiment of the present invention is a decoding device. The device may be integrated on a single semiconductor substrate. According to this aspect, it is possible to access the storage system at a higher speed by including the decoding unit having a stable and high decoding capability. Moreover, since it is not necessary to install extra hardware, a low-scale semiconductor integrated circuit can be realized.

  Yet another aspect of the fifth embodiment of the present invention is also a storage system. This storage system is a storage system, and further includes a storage device that stores data, and a control unit that controls writing to the storage device and reading from the storage device. The read channel reads data stored in the storage device in accordance with an instruction from the control unit, and the write channel writes encoded data in the storage device in accordance with an instruction from the control unit. Yet another embodiment of the present invention is a decoding device. The device may be integrated on a single semiconductor substrate. According to this aspect, it is possible to access the storage system at a higher speed by including the decoding unit having a stable and high decoding capability. Moreover, since it is not necessary to install extra hardware, a low-scale semiconductor integrated circuit can be realized.

  Yet another aspect of the fifth embodiment of the present invention is a decoding device. The decoding device includes: an input unit including a first input unit that generates a data sequence; a second input unit that generates a data sequence different from the first input unit; and a plurality of data sequences input from the input unit. A generation unit that generates different signal sequences, a selection unit that selects one signal sequence among a plurality of signal sequences generated by the generation unit, a decoding unit that decodes a signal sequence selected by the selection unit, and a decoding A detection unit that detects the degree of decoding error of the signal sequence decoded by the unit, and a determination unit that determines whether or not the degree of error detected by the detection unit is within a predetermined tolerance. When the determination unit determines that the degree of error is within the predetermined tolerance, the output of the signal sequence decoded by the decoding unit is instructed.

  If the determination unit determines that the degree of error exceeds the predetermined tolerance, the selection unit instructs the selection of another signal sequence different from the one signal sequence, and the selection unit newly The processing by the decoding unit and below may be re-executed on the selected signal sequence. The selection unit may preferentially select a signal sequence that has a high probability that the determination unit determines that the degree of error is within tolerance. The generating unit may refer to the reliability of other bits when converting the hard decision value of the bits included in the input signal sequence. When generating a hard decision value for a bit included in the input signal sequence, the generation unit calculates the reliability of the bit and the reliability of other bits other than the bit included in the signal sequence. You may refer to it. When generating the hard decision value, the generation unit may refer to the reliability in the output signal from the first input unit and the reliability in the output signal from the second input unit. The generator may refer to the reliability of the output signal from the first input unit and the reliability of the output signal from the second input unit when determining the hard decision value of the bit. When determining the bit hard decision value, the generation unit may compare the reliability of corresponding bits in the output signal from the first input unit and the output signal from the second input unit. The selection unit may preferentially select the output from the first input unit when selecting the output from the first input unit and the output from the second input unit.

  The decoding device may further include a reading unit that reads the recording information recorded on the disk and outputs the information to the input unit, and a reading status determination unit that determines a reading status in the reading unit. The selection unit may determine which of the output from the first input unit and the output from the second input unit is prioritized based on the situation determined by the reading situation determination unit.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  Before specifically describing the fifth embodiment of the present invention, an outline of a storage system 4100 according to the fifth embodiment will be described first. The storage system 4100 according to the fifth embodiment includes a hard disk controller, a magnetic disk device, and a read / write channel including a read channel and a write channel. In the read channel, as decoding processing, data detection processing for removing intersymbol interference, RS decoding for correcting / detecting errors included in the detected data series, and the like are performed. In the data detection process, SOVA that exhibits high detection performance against white noise, DDNP-SOVA that exhibits high detection performance against colored noise, and the like are generally used.

  However, at the stage of reading the data series from the magnetic disk device, it is difficult to determine whether the noise included in the data series is colored noise, white noise, or both noises. There are challenges. For this reason, even if data detection is performed using any of the detection algorithms, intersymbol interference may not be removed correctly. In such a case, even if a decoding process for correcting an error included in the data series is performed in the subsequent stage, the decoding characteristics become unstable. Therefore, in the fifth embodiment of the present invention, decoding performance is improved by generating in advance a plurality of data sequences detected using at least SOVA and DDNP-SOVA, and sequentially executing the decoding processing of the data sequences. Stabilize. Further, in the decoding process, the decoding process is speeded up by giving priority to the data series in which the errors included in the decoded series are reduced. Details will be described later.

  Hereinafter, the fifth embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 38 is a diagram showing a configuration example of a storage system 4100 according to the fifth embodiment of the present invention. The storage system 4100 of FIG. 38 is broadly divided into a hard disk controller 4001 (hereinafter abbreviated as “HDC 4001”), a central processing unit 4002 (hereinafter abbreviated as “CPU 4002”), and a read / write channel 4003 (hereinafter abbreviated as “CPU 4002”). , Abbreviated as “R / W channel 4003”), voice coil motor / spindle motor controller 4004 (hereinafter abbreviated as “VCM / SPM controller 4004”), and disk enclosure 4005 (hereinafter “DE4005”). Abbreviated as)). In general, the HDC 4001, the CPU 4002, the R / W channel 4003, and the VCM / SPM control unit 4004 are configured on the same substrate.

  The HDC 4001 includes a main control unit 4011 that controls the entire HDC 4001, a data format control unit 4012, an error correction coding control unit 4013 (hereinafter abbreviated as “ECC control unit 4013”), and a buffer RAM 4014. The HDC 4001 is connected to the host system via an interface unit (not shown). Further, it is connected to the DE 4005 via the R / W channel 4003, and executes data transfer processing between the host and the DE 4005 under the control of the main control unit 4011. The HDC 4001 receives a read reference clock (RRCK) generated by the R / W channel 4003. The data format control unit 4012 converts the data transferred from the host into a format suitable for recording on the disk medium 4050, and conversely, suitable for transferring the data reproduced from the disk medium 4050 to the host. Convert to format. The disk medium 4050 includes, for example, a magnetic disk. The buffer RAM 4014 temporarily stores data transferred from the host and transfers the data to the R / W channel 4003 at an appropriate timing. Conversely, the read data transferred from the R / W channel 4003 is temporarily stored, and transferred to the host at an appropriate timing after the ECC decoding process or the like is completed.

  The ECC control unit 4013 adds redundant symbols using data to be recorded as information symbols in order to enable correction and detection of errors included in data reproduced from the disk medium 4050. Also, the ECC control unit 4013 determines whether an error has occurred in the reproduced data series as a decoding process, and executes a correction process if there is an error. When an error cannot be corrected, or when an error is detected by CRC (Cyclic Redundancy Code) or the like, decoding processing is performed on another data series depending on the degree. Details will be described later. Note that the number of symbols that can correct errors is limited, and is related to the length of redundant data. That is, if a large amount of redundant data is added, the format efficiency deteriorates, so that there is a trade-off with the number of error correctable symbols. When error correction is performed using Reed-Solomon (RS) code as ECC, up to (number of redundant symbols / 2) errors can be corrected.

  The CPU 4002 includes a flash ROM 4021 (hereinafter abbreviated as “FROM 4021”) and a RAM 4022, and is connected to the HDC 4001, the R / W channel 4003, the VCM / SPM control unit 4004, and the DE 4005. The FROM 4021 stores an operation program for the CPU 4002.

  The R / W channel 4003 is roughly divided into a write channel 4031 and a read channel 4032, and executes transfer processing of data to be recorded and reproduced from the HDC 4001. The R / W channel 4003 is connected to the DE 4005, and executes a recording signal transmission process and a reproduction signal reception process. Details will be described later.

  The VCM / SPM control unit 4004 controls a voice coil motor 4052 (hereinafter abbreviated as “VCM4052”) and a spindle motor 4053 (hereinafter abbreviated as “SPM4053”) in the DE 4005.

  The DE 4005 is connected to the R / W channel 4003 and executes a recording signal reception process and a reproduction signal transmission process. The DE 4005 is connected to the VCM / SPM control unit 4004. The DE 4005 includes a disk medium 4050, a head 4051, a VCM 4052, an SPM 4053, a preamplifier 4054, and the like. In the storage system 4100 of FIG. 38, it is assumed that there is one disk medium 4050 and the head 4051 is disposed only on one surface side of the disk medium 4050. A stacked arrangement may be used. The head 4051 is generally provided corresponding to each surface of the disk medium 4050. The recording signal transmitted through the R / W channel 4003 is supplied to the head 4051 via the preamplifier 4054 in the DE 4005 and is recorded on the disk medium 4050 by the head 4051. Conversely, a signal reproduced from the disk medium 4050 by the head 4051 is transmitted to the R / W channel 4003 via the preamplifier 4054. The VCM 4052 in the DE 4005 moves the head 4051 in the radial direction of the disk medium 4050 in order to position the head 4051 at a target position on the disk medium 4050. Further, the SPM 4053 rotates the disk medium 4050.

  Here, the R / W channel 4003 will be described with reference to FIG. FIG. 39 is a diagram showing the configuration of the R / W channel 4003 of FIG. The R / W channel 4003 is roughly composed of a write channel 4031 and a read channel 4032.

  The write channel 4031 includes a byte interface unit 4301, a scrambler 4302, a run length limited encoding unit 4303 (hereinafter, abbreviated as “RLL encoding unit 4303”), a write compensation unit 4305 (hereinafter, “write precon unit 4305”). A driver 4306.

  In the byte interface unit 4301, data transferred from the HDC 4001 is processed as input data. Data to be written on the medium is input from the HDC 4001 in units of one sector. At this time, not only user data (512 bytes) for one sector but also ECC bytes added by the HDC 4001 are input simultaneously. The data bus is normally 1 byte (8 bits), and is processed as input data by the byte interface unit 4301. The scrambler 4302 converts the write data into a random series. This is because the repetition of data with the same rule adversely affects the detection performance at the time of reading and prevents the error rate from deteriorating.

  The RLL encoding unit 4303 is for limiting the maximum continuous length of 0. By limiting the maximum continuous length of 0, a data series suitable for a timing control unit (not shown) at the time of reading, an automatic gain control unit 4317 (hereinafter abbreviated as “AGC4317”), and the like is obtained.

  The write pre-con unit 4305 is a circuit that compensates for non-linear distortion due to continuous magnetization transitions on the medium. A rule necessary for compensation is detected from the write data, and the write current waveform is adjusted in advance so that the magnetization transition occurs at the correct position. A driver 4306 is a driver that outputs a signal corresponding to the pseudo ECL level. The output from the driver 4306 is sent to the DE 4005 (not shown), sent to the head 4051 through the preamplifier 4054, and the write data is recorded on the disk medium 4050.

  The read channel 4032 includes a variable gain amplifier 4311 (hereinafter abbreviated as “VGA 4311”), a low-pass filter 4312 (hereinafter abbreviated as “LPF 4312”), an AGC 4317, and an analog / digital converter 4313 (hereinafter “ADC 4313”). A frequency synthesizer 4314, a filter 4315, a soft output detection unit 4320, a synchronization signal detection unit 4321, a run length limited decoding unit 4323 (hereinafter abbreviated as “RLL decoding unit 4323”), a descrambler 4324, and It is composed of

  The VGA 4311 and the AGC 4317 adjust the amplitude of the read waveform of data sent from the preamplifier 4054 (not shown). The AGC 4317 compares the ideal amplitude with the actual amplitude, and determines the gain to be set in the VGA 4311. The LPF 4312 can adjust the cut-off frequency and the boost amount, and is responsible for part of the reduction to high-frequency noise and equalization to a partial response (hereinafter referred to as “PR”) waveform. The LPF 4312 performs equalization to the PR waveform, but it is difficult to completely equalize with the analog LPF due to many factors such as head flying height fluctuation, medium non-uniformity, and motor rotation fluctuation. Then, equalization to the PR waveform is performed again using the filter 4315 having more flexibility. The filter 4315 may have a function of adaptively adjusting the tap coefficient. The frequency synthesizer 4314 generates a sampling clock for the ADC 4313.

  The ADC 4313 is configured to obtain a synchronous sample directly by AD conversion. In addition to this configuration, an asynchronous sample may be obtained by AD conversion. In this case, a zero-phase restart unit, a timing control unit, and an interpolation filter may be further provided after the ADC 4313. Synchronous samples need to be obtained from asynchronous samples, and these blocks play that role. The zero phase restart unit is a block for determining an initial phase, and is used to obtain a synchronization sample as soon as possible. After determining the initial phase, the timing controller compares the ideal sample value with the actual sample value to detect a phase shift. A synchronous sample can be obtained by determining parameters of the interpolation filter using this.

  The soft output detection unit 4320 detects a data sequence using SOVA, which is a type of Viterbi algorithm, in order to avoid degradation of decoding characteristics due to intersymbol interference. Generally, with the recent increase in recording density of magnetic disk devices, interference between recorded codes increases, and the decoding characteristics deteriorate accordingly. In order to solve this problem, a method of maximum likelihood decoding (Partial Response Maximum Likelihood; hereinafter abbreviated as “PRML”) using a partial response due to intersymbol interference is used. PRML is a method for obtaining a signal sequence that maximizes the likelihood of a partial response of a reproduction signal. In addition, a plurality of signal sequences to be decoded are generated using the detected data sequence. Details will be described later.

  When the SOVA method is used as the soft output detection unit 4320, a soft decision value is output. For example, assume that a soft decision value (−0.71, +0.18, +0.45, −0.45, −0.9) is output as the SOVA output. These values represent numerical values as to whether the possibility of being 0 or 1 is high. For example, the first -0.71 indicates that the possibility of 1 is large, and the second +0.18 indicates that the possibility of 0 is large but the possibility of 1 is not small. To do. The output of the conventional Viterbi detector is a hard value, and the output of SOVA is hard-decided. In the case of the above example, it is (1, 0, 0, 1, 1). The hard value represents only whether it is 0 or 1, and information on which is more likely is lost. For this reason, decoding performance is improved by inputting a soft decision value to the LDPC iterative decoding unit 4322.

  The RLL decoding unit 4323 performs the reverse operation of the RLL encoding unit 4303 of the write channel 4031 on the data output from the soft output detection unit 4320 to restore the original data series. The descrambler 4324 performs the reverse operation of the scrambler 4302 of the write channel 4031 to restore the original data series. The data generated here is transferred to the HDC 4001.

  40 is a diagram illustrating a configuration example of the software output detection unit 4320 in FIG. The soft output detection unit 4320 includes a data detection unit 4060, a generation unit 4062, and a selection unit 4064. The data detection unit 4060 inputs a data series. The input data series may be one data series or a plurality of data series. FIG. 41 is a diagram illustrating a configuration example of the data detection unit 4060 of FIG. Data detection unit 4060 includes a DDNP-SOVA unit 4066 and a SOVA unit 4068. The DDNP-SOVA unit 4066 detects a data sequence by executing a Viterbi algorithm (DDNP-SOVA) having a function of predicting noise generated depending on past signals and noise on an input signal. To do. The SOVA unit 4068 detects a data series by executing a soft decision Viterbi algorithm on the input signal. Note that the data detection unit 4060 may include a data detection device other than the DDNP-SOVA unit 4066 and the SOVA unit 4068. For example, it may be configured by a data detection device that performs data detection using a normal Viterbi algorithm that outputs a hard decision value. The data detection unit 4060 may further include a data detection device using a normal Viterbi algorithm.

  Returning to FIG. The generation unit 4062 generates a plurality of different signal sequences from the data sequence input by the data detection unit 4060. The plurality of signal sequences are generated by performing signal processing to be described later on one or more data sequences. Further, all the signal sequences may be generated in advance before the decoding process is executed by the subsequent decoding process. In addition, every time it is necessary to execute a decoding process or a re-decoding process, a signal sequence to be decoded may be generated. The selection unit 4064 selects one signal sequence from the plurality of signal sequences generated by the generation unit 4062. Further, the selection unit 4064 may preferentially select a signal sequence that has a high probability of being error-corrected by the ECC control unit 4013 in FIG. Specifically, the selection unit 4064 may preferentially select a signal sequence corresponding to a data sequence detected using DDNP-SOVA among a plurality of signal sequences generated by the generation unit 4062. Further, the selection unit 4064 may select another signal sequence different from the already selected signal sequence in accordance with an instruction from the ECC control unit 4013. Thus, by making a plurality of signal sequences to be decoded, decoding performance can be stabilized regardless of noise characteristics. In other words, by assuming a plurality of noise characteristics in advance and generating a signal sequence strong against the assumed noise characteristics as a decoding target, the decoding performance can be improved within the range of the assumed noise characteristics.

  Here, a case where the generation unit 4062 generates a signal sequence using the two data sequences output from the two data detection units illustrated in FIG. 41 will be described. Hereinafter, 10 signal sequences that are considered to have a relatively high probability that an error can be corrected by the ECC control unit 4013 of FIG. 38 will be described. Note that the selection order in the selection unit 4064 does not necessarily have to be selected from the first signal sequence described later, and may be set arbitrarily.

  The generation unit 4062 converts each of the soft decision values included in the data series that is a series of soft decision values output from the DDNP-SOVA unit 4066 shown in FIG. A signal series). The generation unit 4062 also performs the same processing on the data sequence that is the soft decision sequence output from the SOVA unit 4068, and generates a signal sequence (hereinafter referred to as a “second signal sequence”). Generate. The hard decision value conversion is executed by determining whether or not the soft decision value is larger than a predetermined threshold value and replacing it with 0 or 1 bits based on the determination result. For example, when the soft decision value is in the range of -α to + α (α> 0), when the threshold value is 0, it is replaced with 0 if the soft decision value is positive, and is replaced with 1 if the soft decision value is negative. That's fine. When the soft decision value is in the range of 0 to + β (β> 0), the threshold value may be β / 2. Since the hard decision value conversion (hereinafter referred to as “first correction determination algorithm”) can be realized with a simple configuration, the circuit scale can be reduced.

  Further, generation unit 4062 searches for a reliability having a value smaller than a predetermined threshold among a plurality of reliability included in the data series input by DDNP-SOVA unit 4066 of FIG. Further, in a sequence obtained by converting a soft decision value into a hard decision value, a signal sequence (hereinafter referred to as a “third signal sequence”) is obtained by inverting the bits “0” and “1” corresponding to the searched reliability. Notation). The generation unit 4062 also performs the same processing on the data sequence that is the soft decision sequence output from the SOVA unit 4068 to generate a signal sequence (hereinafter referred to as “fourth signal sequence”). To do. Here, the “reliability” indicates an absolute value of the soft decision value, and indicates a value of 0 or more. Since these hard decision values (hereinafter referred to as “second modification determination algorithm”) can be realized with a simple configuration, the circuit scale can be reduced. Further, by correcting a determination value that is highly likely to contain an error, the error rate of the decoded sequence output from the decoding unit 4070 in FIG. 42 can be improved.

This will be described using an example. The reliability included in the data series is shown below.
{9 1 1 1 5 7 3 3 6 9}
In addition, the data series subjected to the hard decision is shown below.
{1 0 0 1 1 1 0 0 0 1}
Here, assuming that the threshold value is 4, a signal sequence generated using the second correction determination algorithm is expressed as follows. As shown below, the 2nd, 4th, 7th and 8th bits in the previous equation are corrected.
{1 1 1 0 1 1 1 1 0 1}

  Further, the generation unit 4062 continues the reliability having a value smaller than a predetermined threshold among a plurality of reliability included in the data series input by the DDNP-SOVA unit 4066 of FIG. 41 more than a predetermined number. Search the current section. Further, in a sequence obtained by converting a soft decision value into a hard decision value, a signal sequence (hereinafter referred to as a “fifth signal sequence”) is obtained by inverting “0” and “1” of bits corresponding to the searched reliability. Notation). The generation unit 4062 also performs the same processing on the data sequence that is the soft-decision sequence output from the SOVA unit 4068 to generate a signal sequence (hereinafter referred to as “sixth signal sequence”). Generate. Since these hard decision values (hereinafter referred to as “third modification determination algorithm”) can be realized with a simple configuration, the circuit scale can be reduced. Further, burst errors can be reduced by intensive correction of sections including errors, so that the error rate of the decoded sequence output from the decoding unit 4070 in FIG. 42 can be improved.

This will be described using an example. The reliability included in the data series is shown below.
{9 1 1 1 5 7 3 3 6 9}
The data series subjected to the hard decision is shown below.
{1 0 0 1 1 1 0 0 0 1}
Here, assuming that the predetermined threshold is 4 and the predetermined number is 3, a signal sequence generated using the third correction determination algorithm is expressed as follows. As shown below, the second, third, and fourth bits in the above equation are corrected.
{1 1 1 0 1 1 0 0 0 1}

  In addition, in the data series input by the DDNP-SOVA unit 4066 in FIG. 41, the generation unit 4062, when the code of adjacent soft decision data is different in a section longer than a predetermined length, The sign of the judgment data is inverted. Thereafter, the soft decision data is converted into a hard decision value to generate a signal sequence (hereinafter referred to as a “seventh signal sequence”). “When the signs of adjacent soft decision data are different” means that, for example, when the soft decision data is represented by a hard decision value, “010101...” Or “101010. Including. In addition, the generation unit 4062 performs a similar process on a data sequence that is a soft-decision sequence output from the SOVA unit 4068, thereby generating a signal sequence (hereinafter referred to as an “eighth signal sequence”). Is generated. Since these hard decision values (hereinafter referred to as “fourth correction decision algorithm”) can be realized with a simple configuration, the circuit scale can be reduced. Further, by correcting a pattern that is highly likely to contain an error, the error rate of the decoded sequence output from the decoding unit 4070 in FIG. 42 can be improved.

This will be described using an example. The data series subjected to the hard decision is shown below.
{0 0 1 0 1 1 0 1 1 0}
Here, assuming that the predetermined length is 4, a signal sequence generated using the fourth correction determination algorithm is expressed as follows. As shown below, the second to fifth bits in the above are corrected.
{0 1 0 1 0 1 0 1 1 0}

  Also, the generation unit 4062 generates a hard decision value of the other data series based on one of the hard decision values of the two data series input by the DDNP-SOVA unit 4066 and the SOVA unit 4068 of FIG. The signal sequence is generated by correcting. Specifically, for example, generation unit 4062 corrects the data series of DDNP-SOVA unit 4066 as a corrected series, using the data series of SOVA unit 4068. First, generation unit 4062 is a hard decision value of the first data included in the data series of DDNP-SOVA unit 4066 and data included in the data series of SOVA unit 4068 and exists at a position corresponding to the first data. The hard decision value of the second data is compared. Here, when the two are different, by replacing the first data different from the corresponding second data in the data series of the DDNP-SOVA unit 4066 with the second data, the signal series (hereinafter referred to as “first” 9 signal series ”). Since this hard decision value conversion (hereinafter referred to as “fifth correction determination algorithm”) can be realized with a simple configuration, the circuit scale can be reduced. Further, by replacing one of the two data series with data different from the other, the error rate of the decoded series output from the decoding unit 4070 in FIG. 42 can be improved.

This will be described using an example. The hard decision value of the data series output by DDNP-SOVA unit 4066 is shown below.
{0 0 1 0 1 1 0 1 1 0}
The hard decision values of the data series output by the SOVA unit 4068 are shown below.
{0 1 0 1 0 1 0 1 0 0}
Here, a corrected sequence when the data sequence output by the DDNP-SOVA unit 4066 is a corrected sequence is shown below.
{0 1 0 1 0 1 0 1 0 0}

  The generation unit 4062 generates the hard decision value of the first data included in one of the two data series input by the DDNP-SOVA unit 4066 and the SOVA unit 4068 of FIG. 41 and the other data series. The hard decision value of the 2nd data which is the data contained and exists in the position corresponding to 1st data is compared. Furthermore, as a result of the comparison, when the first data and the second data are different, and the condition “reliability of the second data−reliability of the first data> α (α is a predetermined value)” is satisfied, The hard decision value of one data series is corrected by replacing the first data with the second data. Specifically, the hard decision values of the plurality of data included in the data series of the DDNP-SOVA unit 4066 and the hard decision values of the plurality of data included in the data series of the SOVA unit 4068 are respectively corresponding data. Compare. As a result of the comparison, the data corresponding to the reliability 2 in the case where they are different and “reliability 1−reliability 2> α” is replaced with the hard decision value of the data corresponding to the reliability 1. Thus, a signal sequence (hereinafter referred to as “tenth signal sequence”) is generated. Since this hard decision value conversion (hereinafter referred to as “sixth correction determination algorithm”) can be realized with a simple configuration, the circuit scale can be reduced. Also, the error rate of the decoded sequence output from the decoding unit 4070 in FIG. 42 is improved by replacing the data included in one of the two data sequences with data that is considered to have few errors. it can.

This will be described using an example. The reliability and hard decision value of the data series output by the DDNP-SOVA unit 4066 are shown below.
{3 4 6 5 5 1 1 5 2 4}
{0 0 1 0 1 1 1 1 1 1}
In addition, the reliability and hard decision value of the data series output by the SOVA unit 4068 are shown below.
{3 2 5 2 3 3 4 5 4 6}
{0 1 0 1 0 1 0 1 0 0}
A series after being corrected based on the sixth correction determination algorithm is shown below.
{0 0 1 0 1 1 0 1 0 0}

  The first correction determination algorithm to the sixth correction determination algorithm described above can be combined to derive a new correction determination algorithm. This also increases the types and number of signal sequences that can be generated. For example, each of the third and fourth modification determination algorithms can be combined with the fifth and sixth modification determination algorithms to generate a signal sequence under more severe conditions. In this case, decoding candidates in the ECC control unit 4013 in FIG. 38 can be increased, so that decoding stability can be improved. Preferably, a combination of the second and third correction determination algorithms, a combination of the second and third and fourth correction determination algorithms, or a combination of the fourth and sixth correction determination algorithms is set as a new correction determination algorithm. That's fine.

  FIG. 42 is a diagram illustrating a configuration example of the ECC control unit 4013 in FIG. The ECC control unit 4013 shows a decoding unit 4070, an error detection unit 4072, a determination unit 4074, and a switch 4076. Here, only the configuration on the decoding side is shown, and the configuration on the encoding side is omitted. Here, the decoding unit 4070 and the error detection unit 4072 may be connected or integrated devices. Decoding section 4070 decodes the signal sequence selected by selection section 4064 in FIG. The error detection unit 4072 performs a check as to whether or not the error has been corrected by the decoding unit 4070, and performs error detection using a CRC or the like. Note that “the signal sequence selected by the selection unit 4064 in FIG. 40” is output via the RLL decoding unit 4323 and the descrambler 4324 present in the subsequent stage of the software output detection unit 4320 including the selection unit 4064 in FIG. The signal sequence etc. which were made are also included.

  The determination unit 4074 determines that a correct decoding result is obtained when it is determined that the error has been corrected and it is determined that there is no error by CRC or the like. If the determination unit 4074 determines that a correct decoding result has been obtained, the switch 4076 is instructed to output the signal sequence decoded by the decoding unit 4070. In other words, the switch 4076 does not output the signal input from the decoding unit 4070 until instructed. If the determination unit 4074 determines that a correct decoding result has not been obtained, the selection unit 4064 is instructed to select another signal sequence different from the signal sequence already selected by the selection unit 4064. The processing by the decoding unit 4070 and subsequent is re-executed on the newly selected signal sequence. Here, “instructed” may be instructed directly by the ECC control unit 4013 to the switch 4076 or the selection unit 4064 or may be instructed via a control unit (not shown).

  These configurations described above can be realized in hardware by a CPU, memory, or other LSI of an arbitrary computer, and in software by a program having a communication function loaded in the memory. Here, functional blocks realized by the cooperation are depicted. Accordingly, those skilled in the art will understand that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof.

  FIG. 43 is a flowchart illustrating an operation example of the selection unit 4064 in FIG. 40 and the ECC control unit 4013 in FIG. First, the selection unit 4064 selects a signal sequence to be decoded (S4010). Next, a decoding process is executed in the ECC control unit 4013 (S4012). Further, the ECC control unit 4013 determines whether or not a correct decoding result has been obtained (S4014). When it is determined that a correct decoding result has been obtained (Y in S4014), the determination unit 4074 instructs the switch 4076 to output the decoded sequence output from the decoding unit 4070 as it is (S4016), and processing Exit. On the other hand, when it is determined that a correct decoding result has not been obtained (N in S4014), the selection unit 4064 selects the decoding target again, and repeats the processing from S4012 onward (S4018).

  Here, in the selection in S4010 or S4018, priority is given to a signal sequence considered to have a high possibility of correcting an error as a result of decoding. However, the order is not necessarily required, and may be arbitrarily set. For example, the selection order is such that the first signal sequence described above is selected first, and then the second signal sequence, the third signal sequence,..., In order until it is determined in S4014 that a correct decoding result has been obtained. The tenth signal sequence is selected. In this case, the selection order may be defined by the number of the signal sequence, or may be defined by the first modification determination algorithm to the sixth modification determination algorithm described above.

  FIG. 44 is a flowchart illustrating an operation example of the generation unit 4062 of FIG. First, the generation unit 4062 selects a reference data series (S4020). The reference data series refers to a data series to be corrected, and is a data series output from either the DDNP-SOVA unit 4066 or the SOVA unit 4068. Next, it is determined whether or not the data included in the data series selected in S4020 should be corrected one by one (S4022). If it is determined in S4022 that correction is required (Y in S4022), the sign of the data is inverted, and the process proceeds to S4026 (S4024). If it is determined that it should not be corrected (N in S4022), the process proceeds to S4026. Next, in S4026, it is determined whether or not the determination has been completed for all the data included in the data series. It repeats (N of S4026). On the other hand, if it is determined that the determination has been completed for all data (Y in S4026), the process ends. Note that the above-described processing may be executed for each correction determination algorithm for generating a signal sequence, or may be executed for each signal sequence to be generated. Therefore, when a plurality of correction determination algorithms are used or when a plurality of signal sequences are generated, the flowchart shown in FIG. 44 is repeatedly executed.

  According to the fifth embodiment, the decoding performance in the decoding unit can be improved by repeating the decoding process until a correct decoding result is obtained. Also, the decoding performance can be stabilized. In addition, by preferentially selecting a signal sequence that has a high probability of correcting an error, the number of times that it is necessary to repeatedly execute the predetermined processing below the decoding unit can be reduced. In addition, a plurality of candidates to be decoded can be generated. By generating a plurality of candidates, the certainty of decoding can be improved. Also, the decoding characteristic can be improved by correcting the hard decision value corresponding to the soft decision value with low reliability in the reverse direction. Also, by correcting a plurality of hard decision sequences with each other, a signal sequence that is strong against both noise characteristics can be generated, and the decoding characteristics can be improved. Also, the decoding characteristic can be improved by correcting the hard decision value corresponding to the soft decision value with low reliability in the reverse direction. In addition, the storage system can be accessed at higher speed by including a decoding unit having a stable and high decoding capability. Moreover, since it is not necessary to install extra hardware, a low-scale semiconductor integrated circuit can be realized.

  The present invention has been described based on the fifth embodiment. The fifth embodiment is an exemplification, and various modifications can be made to combinations of the fifth embodiments or combinations of their constituent elements and processing processes, and such modifications are also within the scope of the present invention. It will be understood by those skilled in the art.

  In the fifth embodiment, the ECC control unit 4013 has been described as being mounted inside the HDC. However, the present invention is not limited to this, and it may be mounted inside the read / write channel. Also, the HDC and the read / write channel may be integrated as one LSI. Moreover, although demonstrated as producing a candidate using SOVA, Viterbi may be used. In this case, a candidate may be created based on the hard decision value output from Viterbi instead of the soft decision value.

  Note that the fifth embodiment is not limited to the above-described configuration. For example, the decoding device reads the recording information recorded on the disk and outputs the information to the input unit, and the reading status in the reading unit. You may further provide the reading condition determination part which determines. The reading status determination unit determines the characteristics of the disc, for example, the rotational speed of the disc, or whether the reading location is the inner circumference or the outer circumference of the disc. The reading status determination unit may determine the characteristics of the GMR head attached to the disk, the characteristics of the AD conversion unit inside the decoding apparatus arranged at the subsequent stage of the disk, or the room temperature outside the apparatus. When these situations are determined, the selection unit may determine a signal to be output based on the status determined by the reading status determination unit. For example, the output from the input unit showing a better situation than the other may be preferentially selected and output. By such an aspect, a favorable result can be obtained regardless of the situation.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications can be made to combinations of the embodiments or combinations of their constituent elements and processing processes, and such modifications are also within the scope of the present invention. It will be understood by those skilled in the art.

1 is a diagram showing a configuration of a storage system according to a first embodiment of the present invention. It is a figure which shows the structure of the R / W channel of FIG. FIGS. 3A to 3B are diagrams showing examples of DC-free characteristics according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating a configuration example of an RLL / DC free encoding unit in FIG. 2. FIG. 5 is a diagram illustrating a configuration example of a DC component removal encoding unit in FIG. 4. 6A to 6C are diagrams illustrating first to third configuration examples of the encoded sequence selection unit in FIG. It is a figure which shows the difference in operation | movement of the encoding sequence selection part each shown in FIG.6 (b) and FIG.6 (c). FIG. 3 is a diagram illustrating a configuration example of an RLL / DC free decoding unit in FIG. 2. It is a figure which shows the structure of the storage system which concerns on 2nd Embodiment of this invention. FIG. 10 is a diagram showing a configuration of the R / W channel of FIG. 9. FIGS. 11A to 11B are diagrams illustrating examples of DC-free characteristics according to the second embodiment of the present invention. It is a figure which shows the structural example of the RLL / DC free / RS encoding part of FIG. It is a figure which shows the structural example of the RLL / DC free encoding part of FIG. It is a figure which shows the structural example of the DC component removal encoding part of FIG. FIGS. 15A to 15C are diagrams illustrating first to third configuration examples of the encoded sequence selection unit 1074 of FIG. It is a figure which shows the difference in operation | movement of the encoding sequence selection part each shown in FIG.15 (b) and FIG.15 (c). It is a figure which shows the operation example of the RLL / DC free / RS encoding part of FIG. 13 is a flowchart illustrating an operation example of the RLL / DC free / RS encoding unit in FIG. 12. It is a figure which shows the structural example of the RLL / DC free / RS decoding part of FIG. It is a figure which shows the structural example of the RLL / DC free decoding part of FIG. It is a figure which shows the structure of the storage system which concerns on 3rd Embodiment of this invention. It is a figure which shows the structure of the R / W channel of FIG. FIGS. 23A to 23B are diagrams illustrating examples of DC-free characteristics according to the third embodiment of the present invention. It is a figure which shows the structural example of the RLL / DC free encoding part of FIG. It is a figure which shows the structural example of the DC component removal encoding part of FIG. FIGS. 26A to 26C are diagrams illustrating first to third configuration examples of the encoded sequence selection unit in FIG. FIG. 27 is a diagram illustrating a difference in operation between the encoded sequence selection units illustrated in FIG. 26B and FIG. It is a figure which shows the structural example of the RLL / DC free decoding part of FIG. It is a figure which shows the structure of the magnetic disc apparatus based on 4th Embodiment of this invention. FIG. 30 is a diagram showing a configuration of an R / W channel of FIG. 29. FIG. 31A is a diagram showing an example of input / output characteristics of the head of FIG. FIG. 31B is a diagram illustrating an example of output characteristics of the LPF in FIG. FIG. 31C shows an example of the output waveform of the head shown in FIG. 32A to 32C are diagrams showing examples of input / output characteristics of the ADC of FIG. It is a figure which shows the structural example of ADC of FIG. 34A to 34C are diagrams illustrating examples of characteristics of output signals of the soft output detection unit in FIG. It is a figure which shows the modification of the structure of ADC of FIG. It is a figure which shows the modification of a structure of the resistance element of FIG. It is a figure which shows the modification of a structure of the front adjustment part of FIG. It is a figure which shows the structural example of the storage system which concerns on 5th Embodiment of this invention. It is a figure which shows the structure of the R / W channel of FIG. It is a figure which shows the structural example of the soft output detection part of FIG. It is a figure which shows the structural example of the data detection part of FIG. It is a figure which shows the structural example of the ECC control part of FIG. 43 is a flowchart illustrating an operation example of the selection unit in FIG. 40 and the ECC control unit in FIG. 42. It is a flowchart which shows the operation example of the production | generation part of FIG.

Explanation of symbols

  1 HDC, 2 CPU, 3 R / W channel, 4 VCM / SPM controller, 5 DE, 11 Main controller, 12 Data format controller, 13 ECC controller, 14 Buffer RAM, 21 FROM, 22 RAM, 31 Write Channel, 32 read channel, 50 disk medium, 51 head, 52 VCM, 53 SPM, 54 preamplifier, 60 first RLL encoding unit, 62 first signal processing unit, 64 second RLL encoding unit, 66 DC component removal encoding unit 68 determination bit acquisition unit, 70 RLL decoding unit, 72 second signal processing unit, 74 encoded sequence selection unit, 76 selection identification information generation unit, 78 identification information addition unit, 80 first ratio calculation unit, 82 second ratio Calculation unit, 84 selection output unit, 86 first summation unit, 8 second summing unit, 90 first moving addition unit, 92 first maximum value detecting unit, 94 second moving adding unit, 96 second maximum value detecting unit, 100 storage system, 200 first characteristic, 210 third characteristic, 300 second characteristic, 301 byte interface unit, 302 scrambler, 303 RLL / DC free encoding unit, 304 LDPC encoding unit, 305 write precon unit, 306 driver, 310 fourth characteristic, 311 VGA, 312 LPF, 313 ADC , 314 Frequency synthesizer, 315 filter, 316 interpolation filter, 317 AGC, 318 zero phase restart unit, 319 timing control unit, 320 soft output detection unit, 321 synchronization signal detection unit, 322 LDPC iterative decoding unit, 323 RLL / DC Free decoding unit, 324 descrambler.

Claims (7)

A first run-length limited encoding unit that generates a first encoded sequence by subjecting the digital signal sequence to run-length limited encoding;
A signal processing unit that performs predetermined signal processing on the digital signal sequence without changing the number of bits included in the digital signal sequence;
A second run length limited encoding unit that generates a second encoded sequence by performing run length limited encoding on the digital signal sequence that has been subjected to predetermined signal processing by the signal processing unit;
Select and output one of the first encoded sequence generated by the first run-length limited encoding unit and the second encoded sequence generated by the second run-length limited encoding unit A DC component removal encoding unit that performs
With
The DC component removal coding unit is
A first concatenation unit that concatenates the encoded sequence selected in the past and the first encoded sequence to generate a new first encoded sequence ;
A second concatenation unit that concatenates the encoded sequence selected in the past and the second encoded sequence to generate a new second encoded sequence ;
An encoded sequence selection unit that selects one of the first encoded sequence and the second encoded sequence based on the new first encoded sequence and the new second encoded sequence; ,
Encoding device which comprises a.   The encoding apparatus according to claim 1, wherein the first run-length limited encoding unit and the second run-length limited encoding unit have the same configuration.   The encoding apparatus according to claim 1, wherein the signal processing unit inverts at least some of the plurality of bits included in the digital signal sequence. The DC component removal coding unit is
A selection identification information generating unit that generates selection identification information indicating the encoded sequence selected by the encoded sequence selection unit;
An identification information adding unit that adds selection identification information generated by the selection identification information generating unit to any part of the encoded sequence selected by the encoded sequence selection unit;
The encoding device according to claim 1, further comprising: The encoded sequence selection unit includes:
A first ratio calculator that calculates a ratio of a bit indicating 0 to a bit indicating 1 among a plurality of bits included in the new first encoded sequence;
A second ratio calculating unit that calculates a ratio between a bit indicating 0 and a bit indicating 1 among a plurality of bits included in the new second encoded sequence;
A selection output unit that selects and outputs an encoded sequence corresponding to a ratio closer to 50% of the ratio calculated by the first ratio calculation unit and the ratio calculated by the second ratio calculation unit When,
5. The encoding device according to claim 1, comprising: The encoded sequence selection unit includes:
A first summing unit that sums a plurality of bits included in the new first encoded sequence to generate a first summed value;
A second summing unit that sums a plurality of bits included in the new second encoded sequence to generate a second summed value;
By comparing the second sum value from the first sum, the new first coded sequence and of the new second encoding sequence, selecting an encoding sequence corresponding to the sum of smaller A selection output unit for output,
5. The encoding device according to claim 1, comprising: The encoded sequence selection unit includes:
A first moving addition unit that generates a first moving addition value equal to the plurality of bits by calculating a moving addition of the plurality of bits included in the new first encoded sequence;
A first maximum value detection unit that detects a maximum value among the plurality of first movement addition values generated by the first movement addition unit;
A second moving addition unit that generates the same number of second moving addition values as a plurality of bits by moving and adding a plurality of bits included in the new second encoded sequence;
A second maximum value detection unit for detecting a maximum value among the plurality of second movement addition values generated by the second movement addition unit;
The maximum value detected by the first maximum value detection unit and the maximum value detected by the second maximum value detection unit are compared, and the new first encoded sequence and the new second encoding are compared. A selection output unit that selects and outputs an encoded sequence corresponding to the smaller maximum value among the sequences;
5. The encoding device according to claim 1, comprising:

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