JP5083144B2 - Capacitance-type sensor device capacitance change detection circuit, capacitance-type sensor module, capacitance-type sensor device capacitance change detection method, and electronic apparatus - Google Patents

Description

  The invention described in this specification relates to a technique for detecting an operation input or a position input for a capacitive sensor device. The invention proposed in this specification has aspects as a capacitance change detection circuit of a capacitance sensor device, a capacitance sensor module, a capacitance change detection method of a capacitance sensor device, and an electronic apparatus.

  There are various types of position input devices today. One of them is a sensor device that uses a dedicated pointing device having electrical characteristics equivalent to those of a finger or a finger. There are various types of sensor devices of this type depending on applications. In the following, a capacitive sensor module composed of a capacitive sensor device and its drive circuit (capacitance change measurement circuit) will be examined.

  1 and 2 show a schematic configuration example of a capacitive sensor module. The capacitance type sensor module includes a capacitance type sensor device 1 and a circuit (hereinafter referred to as “capacitance change measurement circuit”) 11 that detects a change in the capacitance. The sensor device 1 has a structure in which a plurality of electrode patterns 5 are wired on one surface of a flat substrate 3 and a plurality of electrode patterns 7 are wired on the other surface of the substrate 3.

  For example, the electrode pattern 5 on the upper surface side is wired so as to extend in the Y-axis direction, and the electrode pattern 7 on the lower surface side is wired so as to extend in the X-axis direction. The surface of the upper electrode pattern 5 is covered with a protective film (not shown). Also, a minute capacitance is formed at the intersection of the electrode patterns 5 and 7, and the upper electrode pattern 5 and the lower electrode pattern are electrically connected through the capacitance.

  In the case of the capacitive sensor device 1 that is disposed on the surface of the display device and used as a touch panel, each of the base material 3 and the electrode patterns 5 and 7 is transparent so that the display screen can be visually recognized. Made of high material. For example, a glass substrate or a plastic film is used for the base material 3. For example, ITO electrodes are used for the electrode patterns 5 and 7.

On the other hand, the capacitance change measurement circuit 11 is configured to form a closed circuit with the capacitive sensor device 1 so that the presence / absence of an operation and the operation position can be detected through detection of a change in electrical characteristics generated in the closed circuit. Has been. Incidentally, the closed circuit is constituted by the lead-out wiring pattern, the electrode pattern 5, the capacitance formed at the intersection of the electrode patterns, the electrode pattern 7, the lead-out wiring pattern, and the capacitance change measurement circuit 11.
Japanese translation of PCT publication No. 2002-530680

By the way, the amount of change in the electrical characteristics that the capacitance change measurement circuit 11 detects is generally small. On the other hand, the capacitance change measurement circuit 11 is required to have high detection accuracy. For example, in practice, an accuracy of 2 ns is required.
However, in order to realize this detection accuracy with a general synchronous clock, a 500 MHz clock is required.

Therefore, the inventors propose a technique that can realize detection accuracy equivalent to that when a high-frequency operation clock is used while using a low-frequency operation clock.
(A) Capacitance change detection circuit of a capacitive sensor device For example, a capacitance change detection circuit of a capacitance sensor device is proposed which has the following devices.
(1) to the first electrode pattern of the plurality of rows constituting the capacitive sensor device, the electrode driving unit for inputting a pulse signal sequentially line at a predetermined cycle (2) has a capacitive element, a first electrode A peak hold circuit that holds a voltage corresponding to a peak level of a detection signal extracted through a plurality of rows of second electrode patterns intersecting the pattern at another layer in a capacitor element
(3) A current source that starts discharging the capacitive element at a discharge speed corresponding to the coordinates in the sensor device at a predetermined timing synchronized with the pulse signal.
(4) a comparator that compares the voltage of the capacitive element with a reference value;
(5) A delay circuit stage that sequentially delays the comparison output signal of the comparator, and generates a plurality of delayed output signals having different comparison time points for each unit delay time length
(6) Storage unit for storing signal values corresponding to a plurality of delayed output signals
(7) Detection unit that detects the amount of time to be measured with accuracy of unit delay time length based on a plurality of signal values stored in the storage unit

Note that the range of the delay amount in the above-described delay circuit stage is desirably equal to or greater than the time width in which a change point may appear in the detection signal.
However, the range of the delay amount in the delay circuit stage described above is less than the time width in which a change point may appear in the signal value of the detection signal, and the detection of the time amount to be measured is a signal value for the storage unit. It is desirable to execute the storage operation and the detection operation by repeating the operation for a plurality of time points.

(B) Capacitance type sensor module Moreover, inventors propose what has the following devices as a capacitance type sensor module, for example.
(1) a first electrode pattern of the multi-column, the first electrode pattern and the capacitive sensor device (2) and a second electrode pattern of a plurality of rows that intersect at other layer a plurality of rows first A voltage corresponding to a peak level of a detection signal extracted through a plurality of second electrode patterns having an electrode driver (3) capacitive element that inputs a pulse signal line-sequentially at a predetermined cycle in one electrode pattern Peak hold circuit that holds the current in the capacitor
(4) A current source that starts discharging the capacitive element at a discharge speed corresponding to the coordinates in the sensor device at a predetermined timing synchronized with the pulse signal.
(5) A comparator that compares the voltage of the capacitive element with a reference value.
(6) A delay circuit stage that sequentially delays the comparison output signal of the comparator, and generates a plurality of delayed output signals having different comparison time points for each unit delay time length
(7) Storage unit for storing signal values corresponding to a plurality of delayed output signals
(8) Detection unit that detects the amount of time to be measured with accuracy of unit delay time length based on a plurality of signal values stored in the storage unit
(9) A determination unit that determines an operation input by a human body or an object having equivalent electrical characteristics based on the amount of time detected by the detection unit.

(C) Capacitance Change Detection Method for Capacitance Type Sensor Device Further, the inventors propose, for example, a method having the following processing as a capacitance change detection method for a capacitance type sensor device.
(1) to the first electrode pattern of the plurality of rows constituting the capacitive sensor device, the process of inputting a pulse signal sequentially line by a predetermined period (2) intersects at a first electrode pattern and the other layer Processing for holding a voltage corresponding to the peak level of the detection signal extracted through the plurality of rows of second electrode patterns in the capacitor element
(3) At a predetermined timing synchronized with the pulse signal, a process of starting the discharge of the capacitive element at a discharge rate corresponding to the coordinates in the capacitive sensor device;
(4) a process of comparing the voltage of the capacitive element with a reference value;
(5) Processing for sequentially delaying the comparison output signals obtained by the comparison processing and generating a plurality of delayed output signals having different comparison time points by unit delay time length
(6) Processing for storing signal values corresponding to a plurality of delayed output signals in the storage unit
(7) Processing for detecting the amount of time to be measured with accuracy of unit delay time length based on a plurality of signal values stored in the storage unit

(D) Electronic device Moreover, inventors propose what has the following devices as an electronic device, for example.
(1) In the display device (2) sensor device of a capacitive type arranged on the surface of the display device, a plurality intersecting the first electrode pattern of the multi-column, in the first electrode pattern and the other layer Capacitance type sensor device having a second electrode pattern in a row (3) An electrode driver (4) capacitive element for inputting a pulse signal line-sequentially at a predetermined cycle to a plurality of rows of first electrode patterns And a peak hold circuit that holds a voltage corresponding to a peak level of a detection signal extracted through the second electrode patterns in a plurality of columns in the capacitor element.
(5) A current source that starts discharging the capacitive element at a discharge speed corresponding to the coordinates in the sensor device at a predetermined timing synchronized with the pulse signal.
(6) Comparator that compares the voltage of the capacitive element with a reference value
(7) A delay circuit stage that sequentially delays the comparison output signal of the comparator, and generates a plurality of delayed output signals having different comparison time points for each unit delay time length
(8) Storage unit for storing signal values corresponding to a plurality of delayed output signals
(9) Detection unit that detects the amount of time to be measured with accuracy of unit delay time length based on a plurality of signal values stored in the storage unit
(10) A determination unit that determines an operation input by a human body or an object having equivalent electrical characteristics based on the amount of time detected by the detection unit.
(11) System control unit for controlling the operation of the entire system

(E) Electronic device Moreover, inventors propose what has the following devices as an electronic device, for example.
(1) a first electrode pattern of the multi-column, the first electrode pattern and the capacitive sensor device (2) and a second electrode pattern of a plurality of rows that intersect at other layer a plurality of rows first A voltage corresponding to a peak level of a detection signal extracted through a plurality of second electrode patterns having an electrode driver (3) capacitive element that inputs a pulse signal line-sequentially at a predetermined cycle in one electrode pattern Peak hold circuit that holds the current in the capacitor
(4) A current source that starts discharging the capacitive element at a discharge speed corresponding to the coordinates in the sensor device at a predetermined timing synchronized with the pulse signal.
(5) A comparator that compares the voltage of the capacitive element with a reference value.
(6) A delay circuit stage that sequentially delays the comparison output signal of the comparator, and generates a plurality of delayed output signals having different comparison time points for each unit delay time length
(7) Storage unit for storing signal values corresponding to a plurality of delayed output signals
(8) Detection unit that detects the amount of time to be measured with accuracy of unit delay time length based on a plurality of signal values stored in the storage unit
(9) A determination unit that determines an operation input by a human body or an object having equivalent electrical characteristics based on the amount of time detected by the detection unit.
(10) System control unit for controlling the operation of the entire system

  In the case of the invention proposed by the inventors, the comparison output signal, which is the comparison result between the detection signal and the reference value, is sequentially delayed by the delay circuit stage. At this time, there are always a plurality of comparison output signals having different comparison time points for each unit delay time length in the delay circuit stage. Then, each signal value of the plurality of comparison output signals existing in the delay circuit stage is taken out to the storage unit, and the amount of time to be measured is detected. At this time, the detected amount of time is specified with an accuracy of a unit delay time length corresponding to one stage of the delay elements constituting the delay circuit stage. As a result, even if the operation clock is low speed, it is possible to detect the waveform change of the detection signal accompanying the operation input with high accuracy.

Hereinafter, the best mode of the invention will be described in the following order.
(A) Appearance configuration of capacitance type sensor module (B) Functional configuration of capacitance type sensor module (C) Form example 1: elapsed time measurement type after peak hold (single strobe type)
(D) Embodiment 2: Elapsed time measurement type after peak hold (continuous strobe type)
(E) Form example 3: rise time measurement type (F) form example 4: elapsed time measurement type equivalent to pulse width (G) other form examples

  In addition, the well-known or well-known technique of the said technical field is applied to the part which is not illustrated or described in particular in this specification. Moreover, the form example demonstrated below is one form example of invention, Comprising: It is not limited to these.

(A) External appearance configuration of capacitive sensor module FIG. 3 shows an external configuration example of a capacitive sensor module. The capacitive sensor module 21 includes a capacitive sensor device 23, an FPC (flexible printed wiring board) 25 that is a lead-out wiring thereof, and a capacitance change measuring circuit 27.

  As described above, the capacitive sensor device 23 has a structure in which electrode patterns are formed in a lattice pattern on both surfaces of a base material. Further, the capacitance change measuring circuit 27 has a circuit function of selecting a closed circuit in a line-sequential manner as described above, applying an input pulse signal, and measuring the presence or absence of a change in capacitance based on the detection signal. ing.

  The capacitance change measuring circuit 27 includes not only a case where it is formed as a semiconductor integrated circuit but also a case where it is formed as a circuit pattern on the FPC. Further, part of the processing of the capacitance change measuring circuit 27 may be realized through application processing by a computer.

(B) Functional Configuration of Capacitance Type Sensor Module FIG. 4 shows a functional configuration example of the capacitance type sensor module. In FIG. 4, functional blocks corresponding to those in FIG. 3 are denoted by the same reference numerals.
The capacitive sensor module 21 viewed from the functional aspect is also configured by a capacitive sensor device 23 and a capacitance change measuring circuit 27.

The capacitance change measurement circuit 27 is a circuit device that realizes a function of supplying an input pulse signal to the capacitive sensor device 23 and a function of measuring a change appearing in the response waveform.
In the case of FIG. 4, the capacitance change measurement circuit 27 has a basic configuration of a preprocessing unit 31, a capacitance change detection circuit 33, and a determination unit 35.

  Among these, the preprocessing unit 31 is a processing circuit that performs preprocessing on the response waveform input from the capacitive sensor device 23. Examples of the pre-processing include response waveform amplification processing, response waveform peak hold processing, and the like. The type of processing to be executed is determined according to the relationship with the processing operation of the capacitance change detection circuit 33 and the determination unit 35 located in the subsequent stage. In FIG. 4, the preprocessing unit 31 is arranged in front of the capacitance change detection circuit 33, but the preprocessing circuit 31 is not essential. That is, the minimum configuration of the capacitance change measurement circuit 27 is a capacitance change detection circuit 33 and a determination unit 35.

Therefore, the detection signal in this specification refers to an output signal when the preprocessing unit 31 is used, and refers to an output signal of the capacitive sensor device 23 when the preprocessing unit 31 is not used.
The capacitance change detection circuit 33 is a circuit device that detects a change occurring in the capacitance component of the closed circuit to be measured as a change in the waveform of the detection signal. The capacitance change detection circuit 33 detects a change in the waveform of the detection signal as a measurement amount defined by a change point appearing in a comparison result between the detection signal and the reference value. A specific detection method will be described in each embodiment described later.

  The determination unit 35 is a circuit device that determines, based on the detection result of the capacitance change detection circuit 33, whether or not a capacitance component has changed in the closed circuit to be measured. That is, the determination unit 35 is a circuit device that determines the presence / absence of an operation input by a human body or an object having an electrical characteristic equivalent to the human body based on a change in the measurement amount detected by the capacitance change detection circuit 33.

(C) Form example 1
(C-1) Detection Method In this embodiment, attention is paid to the positive peak level of the response waveform with respect to the input pulse signal. FIG. 5 shows changes in the response waveform focusing on a certain measurement point (closed circuit). The horizontal axis in the figure is the elapsed time from the falling timing of the input pulse signal, and the vertical axis in the figure is the amount of current corresponding to the response waveform.

As shown in FIG. 5, the peak level when the finger is not touching the operation surface is the highest, and the peak level decreases as the capacitance component formed between the finger and the operation surface increases. That is, the peak level decreases as the contact area between the finger and the operation surface increases. The change in the amplitude direction that appears at the peak level is common regardless of the position on the operation surface.
Therefore, in this example, the peak level of the response waveform is stored in the peak hold circuit, extracted by a constant current source, and the time until the peak hold voltage falls below the reference value is measured to detect the peak level amplitude change. To do.

However, the appearance position of the peak level has a characteristic that shifts in the time axis direction depending on the contact state between the operation surface and the finger. In the case of FIG. 5, a shift of 10 ns or more is recognized.
This means that there is a difference in the measurement start time, and that the measurement result includes an error. Therefore, a mechanism for eliminating this error and increasing detection accuracy is required.
Therefore, in the case of this embodiment, a mechanism for aligning the time to start the extraction of the peak hold voltage is adopted.

FIG. 6 shows a mechanism employed in this embodiment. The horizontal axis in the figure is the elapsed time from the falling timing of the input pulse signal, and the vertical axis in the figure is the current amount and voltage corresponding to the response waveform.
As shown in FIG. 6, in this embodiment, the peak hold voltage extraction start time is set to a time point T0 behind the time position where the peak level may appear.

With this setting, the discharge start times can be made uniform regardless of the shape of the response waveform. Only the time difference due to the difference in peak level can be accurately measured.
Hereinafter, an example of the capacitive sensor device 23 that employs this detection method will be described.

(C-2) System Configuration (1) Overall Configuration FIG. 7 shows a system configuration example of the capacitive sensor module 41 according to this embodiment. In the capacitance type sensor module 41, the capacitance type sensor device 43 is simplified.
The capacitance type sensor module 41 includes a capacitance type sensor device 43 and a capacitance change measurement circuit 45.

  The capacitance change measurement circuit 45 includes an oscillator 51, a demultiplexer 53, a multiplexer 55, a sequencer 57, a current input voltage output type amplifier 59, a peak hold circuit 61, a variable current source 63, a current value table 65, a discharge control switch 67, and a comparator 69. The measuring unit 71 and the determining unit 73 are configured.

(2) Oscillator The oscillator 51 is a circuit that generates a rectangular input pulse signal having a preset fixed frequency.
However, the waveform of the input pulse signal is not limited to a rectangular wave, and may be a sine wave, a triangular wave, or other shapes. In the case of this embodiment, the oscillator 51 generates an input pulse signal at a frequency of 500 kHz.

(3) Demultiplexer The demultiplexer 53 is a circuit that switches the supply destination of the input pulse signal in the order instructed by the sequencer 57. The supply destination of the input pulse signal is any one of the plurality of electrode patterns 5.
(4) Multiplexer The multiplexer 55 is a circuit that switches the electrode pattern 7 for extracting the response waveform in the order instructed by the sequencer 57.

(5) Sequencer The sequencer 57 is a circuit that outputs, as coordinate information (X, Y), the connection order to the electrode pattern 5 that supplies the input pulse signal and the connection order to the electrode pattern 7 from which the response waveform is extracted. . In the case of this embodiment, the sequencer 57 manages the control timing in synchronization with the falling edge of the input pulse signal.

  In the case of this embodiment, the sequencer 57 generates control timing for the discharge control switch 67, the measurement unit 71, the determination unit 73, and the like. For example, the sequencer 57 supplies a timing pulse for closing the discharge control switch 67 to the discharge control switch 67 after the reference time T0 has elapsed from the falling edge of the input pulse signal. The reference time T0 is a timing at which discharge of the peak hold value by the variable current source 63 is started. As described with reference to FIG. 6, the reference time T0 is set after the timing when the peak level of the response waveform appears.

Further, for example, the sequencer 57 supplies a timing pulse for giving the timing for storing the comparison output signal input from the comparator 69 in the storage area to the measuring unit 71.
Further, for example, the sequencer 57 supplies the determination unit 73 that determines whether or not there is an operation input to the measurement point.

(6) Current Input Voltage Output Amplifier The current input voltage output amplifier 59 is a circuit that amplifies the response waveform extracted from the capacitive sensor device 43. In the current input voltage output type amplifier 59, the signal format of the response waveform is converted from the current format to the voltage format.

(7) Peak hold circuit The peak hold circuit 61 is a circuit that detects the peak level of the positive side of the detection signal. As shown in FIG. 7, the peak hold circuit 61 includes a diode D and a capacitor C. The diode D is used to extract only the positive electrode portion of the detection signal by the rectification function. The capacitor C is used to store a potential corresponding to the peak level of the detection signal.

(8) Variable Current Source The variable current source 63 is a constant current circuit capable of changing the current value, and is used to discharge the charge of the capacitor C constituting the peak hold circuit 61. Note that the current value of the variable current source 63 is variably specified in accordance with an instruction in the current value table 65. In any current value, the charge of the capacitor C is set so that the determination operation can be completed within one cycle from the start of application of the input pulse signal. Specifically, it is set so that the potential of the capacitor C to be measured is discharged below the reference potential Vref until the next input pulse signal is supplied. In this specification, this discharge operation is referred to as “initialization operation”.

(9) Current Value Table The current value table 65 is a storage area that stores the coordinates of the measurement point and the current value instructed to the variable current source 63 in association with each other. The reason why the current value is varied according to the measurement point is to adjust the rate of decrease of the holding voltage of the capacitor C. Specifically, this is because the appearance range of the timing when the charge of the capacitor C drops below the reference potential Vref falls within the measurement range of the measurement unit 71.
The reason why variable control of the current value is necessary will be described in detail below.

Here, for the sake of explanation, a capacitive sensor device 43 having a simplified structure shown in FIG. 8 is considered. FIG. 8 shows a planar structure of the capacitive sensor device 43 in which the four electrode patterns 5 are formed on the upper surface side of the substrate 3 and the four electrode patterns 7 are formed on the lower surface side. Accordingly, 16 measurement points are formed on the operation surface.
Incidentally, as shown in FIG. 8, conductive wires (for example, carbon conductive wires) 81 of the flexible printed wiring board 25 are connected to the total of eight electrode patterns, respectively.

As shown in FIG. 8, the propagation path passing through each measurement point is defined by the combination of the length of the conductive line 81 and the length of the electrode patterns 5 and 7. From this, it can be seen that the length of the propagation path is different for each measurement point.
In the following, differences in the characteristics of the corresponding propagation paths will be described by assigning numbers I 1 to IV to the respective measurement points located at the four corners of the operation surface.

  FIG. 9 shows an equivalent circuit of the propagation path corresponding to each measurement point. As shown in FIG. 9, the resistance component of the conductive line 81 having a short propagation path is about 100Ω, and the resistance component of the conductive line 81 having a long propagation path is about 1 kΩ. The electrode patterns 5 and 7 having a short propagation path can be considered as a distributed constant low-pass filter including a resistance component of about 100Ω and a capacitance component of about 4.7 pF.

  Note that a series capacitance (about 2 pF) indicated by a solid line in the drawing is a capacitance component that is statically formed between the electrode pattern 5 and the electrode pattern 7. A parallel capacitance 83 indicated by a broken line in the figure represents a capacitance component formed between the electrode pattern 5 and the finger and a capacitance component formed between the electrode pattern 7 and the finger, respectively. FIG. 9 shows that the sum of the capacitance component on the upper surface side and the capacitance component on the lower surface side changes between 0 pF and 20 pF.

FIG. 10 shows an outline of a combination state of electrical characteristics of propagation paths corresponding to these four measurement points I to IV.
FIG. 11 shows waveforms of detection signals corresponding to these four measurement points I to IV. Note that the vertical axis of the four graphs shown in FIG. 11 is the current value μA, and the horizontal axis is the time [ns]. Also from FIG. 11, the peak level when the finger is not in contact with the operation surface is maximum, and the peak level is minimum when the capacitance component formed between the operation surface and the finger is maximum (20 pF). I understand.

By the way, comparing the four graphs in FIG. 11, it can be seen that the scale of the vertical axis is greatly different from the scale of the horizontal axis.
Therefore, FIG. 12 is shown so that the difference in scale of these four graphs can be understood. FIG. 12 is a diagram in which waveforms of four detection signals are mapped on the same scale. However, in FIG. 12, only four detection signals corresponding to the non-contact case (0 pF) are shown.

As shown in FIG. 12, when the position on the operation surface is different (the propagation path length is different), the peak level amplitude and the appearance position are greatly different.
FIG. 13 shows a diagram in which the vertical axis of the previous diagram is changed to the peak hold voltage [mV] and the time scale of the horizontal axis is multiplied by eight. FIG. 13 shows a case where the reference voltage Vref referred to by the comparator 69 is 0 (zero) V, and the current value of the variable current source 63 is fixed for all regions on the operation surface.
FIG. 13 shows a case where the discharge operation of the capacitor C by the variable current source 63 is started 0.2 μs after the rising edge of the input pulse signal.

  In this case, the rate of decrease in the potential of the capacitor C is constant regardless of the difference in peak level. Therefore, the appearance range of the timing when the potential of the capacitor C becomes equal to or lower than the reference potential Vref greatly varies depending on the measurement position on the operation surface. In addition, if the appearance range of the corresponding timing depending on the presence or absence of operation input is dispersed, the monitoring range of the measurement unit 71 becomes very wide.

  Therefore, in this embodiment, the discharge rate of the capacitor C is adjusted as shown in FIG. Specifically, the discharge rate is increased for the measurement point I having a high peak level, and the discharge rate is decreased for the measurement point IV having a low peak level. Note that the discharge rate is set to a medium for the measurement points II and III having a medium peak level. In the case of FIG. 14, by adjusting the discharge speed, the maximum peak level that can appear at each measurement point is determined so that the elapsed time from the start of discharge to the reference potential Vref or less is the same. With this setting, it is possible to narrow the above-described variable range of the elapsed time associated with the fluctuation of the peak level.

From the above viewpoint, the correspondence relationship shown in FIG. 15 is stored in the current value table 65. As shown in FIG. 15, one current value is stored in association with the combination of the X coordinate and the Y coordinate. In FIG. 16, the correspondence relationship of the current value table 65 is displayed on the operation surface so as to overlap. As shown in FIG. 16, in this embodiment, 60 μA is assigned to measurement point I, 20 μA is assigned to measurement points II and III, and 10 μA is assigned to measurement point IV.
The coordinate information of the measurement point is given from the sequencer 57.

(10) Discharge Control Switch The discharge control switch 67 is a switch element that mainly controls the start of discharge of charges stored in the capacitor C of the peak hold circuit 61. In the case of this embodiment, as shown in FIGS. 13 and 14, the start of discharge is set by the sequencer 57 after the reference elapsed time T0 from the falling timing of the input pulse signal.

(11) Comparator The comparator 69 is a circuit device that compares the holding potential of the capacitor C with the reference potential Vref and constantly outputs the comparison result as a comparison output signal. Note that the logic output level of the comparator 69 changes at the timing when the peak hold potential crosses the reference potential Vref. This intersection timing is a change point that the measurement unit 71 detects.
The reference potential Vref is set to a value smaller than the minimum peak level assumed for all measurement points on the operation surface.

(12) Measuring Unit The measuring unit 71 is a circuit device that detects a change point of the logic output level that appears in the comparison output signal input from the comparator 69. FIG. 17 shows a configuration example of the measurement unit 71 according to this embodiment. The measurement unit 71 includes a delay circuit stage 91, a storage unit 93, an enable control circuit 95, an AND circuit 97, and a change point detection unit 99.

  The delay circuit stage 91 is composed of a series circuit of delay elements all having the same unit delay time. In the case of this example, the unit delay time at room temperature is set to 2 ns. This unit delay time corresponds to the change point detection accuracy. Hereinafter, the comparison output signal output from the output terminal of each delay element is referred to as a delayed output signal.

Note that the number of stages of the delay elements is set so that the time length of the delayed output signal at a plurality of time points existing in the delay circuit stage 91 is longer than the time width in which the change point of the logic output level may appear in the delayed output signal. The
The storage unit 93 is configured by a storage device that captures the delayed output signal appearing at each output stage of the delay element into the corresponding storage area in synchronization with the strobe pulse. In the case of this embodiment, the storage unit 93 includes the same number of flip-flop circuits as the delay elements. Note that the input terminals of the flip-flop circuits are respectively connected to the output terminals of the corresponding delay elements.

  The output terminals of the flip-flop circuits are connected to the change point detector 99, respectively. Further, the clock terminal of the flip-flop circuit is used for inputting a strobe signal that defines the timing for taking in the signal value appearing at the input terminal.

  The enable control circuit 95 and the AND circuit 97 are for generating the strobe signal described above. The enable control circuit 95 generates an enable signal that designates a strobe signal output enabled period. For example, the enable control circuit 95 includes a counter. The count operation of the enable control circuit 95 is started when the elapse of the reference time T0 is notified.

  At this time, the enable control circuit 95 counts the clock signal input at 50 MHz, and ends the count operation when the count value reaches a preset value. The enable control circuit 95 outputs only one enable signal at this end point. The AND circuit 97 generates a strobe signal by a logical product operation of the enable signal and the clock signal.

  FIG. 18 shows the phase relationship between the strobe signal and other signals. FIG. 18A shows the waveform of the input pulse signal. FIG. 18B shows a waveform of a discharge control signal for controlling the discharge period. FIG. 18C shows a waveform of the comparison output signal. Here, a period in which the holding potential of the capacitor C is higher than the reference potential Vref is indicated by “H level”, and a period in which the holding potential of the capacitor C is lower than the reference potential Vref is indicated by “L level”. FIG. 18D shows the waveform of the strobe signal. Note that a period indicated by a double-headed arrow in FIG. 18D is a range of the delayed output signal existing in the delay circuit stage 91 at the time of outputting the strobe signal. FIG. 18E shows waveforms of a response waveform (solid line) and a detection signal (broken line).

  The change point detection unit 99 detects the timing at which the holding potential of the capacitor C due to the discharge operation falls below the reference potential Vref based on the delayed output signals at a plurality of time points taken into the storage unit 93 when the strobe signal is output. It is a circuit device. For example, “1” continues during a period when the holding potential of the capacitor C is higher than the reference potential Vref, and “0” continues when the holding potential of the capacitor C is lower than the reference potential Vref. In the case of this example, the change point detection unit 99 counts the number of “1” and outputs the count value as period length information until the change point appears.

  FIG. 19 specifically shows an example of a sequence of numbers captured by the change point detection unit 99. Note that FIG. 19A shows the waveform of the input pulse signal. FIG. 19B shows the waveform of the clock signal. As described above, the clock signal is given at 50 MHz (20 ns). FIG. 19C shows the waveform of the strobe signal. FIG. 19 (D1) is a numerical sequence example of import example 1 corresponding to the case where there is no operation input. FIG. 19D2 is a numerical sequence example of the import example 2 corresponding to the case where there is an operation input. As can be seen by comparing FIG. 19 (D1) and FIG. 19 (D2), the number of “1” varies greatly depending on whether or not there is an operation input.

  Note that one count value difference corresponds to 2 ns (500 MHz) difference. However, in order for the subsequent determination by the determination unit 73 to be executed accurately, the number of count values in the absence of an operation input needs to appear at the reference point. That is, a calibration operation is necessary.

  In addition, the unit delay time of the delay element is characterized by a large fluctuation due to fluctuations in element temperature due to external temperature or heat generation. In other words, the time width stored in the delay circuit stage 91 also varies depending on the temperature condition. Therefore, in order to increase the measurement accuracy of the change point, a calibration operation is necessary before the start of the measurement operation.

  In the case of this embodiment, the calibration operation is executed before the measurement operation is started. Specifically, it is executed by shifting the output phase of the strobe signal until a change point is detected at a preset position.

(13) Determination Unit The determination unit 73 is a circuit device that determines the presence / absence of an operation input based on change point detection position information (that is, a count value output from the change point detection unit 99). The determination unit 73 determines that there is no operation input to the measurement point when the count value detected for the measurement point matches the reference value or falls within the allowable error range. On the other hand, when the count value detected for the measurement point does not match the reference value or when the difference exceeds the allowable error range, the determination unit 73 determines that there is an operation input for the measurement point.

(C-3) Content of Processing Operation Hereinafter, the processing operation of the capacitive sensor module 41 will be described according to the operation flow of the sequencer 57 (FIG. 20). FIG. 20 shows the case where there are four electrode patterns 5 on the upper surface side and four electrode patterns 7 on the lower surface side.

  First, the sequencer 57 generates coordinates for designating a position on the operation surface to be measured (S1). Here, the sequencer 57 increases the coordinate value X of the electrode pattern 5 on the upper surface side by “1” for each cycle of the input pulse signal. In the case of FIG. 20, when the increased coordinate value X reaches “5”, the coordinate value X is returned to “1”, and the coordinate value Y of the electrode pattern on the lower surface side is increased by “1”. When the increased coordinate value Y reaches “5”, the coordinate value Y is returned to “1”.

  The coordinate values X and Y generated in this way are given to the demultiplexer 53, the multiplexer 55, the current value table 65, and the determination unit 73. When the frequency of the input pulse signal is 500 kHz (one cycle is 2 μs), the determination operation of 16 coordinate points defined by the four electrode patterns 5 and the four electrode patterns 7 is performed during 32 μs. Can be executed.

Next, the sequencer 57 waits for detection of the falling edge of the input pulse signal (S2). When the edge is detected, the sequencer 57 waits for the elapse of the reference time T0 that is the discharge start time (S3).
Here, when the passage of the reference time T0 is detected, the sequencer 57 controls the discharge control switch 67 to turn on and instructs the discharge of the potential held in the peak hold circuit 61 (S4). Until the discharge operation is started, the current value of the variable current source 63 is switched to the current value corresponding to the measurement point according to the instruction of the current value table 65. Therefore, after the start of discharge, discharge with a current value corresponding to each measurement point is started.

At this time, in the delay circuit stage 91, a delay output signal having a time difference of 2 ns is generated, and the delay output signal existing at the time of input of the strobe signal is taken into the storage unit 93 all at once.
Then, the change point detection unit 99 performs an operation of detecting a change point appearing in the comparison output signal.
The sequencer 57 waits for the change point detection process to be completed (S5).
Thereafter, the sequencer 57 outputs an interrupt request to the determination unit 73 (S6). The determination unit 73 to which this interrupt request has been input compares the detected count value with a reference value, and determines the presence or absence of an operation input to the measurement point based on the comparison result.

  Thereafter, the sequencer 57 determines whether or not a stop request exists (S7). If the stop request is not confirmed, the operation returns to the XY coordinate generation operation again and the above operation is repeated. When the stop request is confirmed, the sequencer 57 ends a series of operations.

(C-4) Summary As described above, the adoption of the capacitance change measurement circuit 45 according to the first embodiment enables an overwhelmingly high-speed determination operation as compared with the prior art. For example, when executing determination processing for 10 points, 20 ms is required in the prior art, but in the case of the embodiment, 20 μs is sufficient. For this reason, it becomes possible to cope with high-speed input, which was difficult to apply in the prior art.

Of course, the capacitance change measuring circuit 45 according to the embodiment can also be used for multipoint detection.
In addition, since the operation up to the input stage of the current input voltage output type amplifier 59 operates in the current mode, high noise resistance can be expected. That is, the capacitance change measuring circuit 45 according to the embodiment can be expected to have sufficient accuracy in terms of detection accuracy.
Further, in the case of this embodiment, it is possible to detect the appearance position of the change point with the same accuracy as when the clock signal of 500 MHz (2 ns) is used while using the operation clock signal of 50 MHz (20 ns).

  That is, it is possible to realize the capacitance change measuring circuit 45 that operates at a lower frequency than the conventional method. In addition, since the operation clock can be reduced in frequency, the power consumption of the capacitance change measuring circuit 45 can be reduced. This reduction in power consumption is advantageous for realizing a longer operating time, particularly when the capacitive sensor module 41 is mounted on a portable electronic device. This also facilitates the mounting of the capacitive sensor module 41 on a portable electronic device.

In addition, phase-locked PLL is achieved by lowering the operating clock frequency.
Loop circuit such as a clock circuit can be eliminated. Accordingly, the integration of the capacitance change measuring circuit 45 is facilitated.

(D) Embodiment 2
(D-1)
FIG. 21 shows a system configuration example of the capacitive sensor module 101 according to this embodiment. In FIG. 21, the same reference numerals are given to portions corresponding to FIG. 7 according to the first embodiment.
The capacitance type sensor module 101 includes a capacitance type sensor device 43 and a capacitance change measurement circuit 103.

  The capacitance change measurement circuit 103 includes an oscillator 51, a demultiplexer 53, a multiplexer 55, a sequencer 57, a current input voltage output type amplifier 59, a peak hold circuit 61, a variable current source 63, a current value table 65, a discharge control switch 67, and a comparator 69. The measuring unit 105 and the determining unit 73 are configured.

  Below, the structure of the measurement part 105 which is a change point is demonstrated. FIG. 22 shows a configuration example of the measurement unit 105. The measurement unit 105 includes a delay circuit stage 121, a storage unit 123, an enable control circuit 125, an AND circuit 127, a multiplexer 129, and a change point detection unit 131.

The basic configuration of the delay circuit stage 105 is the same as that of the delay circuit stage 71 according to the first embodiment. That is, the delay circuit stage 105 is composed of a series circuit of delay elements all having the same unit delay time. The unit delay time of the delay element at room temperature is also set to 2 ns.
The difference is the number of delay elements constituting the delay circuit stage 105. In the case of this embodiment, the number of delay elements constituting the delay circuit stage 105 may be as many as the number of stages corresponding to the time length corresponding to the output period of the strobe signal.

  In this example, the strobe signal is output in synchronization with the 50 MHz clock signal. Therefore, in the case of this embodiment, the delay elements may be configured with as few stages as possible with 10 stages (= 20 ns / 2 ns) or more. This configuration is possible because the strobe signal is continuously output a plurality of times in this embodiment. That is, even if the detection range per time is narrow, the detection range can be expanded by continuously executing the detection operation a plurality of times. As a result, the circuit area of the delay circuit stage 105 is smaller than that of the first embodiment.

  The storage unit 123 is configured by a storage device that captures the delayed output signal appearing at each output stage of the delay element into the corresponding storage area in synchronization with the strobe pulse. Also in this example, the storage unit is composed of the same number of flip-flop circuits as the delay elements. Therefore, the circuit area of the storage unit 123 is also smaller than that in the first embodiment.

  Incidentally, the input terminals of the flip-flop circuits are respectively connected to the output terminals of the corresponding delay elements. The output terminals of the flip-flop circuits are connected to the change point detector 131, respectively. Further, the clock terminal of the flip-flop circuit is used for inputting a strobe signal that defines the timing for taking in the signal value appearing at the input terminal. In the case of this embodiment, the flip-flop circuit captures and stores the delayed output signal output at that time each time the strobe signal is input.

  The enable control circuit 125 and the AND circuit 127 are for generating the strobe signal described above. Note that the enable control circuit 125 generates an enable signal that designates a period during which the strobe signal can be output. For example, the enable control circuit 125 starts outputting the enable signal when the elapse of the reference time T0 is notified.

Thereafter, the enable control circuit 125 continues outputting the enable signal until the change point detection unit 131 notifies the detection of the change point (that is, the detection of the “0” value).
The enable control circuit 125 forcibly generates an enable signal when a calibration signal (not shown) is input. When the calibration signal is input, the enable control circuit 125 outputs a control signal that instructs the multiplexer 129 to switch the input terminal. This is because the signal input to the delay circuit stage 121 is switched to a calibration signal.

The AND circuit 127 generates a strobe signal by a logical product operation of the enable signal and the clock signal.
FIG. 23 shows the phase relationship between the strobe signal and other signals. FIG. 23A shows the waveform of the input pulse signal. FIG. 23B shows a waveform of a discharge control signal for controlling the discharge period. FIG. 23C shows the waveform of the comparison output signal. Here, a period in which the holding potential of the capacitor C is higher than the reference potential Vref is indicated by “H level”, and a period in which the holding potential of the capacitor C is lower than the reference potential Vref is indicated by “L level”.

  FIG. 23D shows the waveform of the strobe signal. As shown in FIG. 23D, in the case of this embodiment, the strobe signal is executed from the start of discharge until the detection of the change point is notified. As shown in FIG. 23D, it can be seen that the output period length of the strobe signal is long. FIG. 23E shows waveforms of a response waveform (solid line) and a detection signal (dashed line).

  The multiplexer 129 is a circuit device that performs a switching operation between a measurement input signal (comparison output signal) and a calibration input signal. The output terminal of the comparator 69 is connected to the measurement input terminal. On the other hand, the input terminal for calibration is connected to a signal source of a toggle clock (not shown).

  The toggle clock signal will be described with reference to FIG. FIG. 24A shows a clock signal. Here, the case of 50 MHz is assumed. FIG. 25B shows a toggle clock signal. The toggle clock signal is generated by dividing the clock signal. In this example, it is 25 MHz. As a result, the period length when the toggle clock is at the H level or the L level corresponds to one cycle of the clock signal.

The multiplexer 129 operates to input a toggle clock signal to the delay circuit stage 121 during calibration. The input terminal is switched through the enable control circuit 125 as described above.
The change point detection unit 131 sets a plurality of time-delayed output signals taken into the storage unit 123 each time a strobe signal is output, and each time the holding potential of the capacitor C drops below the reference potential Vref. The presence or absence of is detected.

  For example, during a normal measurement operation, the change point detection unit 131 monitors whether “0” appears in the sequence read from the storage unit 123 each time a strobe signal is input. At this time, the number of strobe signals output is incremented by one until the appearance of “0” is detected. In this embodiment, the count value when the first strobe signal is input is set to zero. Therefore, the count value here is given by the number of outputs of the input strobe signal minus one.

In the case of this example, the change point detection unit 131 calculates the appearance position of the change point by the following equation. In the following equation, the number of delay elements per strobe signal is A, and the number of “1” s until “0” appears in the input time of the strobe signal where “0” appears is B.
Appearance position = count value × A + B

  An example of the above-described appearance position measurement operation will be specifically described with reference to FIG. FIG. 25A shows the waveform of the input pulse signal. FIG. 25B shows the waveform of the clock signal. FIG. 25C shows the waveform of the strobe signal. In the case of this embodiment, as shown in the figure, the signals are continuously output over a plurality of clock signal periods.

  FIG. 25D shows the count value of the number of times the strobe signal is output. In the case of this figure, seven strobe signals are output. The count value is 6 (= 7-1) as described above. 26 (E1) to (E7) are a numerical sequence of the delayed output signal taken into the storage unit 123 at each input time of the strobe signal.

In the case of this figure, the numerical sequence of the delayed output signal fetched from the delay circuit stage 121 is given as “11111100000000000000000000000000” in the seventh output of the strobe signal. Here, if the delayed output signal in the delay circuit stage 121 advances by 10 stages of the delay elements between the time when the strobe signal is output and the time when the next strobe signal is output, the change point appears as follows: 66 (= 6 × 10 + 6).
By the way, in the calculation of the appearance position, how many delay elements the delay output signal propagates during the output of one strobe signal is very important in specifying the positional relationship.

  As described above, the delay element has a characteristic that the unit delay time varies greatly depending on the external temperature or heat generation. Hereinafter, a specific example of the calibration operation will be described with reference to FIG. FIG. 26A shows a toggle clock waveform. FIG. 26B shows the waveform of the clock signal. FIG. 26C shows the waveform of the strobe signal. In the calibration operation, only one strobe signal is output. FIGS. 26D1 and 26D2 are numerical examples of the delayed output signal taken into the storage unit 123 by the strobe signal.

  Here, the period length in which the toggle clock is “1” or “0” coincides with the period length of one clock as described with reference to FIG. Therefore, the continuous number of “1” or the continuous number of “0” appearing in the sequence captured by one strobe signal is the delay element in which the delayed output signal advances while one strobe signal is output. It matches the number of steps. Incidentally, FIG. 26 (D1) is an example in which the period length of one shot of the strobe signal corresponds to the delay time of eight delay elements. FIG. 26 (D2) is an example in which the period length of one strobe signal corresponds to the delay time of 10 delay elements.

  When executing the calibration, the change point detection unit 131 counts the number of outputs “0” or “1” sandwiched between “1” or “0” from the numerical sequence read from the storage unit 123, thereby strobe. Determine the length of one signal.

(D-3) Contents of Processing Operation The processing operation of the capacitive sensor module 101 will be described below according to the operation flow of the sequencer 57. The operation flow of the sequencer 57 is the same as that in the first embodiment. Therefore, the sequencer 57 proceeds with the processing operation according to the procedure shown in FIG. It is assumed that the above-described calibration operation is performed before the processing operation is performed.

  First, the sequencer 57 generates coordinates for designating a position on the operation surface to be measured (S1). Here, the sequencer 57 increases the coordinate value X of the electrode pattern 5 on the upper surface side by “1” for each cycle of the input pulse signal. In the case of FIG. 20, when the increased coordinate value X reaches “5”, the coordinate value X is returned to “1”, and the coordinate value Y of the electrode pattern on the lower surface side is increased by “1”. When the increased coordinate value Y reaches “5”, the coordinate value Y is returned to “1”.

  The coordinate values X and Y generated in this way are given to the demultiplexer 53, the multiplexer 55, the current value table 65, and the determination unit 73. When the frequency of the input pulse signal is 500 kHz (one cycle is 2 μs), the determination operation of 16 coordinate points defined by the four electrode patterns 5 and the four electrode patterns 7 is performed during 32 μs. Can be executed.

Next, the sequencer 57 waits for detection of the falling edge of the input pulse signal (S2). When the edge is detected, the sequencer 57 waits for the elapse of the reference time T0 that is the discharge start time (S3).
Here, when the passage of the reference time T0 is detected, the sequencer 57 controls the discharge control switch 67 to turn on and instructs the discharge of the potential held in the peak hold circuit 61 (S4). Until the discharge operation is started, the current value of the variable current source 63 is switched to the current value corresponding to the measurement point according to the instruction of the current value table 65. Therefore, after the start of discharge, discharge with a current value corresponding to each measurement point is started.

Further, the measurement unit 105 starts outputting the enable signal in accordance with the discharge operation start instruction.
When the discharge operation of the capacitor C starts, the delay circuit stage 91 delays the comparison output signal by 2 ns and transfers it to the next stage as a delayed output signal. In the case of this embodiment, the strobe signal is repeatedly generated at the input period of the clock signal.

  Each time the strobe signal is output, the delayed output signal is taken into the storage unit 123 from the delay circuit stage 121 all at once. Then, the change point detection unit 99 determines whether or not “0” is included in these numerical sequences. When only “1” appears, the generation of the enable signal is continued, and when “0” appears, the generation of the enable signal is stopped.

The sequencer 57 waits for the change point detection process to be completed (S5).
Thereafter, the sequencer 57 outputs an interrupt request to the determination unit 73 (S6). The determination unit 73 to which this interrupt request has been input compares the detected count value with a reference value, and determines the presence or absence of an operation input to the measurement point based on the comparison result.

  Thereafter, the sequencer 57 determines whether or not a stop request exists (S7). If the stop request is not confirmed, the operation returns to the XY coordinate generation operation again and the above operation is repeated. If the stop request is confirmed, the sequencer 57 ends the operation.

(D-4) Summary As described above, when the capacitance change measuring circuit 103 according to the second embodiment is employed, the number of elements necessary for the delay circuit stage 121 and the storage unit 123 can be reduced. In comparison, the circuit area can be reduced.

(E) Embodiment 3
(E-1) Detection Principle In this embodiment, attention is paid to the difference in the rising speed of the detection signal with respect to the input pulse signal. FIG. 27 shows the relationship between the response waveform focused on the measurement point (closed circuit) and the measured time length ΔT. In the figure, the detection signal when there is no operation input is indicated by a solid line, and the detection signal when there is an operation input is indicated by a broken line.

As shown in the figure, the rising speed when there is an operation input is slower than when there is no operation input. In this embodiment, the time length from the falling edge of the input pulse signal until the detection signal exceeds the reference potential Vref is measured.
The horizontal axis in the figure is the elapsed time from the falling timing of the input pulse signal, and the vertical axis in the figure is the amount of current corresponding to the response waveform.

(E-2) System Configuration FIG. 28 shows a system configuration example of the capacitive sensor module 141 according to this embodiment. Note that, in FIG. 28, the same reference numerals are given to the portions corresponding to FIG.
The capacitance type sensor module 141 includes a capacitance type sensor device 43 and a capacitance change measurement circuit 143.

The capacitance change measurement circuit 143 includes an oscillator 51, a demultiplexer 53, a multiplexer 55, a sequencer 145, a current input voltage output type amplifier 59, a comparator 69, a reference value table 147, a measurement unit 149, and a determination unit 73.
In the case of this embodiment, since the rising speed of the detection signal output from the current input voltage output type amplifier 59 is measured, the peak hold circuit and its discharge circuit as in Embodiment 1 are unnecessary.
In the following, only components that are novel in this embodiment will be described.

(1) Sequencer The sequencer 145 is a circuit that outputs, as coordinate information (X, Y), the connection order to the electrode pattern 5 that supplies the input pulse signal and the connection order to the electrode pattern 7 from which the response signal is extracted. . In the case of this embodiment, the sequencer 145 manages the control timing based on the falling edge of the input pulse signal. This function is the same as in Embodiment 1.

  In the case of this embodiment as well, the sequencer 145 is common to Embodiment 1 in that it generates control timing for the measurement unit 149, the determination unit 73, and the like. However, the sequencer 145 according to this embodiment outputs a detection signal of the falling edge of the input pulse signal to the measurement unit 149. This is because in this embodiment, the difference in the rising speed of the detection signal is set as the measurement object.

(2) Reference Value Table The reference value table 147 is a storage area that stores the coordinates of the measurement points and the reference value Vref in association with each other. The reason why the reference potential Vref is varied according to the measurement point is that, as shown in FIG. 12, the amplitude and waveform of the detection signal vary greatly according to the measurement point. Further, in the case of this embodiment, the reason is that the appearance range of the timing when the detection signal exceeds the reference potential Vref is included in the measurement range of the measurement unit 149.

(3) Measurement Unit The measurement unit 149 is a circuit device that detects a change point of the logic output level that appears in the comparison output signal input from the comparator 69. FIG. 29 shows a configuration example of the measurement unit 149 according to this embodiment. In FIG. 29, the same reference numerals are assigned to the corresponding parts in FIG.
The measurement unit 149 includes a delay circuit stage 91, a storage unit 93, an enable control circuit 151, an AND circuit 97, and a change point detection unit 153.

  In the case of this embodiment, the measuring unit 149 employs the delay circuit stage 91 having the same structure as that of Embodiment 1. That is, the delay circuit stage 91 is configured by a series circuit of delay elements having the same unit delay time. Also in this embodiment, a delay element having a unit delay time of 2 ns at room temperature is used.

  In the case of this embodiment, the number of delay elements constituting the delay circuit stage 91 is such that the time lengths of the delayed output signals at a plurality of time points existing on the delay circuit stage 91 at the same time are logical output levels. It is set longer than the time width in which the change point may appear. That is, the same detection method as that in Embodiment 1 is adopted. Incidentally, it is possible to adopt the same detection method as in the second embodiment. Below, it demonstrates as what employ | adopts the same detection method as the example 1 of a form.

  The storage unit 93 is configured by a storage device that captures the delayed output signal appearing at each output stage of the delay element into the corresponding storage area in synchronization with the strobe pulse. Also in this embodiment, the storage unit 93 is configured by the same number of flip-flop circuits as the delay elements. The input terminals of the flip-flop circuits are connected to the output terminals of the corresponding delay elements.

  The output terminals of the flip-flop circuits are connected to the change point detector 153, respectively. Further, the clock terminal of the flip-flop circuit is used for inputting a strobe signal that defines the timing for taking in the signal value appearing at the input terminal.

  The enable control circuit 151 and the AND circuit 97 are for generating the strobe signal described above. Note that the enable control circuit 151 generates an enable signal for designating a strobe signal output possible period. For example, the enable control circuit 151 includes a counter. The count operation of the enable control circuit 151 is started by notification of the detection signal ta at the falling edge of the input pulse signal.

  At this time, the enable control circuit 151 counts the clock signal input at 50 MHz, and ends the count operation when the count value reaches a preset value. The enable control circuit 151 outputs only one enable signal at this end point. The AND circuit 97 generates a strobe signal by a logical product operation of the enable signal and the clock signal.

The change point detection unit 153 is a circuit device that detects the timing at which the detection signal rises to the reference potential Vref or more based on the delayed output signals at a plurality of time points taken into the storage unit 93 at the output time point of the strobe signal. For example, the detection signal is a reference potential Vref.
“0” continues during the smaller period, and “1” continues during the period when the detection signal is greater than the reference potential Vref. In the case of this embodiment, the change point detection unit 153 uses the number of “0” s that appear before “1” is detected as a count, and outputs the count value as change point information.

  FIG. 30 specifically shows an example of a sequence of numbers taken into the change point detection unit 153. Note that FIG. 30A shows the waveform of the input pulse signal. FIG. 30B shows the waveform of the clock signal. As described above, the clock signal is given at 50 MHz (20 ns). FIG. 30C shows the waveform of the strobe signal. FIG. 30 (D1) is a numerical sequence example of the import example 1 corresponding to the case where there is an operation input. FIG. 30 (D2) is a numerical sequence example of the capturing example 2 corresponding to the case where there is no operation input. As can be seen by comparing FIG. 30 (D1) and FIG. 30 (D2), the number of “0” that appears before “1” is detected varies greatly depending on the presence or absence of an operation input.

  Note that one count value difference corresponds to 2 ns (500 MHz) difference. However, in order for the subsequent determination by the determination unit 73 to be executed accurately, the number of count values in the absence of an operation input needs to appear at the reference point. That is, a calibration operation is necessary. The calibration method is the same as in the first embodiment.

(E-3) Contents of Processing Operation Hereinafter, the processing operation of the capacitive sensor module 141 will be described according to the operation flow of the sequencer 145 (FIG. 31).

  First, the sequencer 145 generates coordinates that specify the position on the operation surface to be measured (S11). Here, the sequencer 145 increases the coordinate value X of the electrode pattern 5 on the upper surface side by “1” for each cycle of the input pulse signal. In the case of FIG. 31, when the increased coordinate value X reaches “5”, the coordinate value X is returned to “1” and the coordinate value Y of the electrode pattern on the lower surface side is increased by “1”. When the increased coordinate value Y reaches “5”, the coordinate value Y is returned to “1”.

  The coordinate values X and Y generated in this way are given to the demultiplexer 53, the multiplexer 55, the reference value table 147, and the determination unit 73. Thus, the reference value Vref suitable for each measurement point is given from the reference value table 147 to the comparator 69. Further, the demultiplexer 53 and the multiplexer 55 are controlled to be switched in preparation for the input of the input pulse signal.

On the other hand, the sequencer 145 waits for detection of the falling edge of the input pulse signal (S12). Here, when the falling edge is detected, the sequencer 145 notifies the measurement unit 149 of this edge detection, and causes the enable control circuit 151 to start outputting the enable signal.
At this time, in the delay circuit stage 91, a delay output signal having a time difference of 2 ns is generated, and the delay output signal existing at the time of input of the strobe signal is taken into the storage unit 93 all at once.

Thereafter, the change point detector 153 detects the timing at which the detection signal exceeds the reference value Vref (that is, the change point).
The sequencer 145 waits for the change point detection process to be completed (S13).
Next, the sequencer 145 outputs an interrupt request to the determination unit 73 (S14). The determination unit 73 to which this interrupt request has been input compares the detected count value with a reference value, and determines the presence or absence of an operation input to the measurement point based on the comparison result.

  Thereafter, the sequencer 145 determines whether or not a stop request exists (S15). If the stop request is not confirmed, the operation returns to the XY coordinate generation operation again and the above operation is repeated. When the stop request is confirmed, the sequencer 145 ends the operation.

(E-4) Summary As described above, when detecting the length of time until the detection signal exceeds the reference potential Vref and determining the presence / absence of an operation input, it is overwhelmingly faster than the prior art. Judgment operation becomes possible. For example, when executing determination processing for 10 points, 20 ms is required in the prior art, but in the case of the embodiment, 20 μs is sufficient. For this reason, it becomes possible to cope with high-speed input, which was difficult to apply in the prior art.

Of course, the capacitance change measuring circuit 143 according to this embodiment can also be used for multipoint detection.
In addition, since the operation up to the input stage of the current input voltage output type amplifier 59 operates in the current mode, high noise resistance can be expected. That is, the capacitance change measuring circuit 143 according to the embodiment can be expected to have sufficient accuracy in terms of detection accuracy.
Further, in the case of this embodiment, the appearance position of the change point can be detected with the same accuracy as the case of using the clock signal of 500 MHz (2 ns) while using the clock signal of 50 MHz (20 ns).

  That is, it is possible to realize the capacitance change measuring circuit 143 that operates at a lower frequency than the conventional method. Note that by reducing the frequency of the operation clock, the power consumption of the capacitance change measurement circuit 143 can be reduced. This reduction in power consumption is advantageous in realizing a long operating time, particularly when the capacitive sensor module 141 is mounted on a portable electronic device. This also facilitates the mounting of the capacitive sensor module 141 on the portable electronic device.

In addition, phase-locked PLL is achieved by lowering the operating clock frequency.
Loop circuit such as a clock circuit can be eliminated. Accordingly, the integration of the capacitance change measuring circuit 143 is facilitated.

(F) Embodiment 4
(F-1) Detection Principle In this embodiment, attention is paid to the difference in the pulse width of the detection signal with respect to the input pulse signal. FIG. 32 shows the relationship between the response waveform focused on the measurement point (closed circuit) and the measured pulse width ΔT. In the figure, the detection signal when there is no operation input is indicated by a solid line, and the detection signal when there is an operation input is indicated by a broken line.

As shown in the figure, the pulse width ΔT2 when there is an operation input is longer than the pulse width ΔT1 when there is no operation input. In this embodiment, the time length during which the detection signal exceeds the reference potential Vref is measured as the pulse width.
The horizontal axis in the figure is the elapsed time from the falling timing of the input pulse signal, and the vertical axis in the figure is the amount of current corresponding to the response waveform.

(F-2) System Configuration FIG. 33 shows a system configuration example of the capacitive sensor module 161 according to this embodiment. Note that, in FIG. 33, the same reference numerals are given to the portions corresponding to FIG.
The capacitance type sensor module 161 includes a capacitance type sensor device 43 and a capacitance change measurement circuit 163.

The capacitance change measurement circuit 163 includes an oscillator 51, a demultiplexer 53, a multiplexer 55, a sequencer 165, a current input voltage output amplifier 59, a comparator 69, a reference value table 167, a measurement unit 169, and a determination unit 73.
In the case of this embodiment, since the pulse width of the detection signal output from the current input voltage output type amplifier 59 is measured, the peak hold circuit and its discharge circuit as in Embodiment 1 are unnecessary.
In the following, only components that are novel in this embodiment will be described.

(1) Sequencer The sequencer 165 is a circuit that outputs, as coordinate information (X, Y), the connection order to the electrode pattern 5 that supplies the input pulse signal and the connection order to the electrode pattern 7 from which the response signal is extracted. . In the case of this embodiment, the sequencer 165 manages the control timing based on the falling edge of the input pulse signal. This function is the same as in Embodiment 1.

  In the case of this embodiment as well, the sequencer 165 is common to Embodiment 1 in that it generates control timings for the measurement unit 169, the determination unit 73, and the like. However, the sequencer 165 according to this embodiment outputs a detection signal of the falling edge of the input pulse signal to the measurement unit 169. This is because the difference in the pulse width of the detection signal is to be measured in this embodiment.

(2) Reference Value Table The reference value table 167 is a storage area that stores the coordinates of the measurement points and the reference value Vref in association with each other. The reason why the reference potential Vref is varied according to the measurement point is that, as shown in FIG. 12, the amplitude and waveform of the detection signal vary greatly according to the operation point. Therefore, in the case of this embodiment, the reference potential Vref is optimized for each measurement point so that the presence / absence of an operation input can be measured as a change in pulse width.

(3) Measuring Unit The measuring unit 169 is a circuit device that detects a change point of the logic output level that appears in the comparison output signal input from the comparator 69. FIG. 34 shows a configuration example of the measurement unit 169 according to this embodiment. Note that, in FIG. 34, the same reference numerals are given to the portions corresponding to FIG.
The measurement unit 169 includes a delay circuit stage 91, a storage unit 93, an enable control circuit 151, an AND circuit 97, and a change point detection unit 171.

  In the case of this embodiment, the measurement unit 169 employs the delay circuit stage 91 having the same structure as that of Embodiment 1. That is, the delay circuit stage 91 is configured by a series circuit of delay elements having the same unit delay time. Also in this embodiment, a delay element having a unit delay time of 2 ns at room temperature is used.

  In the case of this embodiment, the number of delay elements constituting the delay circuit stage 91 is such that the time lengths of the delay output signals at a plurality of points existing on the delay circuit stage 91 at the same time are “1” as the delay output signal. Is set to be longer than the time width that may appear. That is, the same detection method as that in Embodiment 1 is adopted. Of course, the detection method of embodiment 2 can also be applied. Below, the case where the same detection method as Embodiment 1 is adopted will be described.

  The storage unit 93 is configured by a storage device that captures the delayed output signal appearing at each output stage of the delay element into the corresponding storage area in synchronization with the strobe pulse. Also in this embodiment, the storage unit 93 is configured by the same number of flip-flop circuits as the delay elements. The input terminals of the flip-flop circuits are connected to the output terminals of the corresponding delay elements.

  The output terminals of the flip-flop circuits are connected to the change point detector 171, respectively. Further, the clock terminal of the flip-flop circuit is used for inputting a strobe signal that defines the timing for taking in the signal value appearing at the input terminal.

  The enable control circuit 151 and the AND circuit 97 are for generating the strobe signal described above. Note that the enable control circuit 151 generates an enable signal for designating a strobe signal output possible period. For example, the enable control circuit 151 includes a counter. The count operation of the enable control circuit 151 is started by notification of the detection signal ta at the falling edge of the input pulse signal.

  At this time, the enable control circuit 151 counts the clock signal input at 50 MHz, and ends the count operation when the count value reaches a preset value. The end timing of the count operation is desirably set for each measurement point. This is because the period length necessary for measuring the pulse width varies greatly depending on the measurement point.

The enable control circuit 151 outputs only one enable signal at this end point. The AND circuit 97 generates a strobe signal by a logical product operation of the enable signal and the clock signal.
The change point detection unit 171 is a circuit device that detects a period length in which the detection signal is equal to or higher than the reference potential Vref based on the delayed output signals at a plurality of time points taken into the storage unit 93 when the strobe signal is output. The change point detector 171 counts the number of “1” appearing as a delayed output signal.

  FIG. 35 specifically shows an example of a sequence of numbers taken into the change point detection unit 171. FIG. 35A shows the waveform of the input pulse signal. FIG. 35B shows the waveform of the clock signal. As described above, the clock signal is given at 50 MHz (20 ns). FIG. 35C shows the waveform of the strobe signal.

FIG. 35 (D1) is a numerical sequence example of the import example 1 corresponding to the case where there is no operation input. FIG. 35 (D2) is an example of a numerical sequence of the capturing example 2 corresponding to the case where there is an operation input. As can be seen by comparing FIG. 35 (D1) and FIG. 35 (D2), the number of “1” varies greatly depending on whether or not there is an operation input.
Incidentally, FIG. 35 (D1) shows a case where the pulse width of the detection signal is given by 14 delay elements. On the other hand, FIG. 35 (D2) shows a case where the pulse width of the detection signal is given by 20 delay elements.

  Note that one count value difference corresponds to 2 ns (500 MHz) difference. However, in order for the subsequent determination by the determination unit 73 to be executed accurately, the number of count values in the absence of an operation input needs to appear at the reference point. That is, a calibration operation is necessary. The calibration method is the same as in the first embodiment.

(F-3) Contents of Processing Operation The processing operation of the capacitive sensor module 161 will be described below according to the operation flow of the sequencer 165 (FIG. 36).

  First, the sequencer 165 generates coordinates for designating a position on the operation surface to be measured (S21). Here, the sequencer 165 increases the coordinate value X of the electrode pattern 5 on the upper surface side by “1” for each cycle of the input pulse signal. In the case of FIG. 36, when the increased coordinate value X reaches “5”, the coordinate value X is returned to “1” and the coordinate value Y of the electrode pattern on the lower surface side is increased by “1”. When the increased coordinate value Y reaches “5”, the coordinate value Y is returned to “1”.

  The coordinate values X and Y generated in this way are given to the demultiplexer 53, the multiplexer 55, the reference value table 167, and the determination unit 73. Thereby, the reference value Vref suitable for each measurement point is given from the reference value table 167 to the comparator 69. Further, the demultiplexer 53 and the multiplexer 55 are controlled to be switched in preparation for the input of the input pulse signal.

On the other hand, the sequencer 165 waits for detection of the falling edge of the input pulse signal (S22). Here, when the falling edge is detected, the sequencer 165 notifies the measurement unit 169 of this edge detection, and causes the enable control circuit 151 to start outputting the enable signal.
At this time, in the delay circuit stage 91, a delay output signal having a time difference of 2 ns is generated, and the delay output signal existing at the time of input of the strobe signal is taken into the storage unit 93 all at once.

Thereafter, the change point detection unit 171 detects the length of the period in which the detection signal is greater than the reference value Vref (that is, the pulse width) as the number of “1” s in the read sequence.
The sequencer 165 waits for the elapse of the appearance timing of the second change point assumed for the measurement point (S23).
Next, the sequencer 165 outputs an interrupt request to the determination unit 73 (S24). The determination unit 73 to which this interrupt request has been input compares the detected count value with a reference value, and determines the presence or absence of an operation input to the measurement point based on the comparison result.

  Thereafter, the sequencer 165 determines whether or not there is a stop request (S25). If the stop request is not confirmed, the operation returns to the XY coordinate generation operation again and the above operation is repeated. If the stop request is confirmed, the sequencer 165 ends the operation.

(F-4) Summary As described above, even when the presence / absence of an operation input is determined by detecting the length of a period during which the detection signal is larger than the reference potential Vref, it is overwhelming as compared with the prior art. High-speed judgment operation is possible. For example, when executing determination processing for 10 points, 20 ms is required in the prior art, but in the case of the embodiment, 20 μs is sufficient. For this reason, it becomes possible to cope with high-speed input, which was difficult to apply in the prior art.

Of course, the capacitance change measuring circuit 163 according to this embodiment can also be used for multipoint detection.
In addition, since the operation up to the input stage of the current input voltage output type amplifier 59 operates in the current mode, high noise resistance can be expected. That is, the capacitance change measuring circuit 163 according to the embodiment can be expected to have sufficient accuracy in terms of detection accuracy.
Further, in the case of this embodiment, the appearance position of the change point can be detected with the same accuracy as the case of using the clock signal of 500 MHz (2 ns) while using the clock signal of 50 MHz (20 ns).

  That is, the capacitance change measuring circuit 163 that operates at a lower frequency than the conventional method can be realized. Note that by reducing the frequency of the operation clock, the power consumption of the capacitance change measurement circuit 143 can be reduced. This reduction in power consumption is advantageous for realizing a longer operating time, particularly when the capacitive sensor module 161 is mounted on a portable electronic device. This also facilitates the mounting of the capacitive sensor module 161 on the portable electronic device.

In addition, the PLL (Phase-Locked
Loop circuit such as a clock circuit can be eliminated. Further, since the clock multiplication circuit is not required, the capacitor charging operation is not required, and the integration of the capacitance change measuring circuit 163 is facilitated accordingly. Further, the number of pins required for the integrated circuit can be reduced as compared with the case of using an external capacitor.

(G) Other embodiment examples (G-1) Other configurations 1 of the measurement unit
In the above-described embodiments, the case where the strobe signal is generated by the logical product of the enable signal and the clock signal has been described.
However, a circuit configuration that does not generate a strobe signal is also conceivable.

  FIG. 37 shows a circuit example of the measurement unit 181 corresponding to this type of configuration. Note that, in FIG. 37, the same reference numerals are given to portions corresponding to FIG. The measurement unit 181 includes a delay circuit stage 91, an input selection unit 183, a storage unit 185, an enable control circuit 187, and a change point detection unit 189. As indicated by the same reference numerals, the configuration of the delay circuit stage 91 is the same as that of the above-described embodiment. That is, the delay circuit stage 91 has a circuit configuration in which delay elements having the same unit delay amount are connected in series. Further, the number of stages of delay elements is set according to the measurement period length required in each of the above-described embodiments.

Each of the input selection unit 183 and the storage unit 185 is a circuit device including a multiplexer and a flip-flop corresponding to the output terminal of the delay element.
Here, when the enable signal is an effective value (corresponding to the H level in the above-described embodiment), the multiplexer operates so as to select the delayed output signal input from the corresponding delay element. On the other hand, when the enable signal has an invalid value (corresponding to the L level in the above-described embodiment), the multiplexer operates so as to select the output signal of the corresponding flip-flop.

That is, the multiplexer configuring the input selection unit 183 transfers the delayed output signal of the corresponding delay element to the flip-flop while the enable signal is an effective value, and loops the output value of the flip-flop during other periods. Used.
On the other hand, each time a clock signal is input, the flip-flop forming the storage unit 185 performs an operation of capturing the output signal of the multiplexer. As described above, the input selection unit 183 and the storage unit 185 realize operations equivalent to the above-described embodiments.

  The enable control circuit 187 uses a circuit device that generates an enable signal at a timing corresponding to each of the above-described embodiments. The change point detection unit 189 also uses a circuit device that detects a change point corresponding to each of the above-described embodiments. That is, the measurement unit 181 having this circuit configuration can be applied to any of the above-described embodiments.

(G-2) Other configuration 2 of measurement unit
In the above-described embodiments, the case where the delay circuit stage is configured by connecting delay elements in series has been described.
However, delayed output signals having different delay amounts for each unit delay time can be realized by other circuit configurations.

FIG. 38 shows a circuit example of the measurement unit 191 corresponding to this type of configuration. Note that, in FIG. 38, the same reference numerals are given to portions corresponding to FIG. The measurement unit 191 includes a delay circuit stage 193, a storage unit 93, an enable control circuit 195, an AND circuit 97, and a change point detection unit 197.
As shown in FIG. 38, the delay circuit stage 193 is configured by a parallel circuit in which the number of stages of delay elements is different by one stage.

  That is, the delay circuit stage 193 is a parallel connection of circuits each having a delay amount different by unit delay time, such as a circuit having one delay element, a circuit having two delay elements, a circuit having three delay elements, and so on. Configure. This circuit configuration has a problem that the circuit area increases as the required delay time range increases, but this circuit configuration is sufficiently practical when the delay time range is small.

  Incidentally, as the enable control circuit 195, a circuit device that generates an enable signal at a timing corresponding to each of the above-described embodiments is used. The change point detector 197 also uses a circuit device that detects a change point corresponding to each of the above-described embodiments. That is, the measurement unit 181 having this circuit configuration can be applied to any of the above-described embodiments.

(G-3) Other Measurement Method of Detection Signal In the case of the first and second embodiments, the case where the peak level of the positive electrode cycle of the detection signal is detected has been described. That is, the case where the maximum value of the detection signal is detected and the time length required for the discharge is measured has been described.
However, the technique described above can also be applied when detecting the peak level of the negative electrode period of the detection signal. That is, the present invention can be applied to the case where the minimum value of the detection signal is detected and the time length required for the charging is measured.

FIG. 39 shows a system configuration example of the capacitive sensor module 201 corresponding to this detection method. Note that, in FIG. 39, the same reference numerals are given to the portions corresponding to FIG.
The capacitance type sensor module 201 includes a capacitance type sensor device 43 and a capacitance change measurement circuit 203.

  The capacitance change measuring circuit 203 includes an oscillator 51, a demultiplexer 53, a multiplexer 55, a sequencer 57, a current input voltage output type amplifier 59, a peak hold circuit 205, a variable current source 207, a current value table 65, a discharge control switch 67, and a comparator 69. , A measurement unit 209 and a determination unit 73.

In the case of FIG. 39, the peak hold circuit 205 detects the peak level on the negative side of the detection signal. For this reason, the direction of the anode and the cathode of the diode D constituting the peak hold circuit 205 is connected in the opposite direction to the peak hold circuit 61 of FIG. The ground potential here is connected to a negative power source.
In the case of FIG. 39, a chargeable current source is used as the variable current source 207. 39 measures the number of “0” s that appear before the signal value of the delayed output signal changes to “1” until the potential of the capacitor C exceeds the reference potential Vref ′. A method of detecting the time length for each measurement point is adopted.

(G-4) Product Example (a) System Configuration In the above description, the structure and operation contents of the capacitive sensor module have been described. However, the capacitive sensor module described above is also distributed in the form of products mounted on various electronic devices. Examples of mounting on electronic devices are shown below.

40 and 41 illustrate functional configuration examples of the electronic device.
The electronic device 211 illustrated in FIG. 40 has a functional configuration that assumes a type of electronic device in which a capacitive sensor module 215 is stacked on the surface of the display device 213. The electronic device 211 is equipped with a system control unit 217 that controls the entire system. As the display device 213, for example, a liquid crystal panel, an organic EL display panel, an FED panel, a plasma panel, or the like is used.

  An electronic device 221 illustrated in FIG. 41 has a functional configuration that assumes an electronic device that does not use a display device. As this type of electronic device 221, for example, a scanner or the like that designates the capture range while viewing through the capacitive sensor module 223 is assumed. Of course, in this case, the wiring and the like constituting the capacitive sensor are made of a transmissive material. Of course, the electronic device 221 is equipped with a system control unit 225 for controlling the entire system.

(B) Specific example Below, the specific external appearance example of an electronic device is shown.
FIG. 42 shows an example of the appearance of the television receiver 231. The television receiver 231 has a structure in which a display screen 235 and a capacitive sensor module 237 are arranged on the front surface of the housing 233. The various types of embodiments described above are applied to the capacitance type sensor module 237 here.

FIG. 43 shows an example of the external appearance of the digital camera 241. 43A is an example of the appearance on the front side (subject side), and FIG. 43B is an example of the appearance on the back side (photographer side).
The digital camera 241 includes a protective cover 243, an imaging lens unit 245, a display screen 247, a capacitive sensor module 249, a control switch 251, and a shutter button 253. The various types of embodiments described above are applied to the capacitance type sensor module 249 here.

  FIG. 44 shows an appearance example of the video camera 261. The video camera 261 includes an imaging lens 265 that images a subject in front of the main body 263, a shooting start / stop switch 267, a display screen 269, and a capacitive sensor module 271. The various types of embodiments described above are applied to the capacitance type sensor module 271 here.

  FIG. 45 shows an example of the appearance of a mobile phone 281 as a mobile terminal device. A cellular phone 281 illustrated in FIG. 45 is a foldable type, and FIG. 45A illustrates an appearance example in a state where the housing is opened, and FIG. 45B illustrates an appearance example in a state where the housing is folded.

  The cellular phone 281 includes an upper housing 283, a lower housing 285, a connecting portion (in this example, a hinge portion) 287, a main display screen 289, a capacitive sensor module 291, an auxiliary display screen 293, and a capacitive sensor. A module 295, a picture light 297, and an imaging lens 299 are included. The various embodiments described above are applied to the capacitive sensor modules 291 and 295 here.

FIG. 46 shows an example of the appearance of the notebook computer 301. A notebook computer 301 illustrated in FIG. 46 includes a lower housing 303, an upper housing 305, a keyboard 307, a display screen 309, a capacitive sensor module 311, and a touch panel 313. The various types of embodiments described above are applied to the capacitive sensor module 311 and the touch panel 313 here. Note that the capacitive sensor used for the touch panel 313 can be formed of an impermeable material.
In addition, the “electronic device” in this specification includes a portable audio playback device, a game machine, an electronic book, an electronic dictionary, a stationary home appliance, an industrial machine, an office device, and the like.

(G-5) Others Various modifications can be considered for the above-described embodiments within the scope of the gist of the invention. Various modifications and applications created or combined based on the description of the present specification are also conceivable.

It is a figure which shows schematic plan structure of an electrostatic capacitance type sensor module. It is a figure which shows schematic sectional structure of an electrostatic capacitance type sensor module. It is a figure which shows the example of an external appearance structure of an electrostatic capacitance type sensor module. It is a figure explaining the function structural example of an electrostatic capacitance type sensor module. It is a figure explaining the shape of the response waveform with respect to an input pulse signal. It is a figure explaining the potential change at the time of discharging a peak hold voltage. It is a figure which shows the example of a form of an electrostatic capacitance type sensor module. It is a figure explaining the difference in the propagation path length formed on an operation surface. It is a figure which shows the equivalent circuit of the propagation path formed on an operation surface. It is a figure which shows the general | schematic characteristic of the propagation path formed on an operation surface. It is a figure explaining the change of the detection waveform corresponding to each measurement point. It is a figure explaining the difference in the amplitude of the detection waveform corresponding to a measurement point. It is a figure explaining the difference in the measurement time length by the difference in the amplitude of a detection waveform. It is a figure explaining adjustment of measurement time length by current control for every measurement point. It is a figure which shows an example of an electric current value table. It is a figure explaining the correspondence of an electric current value and a measurement point. It is a figure which shows the internal structural example of a measurement part. It is a figure explaining the output timing of a strobe signal. It is a figure which shows the example of several numbers of the delay output signal taken in by a strobe signal. It is a flowchart figure explaining the operation example of a sequencer. It is a figure explaining the function structural example of an electrostatic capacitance type sensor module. It is a figure which shows the internal structural example of a measurement part. It is a figure explaining the output timing of a strobe signal. It is a figure explaining a toggle clock signal. It is a figure which shows the example of several sequences of the delay output signal taken in continuously by the strobe signal. It is a figure explaining a calibration operation. It is a figure explaining the difference in the measurement time length by the difference in the amplitude of a detection waveform. It is a figure explaining the function structural example of an electrostatic capacitance type sensor module. It is a figure which shows the internal structural example of a measurement part. It is a figure which shows the example of several numbers of the delay output signal taken in by a strobe signal. It is a flowchart figure explaining the operation example of a sequencer. It is a figure explaining the difference in the measurement time length by the difference in the amplitude of a detection waveform. It is a figure explaining the function structural example of an electrostatic capacitance type sensor module. It is a figure which shows the internal structural example of a measurement part. It is a figure which shows the example of several numbers of the delay output signal taken in by a strobe signal. It is a flowchart figure explaining the operation example of a sequencer. It is a figure which shows the other internal structural example of a measurement part. It is a figure which shows the other internal structural example of a measurement part. It is a figure explaining the other functional structural example of an electrostatic capacitance type sensor module. It is a figure which shows the example of a conceptual structure of an electronic device. It is a figure which shows the example of a conceptual structure of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Capacitance type sensor device 21 Capacitance type sensor module 23 Capacitance type sensor device 27 Capacitance change measurement circuit 33 Capacitance change detection circuit 35 Determination part

Claims (7)

An electrode drive unit that inputs a pulse signal line-sequentially at a predetermined period to a plurality of rows of first electrode patterns constituting a capacitive sensor device;
Has a capacity element, said first electrode pattern and a peak hold circuit for holding a voltage corresponding to the peak level of the detection signal taken through the second electrode pattern of a plurality of columns intersecting the capacitive element at the other layers When,
At a predetermined timing synchronized with the pulse signal, a current source that starts discharging the capacitive element at a discharge rate according to coordinates in the sensor device;
A comparator that compares the voltage of the capacitive element with a reference value;
A delay circuit stage that sequentially delays the comparison output signal of the comparator and generates a plurality of delayed output signals having different comparison time points by unit delay time length;
A storage unit for storing signal values corresponding to the plurality of delayed output signals;
Based on the plurality of signal values stored in the storage unit, the electrostatic capacity-type sensor device capacitance change detection circuit and a detection unit for detecting an amount of time to be measured by the unit delay time length accuracy . The capacitance change detection circuit according to claim 1, wherein a range of a delay amount in the delay circuit stage is equal to or longer than a time width in which a change point may appear in the signal value of the detection signal. The range of the delay amount in the delay circuit stage is less than a time width in which a change point may appear in the signal value of the detection signal,
The capacitance change detection circuit according to claim 1, wherein the detection of the amount of time to be measured is performed by repeating a signal value storing operation and a detecting operation for the storage unit at a plurality of time points. A first electrode pattern of the multi-column, and a sensor device of a capacitive type and a second electrode pattern of a plurality of rows that intersect at the first electrode pattern and the other layer,
An electrode driver that inputs a pulse signal line-sequentially with a predetermined period to the plurality of first electrode patterns;
It has a capacity element, a peak hold circuit for holding a voltage corresponding to the peak level of the plurality of rows second detection signals taken through the electrode pattern of the capacitor element,
At a predetermined timing synchronized with the pulse signal, a current source that starts discharging the capacitive element at a discharge rate according to coordinates in the sensor device;
A comparator that compares the voltage of the capacitive element with a reference value;
A delay circuit stage that sequentially delays the comparison output signal of the comparator and generates a plurality of delayed output signals having different comparison time points by unit delay time length;
A storage unit for storing signal values corresponding to the plurality of delayed output signals;
Based on a plurality of signal values stored in the storage unit, a detection unit that detects the amount of time to be measured with accuracy of the unit delay time length;
On the basis of the detected amount of time by the detection unit, capacitive sensor module and a determining unit an operation input by the object with a human body or an equivalent electrical characteristics. A first electrode pattern of a plurality of rows constituting the capacitive sensor device, a process of inputting pulse signals sequentially line at a predetermined cycle,
A process of holding a voltage corresponding to a peak level of a detection signal extracted through a plurality of columns of second electrode patterns intersecting with the first electrode pattern in another layer in a capacitor element;
At a predetermined timing synchronized with the pulse signal, a process of starting discharge of the capacitive element at a discharge rate according to coordinates in the capacitive sensor device;
A process of comparing the voltage of the capacitive element with a reference value;
A process of sequentially delaying the comparison output signal obtained by the comparison process, and generating a plurality of delayed output signals having different comparison time points by unit delay time lengths;
Processing for storing signal values corresponding to the plurality of delayed output signals in a storage unit;
Based on the plurality of signal values stored in the storage unit, the capacitive sensor device capacitance change detection method that includes a process of detecting an amount of time by the unit delay time length of accuracy to be measured. A display device;
A capacitive sensor device which is disposed on a surface of the display device, a first electrode pattern of the multi-column, the second electrode of the plurality of columns intersecting at said first electrode pattern and the other layer A capacitive sensor device having a pattern;
An electrode driver that inputs a pulse signal line-sequentially with a predetermined period to the plurality of first electrode patterns;
It has a capacity element, a peak hold circuit for holding a voltage corresponding to the peak level of the plurality of rows second detection signals taken through the electrode pattern of the capacitor element,
At a predetermined timing synchronized with the pulse signal, a current source that starts discharging the capacitive element at a discharge rate according to coordinates in the sensor device;
A comparator that compares the voltage of the capacitive element with a reference value;
A delay circuit stage that sequentially delays the comparison output signal of the comparator and generates a plurality of delayed output signals having different comparison time points by unit delay time length;
A storage unit for storing signal values corresponding to the plurality of delayed output signals;
Based on a plurality of signal values stored in the storage unit, a detection unit that detects the amount of time to be measured with accuracy of the unit delay time length;
A determination unit that determines an operation input by a human body or an object having an equivalent electrical characteristic based on the amount of time detected by the detection unit;
An electronic device equipped with a system control unit that controls the operation of the entire system. A first electrode pattern of the multi-column, and a sensor device of a capacitive type and a second electrode pattern of a plurality of rows that intersect at the first electrode pattern and the other layer,
An electrode driver that inputs a pulse signal line-sequentially with a predetermined period to the plurality of first electrode patterns;
It has a capacity element, a peak hold circuit for holding a voltage corresponding to the peak level of the plurality of rows second detection signals taken through the electrode pattern of the capacitor element,
At a predetermined timing synchronized with the pulse signal, a current source that starts discharging the capacitive element at a discharge rate according to coordinates in the sensor device;
A comparator that compares the voltage of the capacitive element with a reference value;
A delay circuit stage that sequentially delays the comparison output signal of the comparator and generates a plurality of delayed output signals having different comparison time points by unit delay time length;
A storage unit for storing signal values corresponding to the plurality of delayed output signals;
Based on a plurality of signal values stored in the storage unit, a detection unit that detects the amount of time to be measured with accuracy of the unit delay time length;
A determination unit that determines an operation input by a human body or an object having an equivalent electrical characteristic based on the amount of time detected by the detection unit;
An electronic device equipped with a system control unit that controls the operation of the entire system.