JP5070599B2 - Semiconductor device manufacturing method and plasma etching apparatus - Google Patents

Description

  The present invention relates to a technique for processing a workpiece made of a semiconductor material by etching, and particularly to a technique for processing a workpiece made of a compound semiconductor containing indium as an essential constituent element by dry etching.

  In recent years, there has been a demand for higher performance and higher performance of optical devices such as optical active elements (for example, semiconductor lasers and optical amplifiers) and optical passive elements (for example, multiplexers / demultiplexers and optical waveguides). As this type of optical device, an optical integrated device made of a compound semiconductor such as a III-V group compound semiconductor has attracted attention. In the manufacturing process of an optical integrated device, a technique for processing a compound semiconductor with high accuracy by etching is required. When a groove is formed by processing a compound semiconductor by etching, it is important to precisely control the width, depth, and shape of the groove. For this reason, as compared with wet etching, there is a tendency to use dry etching that can satisfactorily realize the verticality of the sidewall of the formed groove, the reproducibility of the groove, and the etching uniformity.

  In general, in dry etching, in order to obtain a desired etching shape, an etching condition (type of introduced gas type, distribution of introduced gas type, pressure in the chamber, substrate temperature) according to the characteristics of the workpiece is applied. is necessary. As a method of processing a compound semiconductor by dry etching, dry etching using a plasma source is widely used. Examples of the plasma source include a capacitively coupled plasma (CCP) source, an inductively coupled plasma (ICP) source, a microwave-excited surface wave plasma (SWP) source, and an electron. Examples include cyclotron resonance plasma (ECP) sources.

  In particular, when an inductively coupled plasma source, microwave-excited surface wave plasma source, or electron cycloton resonance plasma source is used, the plasma density by discharge power and the incident energy of ions by bias power can be controlled independently. High-precision fine processing of the shape is possible. In particular, dry etching of compound semiconductors using inductively coupled plasma is widely used as a means that can achieve both high speed etching and low damage.

Regarding dry etching using a plasma source, for example, Patent Document 1 (Japanese Patent Laid-Open No. 2006-005317), Patent Document 2 (Japanese Patent Laid-Open No. 2005-150404), and Patent Document 3 (Japanese Patent Laid-Open No. 2004-080862). And Patent Document 4 (Japanese Patent Laid-Open No. 2004-063658).
JP 2006-005317 A JP 2005-150404 A JP 2004-080662 A JP 2004-063658 A

  In dry etching, the etching rate ratio between the underlying workpiece and the mask material, that is, the selection ratio (= workpiece etching rate / mask material etching rate) is an important evaluation parameter. Is desirable to be high. In addition, when a plurality of semiconductor layers having different compositions (for example, an InP layer, an InGaAsP layer, and an InGaAlAs layer) are processed by dry etching, an etching rate difference (etching rate dependency) between semiconductor layers is also an important evaluation parameter. In order to increase the processing accuracy, it is desirable that the difference in etching rate is small.

  In order to increase the selectivity, a metal mask can be used as an etching mask. In this case, when the metal mask is etched, the metal element of the metal mask does not become a volatile product and adheres to the processed surface, which may greatly affect the characteristics of the semiconductor device. Therefore, it is difficult to use a metal mask as a mask for dry etching before performing crystal growth.

For example, when an optical waveguide using a compound semiconductor is manufactured, an InP layer having a relatively low refractive index is used as a cladding layer, and a semiconductor material containing In, such as InGaAsP and InGaAlAs having a relatively high refractive index, is used as a core layer. Used as. When forming an optical waveguide in which a striped mesa structure with a core layer is embedded with a cladding layer, either dry etching or wet etching can be used as a method for forming this mesa structure. From the viewpoint of controlling with high accuracy, it is preferable to use dry etching rather than wet etching. However, if the selection ratio between the compound semiconductor, which is the workpiece, and the mask (for example, SiO ₂ layer) is low, the mask is gradually scraped during the dry etching process, so that etching is performed in a region larger than the original mask pattern. This makes it difficult to produce a pattern with a desired accuracy. Further, when the mask material that has been shaved adheres to the processed surface, there arises a problem that the smoothness of the processed surface deteriorates. Furthermore, if the etching rate of the mask is not uniform, there arises a problem that the smoothness of the side wall of the mesa structure in the optical waveguide direction is deteriorated. In order to suppress such problems, the mask can be thickened. However, if the mask is thick, the thickness of the resist film used in the photolithography process for patterning the mask material must be increased. Therefore, another problem arises that it becomes difficult to pattern the mask material with high accuracy.

  On the other hand, with respect to the etching rate dependency of the workpiece, when the etching rate difference between two layers having different compositions is large, if the laminated structure composed of these two layers is processed by dry etching, the perpendicularity or smoothness of the processed cross section is obtained. As a result, the desired processed shape is difficult to obtain. For example, in the case of an optical integrated device having a compound semiconductor layer such as InGaAsP or InGaAlAs epitaxially grown on an InP substrate, if the etching rate difference between indium compound semiconductors having different compositions is large, high-precision microfabrication becomes difficult. Therefore, there is a demand for optimum process conditions that can reduce the etching rate difference.

  In particular, when an optical integrated device in which a plurality of optical functional elements are monolithically integrated is manufactured, the layer thickness and composition of the semiconductor layer are generally different for each optical functional element formation region. Therefore, if there is the above-described difference in etching rate between the formation regions of the optical functional element, the etching depth differs between the formation regions, so that it is difficult to control the etching depth with high accuracy. In order to cope with this, it is possible to take measures to predict the etching depth in each formation region and to design the active layer and the waveguide so as to match the predicted etching depth. However, there is a problem that the etching depth cannot always be accurately predicted.

  In view of the above, an object of the present invention is to provide a method of manufacturing a semiconductor device and a plasma etching apparatus that can improve the selectivity between the compound semiconductor and the mask when the compound semiconductor is processed by dry etching. is there. Another object of the present invention is to provide a method of manufacturing a semiconductor device and a plasma etching apparatus that can reduce an etching rate difference between compound semiconductors having different compositions when a compound semiconductor is processed by dry etching. It is an object of the present invention to provide a method of manufacturing a semiconductor device and a plasma etching apparatus that can achieve both a reduction in the etching rate difference and a high selectivity.

According to the present invention, a step of forming a hard mask made of an inorganic dielectric material having a predetermined pattern on a group III-V compound semiconductor containing indium as an essential constituent element, and a hard mask made of the inorganic dielectric material , After the formation, a mixed gas composed of two components of hydrogen iodide gas and silicon tetrachloride gas is introduced into the III-V group compound semiconductor disposed in the chamber of the plasma etching apparatus, and the mixed gas is turned into plasma. And a method of selectively etching the group III-V compound semiconductor by causing the plasma-mixed gas to enter the group III-V compound semiconductor. . The mixing ratio of the flow rate of the hydrogen iodide gas to the total flow rate of the mixed gas is 60% or more and 85% or less.

According to the present invention, there is provided a plasma etching apparatus for processing a group III-V compound semiconductor having a hard mask made of an inorganic dielectric material having a predetermined pattern, the plasma etching apparatus being disposed in a chamber, and the group III-V compound Depending on the holder for supporting the semiconductor , the gas supply source for introducing a mixed gas composed of two components of hydrogen iodide gas and silicon tetrachloride gas on the III-V compound semiconductor , and the supply of high-frequency power, A high-frequency antenna that applies a high-frequency magnetic field that generates an induction electric field for generating a plasma of the introduced mixed gas into the chamber, a high-frequency oscillator that supplies the high-frequency power to the high-frequency antenna, and the plasma-mixed mixture It includes a bias voltage application means for forming an electric field for entering a gas into the group III-V compound semiconductor, wherein the III V compound semiconductor contains indium as a constituent element, the gas supply source, adjusts the flow mixing ratio of the hydrogen iodide gas to the total flow rate of the mixed gas in the range of 85% or more and 60% or less A plasma etching apparatus is provided .

  As described above, the method of manufacturing a semiconductor device and the plasma etching apparatus according to the present invention use plasma of a mixed gas composed of two components of hydrogen iodide gas and silicon tetrachloride gas, and hydrogen iodide gas with respect to the total flow rate of the mixed gas. The dry etching is performed by adjusting the mixing ratio of the flow rate of 60% to 85%. As a result, it is possible to realize a high selectivity between a workpiece made of a compound semiconductor containing indium as an essential constituent element and an etching mask, and to reduce an etching rate difference between compound semiconductors having different compositions. .

  Therefore, it is possible to reduce the thickness of the etching mask and increase the patterning. In particular, when an optical integrated device including a plurality of optical functional elements having different semiconductor compositions is manufactured, the processing shape can be precisely controlled without depending on the semiconductor composition.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings.

  1A to 1D are process diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. In this manufacturing method, as shown in FIG. 1A, a mask layer 11 is formed on a workpiece 10 made of a compound semiconductor containing indium (In), and a resist film 12 is formed on the mask layer 11. Is applied. Next, the resist film 12 is patterned by a lithography process to form a resist pattern 12p shown in FIG. By etching the mask layer 11 using the resist pattern 12p as a mask, a mask pattern (etching mask) 11p shown in FIG. 1C is formed. After the mask pattern 11p is formed, the workpiece 10 is placed in the chamber of the plasma etching apparatus.

From the viewpoint of improving the selectivity (= etching rate of the workpiece 10 / etching rate of the mask pattern 11p), the mask pattern 11p includes an inorganic material such as silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ). It is preferable to use a hard mask made of a dielectric.

After the workpiece 10 is disposed in the chamber, the plasma etching apparatus introduces a mixed gas composed of two components of hydrogen iodide (HI) gas and silicon tetrachloride gas (SiCl ₄ ) gas into the chamber, The mixed gas is turned into plasma. Here, the mixing ratio of the flow rate of hydrogen iodide gas to the total flow rate of the mixed gas is adjusted to 60% or more and 85% or less. More preferably, the lower limit of the mixing ratio of the flow rate of hydrogen iodide gas is 65%, and the upper limit is 80%. The plasma etching apparatus causes the plasma mixed gas to enter the workpiece 10, thereby selectively etching the workpiece 10 e as shown in FIG.

  In the etching step, it is desirable that the temperature of the workpiece 10 is adjusted within a range of 160 ° C. or higher and 200 ° C. or lower from the viewpoint of promoting the separation of the indium-containing compound and improving the smoothness of the processed surface.

  The plasma etching apparatus desirably has a configuration capable of independently controlling the plasma density by the discharge power and the ion incident energy by the RF bias power. As this type of plasma etching apparatus, for example, an inductively coupled plasma (ICP) source, a microwave excited surface wave plasma (SWP) source, an electron cycloton resonance plasma (ECP) source, or a helicon wave excited plasma (HWP: Helicon Wave Plasma) source. Among the ICP sources, a plasma source including a magnet that can control the plasma density distribution of the mixed gas by applying a static magnetic field in the chamber is particularly desirable.

  Hereinafter, a suitable manufacturing process of this embodiment will be described in detail.

  The workpiece 10 is an indium III-V group compound semiconductor containing one or more compounds selected from the group consisting of InP, InGaAlAs, and InGaAsP. The workpiece 10 may be composed of a single semiconductor layer, or may be a stacked body of a plurality of semiconductor layers having different compositions. Alternatively, the workpiece 10 may be a single crystal substrate, or a single layer or a multiple layer growth layer structure epitaxially grown on the single crystal substrate. Alternatively, the workpiece 10 may have a plurality of types of growth layer structures formed in parallel on a single crystal substrate.

An inorganic dielectric material is deposited on the workpiece 10 by sputtering or CVD (Chemical Vapor Deposition) to form the mask layer 11 in FIG. Further, a resist is applied on the mask layer 11 to form a resist film 12 in FIG. 1A, and the resist film 12 is exposed and developed to form a resist pattern 12p in FIG. 1B. By using this resist pattern 12p and performing dry etching using a gas such as CF ₄ on the mask layer 11, the mask pattern 11p of FIG. 1C is formed. Thereafter, the resist pattern 12p is removed.

  Here, when the mask layer 11 is made of an inorganic dielectric material, in order to form the mask pattern 11p with high accuracy, the thickness of the mask layer 11 is desirably as thin as possible in consideration of the selection ratio, and is 50 nm. It is preferably set in the range of 1 μm or less.

  Next, the workpiece 10 having the mask pattern 11p is placed in a chamber of an etching apparatus including an ICP source. The ICP source has a magnet that can control the plasma density distribution of the mixed gas by applying a static magnetic field in the chamber. FIG. 2 is a diagram showing a schematic configuration of the plasma etching apparatus 20. The plasma etching apparatus 20 includes a vacuum chamber 21, a quartz plate 22, a high frequency loop antenna 23, a matching circuit 24, a high frequency power supply 25, a loop permanent magnet 26, a planar electrode 27, a substrate holder 30, a bias matching circuit 31, and a bias. A high-frequency power supply 32, a gas supply source 40, and a control unit 41. The high-frequency oscillator according to the present invention can be composed of a high-frequency power supply 25 and a matching circuit 24.

  A substrate holder 30 that supports the workpiece 10 is disposed inside the vacuum chamber 21. The substrate holder 30 is connected to a bias high-frequency power source 32 via a bias matching circuit 31, and the bias high-frequency power source 32 can apply a high-frequency bias to the workpiece 10 via the substrate holder 30. .

  The vacuum chamber 21 has an upper opening. The quartz plate (dielectric member) 22 is attached to the upper opening of the vacuum chamber 21 so as to seal the reaction chamber of the vacuum chamber 21 and form a window. The quartz plate 22 defines a plasma generation region of the vacuum chamber 21.

  Outside the plasma generation region, a high-frequency loop antenna 23 that forms a two-turn loop is disposed above the quartz plate 22. The high frequency loop antenna 23 is connected to a high frequency power source 25 via a matching circuit 24. A loop permanent magnet 26 is disposed coaxially with the high frequency loop antenna 23. The loop permanent magnet 26 generates a static magnetic field in a direction substantially orthogonal to the current flowing through the high-frequency loop antenna 23 and is disposed so as to be parallel to the surface of the quartz plate 22. The high frequency power supply 25 supplies high frequency power to the high frequency loop antenna 23 via the matching circuit 24. The high frequency loop antenna 23 applies a high frequency magnetic field in the vacuum chamber 21 that generates an induction electric field for converting the mixed gas introduced into the vacuum chamber 21 into plasma in response to the supply of the high frequency power.

  The planar electrode 27 is disposed between the quartz plate 22 and the high-frequency loop antenna 23 and in the vicinity of the quartz plate 22 so as to be parallel to the surface of the quartz plate 22. The planar electrode 27 may be made of, for example, a linear metal material. The planar electrode 27 has a shape that matches the shape of the window formed of the quartz plate 22 and has a function of forming a uniform electric field on the inner surface of the quartz plate 22. Further, the planar electrode 27 is connected to the high frequency power supply 25 via the variable capacitor 28 and the matching circuit 24. The control unit 41 can adjust the capacitance of the variable capacitor 28 to an optimal value within a range of 10 pF to 100 pF, and can prevent adhesion of a film on the inner surface of the quartz plate 22. A variable choke may be used instead of the variable capacitor 28.

  The workpiece 10 on which the mask pattern 11 p (FIG. 1C) is formed is placed on the substrate holder 30 in the chamber 21. Thereafter, the gas supply source 40 receives the control of the control unit 41 and introduces a mixed gas composed of two components of hydrogen iodide gas and silicon tetrachloride gas into the vacuum chamber 21 while a vacuum pump (not shown). ) Evacuates the vacuum chamber 21. The total flow rate of the mixed gas is desirably adjusted within the range of 17 sccm or more and 20 sccm or less in order to proceed with physical etching and chemical etching in a balanced manner. The mixing ratio of the flow rate of hydrogen iodide gas to the total flow rate of the mixed gas is adjusted to 60% or more and 85% or less.

  At the same time, the high frequency power supply 25 is controlled by the control unit 41 to supply high frequency power of 300 W at a frequency of 13.56 MHz to the high frequency loop antenna 23. The high frequency loop antenna 23 forms a high frequency magnetic field in the vacuum chamber 21 in response to the supply of the high frequency power, and the induction electric field generated by the high frequency magnetic field converts the mixed gas in the vacuum chamber 21 into plasma to generate active species. . Further, the bias high-frequency power source 32 (bias voltage applying means) applies a bias voltage to the workpiece 10 via the bias matching circuit 31 and the substrate holder 30 to cause the active species to enter the workpiece 10 (FIG. 1 (C)). Time management may be performed to control the target etching rate and etching depth. As a result, the workpiece 10 is processed with high accuracy by etching.

  The pressure (etching pressure) in the chamber 21 in the etching process is adjusted to 0.5 Pa in order to stably generate high-density plasma and advance physical etching and chemical etching in a balanced manner. preferable.

  In addition, the present inventors have found that the temperature of the workpiece 10 in the etching process is experimentally 160 ° C. or higher and 200 ° C. or lower from the vapor pressure of the by-product of the indium compound generated during the etching step. . By setting the temperature of the workpiece 10 to 160 ° C. or more, it is possible to promote the detachment of the In compound generated in the etching process of the compound semiconductor containing In, and to ensure the smoothness of the etching end face. .

  Using the dry etching process conditions, the selectivity, the etching rate difference (%), and the etching rate ratio were measured for a plurality of types of workpieces 10. FIG. 3 is a graph showing the relationship between the mixing ratio (%) of hydrogen iodide (HI) and the selection ratio, and FIG. 4 shows the difference between the mixing ratio (%) of HI and the etching rate difference (%). FIG. 5 is a graph showing the relationship between the HI compounding ratio (%) and the etching rate ratio.

The graph of FIG. 3 shows the measurement results of the selectivity with respect to the workpiece 10 of three types (InP, InP / InGaAlAs / InP, and InP / InGaAsP / InP) having different compositions. The graph of “InP” shows the measurement results when the InP substrate is the workpiece 10. That is, based on the etching rate of the InP substrate and the etching rate of the silicon oxide (SiO ₂ ) mask, the selectivity of the InP substrate (ie, InP layer) with respect to the SiO ₂ mask was calculated as a measurement result. The graph of “InP / InGaAlAs / InP” shows the measurement results when the workpiece 10 is formed by epitaxially growing an InGaAlAs layer on an InP substrate and forming an InP layer (cap layer) on the InGaAlAs layer. Yes. That is, based on the etching rate of the workpiece 10, the etching rate of the InP layer, and the etching rate of the SiO ₂ mask, the selection ratio of the InGaAlAs layer to the SiO ₂ mask was calculated as a measurement result. Here, the value of the etching rate of the InP substrate was used as the etching rate of the InP layer. The graph of “InP / InGaAsP / InP” shows the measurement results in the case where the workpiece 10 is formed by epitaxially growing an InGaAsP layer on an InP substrate and forming an InP layer (cap layer) on the InGaAsP layer. Show. That is, based on the etching rate of the workpiece 10, the etching rate of the InP layer, and the etching rate of the SiO ₂ mask, the selection ratio of the InGaAsP layer to the SiO ₂ mask was calculated as a measurement result.

  As shown in the graph of FIG. 3, when the HI compounding ratio is in the range of 60% or more and 85% or less, a high selection ratio of about 30 or more can be obtained for the InP substrate. InP / InGaAlAs / InP and InP / InGaAsP As for / InP, it can be seen that a high selection ratio of 20 or more is obtained.

  The graph of FIG. 4 shows the measurement result of the etching rate difference (%) for two types of workpieces 10 (InP / InGaAlAs / InP and InP / InGaAsP / InP) having different compositions. This measurement result was calculated based on the etching rate of the workpiece 10. That is, when the etching rate of the InP substrate (that is, the etching rate of the InP layer) is Er and the etching rate of the InGaAlAs layer is Ex, the etching rate difference between the InP layer and the InGaAlAs layer (“InP / InGaAlAs / InP” graph) Was calculated using the equation 100 × | Er−Ex | / Er. When the etching rate of the InGaAsP layer is Ey, the difference in etching rate between the InP layer and the InGaAsP layer (“InP / InGaAsP / InP” graph) is calculated using the equation 100 × | Er−Ey | / Er. Calculated. As shown in the graph of FIG. 4, it can be seen that the etching rate difference is suppressed to a low value for both the InGaAlAs layer and the InGaAsP layer when the HI compounding ratio is in the range of 60% to 85%. .

  The graph of FIG. 5 shows the measurement result of the etching rate ratio for two types of workpieces 10 (InP / InGaAlAs / InP and InP / InGaAsP / InP) having different compositions. This measurement result was calculated based on the etching rate of the workpiece 10. That is, when the etching rate of the InP substrate (that is, the etching rate of the InP layer) is Er and the etching rate of the InGaAlAs layer is Ex, the etching rate ratio of the InGaAlAs layer to the InP layer (“InP / InGaAlAs / InP” graph) Was calculated as Ex / Er. When the etching rate of the InGaAsP layer was Ey, the etching rate ratio of the InGaAsP layer to the InP layer (“InP / InGaAsP / InP” graph) was calculated as Ey / Er. As shown in the graph of FIG. 5, when the HI compounding ratio is in the range of 60% or more and 85% or less, the etching rate ratio of the InGaAlAs layer to the InP layer is approximately 0.6 or more. The etching rate ratio is 0.8 or more. Therefore, it can be seen that a good etching rate ratio close to 1 is obtained for both the InGaAlAs layer and the InGaAsP layer.

  Next, examples of the present embodiment and comparative examples will be described.

Example 1
The workpiece 10 has an (1) InP substrate and (2) an InP / InGaAsP / InP structure in which an InGaAsP layer having a thickness of about 500 nm is epitaxially grown on the InP substrate, and an InP layer (cap layer) is formed on the InGaAsP layer. (3) Three types of compound semiconductors having an InP / InGaAlAs / InP structure in which an InGaAlAs layer having a thickness of about 300 nm is epitaxially grown on an InP substrate and an InP layer (cap layer) is formed on the InGaAlAs layer. The InGaAsP layer has a band gap corresponding to a 1.5 μm wavelength lattice-matched to the underlying InP substrate (Q1.5). The InGaAlAs layer is a layer having an Al composition ratio of 30% and lattice-matched to the underlying InP substrate.

A SiO ₂ mask layer 11 having a thickness of about 500 nm is deposited by thermal CVD, a resist film 12 is applied to the surface of the workpiece 10, and the resist film 12 is formed by using a reduction projection exposure machine (stepper). A resist pattern 12p was formed by processing into a stripe shape so as to have a width of 0.5 μm (FIG. 1B). Next, a mask pattern 11p was formed by dry etching using CF ₄ gas (FIG. 1C).

Then, dry etching using the ICP source shown in FIG. 2 was performed (FIGS. 1C and 1D). Regarding the dry etching process conditions, HI gas having a flow rate of 12 sccm and SiCl ₄ gas having a flow rate of 5 sccm were introduced into the chamber. The total flow rate of the mixed gas at this time is 17 sccm, and the distribution ratio of HI gas is about 70%. The temperature of the workpiece 10 was 180 ° C., the pressure in the chamber was 0.5 Pa, the high frequency power was 300 W, and the RF bias power (RF input power) was 100 W.

  As a result of performing dry etching under these process conditions, a processed cross section schematically shown in FIG. 6 was obtained. When dry etching is performed at about 4 μm, the deviation from the vertical of the etching surface is within ± 3 ° at most, which is favorable. When the etching rate was measured for each of the three types of workpieces 10, the etching rate of the InP substrate was 1102 nm / min, the etching rate of the InP / InGaAsP / InP structure was 1095 nm / min, and InP / InGaAlAs The etching rate of the / InP structure was 1085 nm / min. Therefore, the etching rates of the three types of workpieces 10 are within an error range of ± 1.6%. The difference in etching rate is about 20% between the InP substrate (ie, InP layer) and the InGaAsP layer, and between the InP substrate (ie, InP layer) and the InGaAlAs layer. Therefore, dry etching independent of the semiconductor composition was realized.

In addition, it can be seen that any smoothness and verticality can be realized from any of the workpieces 10 because the columnar residue is not found on the processing bottom surface and a substantially vertical processing end surface is obtained. Further the calculated etching rate of the SiO ₂ mask by measuring the thickness of the SiO ₂ mask after the film thickness and the etching of the SiO ₂ mask before etching, for all of the workpiece 10, 35 nm / min met It was. The selectivity calculated from this etching rate was 25 or more for all the workpieces 10, and a good high selectivity was obtained.

(Example 2)
The workpiece 10 has (1) an InP substrate, (2) an InP / InGaAsP / InP structure in which an InGaAsP layer having a thickness of about 500 nm is epitaxially grown on the InP substrate, and an InP layer (cap layer) is formed on the InGaAsP layer. (3) Three types of compound semiconductors having an InP / InGaAlAs / InP structure in which an InGaAlAs layer having a thickness of about 300 nm is epitaxially grown on an InP substrate and an InP layer (cap layer) is formed on the InGaAlAs layer.

A resist pattern 12p was formed on the workpiece 10 in the same process as in Example 1 above. Then, dry etching using the same plasma source as the ICP source used in Example 1 was performed (FIGS. 1C and 1D). Regarding the dry etching process conditions, HI gas having a flow rate of 13.6 sccm and SiCl ₄ gas having a flow rate of 3.4 sccm were introduced into the chamber. The total flow rate of the mixed gas at this time is 17 sccm, and the distribution ratio of HI gas is about 80%. The temperature of the workpiece 10 was 180 ° C., the pressure in the chamber was 0.5 Pa, the high frequency power was 300 W, and the RF bias power (RF input power) was 100 W.

  As a result of performing dry etching under these process conditions, the etching rate of the InP substrate is 1144 nm / min, the etching rate of the InP / InGaAsP / InP structure is 1114 nm / min, and the etching rate of the InP / InGaAlAs / InP structure is 1093 nm. / Min. Therefore, the etching rates of the three types of workpieces 10 are within an error range of ± 1.9%. The difference in etching rate between the InP substrate (that is, InP layer) and the InGaAsP layer is about 17%, and the difference in etching rate between the InP substrate (that is, InP layer) and the InGaAlAs layer is about 37%. It was. Therefore, dry etching independent of the semiconductor composition was realized.

In addition, for any workpiece 10, no columnar residue was found on the bottom surface of processing, and a substantially vertical processing end surface was obtained. Therefore, good smoothness and verticality were realized. Further the calculated etching rate of the SiO ₂ mask by measuring the thickness of the SiO ₂ mask after the film thickness and the etching of the SiO ₂ mask before etching, for all of the workpiece 10, 34 nm / min met It was. From this etching rate, the selection ratio of the InP substrate to the SiO ₂ mask was calculated to be about 34. Further, the selection ratio of the InGaAlAs layer to the SiO ₂ mask was about 22, which was the smallest selection ratio. Therefore, a good high selection ratio was obtained.

(Example 3)
The workpiece 10 has an (1) InP substrate and (2) an InP / InGaAsP / InP structure in which an InGaAsP layer having a thickness of about 500 nm is epitaxially grown on the InP substrate, and an InP layer (cap layer) is formed on the InGaAsP layer. (3) Three types of compound semiconductors having an InP / InGaAlAs / InP structure in which an InGaAlAs layer having a thickness of about 300 nm is epitaxially grown on an InP substrate and an InP layer (cap layer) is formed on the InGaAlAs layer.

A resist pattern 12p was formed on the workpiece 10 in the same process as in Example 1 above. Then, dry etching using the same plasma source as the ICP source used in Example 1 was performed (FIGS. 1C and 1D). Regarding the dry etching process conditions, HI gas having a flow rate of 14.5 sccm and SiCl ₄ gas having a flow rate of 2.5 sccm were introduced into the chamber. The total flow rate of the mixed gas at this time is 17 sccm, and the distribution ratio of HI gas is about 85%. The temperature of the workpiece 10 was 180 ° C., the pressure in the chamber was 0.5 Pa, the high frequency power was 300 W, and the RF bias power (RF input power) was 100 W.

  As a result of performing dry etching under this process condition, the etching rate difference between the InP substrate (ie, InP layer) and the InGaAlAs layer is only about 40%, and the difference between the InP substrate (ie, InP layer) and the InGaAsP layer is The difference in etching rate was about 20%. Therefore, dry etching independent of the semiconductor composition was realized.

In addition, for any workpiece 10, no columnar residue was found on the bottom surface of processing, and a substantially vertical processing end surface was obtained. Therefore, good smoothness and verticality were realized. Further the calculated etching rate of the SiO ₂ mask by measuring the thickness of the SiO ₂ mask after the film thickness and the etching of the SiO ₂ mask before etching, for all of the workpiece 10, 31 nm / min met It was. From this etching rate, the selection ratio of the InP substrate to the SiO ₂ mask was calculated to be about 36. Further, the selection ratio of the InGaAlAs layer to the SiO ₂ mask was about 22, which was the smallest selection ratio. Therefore, a good high selection ratio was obtained.

Example 4
The workpiece 10 is an InP / InGaAlAs / InP structure in which (1) an InP substrate, (2) an InGaAlAs layer having a thickness of about 300 nm is epitaxially grown on the InP substrate, and an InP layer (cap layer) is formed on the InGaAlAs layer. These are two types of compound semiconductors.

A resist pattern 12p was formed on the workpiece 10 in the same process as in Example 1 above. Then, dry etching using the same plasma source as the ICP source used in Example 1 was performed (FIGS. 1C and 1D). As for the dry etching process conditions, HI gas having a flow rate of 12 sccm and SiCl ₄ gas having a flow rate of 8 sccm were introduced into the chamber. The total flow rate of the mixed gas at this time is 20 sccm, and the distribution ratio of HI gas is about 60%. The temperature of the workpiece 10 was 180 ° C., the pressure in the chamber was 0.5 Pa, the high frequency power was 300 W, and the RF bias power (RF input power) was 100 W.

As a result of performing dry etching under this process condition, the selection ratio of the InP substrate to the SiO ₂ mask was about 25, and the selection ratio of the InGaAlAs layer to the SiO ₂ mask was about 20. Therefore, a high selection ratio of 20 or more was obtained for any workpiece 10.

  The etching rate of the InP substrate was 1516 nm / min, and the etching rate of the InP / InGaAlAs / InP structure was 1480 nm / min. The etching rate of these workpieces 10 was within an error range of ± 1.2%. The difference in etching rate between the InP substrate (that is, InP layer) and the InGaAlAs layer was about 20%.

(Comparative Example 1)
The workpiece 10 is an InP / InGaAlAs / InP structure in which (1) an InP substrate, (2) an InGaAlAs layer having a thickness of about 300 nm is epitaxially grown on the InP substrate, and an InP layer (cap layer) is formed on the InGaAlAs layer. These are two types of compound semiconductors.

A resist pattern 12p was formed on the workpiece 10 in the same process as in Example 1 above. Then, dry etching using the same plasma source as the ICP source used in Example 1 was performed (FIGS. 1C and 1D). Regarding the dry etching process conditions, HI gas having a flow rate of 18 sccm and SiCl ₄ gas having a flow rate of 2 sccm were introduced. The total flow rate of the mixed gas at this time is 20 sccm, and the distribution ratio of HI gas is about 90%. The temperature of the workpiece 10 was 180 ° C., and the pressure in the chamber was 0.5 Pa.

  As a result of performing dry etching under these process conditions, a residue was observed on the bottom surface of the processing in both the InP substrate and the InP / InGaAlAs / InP structure. In particular, a large amount of residue was observed on the processed bottom surface of the InP / InGaAlAs / InP structure, and smooth etching could not be performed.

(Comparative Example 2)
The workpiece 10 has an (1) InP substrate and (2) an InP / InGaAsP / InP structure in which an InGaAsP layer having a thickness of about 500 nm is epitaxially grown on the InP substrate, and an InP layer (cap layer) is formed on the InGaAsP layer. (3) Three types of compound semiconductors having an InP / InGaAlAs / InP structure in which an InGaAlAs layer having a thickness of about 300 nm is epitaxially grown on an InP substrate and an InP layer (cap layer) is formed on the InGaAlAs layer.

A resist pattern 12p was formed on the workpiece 10 in the same process as in Example 1 above. Then, dry etching using the same plasma source as the ICP source used in Example 1 was performed (FIGS. 1C and 1D). Regarding the dry etching process conditions, HI gas having a flow rate of 9.3 sccm and SiCl ₄ gas having a flow rate of 7.7 sccm were introduced into the chamber. The total flow rate of the mixed gas at this time is 17 sccm, and the distribution ratio of HI gas is about 55%. The temperature of the workpiece 10 was 180 ° C., the pressure in the chamber was 0.5 Pa, the high frequency power was 300 W, and the RF bias power (RF input power) was 100 W.

As a result of executing dry etching under these process conditions, the smoothness of the processed surface was good, but the selectivity of the InP substrate to the SiO ₂ mask was about 25. Further, the selection ratio of the InGaAlAs layer to the SiO ₂ mask was about 17, and a slight deterioration of the selection ratio was confirmed. When the composition dependency of the etching rate was examined, the etching rate difference between the InP substrate (ie, InP layer) and the InGaAlAs layer was about 40%, and the difference between the InP substrate (ie, InP layer) and the InGaAsP layer was The difference in etching rate was at most 20%.

(Examples 5 to 8)
The workpiece 10 has an (1) InP substrate and (2) an InP / InGaAsP / InP structure in which an InGaAsP layer having a thickness of about 500 nm is epitaxially grown on the InP substrate, and an InP layer (cap layer) is formed on the InGaAsP layer. (3) Three types of compound semiconductors having an InP / InGaAlAs / InP structure in which an InGaAlAs layer having a thickness of about 300 nm is epitaxially grown on an InP substrate and an InP layer (cap layer) is formed on the InGaAlAs layer. The InGaAsP layer has a band gap corresponding to a 1.5 μm wavelength lattice-matched to the underlying InP substrate (Q1.5). The InGaAlAs layer is a layer having an Al composition ratio of 30% and lattice-matched to the underlying InP substrate.

  A resist pattern 12p was formed on the workpiece 10 in the same process as in Example 1 above. Then, dry etching using the same plasma source as the ICP source used in Example 1 was performed (FIGS. 1C and 1D). The process conditions for this dry etching are as follows.

For Example 5, HI gas with a flow rate of 12 sccm and SiCl ₄ gas with a flow rate of 5 sccm were introduced into the chamber. The total flow rate of the mixed gas at this time is 17 sccm, and the distribution ratio of HI gas is about 70%. The temperature of the workpiece 10 was 200 ° C., the pressure in the chamber was 0.5 Pa, the high frequency power was 300 W, and the RF bias power (RF input power) was 100 W.

For Example 6, HI gas with a flow rate of 12 sccm and SiCl ₄ gas with a flow rate of 5 sccm were introduced into the chamber. The total flow rate of the mixed gas at this time is 17 sccm, and the distribution ratio of HI gas is about 70%. The temperature of the workpiece 10 was 160 ° C., the pressure in the chamber was 0.5 Pa, the high frequency power was 300 W, and the RF bias power (RF input power) was 100 W.

For Example 7, HI gas with a flow rate of 10.2 sccm and SiCl ₄ gas with a flow rate of 6.8 sccm were introduced into the chamber. The total flow rate of the mixed gas at this time is 17 sccm, and the distribution ratio of HI gas is about 60%. The temperature of the workpiece 10 was 160 ° C., the pressure in the chamber was 0.5 Pa, the high frequency power was 300 W, and the RF bias power (RF input power) was 100 W.

For Example 8, HI gas with a flow rate of 12 sccm and SiCl ₄ gas with a flow rate of 5 sccm were introduced into the chamber. The total flow rate of the mixed gas at this time is 17 sccm, and the distribution ratio of HI gas is about 70%. The temperature of the workpiece 10 was 140 ° C., the pressure in the chamber was 0.5 Pa, the high frequency power was 300 W, and the RF bias power (RF input power) was 100 W.

  The results of performing dry etching under the process conditions of Examples 5 to 8 are as follows.

For Example 5, the etching rate difference between the InP substrate (ie, InP layer) and the InGaAlAs layer is at most about 17%, and the etching rate difference between the InP substrate (ie, InP layer) and the InGaAsP layer is at most It was about 11%. Therefore, dry etching independent of the semiconductor composition was realized. In addition, for any workpiece 10, no columnar residue was found on the bottom surface of processing, and a substantially vertical processing end surface was obtained. Therefore, good smoothness and verticality were realized. Further the calculated etching rate of the SiO ₂ mask by measuring the thickness of the SiO ₂ mask after the film thickness and the etching of the SiO ₂ mask before etching, for all of the workpiece 10, 37 nm / min met It was. From this etching rate, the selection ratio of the InP substrate to the SiO ₂ mask was calculated to be about 31. Further, the selection ratio of the InGaAlAs layer to the SiO ₂ mask was about 26, which was the smallest selection ratio. Therefore, a good high selection ratio was obtained.

For Example 6, the difference in etching rate between the InP substrate (ie, InP layer) and the InGaAlAs layer is about 28%, and the difference in etching rate between the InP substrate (ie, InP layer) and the InGaAsP layer is at most It was about 4%. Therefore, dry etching independent of the semiconductor composition was realized. In addition, for any workpiece 10, no columnar residue was found on the bottom surface of processing, and a substantially vertical processing end surface was obtained. Therefore, good smoothness and verticality were realized. Further the calculated etching rate of the SiO ₂ mask by measuring the thickness of the SiO ₂ mask after the film thickness and the etching of the SiO ₂ mask before etching, for all of the workpiece 10, 38 nm / min met It was. From this etching rate, the selection ratio of the InP substrate to the SiO ₂ mask was calculated to be about 30. Further, the selection ratio of the InGaAlAs layer to the SiO ₂ mask was about 22, which was the smallest selection ratio. Therefore, a good high selection ratio was obtained.

For Example 7, the etching rate difference between the InP substrate (ie, InP layer) and the InGaAlAs layer is at most about 24%, and the etching rate difference between the InP substrate (ie, InP layer) and the InGaAsP layer is at most It was about 5%. Therefore, dry etching independent of the semiconductor composition was realized. In addition, for any workpiece 10, no columnar residue was found on the bottom surface of processing, and a substantially vertical processing end surface was obtained. Therefore, good smoothness and verticality were realized. Furthermore, when the SiO ₂ mask thickness after measurement and the thickness of the SiO ₂ mask after etching were measured to calculate the etching rate of the SiO ₂ mask, it was 41 nm / min for all the workpieces 10. It was. From this etching rate, the selection ratio of the InP substrate to the SiO ₂ mask was calculated to be about 27. Further, the selection ratio of the InGaAlAs layer to the SiO ₂ mask was about 21, which was the smallest selection ratio. Therefore, a good high selection ratio was obtained.

For Example 8, the difference in etching rate between the InP substrate (ie, InP layer) and the InGaAlAs layer is about 30%, and the difference in etching rate between the InP substrate (ie, InP layer) and the InGaAsP layer is at most It was about 5%. Therefore, dry etching independent of the semiconductor composition was realized. Further, when the thickness of the SiO ₂ mask before etching and the thickness of the SiO ₂ mask after etching were measured to calculate the etching rate of the SiO ₂ mask, it was 38 nm / min for all the workpieces 10. It was. From this etching rate, the selection ratio of the InP substrate to the SiO ₂ mask was calculated to be about 29. Further, the selection ratio of the InGaAlAs layer to the SiO ₂ mask was about 21, which was the smallest selection ratio. Therefore, a good high selection ratio was obtained. However, a columnar residue was observed on the bottom surface of any workpiece 10 and it was confirmed that the verticality of the processed end surface was not good as compared with Examples 5-7.

  The embodiment and the example according to the present invention have been described above. In the etching method of the present embodiment, a high selection ratio can be realized between the workpiece 10 and the mask pattern 11p by adjusting the HI compounding ratio within a range of 60% to 85%. Therefore, it is possible to reduce the thickness of the mask pattern 11p and increase the patterning. In the case of forming an optical waveguide having a mesa structure, verticality, high smoothness, and a high-definition pattern of the side wall of the mesa structure can be realized.

  In addition, it is possible to reduce the etching rate difference between compound semiconductors having different compositions. Therefore, when an optical integrated device including a plurality of optical functional elements having different semiconductor compositions is manufactured, the processing shape can be precisely controlled without depending on the semiconductor composition. Even when the entire formation region of these optical functional elements is etched at once, the etching depth can be controlled uniformly.

  In the etching step, the temperature of the workpiece 10 is adjusted to a range of 160 ° C. or higher and 200 ° C. or lower, so that the In compound generated during the etching process can be sufficiently removed, and the smoothness of the processed end face can be secured sufficiently. It becomes possible.

  By using an inorganic dielectric as the material of the etching mask, it is easy to remove the mask after etching even if a high temperature condition is employed to ensure sufficient smoothness of the processed end face. Furthermore, since the etching amount of the mask in the dry etching process can be reduced, the inorganic dielectric can practically function as a mask.

Furthermore, the verticality and smoothness of the side wall of the mesa structure formed by dry etching can be improved, and a high-definition pattern can be formed. As described above, the selection ratio between the InP material and the SiO ₂ mask can be set to 30 or more by optimizing the process conditions. This selection ratio is larger than that in the case of using a dielectric mask under the conventional dry etching process conditions for forming a mesa structure. For this reason, the film thickness of a dielectric mask required when etching a to-be-processed object to the same depth can be made thin. As a result, the patterning accuracy of the dielectric mask is improved and higher definition can be achieved.

  The above embodiment is an exemplification of the present invention, and various forms other than the above can be adopted. For example, the mask pattern 11p in FIG. 1C is preferably a hard mask made of an inorganic dielectric, but is not limited thereto. As described above, when a metal mask is used as the mask pattern 11p, if the mask pattern 11p is etched, the metal element of the metal mask may adhere to the processed surface. Therefore, the metal mask is used before the crystal growth is performed. Although it is difficult to do, a metal mask may be used as the mask pattern 11p in the final process after the crystal growth is performed. In this case, the mask layer 11 in FIG. 1A may be deposited by sputtering or vapor deposition.

  Alternatively, a method called lift-off is used, in which a resist is applied only to the element formation region to be finally etched, metal is deposited on the entire surface by vapor deposition, and then the resist is removed and the metal above the resist is also removed. You can also

(A)-(D) are process drawings for demonstrating the manufacturing method of the semiconductor device which is one Embodiment which concerns on this invention. It is a figure which shows schematic structure of a plasma etching apparatus. It is a graph which shows the relationship between the compounding ratio of HI, and a selection ratio. It is a graph which shows the relationship between the compounding ratio of HI, and an etching rate difference. It is a graph which shows the relationship between the compounding ratio of HI, and an etching rate ratio. It is a schematic diagram of the process cross section obtained by dry etching.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Workpiece 11 Mask layer 11p Mask pattern 12 Resist film 12p Resist pattern 20 Plasma etching apparatus 21 Vacuum chamber 22 Quartz plate 23 High frequency loop antenna 24 Matching circuit 25 High frequency power supply 26 Loop permanent magnet 27 Planar electrode 28 Variable capacitor 30 Substrate Holder 31 Bias matching circuit 32 High frequency power supply for bias 40 Gas supply source 41 Control unit

Claims (12)

Forming a hard mask made of an inorganic dielectric material in a predetermined pattern on a group III-V compound semiconductor containing indium as an essential constituent element;
After the formation of the hard mask made of the inorganic dielectric material, a mixed gas comprising two components of hydrogen iodide gas and silicon tetrachloride gas is formed on the III-V compound semiconductor disposed in the chamber of the plasma etching apparatus. And introducing the mixed gas into plasma,
A step of selectively etching the III-V compound semiconductor by causing the plasma-mixed gas to enter the III-V compound semiconductor ;
Including
The method for manufacturing a semiconductor device, wherein a mixing ratio of the flow rate of the hydrogen iodide gas to the total flow rate of the mixed gas is 60% or more and 85% or less. A process according to claim 1, wherein, in the step of selectively etching said III-V compound semiconductor, for adjusting the temperature of the group III-V compound semiconductor in the range of 160 ° C. or higher 200 ° C. or less, A method for manufacturing a semiconductor device. A method according to claim 1 or 2, wherein the group III-V compound semiconductor, InP, comprising one or more compounds selected from the group consisting of InGaAlAs and InGaAsP, a method of manufacturing a semiconductor device. The manufacturing method according to any one of claims 1 to 3 ,
The plasma etching apparatus includes:
A gas supply source for introducing the mixed gas into the chamber;
A high-frequency antenna that applies a high-frequency magnetic field in the chamber to generate an induction electric field for converting the introduced mixed gas into plasma in response to a supply of high-frequency power;
A high frequency oscillator for supplying the high frequency power to the high frequency antenna;
A magnet for applying a static magnetic field in the chamber to control a plasma density distribution of the mixed gas;
Bias voltage applying means for forming an electric field for causing the plasma mixed gas to enter the III-V compound semiconductor ;
A method for manufacturing a semiconductor device, which is an inductively coupled plasma generator. 5. The manufacturing method according to claim 4 , wherein the high-frequency antenna is formed in a loop shape, and the magnet is a loop-shaped permanent magnet arranged coaxially with the high-frequency antenna. It is a manufacturing method of Claim 4 or 5 , Comprising:
The plasma etching apparatus includes:
A dielectric member defining a plasma generation region of the chamber;
An electrode provided between the high-frequency antenna and the dielectric member disposed outside the plasma generation region;
A variable capacitor or a variable choke that is supplied with high-frequency power from the high-frequency oscillator;
With
The method for manufacturing a semiconductor device, wherein the electrode is connected to the high-frequency oscillator through the variable capacitor or a variable choke. A plasma etching apparatus for processing a III-V group compound semiconductor in which a hard mask made of an inorganic dielectric material of a predetermined pattern is formed,
A holder disposed in the chamber and supporting the III-V compound semiconductor ;
A gas supply source for introducing a mixed gas composed of two components of hydrogen iodide gas and silicon tetrachloride gas on the III-V compound semiconductor ;
A high-frequency antenna that applies a high-frequency magnetic field in the chamber to generate an induction electric field for converting the introduced mixed gas into plasma in response to a supply of high-frequency power;
A high frequency oscillator for supplying the high frequency power to the high frequency antenna;
Bias voltage applying means for forming an electric field for causing the plasma mixed gas to enter the III-V compound semiconductor ;
With
The III-V compound semiconductor contains indium as a constituent element thereof,
The said gas supply source is a plasma etching apparatus which adjusts the compounding ratio of the flow rate of the said hydrogen iodide gas with respect to the total flow rate of the said mixed gas in the range of 60% or more and 85% or less. The plasma etching apparatus according to claim 7 , wherein the temperature of the group III-V compound semiconductor is adjusted within a range of 160 ° C. or more and 200 ° C. or less. 9. The plasma etching apparatus according to claim 7 , wherein the group III-V compound semiconductor includes one or more compounds selected from the group consisting of InP, InGaAlAs, and InGaAsP. A plasma etching apparatus according to any one of claims 7 9, further comprising a plasma etching apparatus a magnet for controlling the plasma density distribution of the mixed gas by applying a magnetic field to the chamber. 11. The plasma etching apparatus according to claim 10 , wherein the high-frequency antenna is formed in a loop shape, and the magnet is a loop-shaped permanent magnet disposed coaxially with the high-frequency antenna. The plasma etching apparatus according to claim 10 or 11 ,
A dielectric member defining a plasma generation region of the chamber;
An electrode provided between the high-frequency antenna and the dielectric member disposed outside the plasma generation region;
A variable capacitor or a variable choke that is supplied with high-frequency power from the high-frequency oscillator;
With
The plasma etching apparatus, wherein the electrode is connected to the high-frequency oscillator via the variable capacitor or a variable choke.

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