JP2012521659A - Plasma etching method - Google Patents

Abstract

  A method of processing the substrate so as to form a desired pattern by an etching process after forming a mask pattern on the substrate includes forming two layers on the substrate, the mask pattern or the two layers. Measuring the width of one layer of the etching pattern, and adjusting the flow rate of any one of HBr and other gases used in the etching process based on the measured width . The two layers may include a silicon nitride layer and an organic dielectric layer.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. More particularly, the present invention relates to a plasma etching method that provides a high resolution pattern having a desired critical dimension (CD) value.

  In the semiconductor manufacturing process, a photolithography technique is used to form a resist pattern. In photolithography technology, a resist solution is first coated on a semiconductor substrate or a liquid crystal display (LCD) substrate. By using a photomask, the resist film is exposed to intense light and then developed. As a result, a desired resist pattern is formed on the semiconductor substrate or the LCD substrate. After forming a desired resist pattern, an etching process for etching the semiconductor substrate or the LCD substrate is performed.

  Even if the process steps described above are performed under certain process conditions, it is known that none of the process results of the process steps described above can meet the target value. The reason why this occurs is due to the presence of unintended factors such as substrate surface conditions, ambient pressure, and temperature and relative humidity fluctuations.

  Conventionally, after processing a certain number of substrates, one substrate is extracted for inspection. During the inspection, various parameters are measured and a determination is made as to whether the process conditions are appropriate based on the inspection results. Examples of these parameters are resist film thickness after coating process, resist pattern line width or critical dimension (CD) after development process, bottom pattern matching accuracy to resist pattern, developed surface mismatch, Development defects, etched substrate linewidth or critical dimension (CD), and defects on the etched surface after the etching process are included.

  Therefore, the process conditions for each process step can be corrected according to the judgment made based on the inspection result. This highly problematic correction operation can be performed by an experienced operator. In order to assist the correction operation, a resist pattern formation process has been proposed in Patent Document 1. In this process, a predetermined set of modified parameters associated with each particular measured parameter is first determined. Subsequently, the predetermined set of correction parameters is corrected according to the result of the automated inspection.

  For example, if the etched substrate line width or critical dimension (CD) is a specific measured parameter, the following correction parameters may be modified to achieve the target value. The correction parameters are 1) exposure intensity, 2) heating time, 3) development time, 4) etching time, and 5) composition ratio of etching gas. However, Patent Document 1 does not clarify how the gas composition ratio affects the etching process that achieves a desired target value of the critical dimension (CD).

  Further, Patent Document 2 discloses a substrate processing process. In the substrate processing process, the critical dimension (CD) of the resist pattern is strictly measured to form a desired circuit pattern after the etching process. In this process, the critical dimension (CD) of the resist pattern is first measured. The measurement results are then fed forward to an etching process unit that adjusts the processing conditions. By setting optimum processing conditions, a strict and desired circuit pattern can be obtained after the etching process. This technique provides a feedforward method for etching a desired pattern based on the measured critical dimension (CD) of the resist film. However, like Patent Document 1, Patent Document 2 cannot point out specific conditions regarding the type of etching gas and its composition ratio in order to achieve a desired critical dimension (CD).

Published Application No. 2002/190446 Application Publication No. 2003/209093 Specification

  The present invention is proposed in view of the above problems. The present invention provides a process for producing a high resolution pattern having a desired critical dimension (CD) using a particular type of etching gas and its composition ratio.

  According to the first aspect of the present invention, there is provided a method of processing a substrate so as to form a desired pattern by an etching process after forming a mask pattern on the substrate. The method includes forming two layers having a silicon nitride layer and an organic dielectric layer on the substrate, measuring a width of the mask pattern or an etched pattern of one of the two layers, And adjusting a flow rate of any one of HBr and other gases used in the etching process based on the measured width.

According to the second aspect of the present invention, there is provided a method of processing a substrate so as to form a desired pattern by an etching process after forming a mask pattern on the substrate. The method includes forming three layers on the substrate having a silicon nitride layer, an organic dielectric layer, and a silicon-containing antireflection coating layer, the mask pattern or one of the three layers being etched. Measuring the width of the pattern, and adjusting the flow rate of any one of CF ₄ and CHF ₃ used in the etching process based on the measured width.

Figure 2 schematically illustrates an example of a target structure before and after a plasma etching process. FIG. 3 schematically illustrates an alternative embodiment of a target structure after patterning a silicon nitride (SiN) layer and a cross-sectional image of an experimental sample. 1 shows a schematic diagram of an embodiment of a plasma process apparatus. 1 is a schematic view of an embodiment of a line width measuring device integrated with a coater developing device. Fig. 6 shows a schematic view of an alternative embodiment of a line width measuring device integrated with an etching device. Fig. 4 illustrates an example of a process for adjusting the line width of a pattern when multiple layers are etched. Fig. 2 represents a schematic diagram of an alternative embodiment of a line width measuring device used alone. FIG. 6 shows a cross-sectional view of an experimental sample showing dense and sparse patterns after performing a plasma etching process on each particular layer. The experimental sample and its critical dimension (CD) are represented as a function of overetch (OE) processing time. The experimental sample and its critical dimension (CD) are expressed as a function of the HBr flow rate. FIG. 3 shows a cross-sectional view of an experimental sample showing dense and sparse patterns for various etching gas types. The experimental sample and its critical dimension (CD) are expressed as a function of a series of Ar / HBr / O ₂ flow rates. 2 shows a cross-sectional view of an experimental sample and its critical dimension (CD). The microwave output, RF output, and RF voltage of each mask layer are represented as a function of time. 2 shows a cross-sectional view of an experimental sample and its critical dimension (CD). 2 shows a cross-sectional view of an experimental sample and its critical dimension (CD).

  In the following, embodiments of the present invention will be described with reference to the accompanying drawings, in which typical preferred embodiments are shown. The following description should not be construed as limiting the scope, applicability, or configuration of the disclosure. Rather, the following description of exemplary preferred embodiments provides those skilled in the art with a description that allows exemplary exemplary embodiments of the present disclosure to be implemented. It should be noted that the present invention can be implemented in various forms without departing from the technical idea and scope of the present invention as defined in the claims.

  The present disclosure generally relates to semiconductor devices and methods of manufacturing such semiconductor devices. More specifically, the present disclosure relates to a plasma etching method that provides a high resolution pattern having a desired critical dimension (CD) value.

Embodiments of the present invention relate to an etching process that controls the line width or critical dimension (CD) of a silicon (Si) pattern. The silicon (Si) pattern is formed using a silicon nitride (SiN) hard mask. In addition, a silicon nitride (SiN) hard mask is formed using a three-layer mask pattern. The three-layer mask pattern has an organic dielectric layer (ODL). In order to obtain a desired silicon (Si) pattern having a predetermined critical dimension (CD), the line width or critical dimension (CD) of a silicon nitride (SiN) hard mask pattern formed on a silicon (Si) substrate is: Must be strictly controlled. This is achieved by patterning the organic dielectric layer (ODL) and simultaneously adding hydrogen bromide (HBr) in a mixed atmosphere of nitrogen and oxygen (N ₂ / O ₂ ).

  By adding hydrogen bromide (HBr) and increasing the flow rate of HBr, oxygen (O) is extracted, so the hydrogen (H) concentration decreases at the surface of the ODL layer. An organic dielectric layer (ODL) with a high carbon content is produced. Increasing the carbon content of the ODL layer produces carbon-carbon bonds that make the organic dielectric layer (ODL) more rigid. The stiffness of the ODL provides good control ability to obtain a predetermined value for the critical dimension (CD) by reducing the horizontal etch rate, especially when the CD value is smaller than the target value.

In addition, since the carbon content of the ODL layer is high, a plurality of Br—C bonds are generated on the surface of the ODL pattern. As a result, a thin film of carbon bromide (CBr _x ) is deposited over the ODL pattern as sidewall protection. This increases the critical dimension (CD) of the ODL.

  According to one embodiment of the present invention, the desired critical dimension (CD) value adjusts the hydrogen bromide (HBr) flow rate during the main etch (ME) step on the organic dielectric layer (ODL). Is realized. By increasing the flow rate of hydrogen bromide (HBr), the critical dimension (CD) value of the ODL pattern tends to increase.

According to another embodiment, the critical dimension (CD) of the ODL pattern may also be adjusted by performing an overetch (OE) process after the main etch (ME) process is completed. The over-etching (OE) step, the desired critical dimension (CD) value, achieved by the addition of adjusting the ratio of nitrogen to oxygen (N ₂ / O _2), and an appropriate amount of hydrogen bromide (HBr) May be good. Therefore, if the difference between the actual CD value and the target value is relatively large, the main etching (ME) process may be adjusted, and if the difference is relatively large, the overetch (OE ) Process adjustments may be made.

  In one embodiment, the critical dimension (CD) value may be increased by setting the hydrogen bromide (HBr) flow rate to a constant value while extending the overetch period. In an alternative embodiment, the critical dimension (CD) value may be increased by increasing the hydrogen bromide (HBr) flow rate. This increases the composition ratio of hydrogen bromide (HBr) to other gases in the entire atmosphere.

According to yet another embodiment, the desired critical dimension (CD) value in the ODL adjusts the ratio of nitrogen to oxygen (N ₂ / O ₂ ) and chlorine (Cl ₂ ) in an overetch (OE) process. ) Can be added.

According to yet another embodiment, the desired critical dimension (CD) value can be obtained by patterning an organic dielectric layer (ODL) while using argon and oxygen (Ar / O ₂ ) instead of oxygen and nitrogen (N ₂ / O ₂ ). _It may be realized by adding hydrogen bromide (HBr) in the mixed atmosphere of ₂ ). In this embodiment, the critical dimension (CD) of the ODL layer may be increased by increasing the oxygen (O ₂ ) flow rate.

According to an alternative embodiment of the present invention, a desired pattern having a predetermined critical dimension (CD) value may be achieved while patterning a silicon-containing anti-reflective coating (Si-ARC) layer. In this embodiment, the line width or critical dimension of the Si-ARC layer may be increased or decreased by adjusting the ratio of tetrafluoromethane gas to trifluoromethane gas (CF ₄ / CHF ₃ ).

  According to yet another embodiment, a desired pattern having a predetermined critical dimension (CD) value may be achieved by adjusting the level of the RF bias power supply. In this example, the critical dimension (CD) value is proportional to the applied RF bias level (output). This means that the higher the RF bias level, the greater the critical dimension (CD) value. Conversely, if the RF bias level is lowered, the given critical dimension (CD) value is also reduced.

Parameters adjusted in the above-described embodiments, such as the hydrogen bromide (HBr) flow rate in the ODL patterning process, the (CF ₄ / CHF ₃ ) ratio in the Si-ARC patterning process, and the RF bias level, Alternatively, it is determined based on measurement of a critical dimension (CD) of an arbitrary mask pattern.

  According to one embodiment, the measured value of the resist pattern in the semiconductor substrate after the development process is obtained from a subsequent layer--for example, an organic dielectric layer (ODL) or silicon-containing antireflection coating (Si-ARC) in the same semiconductor substrate. It is used to determine the appropriate set-up conditions for performing the layer etching process.

  According to another embodiment, a resist pattern or etching pattern measurement of an organic dielectric layer (ODL) or a silicon-containing anti-reflective coating (Si-ARC) layer in one semiconductor substrate may be performed on another semiconductor substrate. Used to determine the appropriate setting conditions for execution.

  According to yet another embodiment, the measured value of the etching pattern of the organic dielectric layer (ODL) or the silicon-containing antireflection coating (Si-ARC) layer in the semiconductor substrate is measured while performing the etching process on the same semiconductor substrate. Used to determine the appropriate setting conditions in

  Referring initially to FIG. 1, an example of a target structure 10 before and after a plasma etching process is illustrated. As shown in FIG. 1, the target structure 10 may include a silicon (Si) substrate 12, a hard mask silicon nitride (SiN) layer 14, and a three-layer structure 16. The three-layer structure 16 includes an organic dielectric layer (ODL) 16a, a silicon-containing antireflection coating (Si-ARC) layer 16b, and a resist pattern 16c. In order to strictly control the final silicon (Si) pattern, the hard mask pattern of the SiN layer 14 must be accurately formed on the Si substrate 12. In order to realize the desired shape (including CD value or line width) of the hard mask pattern of the SiN layer 14, the hard mask pattern of the SiN layer 14 is etched by using a three-layer structure 16 (16a, 16b, 16c) May be good. More specifically, after the formation of the desired resist pattern 16c, a subsequent etching process is performed on each of the Si-ARC layer 16b, the ODL layer 16a, and the hard mask silicon nitride (SiN) layer 14 to form a hard mask. By etching the silicon (Si) substrate 12 through the SiN layer 14, the entire pattern is transferred to the Si substrate 12. The final silicon (Si) substrate pattern 12 with some remaining SiN patterns 14 is also illustrated in FIG.

  As described above, because there are unintended factors such as substrate surface conditions, ambient pressure, and temperature and relative humidity fluctuations, the line width or critical dimension (CD) of the resist pattern 16c is set to a desired target value. Can't meet. Thus, subsequent etching processes cannot provide the desired target pattern of Si-ARC, ODL, and silicon (Si) substrate 12. To evaluate the above points, an experimental sample is first manufactured based on an alternative target structure. The experimental sample is then subjected to a conventional plasma etching process. Hereinafter, the alternative target structure having a desired target pattern after performing the plasma etching process will be described in detail.

Referring now to FIG. 2, an alternative embodiment of the target structure 20 used to perform a plasma etching process is illustrated. The target structure 20 and the target structure 10 are different in that additional silicon dioxide (SiO ₂ ) is interposed between the silicon substrate layer 12 and the silicon nitride (SiN) layer 14 that is a hard mask. Similar to the target structure 10, a three-layer structure 16 is formed on a silicon nitride (SiN) layer 14, which is a hard mask. In this embodiment, the desired critical dimension (CD) for the resist pattern 16c is set to about 40 to 45 nm. Note that such embodiments are shown for illustrative purposes and are not intended to be limiting. The desired target pattern after the plasma etching process is also schematically illustrated in FIG.

  A cross-sectional view of the experimental sample after patterning of the silicon nitride (SiN) layer 14 is shown in FIG. As shown in FIG. 2, the critical dimension (CD) of the silicon nitride pattern is about 33.4 nm, which is about 7 nm smaller than the desired critical dimension (40-45 nm). The measured distance between patterns is about 65.7 nm, while the measured pattern height is about 49.9 nm.

  In conventional plasma etching processes, most mask materials are etched isotropically to some extent. This means that the etching proceeds to some extent horizontally. Thus, when a plasma etching process is used for a layer, such as an organic dielectric layer (ODL) 16a, side etching also occurs simultaneously with the vertical etching of ODL 16a. As a result, the cross-sectional shape of the mask pattern of the ODL 16a is far from the desired rectangular shape, and instead becomes, for example, a tapered skirt shape. Therefore, the SiN layer 14 etched through the ODL mask does not have the target shape as designed. Ideally, directional etching that does not cause etching in the horizontal direction is preferable. However, in practice, anisotropic etching with a low etching rate in the horizontal direction is desirable.

The present invention provides a plasma over-etching (OE) process for lateral etching of the ODL layer 16a and as a countermeasure to control the critical dimension (CD) of the pattern of the SiN layer. In the plasma OE process, an organic dielectric layer (ODL) 16a is patterned while a certain amount of hydrogen bromide (HBr) is added into a mixed atmosphere of oxygen and nitrogen (N ₂ / O ₂ ). Various process conditions for the addition of hydrogen bromide (HBr) were investigated. These studies are primarily performed to verify the ODL sidewall protection mechanism and to establish a method for controlling critical dimension (CD) while etching. Examples of these process conditions may include HBr flow rate, etch time, etch gas type, bias power applied to the substrate, and composition ratio.

  On the other hand, during the plasma etching process of the present invention, a plurality of control methods may be used to provide a high resolution (accurate) pattern having a predetermined critical dimension (CD) on the silicon (Si) substrate 12. Examples of these control methods may include feedforward control processes, feedback control systems, and dynamic (in situ) control processes. Hereinafter, each of the above-described control processes will be described in detail.

  In one embodiment, feedforward process control is used to obtain a pattern having a predetermined critical dimension (CD). In this example, the line width or critical dimension (CD) of the resist pattern 16c is first measured using any commercially available apparatus. An instrumentation (IM) device incorporating an optical measurement—for example, scatterometry—may be employed. As described in detail below, in some embodiments, a line width (CD) measurement device is incorporated into the coater development device. In the coater development apparatus, the latent image of the photoresist after exposure or the value of the developed CD is measured before the substrate is transferred to the etching apparatus for the subsequent etching process. In other embodiments, the CD measurement may be performed in an IM device combined with an etching device. In the IM apparatus, CD measurement is performed before the actual etching process is started. In an alternative embodiment, the CD measurement may be performed by a single measurement system instead of the IM device. A detailed description of the line width or CD measuring apparatus will be given later. After measuring the line width or the critical dimension (CD) of the resist pattern 16c, it is determined whether or not the critical dimension (CD) of the resist pattern 16c satisfies the desired target value. If the critical dimension (CD) of the resist pattern 16c does not meet its desired target value, appropriate setting conditions for the flow rate and type of plasma etching gas are first determined. Subsequently, for the subsequent etching process of the Si-ARC layer 16b or the ODL layer 16a, the setting conditions on the same semiconductor substrate are adjusted.

  In an alternative embodiment, feedback process control is used to obtain a pattern having a predetermined critical dimension (CD). In this alternative embodiment, the line width or critical dimension (CD) of the Si-ARC pattern 16b or ODL layer 16a is first inspected. It is determined whether or not the critical dimension (CD) of the ODL pattern 16a (Si-ARC pattern 16b) satisfies the desired target value. When the critical dimension (CD) of the ODL pattern 16a (Si-ARC pattern 16b) does not satisfy the desired target value, appropriate setting conditions regarding the flow rate and type of the plasma etching gas are determined. The setting conditions are sent to the etching apparatus and then adjusted for other semiconductor substrates, and mask patterns on the silicon (Si) substrate 12, such as SiN hard mask pattern 14, ODL pattern 16a, Si-ARC pattern 16b, and A predetermined critical dimension (CD) of the resist pattern 16c- is provided.

  In yet another alternative embodiment, dynamic process control (in-situ) can be used to obtain a pattern having a predetermined critical dimension (CD). In this embodiment, the line width or critical dimension (CD) of the ODL pattern 16a or SiN hard mask pattern 14 is first measured during etching, and appropriate setting conditions regarding the flow rate and type of the plasma etching gas are determined by the ODL layer. 16a or SiN layer 14 is dynamically adjusted during the plasma etching process. Hereinafter, the etching apparatus and the line width or CD measurement apparatus will be described in detail.

[Etching device]
FIG. 3 shows a schematic diagram of an embodiment of the plasma processing apparatus 30. As shown in FIG. 3, the plasma processing apparatus 30 includes a processing vessel 120, a radial line slot plate 300, a substrate holder 140, and a dielectric window 160. The processing container 120 has a bottom 17 located near the substrate holder 140 and a cylindrical side wall 18 extending upward from the periphery of the bottom 17. The upper surface of the processing container 120 is an open end. The dielectric window 160 is provided so as to face the substrate holder 140 and seals the upper surface of the processing container 120 via the O-ring 20. The plasma processing apparatus 30 further includes a control device (not shown) that controls the processing conditions and overall operation of the apparatus 30.

The external microwave generator 15 provides a microwave output of a predetermined frequency, for example, 2.45 GHz, to the radial line slot plate 300 via the coaxial waveguide 24 and the slow wave tube 28. The coaxial waveguide 24 may have a center conductor 25 and a peripheral conductor 26. Subsequently, the microwave output is transmitted to the dielectric window 160 via a plurality of slots 29 provided on the radial line slot plate 300. The microwave from the microwave generator 15 generates an electric field below the dielectric window 160. The electric field causes excitation of a plasma gas, such as nitrogen (N ₂ ) gas or argon (Ar) gas, in the processing vessel 120. The recess 27 provided on the inner surface of the dielectric window 160 enables effective plasma generation inside the processing vessel 120.

  The external high frequency power supply 37 is electrically connected to the substrate holder 140 via the matching unit 38 and the power supply column 39. The high frequency power source 37 generates an RF bias output of a predetermined frequency, for example, 13.56 MHz, in order to control ion energy drawn into the substrate. The matching unit 38 matches the impedance of the RF power source 37 with the impedance of the power supply device, for example, the processing container 120. An electrostatic chuck 41 is provided on the upper surface of the substrate holder 140 in order to hold the substrate by electrostatic attraction force via the DC power source 46.

  The plasma processing apparatus 30 further includes a reactive gas supply unit 13. An enlarged view of the reaction gas supply unit 13 is also shown in FIG. As shown in FIG. 3, the reactive gas supply unit 13 may include a base injector 61. The base injector 61 is provided inside the dielectric window 160 and at a position behind the lower surface 63 of the dielectric window 160. The reactive gas supply unit 13 further includes a base holder 64. The base holder 64 further includes a base holder 64 that penetrates the dielectric window 160 in the thickness direction that holds the base injector 61. A top view of the base injector 61 is also illustrated in FIG. As shown in FIG. 3, a plurality of supply holes 66 are provided on a flat wall surface 67 provided to face the substrate holder 140. The plurality of supply holes 66 are provided radially at the center of the flat wall surface 67.

  The reaction gas supply unit 13 further includes a gas duct 68. As shown in FIG. 3, the gas duct 68 passes from the coaxial waveguide 24, the radial line slot plate 300, and the dielectric window 160 through the central conductor 25 to the plurality of supply holes 66. The gas supply system 72 is connected to a gas inlet 69 formed at the upper end of the center conductor 25. The gas supply system 72 may include an on / off valve 70 and a control device, such as a mass flow controller.

  Further, the reaction gas may be supplied to the processing vessel 120 by two gas ducts 89 provided on the cylindrical side wall 18. Note that the reactive gas is at least one of a plasma excited gas and a material gas. By adjusting the flow rate of the reaction gas supplied from the gas ducts 68 and 89, an optimized decomposition of the material gas in the processing vessel 120 can be realized.

[Line width or CD measuring device]
The line width of the resist pattern 16c, the silicon-containing antireflection coating (Si-ARC) layer 16b, the organic dielectric layer (ODL) 16a, or the silicon nitride (SiN) layer 14 is measured and measured by using a line width measuring device. Calculated. This apparatus may be any of a single type, a type integrated with a coater developing device, or a type integrated with an etching apparatus. When the line width measuring device is incorporated into a coater developing device, the latent image of the resist or the line width of the resist after development can be measured immediately after the process. When the line width measuring device is incorporated in an etching apparatus, the line width can be measured before and after etching as well. On the other hand, line width or CD measurements may be performed using a single measurement system. Hereinafter, each of the above-described embodiments will be described in detail.

1) Line width measuring device integrated with coater developing device FIG. 4 shows a schematic diagram of an embodiment of a line width measuring device 402A integrated with the entire structure of the photoresist forming apparatus 40A. For convenience, the overall structure of the photoresist forming apparatus 40A is simplified. As shown in FIG. 4, the entire structure of the photoresist forming apparatus 40A may include a coater developing apparatus 400A and an exposure apparatus 420. The coater developing device 400A is attached to the exposure device 402. On the other hand, the coater developing device 400A may be connected to the etching device 440.

  The photoresist forming apparatus 40A may include a line width measuring device 402A, a plurality of processing units (coating units or developing units) 404A, and two substrate transfer units 406A. The plurality of processing units 404A may further include a coating unit and / or a developing unit. The substrate transport unit 406A has a function of transporting the substrate between different adjacent members in the overall structure of the photoresist forming apparatus 40A. Further, the substrate transport unit 406A has a structure that can move vertically and horizontally, and may rotate about a vertical axis.

  After executing the development process, the line width or critical dimension (CD) of the resist pattern is measured. In the next step, appropriate setting conditions, such as the flow rate of the etching gas, are calculated based on the measured line width. Subsequently, the appropriate setting conditions are fed forward from the coater developing device 400A to the etching device 440. In some embodiments, the measured raw data is transmitted from the coater developer 400A to the etcher 440 and processed to obtain the proper etch conditions. In some embodiments, the appropriate setting conditions are calculated from the measured raw data (not shown) using a processing condition database. The processing condition database stores various processing conditions in the memory of the computer 442.

2) Line width measuring apparatus integrated with etching apparatus Referring to FIG. 5, a schematic diagram of an embodiment of the overall structure of a photoresist forming apparatus 40B is shown. As shown in FIG. 5, the overall structure of the photoresist forming apparatus 40B and the photoresist forming apparatus 40A are integrated with the etching apparatus 440B instead of the line width measuring apparatus 402B being integrated with the coater developing apparatus 400. Is different. The other members are basically the same as the structure 40A. In this embodiment, all three control methods including 1) feedforward control process, 2) feedback control process, and 3) dynamic (in situ) control process may be used to control the pattern of the substrate. .

  In the feedforward control process, after the developed substrate is carried into the etching apparatus 440B, the line width of the resist pattern is measured by the line width measuring apparatus 402B in the etching apparatus 440B, and an appropriate setting condition such as an etching gas is used. The flow rate of-is calculated based on the measured line width. Thereafter, the appropriate setting conditions are adjusted in the etching apparatus 440B for the etching process.

  In the feedback control process, the line width of the etching pattern is measured by the line width measuring device 402B, and an appropriate setting condition, such as the flow rate of the etching gas, is calculated based on the measured line width. Thus, the etching process for other substrates may be optimized by performing the etching process under appropriate set conditions.

  In the dynamic (in-situ) control process, the line width of the etching pattern is measured by the line width measuring device 402B, and appropriate setting conditions, such as the flow rate of the etching gas, are dynamically adjusted during the etching process. The In all the control processes described above, the appropriate setting conditions are calculated from raw data measured by using a processing condition database (not shown in FIG. 5). The processing condition database stores various processing conditions in the memory of the computer 442B.

  According to one aspect of the present invention, the multilayer structure needs to be etched continuously. In this example, the line width of the first patterning layer is first measured. Subsequently, appropriate etching conditions are set for the second layer formed in the vicinity of the first layer. In the next step, the second layer is etched using optimized etching conditions. Thereafter, the line width of the etched second layer is measured, and then appropriate etching conditions are set for the third layer. This process may be continued for multiple layers in the multilayer structure. In this manner, the line width (CD value) of the final etching pattern approaches the desired target value. The measurement of the line width (CD value) may be performed by either an IM module provided outside the chamber or a line width measuring device provided in the chamber. With this line width measurement device equipped with an etching chamber, CD is measured after the main etch (ME) process, and the preferred etch conditions for the overetch (OE) process are adjusted to tightly control the CD. Good.

As an example, the target structure 10 illustrated in FIG. 1 can be considered a multilayer structure. Since the etching process of each layer is performed according to the process described in the previous paragraph, the subsequent processes can be understood with reference to the structure of FIG. First, CD change values (ΔCD) per unit time for a plurality of HBr / O ₂ ratios (conditions) are obtained and stored as a table. Second, the line width of the Si-ARC layer 16b is measured. In the third step, the measured Si-ARC line width (CDs) and the target value (CDt) of the line width are calculated (CDt-CDs). Finally, an optimized HBr / O ₂ flow rate ratio is obtained based on the difference (CDt-CDs) and the ODL layer overetch time (T). The optimized HBr / O ₂ flow rate ratio is obtained in advance for the ODL etching process. The etching process is thus carried out under the optimized HBr / O ₂ flow rate. In this way, the final ODL pattern 16a is obtained in a shape close to the target line width (CDt). When the Si-ARC layer 16b is etched using the photoresist mask 16c, the flow rate of CF ₄ / CHF ₃ is optimized according to the process described above, and the etching is performed using the optimized CF ₄ / CHF ₃ Note that it runs at a flow rate of. Under certain etching conditions (eg, etching gas flow rate), the CD value may be adjusted by the etching time. Further, the CD value may be changed by adjusting both the ratio (flow rate) of the flow of the plurality of etching gases and the etching time.

When the difference between the target CD value of the resist pattern on the Si-ARC layer 16b and the measured line width exceeds a predetermined threshold (trimming ability), both the Si-ARC layer and the ODL layer are completed. To obtain the target CDt value, the flow rate ratio (in this particular example, the ratio of HBr / O ₂ to CF ₄ / CHF ₃ ) may be optimized. When a person skilled in the art estimates that the target value cannot be reached at the end of the Si-ARC etching process by comparing the measured resist CD value with the target CD value before the start of etching, the predetermined threshold is It may be obtained. In this way, the target value of the line width can be reached when the etching process of two successive layers of the Si-ARC layer and the ODL layer is completed. In this embodiment, the flow rate ratio between HBr / O ₂ and CF ₄ / CHF ₃ is determined by considering various parameters such as etching time and etching shape of each layer. In this embodiment, the target value of the line width of Si-ARC and the target value of the line width of ODL are given in advance.

3) Single Line Width Measuring Device FIG. 7 shows a schematic diagram of an embodiment related to the single line width measuring device 402C of the entire structure of the photoresist forming apparatus 40C. As shown in FIG. 7, the entire structure of the photoresist forming apparatus 40C and the entire structure of the photoresist forming apparatuses 40A and 40B are the same as the line width measuring apparatus 402C as a single measuring apparatus. Both are different in that they are not integrated. Other members are basically the same as the structure of the photoresist forming apparatus 40A. In this embodiment, a substrate container (generally called FOUP) is used (not shown in FIG. 7). Each substrate is transferred to the container after the development process or the etching process by using, for example, an automatic guide vehicle (AGV), and is transferred to the line width measuring device 402C. For each substrate, the line width of each substrate is first measured and then the appropriate set conditions are calculated. The measured CD value and appropriate setting conditions are transmitted to the etching apparatus 440.

[Experimental sample]
To evaluate the effect of hydrogen bromide (HBr) on the sidewall protection mechanism and also establish a process to control the critical dimension (CD), multiple experimental samples are made. Here, the target structure is the same as the target structure described in FIG. 1 or FIG. The experimental sample is then subjected to a plasma etching process according to the present invention. In the plasma etching process, an appropriate amount of hydrogen bromide (HBr) is added into a mixed atmosphere of nitrogen and oxygen (N ₂ / O ₂ ) during the over-etching (OE) step of the organic dielectric layer (ODL). . Hereinafter, these evaluation results will be described in detail.

  Referring to FIG. 8, a cross section of the two experimental samples after performing a plasma etching process on each particular layer of the target structure of the two experimental samples is illustrated. The first experimental sample is characterized by having a dense array pattern, while the second experimental sample represents a sparse pattern. Cross sections of both patterns are shown in the upper and lower parts of FIG. 8, respectively. As shown in FIG. 8, a cross-sectional image was taken after performing the etching process for each mask layer. For both experimental samples, 1-5 columns of these cross-sectional views correspond to the resist pattern, Si-ARC pattern, ODL main etch (ME) pattern, ODL overetch (OE) pattern, and hard mask SiN pattern, respectively. ing. Table 1 summarizes the etching conditions applied to each mask layer.

図8に図示されているように、Si-ARC及びODL主エッチング(ME)工程において限界寸法(CD)は減少している。ODL層のオーバーエッチング(OE)工程中に、臭化水素(HBr)を窒素と酸素の混合雰囲気(N₂/O₂)中に加えることによって、密なパターンと疎なパターンのいずれの限界寸法も増大することができる。図8に図示されているように、ODLオーバーエッチング(OE)における密なアレイパターンが約46nmである一方で、同一の層における疎なパターンの限界寸法(CD)は約115nmである。限界寸法のこのような増大は、薄い臭化炭素(CBr_x)の堆積によるものと考えられる。前記堆積は、エッチングに対する側壁保護として機能する。

As shown in FIG. 8, the critical dimension (CD) decreases in the Si-ARC and ODL main etching (ME) process. By adding hydrogen bromide (HBr) in a mixed atmosphere of nitrogen and oxygen (N ₂ / O ₂ ) during the overetching (OE) process of the ODL layer, both critical and sparse pattern critical dimensions Can also be increased. As illustrated in FIG. 8, the dense array pattern in ODL overetch (OE) is about 46 nm, while the critical dimension (CD) of the sparse pattern in the same layer is about 115 nm. This increase in critical dimension is believed to be due to the deposition of thin carbon bromide (CBr _x ). The deposition functions as sidewall protection against etching.

  The final critical dimension (CD) after execution of the hard mask SiN etching process is 40 nm for dense patterns and 119 nm for sparse patterns. The trimming capability is a range in which the critical dimension of the mask layer changes after execution of the etching process by adjusting the gas flow conditions (gas ratio, total flow rate, etc.). FIG. 8 shows that the CD value changes in both dense and sparse patterns.

In the following, the influence of each parameter, such as the flow rate of HBr, the time dependency of the overetching (OE) process, the type of etching gas, and the composition ratio, on the critical dimension (CD) of the ODL layer will be examined. For this purpose, various experimental samples with dense and sparse patterns were formed under different etching conditions. Unless otherwise stated, the following etching conditions are used for patterning the ODL layer of each experimental sample. Specifically, 1) Regarding the main etching (ME) conditions, the pressure is 10 mTorr, the N ₂ / O ₂ flow rate is 400 sccm / 200 sccm, the microwave output is 3 kW, the RF output is 200 W, and the main etching (ME) cycle is 40) 2) Over-etching (OE) conditions: pressure 10 mTorr, N ₂ / O ₂ flow rate 400 sccm / 4 sccm, microwave power 3 kW, and RF power 200 W.

  Two sets of experimental samples were made to evaluate the dependence of critical dimension (CD) on the overetch period. In each set, three experimental samples with the same mask pattern were produced. Similar to the previous case, the first set of experimental samples is characterized by having a dense array pattern, while the second set of experimental samples represents a sparse pattern. The main etching (ME) and over-etching (OE) of the ODL layer are performed in the plasma processing apparatus 30. The main etching (ME) conditions and over-etching (OE) conditions used for patterning the ODL layer are the same as those described in the previous paragraph.

  For this evaluation, the HBr flow rate was set at 60 sccm. In addition, in each set, three experimental samples were patterned with an overetch processing time of 0, 20, and 40 seconds.

FIG. 9 shows the cross section of the experimental sample and its critical dimension (CD) as a function of overetch (OE) processing time. As illustrated in FIG. 9, the critical dimension (CD) can be increased by extending the over-etch (OE) processing time. This is believed to be mainly due to the increased deposition of reactive byproducts such as carbon bromide (CBr _x ) across the ODL pattern due to the extended over-etch (OE) period.

  Referring now to FIG. 10, the cross-sectional view and critical dimension (CD) of the experimental sample are shown as a function of HBr flow rate. Similar to the previous examples, two sets of experimental samples were made. Each set has three samples with a similar pattern. The first set of experimental samples is characterized by having a dense array pattern, while the second set of experimental samples represents a sparse pattern. The main etching (ME) and over-etching (OE) of the ODL layer are performed in the plasma processing apparatus 30. The main etching (ME) conditions and over-etching (OE) conditions used for patterning the ODL layer are the same as those described in the previous paragraph. For this evaluation, the overetching (OE) processing time conditions were all set to 20 seconds. In addition, each of the three experimental samples in each set was patterned with HBr flow rates of 0 sccm, 60 sccm, and 120 sccm, respectively.

As illustrated in FIG. 10, the critical dimension (CD) increases with increasing HBr flow rate. The mechanism used to control the critical dimension (CD) of the ODL layer is considered as follows. That is, hydrogen (H) reduces oxygen at the surface of the ODL layer by adding hydrogen bromide (HBr) to a gas mixture of hydrogen and nitrogen (N ₂ / O ₂ ). In other words, oxygen (O) atoms are extracted from the ODL. As a result, an organic dielectric layer (ODL) with a high carbon content on the surface is produced. Therefore, as the carbon-carbon bond increases, the organic dielectric layer (ODL) becomes more rigid. The stiffness of the ODL functions as a side wall protection, which prevents etching.

On the other hand, it is considered that the bromine-carbon bond near the surface of the ODL pattern increases as the carbon content of the ODL layer increases. It can also be said that a thin layer of carbon bromide (CBr _x ) deposited over the entire ODL pattern functions as a sidewall protection, thus preventing etching. By increasing the flow rate of hydrogen bromide (HBr), the deposition of carbon bromide (CBr _x ) increases due to the increase in Br element, eventually increasing the critical dimension (CD) of ODL. On the other hand, by increasing the HBr flow rate, the increase in CD is reduced. In this way, good controllability for obtaining a predetermined value of the critical dimension (CD) can be realized.

The critical dimension (CD) of the ODL layer may be controlled using other types of etching gases, such as chlorine (Cl ₂ ) gas. To evaluate how other types of etchant gases can affect the controllability of critical dimension (CD), two sets of experimental samples were made. In each set, two experimental samples with the same mask pattern were produced. Similar to the previous example, the first set of experimental samples is characterized by a dense array pattern, while the second set of experimental samples represents a sparse pattern. In each set, the first experimental sample and the second experimental sample are first subjected to a main etching (ME) step under the same etching conditions as described in the previous seven paragraphs. Subsequently, an overetching (OE) step is performed on each set of first experimental samples by adding hydrogen bromide (HBr) gas to a mixed gas of hydrogen and nitrogen (N ₂ / O ₂ ). However, each set of second experimental samples is subjected to an over-etching step by adding chlorine (Cl ₂ ) gas to a mixed gas of hydrogen and nitrogen (N ₂ / O ₂ ). For this evaluation, both the HBr flow rate and the Cl ₂ flow rate were set to 60 sccm. Furthermore, the condition of the overetching (OE) processing time was set to 20 seconds in each experimental set.

FIG. 11 shows cross-sectional views of experimental samples for various etching gas types. As shown in Figure 11 comparison, the critical dimensions of ODL layer in overetching (OE) step (CD), for any kind of etching gas (HBr and Cl _2), a main etch (ME) process Has increased. Although the exact mechanism for controlling the critical dimension (CD) of the ODL layer in the case of chlorine (Cl ₂ ) gas is not known, similar results have been obtained for increasing the critical dimension (CD). However, other harmful effects were also observed in this example. For example, the underlying hard mask silicon nitride (SiN) layer is thinned so that its mask height is reduced (tapered).

In an alternative embodiment, the desired critical dimension (CD) is performed by adding hydrogen bromide (HBr) into a mixed atmosphere of argon and oxygen (Ar / O ₂ ). In this alternative embodiment, a series of argon / hydrogen bromide / oxygen (Ar / HBr / O ₂ ) is used to perform the ODL main etch (ME) process. Similar to the previous example, two sets of experimental samples were made, each set having three samples with a similar pattern. The first set of experimental samples is characterized by having a dense array pattern, while the second set of experimental samples represents a sparse pattern. More specifically, a small piece of substrate (cleaved sample, also referred to as a coupon) having the structure illustrated in FIG. 1 was used in this experiment. When Si-ARC and ODL main etch (ME) were performed, the cut specimens were mounted on a substrate with a full photoresist coating thereon. When ODL overetch (OE) was performed, the cut specimens were mounted on a substrate that was fully coated with silicon nitride (SiN). ODL overetch (OE) was performed for 15 seconds. Table 2 summarizes the etching conditions in the Si-ARC layer and the ODL layer.

Si-ARC及びODL主エッチング(ME)工程の実行後、オーバーエッチング(OE)工程が、プラズマ処理装置30を用いて実行された。各組の第1実験用試料、第2実験用試料、及び第3実験用試料のオーバーエッチング(OE)工程はそれぞれ、100/150/20、100/150/10、及び100/150/5sccmのAr/HBr/O₂流速比で実行された。

After performing the Si-ARC and ODL main etching (ME) process, an over-etching (OE) process was performed using the plasma processing apparatus 30. The overetching (OE) process for each set of the first experimental sample, the second experimental sample, and the third experimental sample is 100/150/20, 100/150/10, and 100/150/5 sccm, respectively. Run at Ar / HBr / O ₂ flow rate ratio.

Referring now to FIG. 12, the cross section of the experimental sample and its critical dimension (CD) are represented as a function of the HBr / O ₂ ratio. As illustrated in FIG. 12, the critical dimension (CD) of the ODL layer increases with increasing HBr / O ₂ ratio. In other words, as the oxygen (O ₂ ) flow rate decreases, the critical dimension (CD) of the ODL layer increases.

  In the conventional plasma etching process, there is a problem that the pattern shape varies after the etching process. In order to avoid such variations in pattern shape, a mask for photolithography purposes is designed by taking into account variations in the dimensions of the completed etching pattern. However, the above problem cannot be completely avoided by this solution.

The plasma etching process of the present invention provides a solution to the above problems. It is considered that hydrogen (H) decreases oxygen (O) on the surface of the ODL layer by adding hydrogen bromide (HBr) into a mixed atmosphere of N ₂ / O ₂ or Ar / O ₂ . In other words, oxygen (O) atoms are extracted from the ODL layer. As a result, an organic dielectric layer (ODL) with a high carbon content on the surface is produced. Therefore, the carbon-carbon bond increases and the organic dielectric layer (ODL) becomes more rigid. The rigidity of the ODL layer functions as a side wall protection. As a result, the etching is protected.

In addition, it is considered that a plurality of bromine-carbon bonds in the vicinity of the ODL pattern are increased by increasing the carbon content of the ODL layer. As a result, a thin layer of carbon bromide (CBr _x ) is deposited over the entire ODL pattern. A thin layer of carbon bromide (CBr _x ) deposited in this manner serves as sidewall protection. Therefore, the lateral etching of the ODL layer can be suppressed. Furthermore, by increasing the flow rate of hydrogen bromide (HBr), the deposition of carbon bromide (CBr _x ) increases due to the increase in Br. This increases the critical dimension (CD) of ODL. On the other hand, by increasing the HBr flow rate, the CD increase rate is reduced. In this way, good controllability to obtain a predetermined value of the critical dimension (CD) can be realized by selecting an appropriate HBr flow rate.

  Two sets of experimental samples were made to evaluate the variation in pattern shape and the uniformity of its critical dimensions. Each sample has a different pattern (dense pattern and sparse pattern). In each set, two experimental samples with similar patterns were made. Table 3 summarizes the etching conditions used in each mask layer of the experimental sample.

この実験については、Si-ARC及びODL主エッチング(ME)工程でのエッチング時間はそれぞれ、16秒及び40.8秒に設定された。オーバーエッチング(OE)工程では、一の実験用試料のエッチング時間が20秒に設定される一方で、他の実験用試料のエッチング時間は40秒に設定された。

For this experiment, the etching times in the Si-ARC and ODL main etching (ME) steps were set to 16 seconds and 40.8 seconds, respectively. In the overetching (OE) process, the etching time for one experimental sample was set to 20 seconds, while the etching time for the other experimental sample was set to 40 seconds.

  FIG. 13 shows a cross-sectional view of an experimental sample and its critical dimension (CD). For each experimental sample, a cross-sectional view was taken along the center and edge of the substrate, respectively. The center and end of the substrate are defined by “center” and “end” in FIG. As illustrated in FIG. 13, the critical dimension (CD) does not depend on the overetch (OE) processing time for all experimental samples. In addition, no variation in pattern shape was observed across all samples.

  FIG. 14 shows the microwave output, RF output, and RF voltage of each mask layer as a function of time. The horizontal axis represents the processing time, the left vertical axis represents the microwave output and the RF bias output, while the right vertical axis represents the RF bias voltage. The experimental data illustrated in FIG. 14 represents an example in which the multilayer structure etching process is continuously performed in the same processing vessel 120 of the plasma processing apparatus 30. Note that the upper microwave power at the start of each process step is applied as a δ function that initiates the plasma generation process.

An RF bias voltage (lower V _pp ) was applied to the substrate holder 140 from the plasma processing apparatus 30 (see FIG. 3). As described above, this RF bias voltage controls the ion energy drawn into the substrate. As illustrated in FIG. 14, the RF bias voltage decreases as the etching process proceeds to the next mask layer. Thereby, the energy of ions impinging on the substrate decreases as the etching process proceeds toward the lower mask layer.

  Furthermore, another problem observed in conventional plasma etching processes is that the resist pattern is formed non-uniformly depending on whether the pattern on the region is sparse or dense. . In other words, there is a variation in pattern shape depending on whether the resist pattern is sparse (also called coarse) or dense (also called fine). In order to avoid variations in coarse and fine shapes, a mask for photolithography purposes is designed by taking these variations into account. However, the above problem cannot be completely avoided by this solution. Also, when controlling the critical dimension (CD), it was observed that variations in coarse and fine shapes occur.

While patterning the silicon-containing anti-reflective coating (Si-ARC) layer according to the process of the present invention, variations in rough and fine shapes can be avoided. In this example, the line width or critical dimension (CD) of the final pattern, eg, hard mask SiN, is adjusted by adjusting the ratio of tetrafluoromethane gas to trifluoromethane gas (CF ₄ / CHF ₃ ). Is controlled through. By adjusting the CF ₄ / CHF ₃ ratio in the Si-ARC etching process, the critical dimension of the Si-ARC pattern can be controlled within the final critical dimension (CD) of about -2 nm to +10 nm. May change as you like.

The Si-ARC pattern is mainly composed of silicon (Si) atoms and carbon (C) atoms. It is believed that the Si-ARC layer containing carbon helps to create multiple carbon-fluorine bonds on the surface of the Si-ARC layer. Therefore, by adjusting the ratio of CF ₄ / CHF ₃ in the Si-ARC layer, the CF _x series thin films are caused by Si— due to the difference in binding energy between CF ₄ gas and CHF ₃ gas. Deposited over the entire ARC pattern. As a result, by adjusting the CF ₄ / CHF ₃ ratio in the Si-ARC etching process, the lateral etching of the Si-ARC layer according to the process of the present invention is suppressed, and the limitation of the Si-ARC pattern The dimension (CD) can be increased.

In order to evaluate the controllability of the critical dimension (CD) by the etching process of the Si-ARC layer, and to investigate the variation in the rough shape and the fine shape, various experimental samples were prepared. Similar to the previous examples, two experimental samples were made. Each sample has a different pattern (dense pattern and sparse pattern). Table 4 summarizes the etching conditions used in each mask layer of the experimental sample. In this experiment, the etching times in Si-ARC, ODL main etching (ME) process, ODL overetching (OE) process, SiN, and ashing processes were set to 17.7 seconds, 40.8 seconds, 20 seconds, and 30 seconds, respectively. It was. Furthermore, the ratio of CF ₄ / CHF ₃ was set to 1 (180/180).

図15を参照すると、実験用試料の断面及びその限界寸法(CD)が図示されている。図15に図示されているように、垂直プロファイルは、全実験用試料にわたって90°に非常に近く、粗い形状と微細な形状にはほとんどばらつきがないことを示している。それに加えて、Si-ARCのパターンの限界寸法(CD)は、全実験用試料にわたって所望の目標パターンからのズレが最小（±0nm〜±2nm）であることを示している。この実験では、密なパターンと疎なパターンの所望の目標パターンはそれぞれ、45nm及び75nmに設定された。

Referring to FIG. 15, a cross section of the experimental sample and its critical dimension (CD) are shown. As illustrated in FIG. 15, the vertical profile is very close to 90 ° across all experimental samples, indicating that there is little variation in the rough and fine shapes. In addition, the critical dimension (CD) of the Si-ARC pattern indicates that the deviation from the desired target pattern is minimal (± 0 nm to ± 2 nm) across all experimental samples. In this experiment, the desired target patterns of dense and sparse patterns were set to 45 nm and 75 nm, respectively.

When the CF ₄ / CHF ₃ ratio changed for each experimental sample, the controllability of the critical dimension (CD) by the etching process of the Si-ARC layer and the changes in the roughness and fineness shapes were also investigated. Again, two sets of experimental samples were made. Each sample has a different pattern (dense pattern and sparse pattern). In each set, three experimental samples were made. The etching conditions used for each mask layer of the experimental sample are the same as the etching conditions summarized in Table 4. However, in each set of experimental samples, the ratio of CF ₄ / CHF ₃ for the first experimental sample, the second experimental sample, and the third experimental sample is (210/150), (180/180), respectively. , And (150/210).

  Referring now to FIG. 16, a cross section of the experimental sample and its critical dimension (CD) are illustrated. As illustrated in FIG. 16, the vertical profile is very close to 90 ° across all experimental samples, indicating that there is little variation in coarse and fine shapes. In addition, the critical dimension (CD) of the Si-ARC pattern shows that the deviation from the initial target pattern is minimal (-3 nm to +12 nm) across all experimental samples. The maximum deviation over the pattern is +2 nm. In this experiment, the initial target patterns of dense and sparse patterns were set to 45 nm and 75 nm, respectively.

Claims (19)

A method of processing a substrate to form a desired pattern by an etching process after forming a mask pattern on the substrate:
Forming two layers on the substrate having a silicon nitride layer and an organic dielectric layer;
Measuring the width of the mask pattern or the etched pattern of one of the two layers; and
Adjusting the flow rate of any one of HBr and other gases used in the etching process based on the measured width;
Having a method.   The method of claim 1, further comprising etching one of two layers of the same substrate as the substrate at a flow rate adjusted based on a measured width of the mask pattern.   2. The method of claim 1, further comprising etching one of the two layers of the other substrate at a flow rate adjusted based on the measured width of the mask pattern. The method of claim 1, further comprising etching one of two layers of the same substrate as the substrate at a flow rate adjusted based on a measured width of the etched pattern. There,
The measuring and adjusting steps are performed during the etching process;
Method. The adjusting step includes increasing a flow rate ratio of HBr to the other gas when the measured width is narrower than a desired width; and when the measured width is wider than the desired width. The step of reducing the flow rate ratio of HBr to the other gas,
The method of claim 1.   The method of claim 2, wherein the organic dielectric layer is etched in the etching step. The adjusting step increases the etching time when the measured width is narrower than the desired width; and reduces the etching time when the measured width is wider than the desired width. Having a step of
The method of claim 6. The step of etching comprises main etching and overetching following the main etching; and
The HBr is used in the overetching,
The method of claim 6. The adjusting step increases the etching time when the measured width is narrower than the desired width; and reduces the etching time when the measured width is wider than the desired width. Having a step of
The method according to claim 8. The adjusting includes increasing an RF bias output applied to the substrate when the measured width is narrower than a desired width; and when the measured width is wider than the desired width Reducing the RF bias output applied to the substrate.
The method of claim 1. The method of claim 1, wherein the other gas comprises N ₂ and O ₂ . The method of claim 1, wherein the other gas comprises Ar and O ₂ . A method of processing a substrate to form a desired pattern by an etching process after forming a mask pattern on the substrate:
Forming three layers on the substrate having a silicon nitride layer, an organic dielectric layer, and a silicon-containing antireflection coating layer;
Measuring the width of the mask pattern or the etched pattern of one of the three layers; and
Adjusting the flow rate of any one of CF ₄ and CHF ₃ used in the etching process based on the measured width;
Having a method.   14. The method of claim 13, further comprising etching one of three layers of the same substrate as the substrate at a flow rate adjusted based on a measured width of the mask pattern.   14. The method of claim 13, further comprising etching one of the three layers of the other substrate at a flow rate adjusted based on the measured width of the mask pattern. The method of claim 13, further comprising etching one of two layers of the same substrate as the substrate at a flow rate adjusted based on a measured width of the etched pattern. There,
The measuring and adjusting steps are performed during the etching process;
Method.   14. The method of claim 13, further comprising etching the silicon-containing antireflective coating layer at a flow rate adjusted based on the measured width of the mask pattern. The adjusting comprises increasing the flow rate ratio of CF _{4 to} CHF ₃ when the measured width is narrower than the desired width; and when the measured width is wider than the desired width. comprises the step of reducing the flow rate ratio of CF ₄ for CHF _3, the method of claim 13.   The adjusting includes increasing an RF bias output applied to the substrate when the measured width is narrower than a desired width; and when the measured width is wider than the desired width 14. The method of claim 13, further comprising reducing an RF bias output applied to the substrate.

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