JP5067043B2 - Image processing apparatus, image processing method, and projection display apparatus - Google Patents

Description

  The present invention relates to an image processing apparatus, an image processing method, and a projection display apparatus that perform registration correction.

  Projection-type display devices in which red light, green light, and blue light are modulated according to RGB video signals and projected onto a screen by three liquid crystal panels have become widespread.

  FIG. 1 is a diagram showing an example of an optical system of a rear projection television which is a kind of such a projection display device. The light emitted from the light source 31 is collimated by the reflector 30 and then separated into red light and cyan light by the color separation dichroic mirror 34.

  The red light is incident on the panel surface of the LCD device (liquid crystal panel and its driving circuit) 41 through the total reflection mirror 36 and the relay lens 44. The cyan light is separated into green light and blue light by the color separation dichroic mirror 32. The green light enters the panel surface of the LCD device 40 through the relay lens 43. The blue light enters the panel surface of the LCD device 42 through the total reflection mirror 33, the total reflection mirror 35, and the relay lens 45.

  In the LCD devices 41, 40, and 42, the incident red light, green light, and blue light are modulated according to the level of the RGB video signal. Red light, green light, and blue light emitted from the panel surfaces of the LCD devices 41, 40, and 42 are combined by a cross dichroic prism 46 and projected from a rear surface onto a transmissive screen 49 through a close-up lens 47 and a total reflection mirror 48. Is done.

  In the projection display device illustrated in FIG. 1, since the paths through which red light, green light, and blue light pass are different from each other, the screen is caused by variations in the mounting position accuracy of optical components such as a total reflection mirror and a relay lens. Registration shift, which is a phenomenon in which the position of the image projected on the screen is shifted from each other in red, green, and blue, occurs. Normally, the size of this registration shift is about several pixels or several lines at the edge of the screen, and this shift causes color blurring and affects the image quality.

  Conventionally, as a technique for correcting this registration shift, an alignment mechanism for improving the workability is provided on the premise that the alignment of the light emitted from each LCD device is performed manually. Has been proposed (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 8-184928

  However, even if such an alignment mechanism is provided, manual registration correction itself is still complicated and takes time.

  In view of the above-described points, the first object of the present invention is to perform registration correction by signal processing instead of manual work.

  Further, in a display device using a liquid crystal panel as a light modulation element, as one of signal processing, the signal level of the current frame and the signal level of the previous frame are used for the purpose of improving the response characteristics of liquid crystal molecules during moving image display. There is one that performs processing (overdrive) for correcting the signal level of the current frame in accordance with the difference between the current frame level and the current frame level.

  Therefore, the second object of the present invention is to perform registration correction by signal processing while reducing the circuit scale and cost by using a circuit for performing such overdrive.

Engaging Ru images processing device of the present invention,
Data on the shift amount of the pixel position for distorting any two of the first image and the second image of the red image, the blue image, and the green image with respect to the remaining one third image respectively. Means for supplying;
A static RAM for temporarily writing video signals of colors corresponding to the first and second images of the RGB video signals;
The video signals of the colors corresponding to the first and second images are respectively written in the static RAM, and at the time of reading, the value of each pixel is changed to the value of the pixel at the pixel position shifted based on the shift amount data. First and second static RAM controllers to be obtained using;
For the first, second and third images, the first and second static RAMs have a capacity larger than the capacity required for simultaneously reading out the current one-frame video signal and the previous one-frame video signal at double speed. A dynamic RAM having a capacity large by the amount of signal processing delay in the controller ;
A video signal of a color corresponding to the first and second images read from the static RAM is sent to write the video signal to the dynamic RAM, and the third of the RGB video signals. The video signal of the color corresponding to the image is directly sent without being read and written in the static RAM, and the video signal is written to the dynamic RAM. The video signal of the color corresponding to the first and second images is currently The one-frame video signal and the one-frame previous video signal are simultaneously read at double speed, and the video signal of the color corresponding to the third image is subjected to signal processing delay in the first and second static RAM controllers. A dynamic RAM that reads the current video signal of one frame and the video signal of the previous frame at a double speed at the same time with a delay according to the amount. And a controller,
And an overdrive processing circuit for overdriving video signals of colors corresponding to the first, second, and third images read from the dynamic RAM.
Further, engagement Ru images processing method according to the present invention,
Data on the shift amount of the pixel position for distorting any two of the first image and the second image of the red image, the blue image, and the green image with respect to the remaining one third image respectively. A first step of supplying;
Of the RGB video signals, video signals of colors corresponding to the first and second images are respectively written in the static RAM, and when reading from the static RAM, the value of each pixel is based on the shift amount data. A second step of obtaining using the pixel value of the pixel position shifted by
A video signal of a color corresponding to the first and second images read from the static RAM is converted into a current one-frame video signal and a previous one-frame video signal for the first, second, and third images, respectively. It said than the capacity required to read at the same time speed a video signal first, write to the dynamic RAM of the signal processing delay amount greater volume in the second static RAM controller Mutotomoni, among the RGB video signals The video signal of the color corresponding to the third image is directly written into the dynamic RAM without being read / written by the static RAM, and the video signal of the color corresponding to the first and second images is the current one frame. The video signal of 1 frame and the video signal of the previous frame are simultaneously read at double speed, and the video signal of the color corresponding to the third image is Combined to the signal processing delay in the second step and delays, a third step of reading the video signal and the previous frame of the video signal of the current frame at the same time speed,
And a fourth step of performing overdrive on the video signals of colors corresponding to the first, second and third images read from the dynamic RAM, respectively.
Further, projecting elevation-type display device engaging Ru in the present invention,
In a projection display device having three liquid crystal display devices that modulate red light, green light, and blue light according to the levels of RGB video signals,
Comprising a locking Ru images processing device according to the present invention, RGB image signal output from the overdrive processing circuit is characterized in that is sent to a liquid crystal display device.

  According to the image processing device, the image processing method, and the projection display device, video signals of two colors out of RGB video signals are written in the static RAM, and values of each pixel are read out from the static RAM. Is obtained by using the pixel value at the pixel position obtained by shifting the two color images so as to be distorted with respect to the remaining one color image. Since the static RAM has good random accessibility, the value of the pixel at the pixel position shifted in this way can be read quickly.

Further, the remaining one of the RGB video signals has a capacity larger than the capacity required for simultaneous readout of the current frame and the previous frame for each of RGB without providing a static RAM . First, data is directly written in a dynamic RAM having a capacity larger by the signal processing delay amount in the second static RAM controller, and delayed in accordance with the signal processing delay amounts for the other two color video signals.

  In this way, registration processing is canceled by distorting any two of the red, blue, and green images with respect to the remaining one image in advance by signal processing. Is possible.

In addition, the static RAM has good random access, but the area on the silicon chip increases, which is disadvantageous in terms of cost. On the other hand, the dynamic RAM has a smaller area than the static RAM . The dynamic RAM is originally necessary for the double-speed reading process as a pre-stage of overdrive. Therefore, in the delay processing that does not require random accessibility, the circuit scale and cost can be reduced by using a dynamic RAM for overdrive without providing a static RAM .

Engaging Ru images processing device according to the present invention, an image processing method, according to the projection display device, by utilizing a dynamic RAM for performing overdrive, the signal processing registration correction while reducing the circuit scale and cost The effect that it can be performed is obtained.

  Embodiments of the present invention will be specifically described below with reference to the drawings. In the following, an embodiment in which the present invention is applied to a rear projection television will be described. However, the optical system of the rear projection television has already been illustrated in FIG.

  In a rear projection television to which the present invention is applied, as a method of registration correction, a video signal sent to an LCD device is subjected to signal processing in a direction opposite to distortion caused by mounting accuracy of an optical component such as a total reflection mirror or a relay lens. In addition, a method is used in which the registration deviation generated on the screen is canceled by pre-distorting by a magnitude corresponding to the distortion.

  FIG. 2 is a diagram showing a range in which an image is distorted by the registration correction signal processing. “Image active” represents a video area (for example, an area of 1920 pixels × 1080 lines in an HDTV signal) in a television signal for one frame. “Image total” represents the entire area (video area and blanking area) of a television signal for one frame.

  “Panel active” is an area where video can be displayed on the rear projection television, and is somewhat wider than “image active”. Registration correction signal processing is performed by distorting an image (in the example of FIG. 2, an image of a checkered pattern) in an area within the panel active.

  At that time, as shown on the right side of FIG. 2, the green image is not distorted at all, and the red image and the blue image are distorted with respect to the green image. Since green accounts for about 70% of the brightness of the image, the green image is not distorted as a measure for preventing image quality deterioration.

  In the example on the right side of FIG. 2, the red image is given distortion in the upper left direction with respect to the green image, and the blue image is given distortion in the lower right direction and left rotation direction with respect to the green image. ing. The distorted red image and blue image are within the area within the panel active.

  Hereinafter, the area in the image active is also referred to as “image frame”, and the area in the panel active is also referred to as “panel frame”.

[First Embodiment of Signal Processing System]
Next, a signal processing system for registration correction in a rear projection television to which the present invention is applied will be described. FIG. 3 is a block diagram showing a first embodiment of this signal processing system. As circuits for registration correction signal processing, there are SRAM (static RAM) 1, SRAM 2 and SRAM 3, SRAM controller 11, SRAM controller 12, SRAM controller 13, SRAM 4 and CPU I / F 5 for controlling them. Is provided.

  A DRAM (dynamic RAM) 6, a DRAM controller 7 that controls the DRAM 6, and an overdrive processing circuit 8 are provided as circuits for overdrive, following the SRAM controllers 11, 12, and 13.

  The CPU I / F 5 is connected to a CPU (not shown) that controls the entire rear projection television. The ROM in the CPU stores control point data that is data of the shift amount of the pixel position for distorting the red image and the blue image with respect to the green image. Since the registration deviation due to the mounting accuracy of the optical components is determined for each rear projection television, this shift amount is based on the actual measurement result of the registration deviation for each rear projection television. The red image and the blue image are determined to be distorted in a direction opposite to the distortion of the red image and the blue image with respect to the green image by the amount corresponding to the distortion.

  The control point data is prepared for every 128 pixels in the H direction (horizontal direction of the screen) and for every 128 lines in the V direction (vertical direction of the screen), and values between them are obtained by linear interpolation calculation. Has been. Thereby, the data amount of the control point data can be reduced to 1 / (128 pixels × 128 lines) as compared with the case where the control point data is prepared for each pixel / line.

  When the rear projection television is turned on, the control point data is read from the ROM in the CPU and written to the SRAM 4 from the CPU I / F 5 via the SRAM controller 11 or 12.

  In the rear projection television, after being selected by a tuner (not shown), an RGB video signal whose frame frequency is doubled by a double speed processing circuit (not shown) is input to this signal processing system. Note that the frame frequency shown in FIG. 3 is a frequency when (outside) is NTSC, and () is a frequency when inside PAL.

  Of the RGB video signals input to the signal processing system, the Red video signal S1 is written into the SRAM 1 by the SRAM controller 11. The blue video signal S7 is written to the SRAM 2 by the SRAM controller 12. The green video signal S11 is written into the SRAM 3 by the SRAM controller 13. In the figure, red, blue, and green video signals output from the SRAM controllers 11, 12, and 13 to the SRAMs 1, 2, and 3 are shown as S2, S8, and S12, respectively.

  The SRAM controllers 11 and 12 read the control point data from the SRAM 4 and perform registration correction signal processing on the Red and Blue video signals using the SRAMs 1 and 2 as ring buffers. 4 to 6 are diagrams showing the contents of this registration correction signal processing (method of controlling the SRAMs 1 and 2 by the SRAM controllers 11 and 12). 4A is a diagram showing the timing of writing (writing) and reading (reading) video signals of Red and Blue to the SRAMs 1 and 2, and FIGS. 4B, 5 and 6 show the SRAM1. , 2 is a diagram showing pixel data written in 2 and pixel data read out from SRAMs 1 and 2.

  If the distortion of the red image and the blue image due to registration deviation is within ± 7 pixels in the H direction and within ± 5 lines in the V direction, for example, at least 6 lines + 8 pixels (FIG. 4) A difference between A and B) is required, and the memory capacity of the SRAMs 1 and 2 is at least 12 lines + 20 pixels (area F in FIG. 5).

  As shown in FIGS. 4 and 5, the writing and reading to the SRAMs 1 and 2 are performed in units of four pixels adjacent in the H direction. At the time of reading, the value of each pixel is obtained by a shift process. The shift process is a process for obtaining the value of each pixel using the value of the pixel at the pixel position shifted based on the control point data. In this shift process, as shown in the upper part of FIG. 6, in order to obtain the value of one pixel (white circle) after the shift process, pixels of 3 pixels × 3 lines are read and a filter is applied to the values of those pixels. Multiply (multiply those pixel values by multiplying each coefficient). Therefore, at the time of reading, a search range of ± 8 pixels in the H direction and ± 6 lines in the V direction (area D in FIGS. 4 and 5) is required.

  Further, if the distortion of the red image and the blue image due to registration deviation is within ± 7 pixels in the H direction and within ± 5 lines in the V direction, the distortion difference between the four pixels adjacent to each other in the H direction is 1. Since it can be said that it is within pixels and within one line (details will be described later), 1 pixel + 1 line is added to 6 pixels × 3 lines, and pixels of 7 pixels × 4 lines (region C in FIGS. 4 to 6). If read out, four pixels adjacent to each other in the H direction after the shift processing can be obtained.

  The details that the difference in distortion between four pixels adjacent to each other in the H direction can be said to be within one pixel and within one line are as follows. Since the second derivative value of distortion caused by the mounting accuracy of the optical component is substantially constant, in the case of full HD (1920 pixels × 1080 lines), distortion of ± 7 pixels in 1920 pixels in the H direction per pixel When converted into distortion, 14 pixels / 1920 pixels = 0.0729 pixels. Accordingly, as shown in FIG. 7A, the difference in distortion in the H direction between the four pixels adjacent to each other in the H direction is 14 pixels / 1920 pixels × 4 = 0.0292 pixels. is there.

  Similarly, when distortion of ± 5 lines at 1080 lines is converted into distortion in the V direction per pixel, 10 lines / 1920 pixels = 0.005 pixels. As a result, as shown in FIG. 7B, the difference in distortion in the V direction between the four pixels adjacent to each other in the H direction is 10 lines / 1920 pixels × 4 = 0.0208 pixels. is there. Accordingly, it can be said that the difference in distortion between four pixels adjacent to each other in the H direction is within one pixel and within one line.

  The SRAM controllers 11 and 12 obtain the shift amount by performing linear interpolation calculation on the control point data read from the SRAM 4 for each pixel when reading from the SRAM 1 and SRAM 2. FIG. 8 is a diagram showing a linear interpolation calculation formula for the control point data.

  Then, the SRAM controllers 11 and 12 read the values of the pixels of 3 pixels × 3 lines (FIG. 6) before the shift process determined by the obtained shift amount from the SRAMs 1 and 2, and the pixels of the pixels of the 3 pixels × 3 lines are read out. The value of one pixel after the shift processing is obtained by filtering the value. Since the SRAM has good random accessibility, it is possible to quickly read out the values of the pixels of 3 pixels × 3 lines before the shift process.

  As described with reference to FIG. 2, in the registration correction signal processing, the image is distorted in the area (panel frame) in the panel active. In FIG. 3, writing to the SRAM 1 and 2 is performed in the image active. The fact that the data is read in the area (image frame) and the reading from the SRAM 1 and 2 is performed in the panel frame is indicated by a dotted boundary line at the center of the block of the SRAM 1 and 2 and the SRAM controllers 11 and 12. .

  The SRAM controller 13 reads the Green video signal written in the SRAM 3 from the SRAM 4 with a delay so as to match the signal processing delay amount by the SRAM controllers 11 and 12. As shown in FIG. 4, since the signal processing delay amount by the SRAM controllers 11 and 12 is a time corresponding to 6 lines + 8 pixels, the readout is performed with a delay of the time corresponding to 6 lines + 8 pixels in the SRAM controller 13. .

  In this way, registration correction is performed by signal processing using an SRAM with good random accessibility.

  The SRAM controllers 11, 12, and 13 send Red, Blue, and Green video signals read from the SRAMs 1, 2, and 3 to the DRAM controller 7. In the figure, red, blue, and green video signals output from the SRAMs 1, 2, and 3 to the SRAM controllers 11, 12, and 13 are shown as S3, S9, and S13, respectively, and from the SRAM controllers 11, 12, and 13 to the DRAM controller 7. The output Red, Blue, and Green video signals are shown as S4, S10, and S14, respectively.

  The DRAM controller 7 once writes Red, Blue, and Green video signals into the DRAM 6, then reads the Red, Blue, and Green video signals from the DRAM 6 at a double speed and sends them to the overdrive processing circuit 8. At this time, since only the Green video signal remains in the image frame, it is converted into a panel frame and sent to the overdrive processing circuit 8. Specifically, by forcing the data to zero level for areas inside the panel frame and outside the image frame, the green video signal of the image frame is converted into a video image of the panel frame in which the area outside the image frame is a black image. Convert to signal.

  The DRAM controller 7 simultaneously reads out the video signal of the previous frame (for example, the fourth frame if the current frame is the fifth frame) simultaneously with the video signal of the current frame, and sends it to the overdrive processing circuit 8. Therefore, the DRAM controller 7 performs reading at substantially 4 times speed. In the figure, the red, blue and green video signals output from the DRAM controller 7 to the DRAM 6 are collectively shown as S15, and the red, blue and green video signals output from the DRAM 6 to the DRAM controller 7 are collectively shown as S16. The red, blue, and green video signals output from the DRAM controller 7 to the overdrive processing circuit 8 are shown as S17, S19, and S21, respectively.

  The overdrive processing circuit 8 performs an overdrive process for improving response characteristics of liquid crystal molecules when displaying a moving image. In this overdrive process, the actual signal level of the current frame and the drive amount of the previous frame (the drive level of the LCD device) are compared for each pixel of each RGB video signal as shown in FIG. The drive amount of the current frame is determined according to the difference between the two. Red, Blue, and Green video signals subjected to overdrive processing are sent from the overdrive processing circuit 8 to LCD devices (LCD devices 41, 42, and 40 in FIG. 1) in the rear projection television. In the figure, Red, Blue, and Green video signals output from the overdrive processing circuit 8 to the LCD device are shown as S18, S20, and S22, respectively.

  FIG. 10 is a diagram showing signal processing timings of Red, Blue, and Green video signals in the signal processing system of FIG. 3, and S1, S2,... Are the same video signals as shown in FIG. The numbers 0, 1, 2,... On the time axis are frame numbers.

  In the SRAM controllers 11, 12, and 13, a signal processing delay is caused by a time difference M between writing to the SRAMs 1, 2, and 3 and reading from the SRAMs 1, 2, and 3.

  In the figure, the data amounts stored in the SRAMs 1, 2, and 3 at the time difference M are shown as P, Q, and R, respectively. P and Q have the same data amount, but R is a data amount smaller than P and Q by the amount not subjected to the shift processing. The memory capacity required for the entire SRAM 1, 2, and 3 is the sum of P, Q, and R.

  Since the DRAM controller 7 performs double speed reading, the video signals S16, S17, and S18 take half the time per frame. As a liquid crystal panel drive system, a polarity inversion drive system that alternately repeats + (plus) drive and-(minus) drive using video signals in the same frame is adopted in order to balance the voltage applied to the liquid crystal. The In the figure, the video signal of the current frame (frame number 1) to be + driven is H1, the video signal of the current frame to be driven −J1, the video signal of the previous frame (frame number 0) to be + driven is H2, −. The video signal of the previous frame for driving is shown as J2.

  At this time, the maximum delay time of the current frame read from the DRAM 6 by the DRAM controller 7 with respect to the frame written in the DRAM 6 by the DRAM controller 7 has a magnitude indicated by K in the figure. Specifically, this K is the maximum delay time of the frame of frame number 1 indicated by J1 with respect to the frame of frame number 1 indicated by N.

  Further, the minimum delay time of the current frame read from the DRAM 6 by the DRAM controller 7 with respect to the frame written in the DRAM 6 by the DRAM controller 7 has a size indicated by L in the drawing. Specifically, L is the minimum delay time of the frame of frame number 1 indicated by H1 with respect to the frame of frame number 1 indicated by N. L must in principle be greater than zero.

  The maximum delay time of the previous frame read from the DRAM 6 by the DRAM controller 7 with respect to the frame written in the DRAM 6 by the DRAM controller 7 has a magnitude indicated by K ′ in the drawing. For this reason, the amount of data stored in the DRAM 6 is the portion indicated as S in the figure for the Red video signal. Specifically, the magnitude of S has already been written into the DRAM 6 at the right end of K ′ and all the frames of frame numbers 2 and 3 that are read for the next-drive, and at the right end of K ′. This is the sum of a part of the frame with frame number 4. Similarly for the blue and green video signals, the data amounts stored in the DRAM 6 are portions indicated by T and U in the figure, respectively. Accordingly, the memory capacity required for the DRAM 6 is the sum of S, T, and U.

  As described above, in the signal processing system of FIG. 3, the SRAMs 1, 2 and 3 as a whole need a memory capacity corresponding to the total of P, Q and R shown in FIG. In addition, a memory capacity corresponding to the sum of S, T, and U is required.

[Second Embodiment of Signal Processing System]
As described above, according to the signal processing system of FIG. 3, overdrive processing can be performed after performing registration correction by signal processing using an SRAM with good random accessibility.

  However, the SRAM has good random accessibility, but has a structure including six transistors per memory cell, as shown in FIG. 11, so that the area on the silicon chip in the LSI increases. There is. On the other hand, as shown in FIG. 12, the DRAM has a structure in which one memory cell includes one transistor and one capacitor, so that the area on the silicon chip is smaller than that of the SRAM. Generally, an SRAM has an area on a silicon chip that is about four times that of a DRAM. Since the area on the silicon chip directly affects the cost, the signal processing system of FIG. 3 has a large proportion of SRAM, which is disadvantageous in terms of cost.

  Therefore, a second embodiment of a signal processing system for registration correction in a rear projection television to which the present invention is applied will be described. FIG. 13 is a block diagram showing the second embodiment. Circuits common to the signal processing system of FIG.

  In this signal processing system, the SRAM 3 and the SRAM controller 13 shown in FIG. 3 are not provided. A DRAM 9 having a larger memory capacity than the DRAM 6 shown in FIG. 3 is provided as a DRAM controlled by the DRAM controller 7.

  Of the Red, Blue, and Green video signals input to the signal processing system, the processing for the Red and Blue video signals is the same as that in the signal processing system of FIG. (In FIG. 13, the codes themselves of the video signals are different from those in FIG. 3, such as S60, S61,...)

  The Green video signal input to the signal processing system is directly sent to the DRAM controller 7 and written into the DRAM 9 by the DRAM controller 7.

  The DRAM controller 7 reads out the green video signal from the DRAM 9 at a double speed (substantially at a quadruple speed by reading the previous frame at the same time) with a delay so as to match the signal processing delay amount by the SRAM controllers 11 and 12. . Then, as described above, the green video signal of the image frame is converted into the video signal of the panel frame in which the area outside the image frame is a black image, and sent to the overdrive processing circuit 8.

  Accordingly, the DRAM controller 7 outputs Red, Blue, and Green video signals S73, S75, and S77 having the same delay time to the overdrive processing circuit 8.

  FIG. 14 is a diagram showing signal processing timings of Red, Blue, and Green video signals in the signal processing system of FIG. 13 in the same manner as in FIG. 10, and S60, S61... Are the same video signals as shown in FIG. It is. Reference numerals M, P, Q, H1, J1, H2, J2, K, N, L, K ', S, and T denote the same as in FIG.

  The difference from the signal processing timing shown in FIG. 10 is as follows. Of the Red, Blue, and Green video signals S71 output from the DRAM controller 7 to the DRAM 9, the Red and Blue video signals are delayed by P and Q (P and Q are the same amount of data). The video signal is not delayed. However, by holding the Green video signal for a long time by the same delay as P or Q in the DRAM 9, the Red, Blue, and Green video signals S72 output from the DRAM 9 to the DRAM controller 7 are the Red video signal and Blue. The delay times of the video signal and the green video signal coincide with each other.

  In this way, in the signal processing system of FIG. 13, the delay times of the Red and Blue video signals and the Green video signal are different during the signal processing. However, since the red, blue, and green video signals do not depend on each other (processed independently of each other) during the signal processing, even if the delay time is different in the middle of the signal processing, it is delayed at the final output stage. As long as the times match, there is no problem in displaying the video.

  The amount of data stored in the DRAM 9 is the portion indicated as U 'in FIG. U ′ is obtained by adding the data amount corresponding to the same delay as P or Q to U shown in FIG. The DRAM 9 needs a memory capacity corresponding to the sum of S, T, and U ′ (that is, a capacity larger than the DRAM 6 in FIG. 3 by the data amount equivalent to the delay of P or Q).

  On the other hand, the memory capacity required for the entire SRAMs 1 and 2 is the sum of P and Q. Therefore, the memory capacity required for the entire SRAM is reduced by the amount that the SRAM 3 shown in FIG. 3 is not provided.

  As described above, in the signal processing system of FIG. 13, the delay generated in the SRAM 3 in the signal processing system of FIG. 3 is generated in the DRAM 9 without providing the SRAM 3. It is running low. This reduces the area of the SRAM on the silicon chip, which is advantageous in terms of cost. Further, since the SRAM 3 is not required because the SRAM 3 is not provided, the circuit scale can be reduced and the cost can be reduced in this respect.

  In addition, since the DRAM 9 is originally necessary for the double speed reading process as a pre-stage of overdrive, the use of the DRAM 9 for delay generation eliminates the need for introducing a new DRAM.

  Finally, FIG. 15 shows an example in which the signal processing system of FIG. 13 is mounted on an LSI (ASIC that is an application specific LSI) chip. The LSI chip 80 includes an SRAM 81, a logic 82, a CPU I / F 5, and a DRAM controller 7. The CPU I / F 5 and the DRAM controller 7 are the same as those shown in FIG. The DRAM 9 includes a capacitor in addition to the logic (transistor) as shown in FIG. 12, and is externally attached to the LSI chip 80 because the manufacturing process of the chip increases when mounted on the LSI chip.

  The SRAM 81 corresponds to a combination of the SRAM 1, SRAM 2, and SRAM 4 of FIG. The area of the SRAM 81 on the LSI chip 80 is reduced by an amount that does not require a portion corresponding to the SRAM 3 shown in FIG.

  The logic 82 corresponds to the SRAM controllers 11 and 12 and the overdrive processing circuit 9 in FIG. The circuit scale of the logic 82 is reduced by the amount that does not require the logic corresponding to the SRAM controller 13 shown in FIG.

  In the above embodiment, the present invention is applied to the rear projection television. However, the projection display device according to the present invention is not limited to the rear projection television, and may be applied to a front projection projector.

  In addition, the image processing apparatus and the image processing method according to the present invention distorts a red image and a blue image with respect to a green image by signal processing for purposes other than correcting registration deviation of a projection display device. May be used for

  In the above embodiment, the green image that occupies about 70% of the brightness of the image is not distorted, and the red image and the blue image are distorted with respect to the green image. In a use that does not pose a problem, a green image and a blue image may be distorted with respect to a red image, or a green image and a red image may be distorted with respect to a blue image.

It is a figure which shows the optical system of a rear projection television. It is a figure which shows the range which distorts an image by registration correction signal processing. It is a block diagram which shows 1st Embodiment of the signal processing system for registration correction | amendment. It is a figure which shows the content of the registration correction signal process. It is a figure which shows the content of the registration correction signal process. It is a figure which shows the content of the registration correction signal process. It is a figure which shows the distortion of the H direction between 4 pixels which adjoin, and a V direction. It is a figure which shows the linear interpolation calculation formula of control point data. It is a figure which shows an overdrive process. It is a figure which shows the signal processing timing of the video signal in the signal processing system of FIG. It is a figure which shows the memory cell structure of SRAM. It is a figure which shows the memory cell structure of DRAM. It is a block diagram which shows 2nd Embodiment of the signal processing system for registration correction | amendment. It is a figure which shows the signal processing timing of the video signal in the signal processing system of FIG. It is a figure which shows a mode that the signal processing system of FIG. 13 was mounted in LSI.

Explanation of symbols

  1 SRAM, 2 SRAM, 3 SRAM, 4 SRAM, 5 CPU I / F, 6 DRAM, 7 DRAM controller, 8 Overdrive processing circuit, 9 DRAM, 11 SRAM controller, 12 SRAM controller, 13 SRAM controller, 30 reflector, 31 Light source, 32 color separation dichroic mirror, 33 total reflection mirror, 34 color separation dichroic mirror, 35 total reflection mirror, 36 total reflection mirror, 40 LCD device, 41 LCD device, 42 LCD device, 43 relay lens, 44 relay lens, 45 Relay lens, 46 Cross dichroic prism, 47 Close-up lens, 48 Total reflection mirror, 49 screen

Claims (5)

Data on the shift amount of the pixel position for distorting any two of the first image and the second image of the red image, the blue image, and the green image with respect to the remaining one third image respectively. Means for supplying;
A static RAM for temporarily writing video signals of colors corresponding to the first and second images of the RGB video signals;
The video signals of the colors corresponding to the first and second images are respectively written in the static RAM, and at the time of reading, the value of each pixel is changed to the value of the pixel at the pixel position shifted based on the shift amount data. First and second static RAM controllers to be obtained using;
For the first, second and third images, the first and second static RAMs have a capacity larger than the capacity required for simultaneously reading out the current one-frame video signal and the previous one-frame video signal at double speed. A dynamic RAM having a capacity large by the amount of signal processing delay in the controller;
A video signal of a color corresponding to the first and second images read from the static RAM is sent to write the video signal to the dynamic RAM, and the third of the RGB video signals. The video signal of the color corresponding to the image is directly sent without being read and written in the static RAM, and the video signal is written to the dynamic RAM. The video signal of the color corresponding to the first and second images is currently The one-frame video signal and the one-frame previous video signal are simultaneously read at double speed, and the video signal of the color corresponding to the third image is subjected to signal processing delay in the first and second static RAM controllers. A dynamic RAM that reads the current video signal of one frame and the video signal of the previous frame at a double speed at the same time with a delay according to the amount. And a controller,
An overdrive processing circuit for overdriving video signals of colors corresponding to the first, second, and third images read from the dynamic RAM.
Image processing device. The image processing apparatus according to claim 1.
The third image is a green image
Image processing device. The image processing apparatus according to claim 1.
The shift amount data is obtained by distorting the first and second images in a direction opposite to the distortion based on the measurement result of the distortion of the first and second images with respect to the third image on the screen. The data is determined to be
Image processing device. Data on the shift amount of the pixel position for distorting any two of the first image and the second image of the red image, the blue image, and the green image with respect to the remaining one third image respectively. A first step of supplying;
Of the RGB video signals, video signals of colors corresponding to the first and second images are respectively written in the static RAM, and when reading from the static RAM, the value of each pixel is based on the shift amount data. A second step of obtaining using the pixel value of the pixel position shifted by
A video signal of a color corresponding to the first and second images read from the static RAM is converted into a current one-frame video signal and a previous one-frame video signal for the first, second, and third images, respectively. The video signal is written into the dynamic RAM having a capacity larger than the capacity required for simultaneously reading the video signal at a double speed by the signal processing delay amount in the first and second static RAM controllers, and the RGB video signal The video signal of the color corresponding to the third image is directly written into the dynamic RAM without reading / writing with the static RAM, and the video signal of the color corresponding to the first and second images is the current one frame. The video signal and the video signal of the previous frame are simultaneously read at a double speed, and the color video signal corresponding to the third image is Combined to the signal processing delay in the second step and delays, a third step of reading the video signal and the previous frame of the video signal of the current frame at the same time speed,
And a fourth step of overdriving the video signals of colors corresponding to the first, second and third images read from the dynamic RAM.
Image processing method. In a projection display device having three liquid crystal display devices that modulate red light, green light, and blue light according to the levels of RGB video signals,
Data on the shift amount of the pixel position for distorting any two of the first image and the second image of the red image, the blue image, and the green image with respect to the remaining one third image respectively. Means for supplying;
A static RAM for temporarily writing video signals of colors corresponding to the first and second images of the RGB video signals;
The video signals of the colors corresponding to the first and second images are respectively written in the static RAM, and at the time of reading, the value of each pixel is changed to the value of the pixel at the pixel position shifted based on the shift amount data. First and second static RAM controllers to be obtained using;
For the first, second and third images, the first and second static RAMs have a capacity larger than the capacity required for simultaneously reading out the current one-frame video signal and the previous one-frame video signal at double speed. A dynamic RAM having a capacity large by the amount of signal processing delay in the controller;
A video signal of a color corresponding to the first and second images read from the static RAM is sent to write the video signal to the dynamic RAM, and the third of the RGB video signals. The video signal of the color corresponding to the image is directly sent without being read and written in the static RAM, and the video signal is written to the dynamic RAM. The video signal of the color corresponding to the first and second images is currently The one-frame video signal and the one-frame previous video signal are simultaneously read at double speed, and the video signal of the color corresponding to the third image is subjected to signal processing delay in the first and second static RAM controllers. A dynamic RAM that reads the current video signal of one frame and the video signal of the previous frame at a double speed at the same time with a delay according to the amount. And a controller,
An overdrive processing circuit for overdriving video signals of colors corresponding to the first, second and third images read from the dynamic RAM;
The RGB video signal output from the overdrive processing circuit is sent to the liquid crystal display device.
Projection display device.

Images