JP5063709B2 - Reverse concatenated coding system, method, and computer program - Google Patents

Description

  The present invention relates generally to encoded data that is written to a recordable medium, and more particularly to performing reverse concatenation coding on product codes.

  Data storage systems such as tape drives and optical disks that use removable media and typically record large volumes of data rely on powerful error correction codes (ECC). Tape drives and CD devices use powerful, complex and efficient ECC based on code concatenation of outer C2 code and inner C1 code. The product code defined in the 3rd generation linear tape open (LTO-3) standard is a specific example of a concatenated coding scheme, where the internal code and Both outer codes are RS base codes of length 480 and length 64, respectively.

The sub-data set is a 64 × 480 array of bytes, ie contains 30,720 bytes, of which the data bytes are 54 × 468 = 24,272 and the code rate is 0.8227. Each of the 480 byte rows contains a codeword pair. More specifically, the outer C2 code is a [N ₂ = 64, K ₂ = 54, d ₂ = 11] RS code on the Galois field GF (256), where N ₂ represents the length and K ₂ is represents a dimension, d ₂ represents the minimum Hamming distance of the code. The inner C1 code is obtained by even / odd interleaving of [240,234,7] Reed-Solomon (RS) codes on GF (256).

  In magnetic and optical recording, modulation codes are used to enable timing recovery from the readback signal and to enable short path memories at the detector without substantial performance loss. Therefore, the ECC encoded data passes through the modulation encoder in the writing path before writing the ECC encoded data to the medium. Referring to FIG. 1, a method in which user data is first encoded in ECC 102 and then passed through a modulation encoder 104, such as a 16/17 run length limited (RLL) encoder, is a forward concatenation (FC). Known as architecture 100. In order to improve ECC performance, there is a long block interleaver 106 in the LTO-3 write path labeled Interleave and Track Allocation Block. This block 106 buffers 64 consecutive product sub-data sets, for a total of 64 × 64 = 4096 rows. These 4096 rows are allocated to 16 tracks 108 of the tape medium in a predetermined order. For each track, there is one rate 16/17 modulation encoder that encodes the assigned rows and guarantees the predetermined modulation constraints, namely global G = 13 and interleave I = 11 constraints.

In recent years, in the hard disk drive (HDD) industry, reverse link (RC) architecture has attracted attention. FIG. 2 is a block diagram of such an architecture 200. In the RC architecture 200, the order of the ECC encoder and modulation encoder is reversed, the data first passes through the modulation encoder 202, and the modulated data passes through the systematic encoder 204 for error correction code. ECC encoding is used. The ECC parity symbols are encoded using the second modulation encoder 206 as shown, or inserted at the bit level or symbol level into the data symbol stream. Inserting the entire parity symbol into the data symbol stream is called partial symbol interleaving. The method with parity insertion leads to a simple scheme without error propagation, but such a method may weaken the original modulation constraints. Nevertheless, there are three main advantages that make RC attractive. That is,
a) There is no error propagation through the modulation decoder.
b) Since error propagation is not a problem, the first modulation code can be made very long, allowing the use of high-capacity efficient high-speed modulation codes, which results in code rate gain.
c) In the readback path, the ECC decoding block is arranged immediately after the channel detection block, so that soft information can be passed from the detector to the decoder in bit units. This creates a suitable framework for using novel ECC technology that promises significant performance improvements based on turbo codes and LDPC codes. Furthermore, in this framework, a post-parity scheme can be easily implemented.

It would be desirable to provide the same benefits to a tape recording framework. However, the ECC used in the HDD has a different structure from the ECC used in tape recording. In HDDs, ECC is essentially based on a single high-speed Reed-Solomon (RS) code, whereas in tapes, large, powerful product codes that require a new RC architecture are used. RC has been proposed for a one-dimensional ECC architecture, and an ECC is typically composed of a single code, such as a Reed-Solomon code or an LDPC code. However, known RS schemes have not addressed the specific problems arising from ECC based on concatenated codes or product codes. In the case of a concatenated code or product code, the output of the inner C1 code is mapped to a track / channel, so all rows must satisfy a predetermined modulation constraint. Thus, the significant drawbacks presented for the LTO-3 product code are presented. Referring again to Table 1, by placing a modulation coder in front of the systematic ECC encoder, only K ₂ rows will satisfy the modulation restriction except for the C1 parity portion. The remaining N ₂ -K ₂ rows (rows 54-63) composed of C2 parity bytes do not satisfy the modulation constraints. Since the C1 parity part can be processed independently as in the case of the one-dimensional ECC, it is not a problem. However, no effective solution has yet been proposed for the C2 parity part. Thus, a significant number of rows do not satisfy the modulation constraint and require further processing. According to the one-dimensional RC method, these rows need to be passed through a second modulation encoder or handled using a parity insertion method. In both techniques, a) the second modulation code can lead to error propagation, making it impossible to pass soft information from the channel detector to the ECC decoder in bits, b) the entire defective row Partial symbol interleaving creates the undesirable feature of staying low performance in the case of dead tracks, because it is subdivided and spread to other rows, causing many errors in many rows.

  If the outer C2 encoder is interchangeable with the first modulation encoder, i.e. if the order of encoding does not matter, the above drawbacks may be avoided. However, this is not the case, and to date, no reverse link architecture for product code has been proposed.

  The preferred embodiment of the present invention provides a deconcatenated coding system for a recording write path. The system implements a first modulation constraint on each row of the first data array and means for generating a first data array of unencoded user data and includes modulation constraint data A first modulation encoder for generating a second data array. The system includes a formatter operable to process the second data array to generate a third data array by inserting a predetermined empty position in each column interleaved with the modulation constraint data. In addition. The C2 encoder is operable to calculate a C2 parity byte for each of a plurality of empty positions in each column of the third data array to generate a fourth data array. The C1 encoder is operable to calculate a C1 parity symbol for each row of the fourth data array and generate a fifth data array. The system includes a second modulation encoder operable to impose a second modulation constraint on each of the C1 parity symbols of the fifth data array and generate a sixth data array. In addition. The system further includes means for recording the rows of the sixth data array on the tracks of the recording medium.

  Another preferred embodiment of the present invention provides a method for encoding data to be recorded on a medium, generating a first data array of unencoded user data, Imposing a first modulation constraint on each row of the data array to generate a second data array including modulation constraint data; and each of the second data arrays interleaved with the modulation constraint data Formatting a second data array by inserting predetermined empty positions into a plurality of columns to generate a third data array; and a plurality of empty positions in each column of the third data array. A C2 parity byte is calculated for each to generate a fourth data array, and a C1 parity symbol is calculated for each row of the fourth data array to obtain a fifth data array. Generating a sixth data array, imposing a second modulation constraint on each of the C1 parity symbols of the fifth data array, and generating a sixth data array row, On a track of a recording medium.

  A further preferred embodiment of the invention is a computer program product of a computer readable medium usable on a programmable computer, storing computer readable code for encoding data to be recorded on the medium, The computer readable code imposes a first modulation constraint on each row of the first data array, instructions for generating a first data array that is uncoded user data, and modulation constraint data A second data array by inserting a predetermined empty position into each column of the second data array interleaved with modulation constraint data and instructions for generating a second data array comprising: For each instruction for formatting and generating a third data array, and each empty position in each column of the third data array, An instruction for calculating a C2 parity byte and generating a fourth data array; an instruction for calculating P C1 parity symbols in each row and generating a fifth data array; , Implement a second modulation constraint on each of the C1 parity symbols in each row, generate a sixth data array, and record the sixth data array row on a track of the recording medium And a computer program product including instructions for performing.

FIG. 2 is a block diagram of prior art data encoding using forward concatenation. 1 is a block diagram of prior art data encoding using reverse concatenation. FIG. It is a block diagram of a prior art LTO-3 write path. FIG. 3 is a high level block diagram of the reverse-coupled architecture of the present invention. FIG. 3 is a block diagram of a write path that can incorporate the reverse-coupled architecture of the present invention. FIG. 4 is a block diagram of a portion of a write path of one embodiment of the present invention. FIG. 3 is a more detailed block diagram of the reverse link architecture of the present invention. FIG. 4 is a diagram of a dataset array provided with empty positions by the formatter of the present invention. It is a functional diagram of the systematic 2nd modulation | alteration encoder of this invention. FIG. 3 is a diagram of a codeword quad structure according to data encoding according to the present invention. FIG. 6 is a block diagram of an alternative embodiment in which both unconstrained data bytes and parity bytes are inserted into empty positions provided by the formatter.

Architecture Overview FIG. 3 is a block diagram of a write path 300 according to the LTO-3 standard. The host record is compressed 302 and the data set and DSIT generator 304 generates a sub data set from the stream of symbols. The ECC encoder 306 performs ECC encoding and passes the encoded sub-data set to the codeword pair header and codeword quad generator 308. The resulting codeword quad is passed to the write formatter 310 where a 16 track bit stream is generated. The bit stream is processed in a data random number generator 312 and then modulation encoded 314. The RLL encoded bit stream is converted to a synchronized bit stream by synchronizing and formatting the pattern in the sync generation block 316, which passes through the write equalizer 318 and then onto the media. A bit stream that can be recorded.

  As shown in the high level schematic of FIG. 4, the present invention 400 provides a deconcatenated architecture where data is first passed through the serial / parallel block 401 to produce an uncoded array. Each row of the array is modulation encoded in a first modulation encoder 402 and then ECC is applied in an ECC encoder 404. Each row is processed by a second modulation encoder 406 or subjected to partial symbol interleaving (not shown) to meet the required modulation constraints.

  FIG. 5 is a block diagram of a write path 500 that can incorporate the reverse concatenation architecture of the present invention. Similar to the LTO-3 write path of FIG. 3, the host record in the write path 500 of the present invention is compressed 502 and the data set and DSIT generator 504 generates a sub-data set from the stream of symbols. The sub-data set is then randomized in a row-wise fashion in a data random number generator 506 and the randomized data is passed to a first row-wise modulation encoder 508. C2 and C1 ECC encoders 510 encode the modulation encoding sub-data sets, as described in more detail below. Second modulation encoder 512 applies further modulation encoding to the encoded sub-data set, after which the modulated data is processed by interleave and track allocation block 520. The resulting multi-track stream of C1 codewords and codeword headers is converted to a synchronization bit stream by synchronizing and formatting the pattern in synchronization generation block 514, and the synchronization bit stream is written It becomes a write stream that passes through the equalizer 516 and can be recorded on the medium 518.

  FIG. 6 is a block diagram of a portion of a write path according to an embodiment of the present invention, where an interleave and track allocation block 520 processes the sub-data set into a formatted row for LTO-3 tape media. . In this embodiment, the interleave and track allocation block 520 generates codeword pair headers and codeword quads where the modulation data from the second modulation encoder 512 is interleaved with the codeword header to form a codeword quad. Instrument 522. The interleave and track allocation block 520 further includes a write formatter 524 that maps codeword quads to logical tracks. The resulting 16-track bit stream is converted to a synchronized bit stream by synchronizing and formatting the pattern in the sync generation block 514, the synchronized bit stream passes through the write equalizer 516, This is a bit stream that can be recorded on tape 530. It will be appreciated that the present invention is not limited to combining C1 codewords and codeword headers in this way, but can be combined in other ways.

FIG. 7 is a more detailed block diagram of the RC architecture 600 of the present invention. Architecture 600 includes a set of fast modulation encoders 602 for each of the N ₂ rows receiving data from serial / parallel block 601 (collectively referred to herein as “modulation encoders 602”) and external A column-by-column C2 encoder 604. Architecture 600 further comprises a format block 606 that is inserted between modulation encoder 602 and C2 encoder 604. As described in more detail below, format block 606 performs a reorganization such that the size of the modulation encoded user data array is based on the length rather than the dimension of the outer code. After the C2 encoder 604 is an internal C1 encoder 608 for each row that generates a parity byte at the end of each row. The processing of the encoded rows is completed by a set of systematic modulation encoders 610. The data from the C2 encoder 604 and the data from the second set of modulation encoders 610 are then multiplexed within the multiplexer 612 to form a completed sub-data set.

Reorganization of user data If K ₂ is the dimension of C2, the uncoded user of the present invention is in contrast to the conventional encoding of a C2 code of length N ₂ where user data is organized in K ₂ rows. The data array consists of N ₂ rows generated by the serial / parallel block 601. An example of such an uncoded user data array is shown in Table II, which is a modification of the LTO-3 standard (Table I) sub-data set array.

Specifically, the array contains 520 more user bytes than a conventional LTO-3 subdata set. Each row of the uncoded user data array passes through a first modulation encoder 602 that imposes modulation constraints on the input of format block 606. At this point, the modulation user data array still contains N ₂ rows of modulation constraint data that has been lengthened several bytes by the first modulation encoder 602. In one embodiment, the first modulation encoder 602 may also derive from rate 215/216 interleaved Fibonacci modulation codes that satisfy the modulation constraints of global G = 14 and interleave I = 7 constraints. Each row contains 8 x 403 = 3224 data bytes, which has the following length:
214, 215, 215, 215, 215, 215, 215, 215, 215, 215, 215, 215, 215, 215, 215
Are grouped into 15 bit sequences. A dummy zero bit is prepended to the length 214 bit sequence, then all sequences are encoded, resulting in a 15 bit sequence, all of length 216, which is summed 405 bytes for each row. The first modulation code converts the uncoded user data array of Table II to the modulation constrained user data array of Table III.

  More generally, a code that supports partial interleaving of unconstrained symbols is selected as the first modulation code so that predetermined global G and interleave I constraints are satisfied after partial symbol interleaving.

Formatting block formatting block 606, the modulated user data array of Table III, is converted into each of the columns in the array having N ₂ -K ₂ pieces of empty component. The N ₂ -K ₂ empty positions are place-holding positions where the parity symbols generated by the C2 encoder 604 will be introduced. In the format block design phase, the parity pattern array is determined. Given a parity pattern array, format block 606 interleaves empty cells row by row into the modulated user data array of Table III, thereby extending the length of each row by L bytes. . This interleaving operation is similar to partial symbol interleaving and weakens the modulation constraint of the first modulation code. In the example described, inserting an 8-bit parity symbol into the array would weaken the global and interleave constraints to G = 22 and I = 11.

To determine the parity pattern array, the modulation user data array dimensions are: L is the number of C2 parity symbols per row, and M + L = K ₁ is the dimension of the C2 symbol based C1 code (ie, If the dimension of the C1 code must be expressed in C2 symbol units, eg, bytes, it must satisfy the Diophantine equation, ie, (M + L) × (N ₂ −K ₂ ) = N ₂ × L. Don't be. This Diophantine equation may require adjusting the parameters of the C1 code. In the above example based on LTO-3, M + L = K ₁ = 480 satisfies the equation when C2 parity byte position L = 75 for each row. Furthermore, the parity bytes must be separated by a predetermined minimum amount so as not to completely remove the modulation constraints of the first modulation code. In this example, an interval of at least 2 bytes is sufficient to obtain the (G, I) = (22,11) constraint. Since there are 64 rows in each parity pattern array, there are a total of 64 × 75 = 4800 C2 parity byte positions per parity pattern array. The insertion position is the following 10 linear equations (modulo 64) relating column number x to row number y:
y = x + c _i (mod 64)
Where c _i ε {0, 6, 13, 19, 26, 32, 38, 45, 51, 58}, 0 <x <480 = K ₁ . The parity pattern is preferably selected such that each column contains N ₂ −K ₂ = 10 parity positions and the pattern is repeated in as few columns as possible. In this example, the parity pattern repeats every 32nd column. This particular parity pattern array is shown in FIG. 8 where the plotted dots represent 10 empty parity insertion positions per column.

Column Dependent C2 Coding Since each column includes 10 parity location holding positions, each column can be encoded into a rate 54/64 RS C2 codeword. Furthermore, since the parity position varies from column to column, the C2 encoder also preferably varies from column to column.

The C2 code can be a Reed-Solomon code, but other codes may be used. Preferably, the code has the useful property that all sets of K ₂ components form a set of information is the maximum distance allowed content code (maximum-distance separable code). Thus, every pair of _{K 2} component, uniquely determines the remaining _N 2 -K ₂ parity symbols. At the input of C2 encoder 604, every column contains K ₂ modulated data bytes and N ₂ -K ₂ empty parity positions. In each column, C2 encoder 604 obtains the N ₂ -K ₂ parity bytes from the K ₂ pieces of modulated data bytes and inserts them into the empty parity position. The output of C2 encoder 604 is a C2 encoded array of size N ₂ × K ₁ as shown in Table IV. The C2 encoded array satisfies a predetermined modulation constraint along each row.

More generally, the C2 encoder is an encoder for a rate N ₂ / K ₂ Reed-Solomon code over a Galois field GF (2 ^m ), and in particular the codeword component is m bits Consisting of symbols.

C1 encoding The rows of the C2 encoding array then pass through the C1 encoder 608 for the C1 code. The resulting C1 parity symbol is processed by the second modulation encoder 610 as shown in FIG. 7, or the bits or bytes are partially interleaved in the data stream of the C1 encoder 608. Can do. In the above LTO-3 based example, a C1 code with dimension K ₁ = 480 and length N ₁ = 492 is an even / odd interleaved Reed-Solomon with dimension 240 on GF (256) and length 246 Obtained as a code. Such a code generates 2 × 6 = 12 interleaved RS parity bytes per row, which are appended to the end of each row as shown in Table V. Even parity bytes in a row are represented by asterisks, and odd parity bytes are represented by dots.

More generally, the C1 encoder can be derived from an even / odd interleaved Reed-Solomon code of dimension K ₁ on GF (2 ⁸ ), length N ₁ . The C1 encoder may be derived using a linear code on the Galois field GF (2 ^r ), ie an r-bit symbol, which has dimension mK ₁ on GF (2). Further, the C1 encoder may be derived from a low density parity check code on the Galois field GF (2 ^r ), which has a dimension mK ₁ on GF (2).

Final Modulation Coding FIG. 9 shows how to impose a (G, I) = (22,11) constraint throughout the appended C1 parity bytes, where 12 C1 parity bytes in each row are Preferably, it passes through a systematic second modulation encoder 610 that adds a single modulation bit to the beginning of each of the C1 parity bytes in each row. Modulation bit inverts the second bit p ₁ in each of the C1 parity bytes characterizing the secondary systematic encoder, it is preferred that obtained by adding it to the head of parity bytes. A simple second modulation encoder 610 can be an inverter with simple inversion, passing soft information bit by bit from the channel bit detector to the ECC decoder as the data is read. Enable. Further, the second modulation encoder 610 maintains G = 22 and I = 11 constraints. Other non-systematic modulation schemes may be used, such as by applying LTO-3 16/17 codes. However, in that case, the delivery of the software information is not performed in bit units.

  After the C1 / C2 encoded sub-data set is generated, a codeword quad is constructed by multiplexer 612 in a manner similar to the LTO-3 standard. As shown in FIG. 10, a C1 / C2 encoded sub-data set row 904A, such as the first row, is interleaved with an encoded header 906A to form a first codeword pair 902A, and a second Consecutive rows 904B of the C1 / C2 encoded sub-data set, such as, are interleaved with encoded header 906B to form a second codeword pair 902B. The two codeword pairs 902A and 902B constitute a codeword quad 900.

The proposed RC architecture features for concatenated codes are: (i) reorganization of user data into N ₂ rows, (ii) format blocks based on a predetermined C2 parity pattern, and (iii) column dependent C2 encoding. As a result, the present invention benefits from the features of the deconcatenation scheme described in the background art: elimination of error propagation in the demodulator, improved modulation code rate, and post-parity processor or turbo coding scheme. Implementation of a novel soft decoding technology based on the above can be achieved.

The RC architecture of the present invention adds 16 + 12 = 28 bits for modulation to each row. Each row contains 403 × 8 = 3224 data bits. Therefore, the rate of the RC modulation scheme is
R _RC = 3224/3252 = 0.9914
It is. A typical forward concatenation architecture is based on 16/17 codes. Therefore,
R _FC = 16/17 = 0.9412
It is. As a result, the RC architecture of the present invention has a 5.34% higher rate compared to the standard LTO-3 format, while maintaining the I = 11 constraint and reducing the G constraint from 13 to 22. . Furthermore, the RC architecture of the present invention can be extended to 10-bit ECC and longer C1 codes at the expense of weakening the modulation constraint to (G, I) = (24,12).

By selecting a longer C2 code that is essentially the same rate as the LTO-3 code, the performance of the C2 code can be improved. The present invention provides a second embodiment of a reverse concatenation (RC) scheme, where N ₂ represents the length, K ₂ represents the dimension, and d ₂ is the minimum Hamming distance of the C2 code. Then, it is based on a Reed-Solomon (RS) code having parameters [N ₂ = 96, K ₂ = 80, d ₂ = 17] on the Galois field GF (256). Since the RS code has a length of 96, the corresponding RC scheme utilizes an uncoded user data array with N ₂ = 96 rows. An example of such an uncoded user data array of size N ₂ × U = 96 × 398 with U = 398 uncoded user bytes per row is shown in Table VI.

Each row of the uncoded user data array passes through the first modulation encoder 602 and thus satisfies the modulation constraints at the input of the format block 606. In this second embodiment, the first modulation encoder 602 is similar to that used in the previous embodiment (having a length 64 C2 code), but with global G = 14 and interleaving. Derived from rate 199/200 interleaved Fibonacci codes with I = 7 constraints. The 8 × 398 = 3184 data bits in each row are grouped into 16 bit sequences, all of length 199. All 16 bit sequences are then modulation encoded to obtain 16 bit sequences all of length 200, for a total of M = 400 bytes per row. Thus, the first modulation code converts the uncoded user data array of Table VI into a modulated user data array of size N ₂ × M = 96 × 400 of Table VII.

Format block 606 converts the modulated user data array into an array with N ₂ −K ₂ = 16 “empty” components in each column. To satisfy Diophantine equation (M + L) × (N ₂ −K ₂ ) = N ₂ × L at M = 400, the number of C2 parity symbols per row must be L = 80, and the result As for the dimension of the C1 code expressed in C2 symbol base or byte, K ₁ = L + M = 480. Note that for a particular choice of C2 code parameters, the Diophantine equation is simplified to M = 5L. Since there are 96 rows in each parity pattern array, there are a total of 96 × 80 = 7680 C2 parity bytes per parity pattern array. The insertion positions of these 7680 C2 parity bytes are the following 16 linear equations (modulo 96) that relate column number x to row number y:
y = x + c _i (mod 96)
Where c _i = 6i, i = 0, 1, 2,. . . Is 15, is _{0 <x <480 = K 1} . At the input of C2 encoder 604, all _columns, and a and _N 2 _-K 2 = 16 pieces of empty parity position K 2 = 80 pieces of modulated data bytes. In each column, the C2 encoder 604 determines N ₂ −K ₂ = 16 parity bytes from K ₂ = 80 modulated data bytes and inserts them into empty parity positions. The output of C2 encoder 604 is a C2 encoded array of size N ₂ × K ₁ = 96 × 480 shown in Table VIII, where the position of the C2 parity byte is represented by “x”.

The C1 code is selected in the same way as the embodiment described above, ie it has dimension K ₁ = 480, length N ₁ = 492, dimension 240 on GF (256), length 246 Reed-Solomon code Is obtained by even / odd interleaving. The 12 parity bytes in each row pass through a simple systematic second modulation encoder 610 that adds a single bit to the beginning of each parity byte. The modulation bits are obtained by inverting the second bit in each parity byte and adding it to the beginning of the parity byte, which results in G = 22 and I = 11 constraints throughout all rows. It is.

In terms of implementation, the second embodiment based on a C2 code of length 96, dimension 80 has advantages over the first embodiment described above based on a C2 code of length 64, dimension 54, i.e.
(I) The first modulation encoder 602 of the second embodiment is based on rate 199/200 Fibonacci codes, the length of which is equal to the row length of the modulated user data array. Therefore, in the second embodiment, it is possible to apply the same Fibonacci encoder 16 times for each row.
(Ii) For the second embodiment, the parity pattern is repeated every six columns, so there may be at most six different C2 encoders 604, whereas for the first embodiment Column-dependent C2 encoding is simpler because the proposed parity pattern is repeated only every 32 columns.

  The present invention further provides a third embodiment of the RC architecture based on partial interleaving of a predetermined number of unconstrained data bytes, indicating the versatility of the empty positions generated by the format block 606. In the first two embodiments described above, the C2 encoder inserts a parity byte into the empty position. However, the empty position can be used in different ways, i.e. it can be filled with C2 parity bytes or it can be filled with unconstrained data bytes. FIG. 11 shows a block diagram of the RC architecture 1000 for the product code, where unconstrained data bytes are inserted into some of the empty positions provided by the formatter 606, and parity is added to the remaining empty positions. -A byte is inserted. Since the C2 encoder requires unconstrained data bytes for the calculation of parity bytes, these bytes are inserted before the C2 encoder. Unconstrained data bytes are generated by demultiplexer 1002. The demultiplexer 1002 bypasses the user data with one part processed by the first set of modulation encoders 602 and the first set of modulation encoders 602 before the C2 encoder 604. And the second part processed by the insertion block 1004.

The RC architecture of the third embodiment uses an RS code having parameters [N ₂ = 96, K ₂ = 81, d ₂ = 16] on the Galois field GF (256) as the C2 code, where , N ₂ represents the length, K ₂ represents the dimension, and d ₂ is the minimum Hamming distance of the C2 code. For each sub-data set, there are N ₂ × (U + D) = 96 × 399 = 38,304 bytes of user data, which is N ₂ × encoded by the first modulation encoder 602. U = 96 × 394 = 37,824 bytes and N ₂ × D = 96 × 5 = 480 bytes processed by the insertion block 1004 in front of the C2 encoder 604. Thus, the unencoded user data array has a size of N ₂ × U = 96 × 394. Each row of this array is encoded with a rate 197/200 interleaved Fibonacci modulation code with global G = 10 and interleave I = 5 constraints. Applying a rate 197/200 modulation encoder 16 times per row, each row of the uncoded sub-data set with 8 × 394 = 3152 bits is N ₂ × M = 96 × 400 in size. Maps to a row in the modulated user data array.

If T is the number of unconstrained data bytes per column inserted by the insert block 1004, then the format block 606 generates a modulated user data array with N ₂ −K ₂ + T in each column. Convert to an array with "empty" positions. It will be appreciated that if T = 1, there are 16 empty positions in each column, but T may be equal to some other number. One of these 16 empty positions will be filled with unconstrained data bytes and the remaining N ₂ -K ₂ empty positions will be filled with C2 parity bytes. In order to satisfy the Diophantine equation (M + L) × (N ₂ −K ₂ + T) = N ₂ × L with M = 400 and T = 1, the number of empty positions per row must be L = 80 Rather, the result is K ₁ = L + M = 480 for the dimension of the C1 code expressed in C2 symbol base or bytes. Since there are 96 rows in each parity pattern array, there are a total of 96 × 80 = 7680 empty positions per parity pattern array. The 7680 insertion positions are the following 16 linear equations (modulo 96) that relate column number x to row number y:
y = x + c _i (mod 96)
Where c _i = 6i, i = 0, 1, 2,. . . Is 15, is _{0 <x <480 = K 1} .

Unconstrained N ₂ × D = 96 × 5 = 480 = (M + L) × T data bytes are in 480 empty positions within the first 6 rows of the array, ie the additional condition 0 < Inserted at the location specified by the above equation according to y <6. In each column, exactly T = 1 unconstrained data bytes are inserted, leaving N ₂ −K ₂ = 15 empty positions filled with C2 parity bytes.

At the input of the C2 encoder 604, all columns include K ₂ = 81 modulated data bytes or unconstrained data bytes and N ₂ −K ₂ = 15 empty parity positions. In each column, the C2 encoder 604 determines N ₂ −K ₂ = 15 parity bytes from these K ₂ = 81 bytes and inserts them into empty parity positions. The output of C2 encoder 604 is a C2 encoded array of size N ₂ × K ₁ = 96 × 480 shown in Table IX, where the position of the C2 parity byte is represented by “p”, Previously inserted unconstrained data bytes are represented by “d”. Note that since the parity pattern repeats every six columns, there need only be at most six different column dependent C2 encoders 604. Insertion of parity bytes and unconstrained data bytes weakens I = 5 and G = 10 modulation constraints of the first modulation code to I = 9 and G = 18 along each row after C2 encoding .

The C1 code is selected in the same way as it was selected for the first and second embodiments described above. The C-1 code has dimension K ₁ = 480 and length N ₁ = 492, and is obtained by even / odd interleaving a Reed-Solomon code of dimension 240, length 246 on GF (256). The 12 parity bytes in each row pass through a simple systematic second modulation encoder ME2 610 that adds a single bit to the beginning of each parity byte. The modulation bits can be obtained by inverting the second bit in each parity byte and adding it to the beginning of the parity byte, so that I = 9 and G = 18 constraints throughout all rows. Is brought about.

  Although the present invention has been described with respect to a fully functional data processing system, those skilled in the art can distribute the process of the present invention in the form of computer-readable media consisting of instructions and in various forms. It is important to note that the invention is found to apply regardless of the specific type of signal support medium actually used in the distribution. Examples of computer readable media include recordable type media such as floppy disk, hard disk drive, RAM, and CD-ROM, and transmission type media such as digital and analog communication links. It is done.

  The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to practitioners skilled in this art. This embodiment best describes the principles and practical applications of the present invention, and other persons skilled in the art will recognize the present invention for various embodiments with various modifications adapted to the particular application considered. Was selected and described in order to be able to understand. Furthermore, although described above with respect to systems and methods, the need in the art can also be met by a computer program product that includes instructions for encoding data for recording on a medium.

Claims (21)

A reverse concatenated coding system for a recording write path,
A user data array generator operable to process input user data and generate a first data array;
A first modulation encoder operable to impose a first modulation constraint on each row of the first data array and generate a second data array including modulation constraint data;
Processing the second data array by inserting a predetermined empty position in each column of the second data array interleaved with the modulation constraint data to generate a third data array; A formatter that can be
A C2 encoder operable to calculate a C2 parity byte for each of a plurality of the empty locations in each column of the third data array to generate a fourth data array;
A C1 encoder operable to calculate a C1 parity symbol for each row of the fourth data array and generate a fifth data array;
A second modulation encoder operable to impose a second modulation constraint on each of the C1 parity symbols of the fifth data array to generate a sixth data array;
Means for recording a row of the sixth data array on a track of a recording medium;
Including
The formatter is configured such that the empty positions in the third data array are separated by a predetermined number of bytes, and the dimensions of the second data array and the third data array are Diophantine equations. A system further operable to process the second data array to fill.   The system of claim 1, wherein the C2 encoder is operable to calculate a C2 parity byte for each empty position in each column of the third data array. A demultiplexer operable to generate a plurality of unconstrained data bytes;
Inserting the unconstrained data byte into at least one of the empty positions in each column of the third data array, and calculating the calculated C2 parity byte to each of the third data array; An insertion block operable to insert into the remaining empty positions in a row of
The system of claim 1, further comprising: The formatter has a Diophantine equation (M + L) × (N2−K2 + 1) = N2 × L where the third data array is satisfied by M + L = K1 = 480, L = 80, and N2−K2 = 15. Determine the empty position to satisfy,
The empty positions are separated by a predetermined minimum amount which is at least 2;
x and y are the column number and row number of the third data array, respectively, and ci = 6i, i = 0, 1, 2,. . . 15 and 0 <x <480 = K1, the empty position is specified by y = x + ci (mod 96).
The system according to claim 3. The Diophantine equation is (M + L) × (N2−K2) = N2 × L,
M is the number of columns in the second data array, L is the range in which the number of rows in the second data array is expanded during processing of the second data array by the formatter, and K1 is the If the number of columns in the third data array is M + L = K1,
If N2 is the number of rows in the second data array and K2 is the dimension of the C2 code of the C2 encoder, N2-K2 is a predetermined number of bytes separating the empty position in the third data array. The number of
The system of claim 1. The Diophantine equation is satisfied by M + L = K1 = 480, L = 75, N2 = 64, and N2-K2 = 10,
The predetermined number of bytes from which the empty position of the third data array is separated is at least two;
x and y are respectively the column number and row number of the third data array, ciε {0, 6, 13, 19, 26, 32, 38, 45, 51, 58}, 0 <x <480 = K1 Then, the empty position of the third data array is specified by y = x + ci (mod 64).
The system according to claim 5. The Diophantine equation is satisfied by M + L = K1 = 480, L = 80, and N2-K2 = 16,
The predetermined number of bytes from which the empty position of the third data array is separated is at least two;
x and y are the column number and row number of the third data array, ci = 6i, i = 0, 1, 2,. . . 15, 0 <x <480 = K1, the empty position of the third data array is specified by y = x + ci (mod 96).
The system according to claim 5.   The first modulation encoder is derived from a modulation code that supports partial symbol interleaving to satisfy predetermined global G and interleave I modulation constraints after partial symbol interleaving. system.   The first modulation encoder is derived from a rate 215/216 interleaved Fibonacci modulation code that satisfies modulation constraints of global G = 14 and interleave I = 7 constraints prior to partial symbol interleaving. The system described in.   Moreover, the first modulation encoder is derived from a rate 199/200 interleaved Fibonacci modulation code that satisfies a modulation constraint of global G = 14 and interleave I = 7 constraints prior to partial symbol interleaving. The system according to 1.   2. The first modulation encoder is derived from a rate 197/200 interleaved Fibonacci modulation code that satisfies a modulation constraint of global G = 10 and interleave I = 5 constraints prior to partial symbol interleaving. The system described in. If N2 is the number of rows in the second data array and K2 is the dimension of the C2 code of the C2 encoder, the C2 encoder reads the rate K2 / N2 on the Galois field GF ( 2 ^m ). The system of claim 1 including a Solomon encoder, wherein the codeword component is an m-bit symbol. When K1 is the number of columns in the third data array and N1 is the length of the C1 code of the C1 encoder, the C1 encoder has a dimension K1 on the Galois field GF ( 2 ⁸ ), a length N1. 13. The system of claim 12, comprising an encoder for a plurality of even / odd interleaved Reed-Solomon codes. Where K1 is the number of columns in the third data array and N1 is the length of the C1 code, the C1 encoder generates N1-K1 interleaved Reed-Solomon parity symbols;
The C1 encoder appends the parity symbols to the end of each row;
The system of claim 12. The C1 encoder is derived from a linear code on a Galois field GF ( 2 ^r ), the linear code has a dimension mK1 on GF (2), and the codeword component is an r-bit symbol. Item 4. The system according to Item 1. The C1 encoder is derived from the low-density parity check code over Galois field GF (2 ^r), the low-density parity check code has dimensions mK1 on GF (2), according to claim 1 System.   The system of claim 1, wherein the second modulation encoder comprises a systematic modulation encoder.   The second modulation encoder includes an inverter for inverting the second bit of each C1 parity symbol and adding the inverted bit to the beginning of the C1 parity symbol. Item 18. The system according to Item 17. A codeword pair header and codeword quad generator operable to generate a codeword quad by interleaving a codeword header in the rows of the sixth data array;
A write formatter operable to map the codeword quad to a logical track of the recording medium;
The system of claim 1, further comprising: A method for encoding data to be recorded on a medium,
Generating a first data array of unencoded user data;
Imposing a first modulation constraint on each row of the first data array to generate a second data array including modulation constraint data;
Formatting the second data array by inserting a predetermined empty position in each column of the second data array interleaved with the modulation constraint data to generate a third data array; When,
Calculating a C2 parity byte for each of the plurality of empty locations in each column of the third data array to generate a fourth data array;
Calculating a C1 parity symbol for each row of the fourth data array to generate a fifth data array;
Imposing a second modulation constraint on each of the C1 parity symbols of the fifth data array to generate a sixth data array;
Recording a row of the sixth data array on a track of a recording medium,
Determining the empty positions so that the empty positions are separated by a predetermined number of bytes, and the respective dimensions of the second data array and the third data array satisfy the Diophantine equation. Further comprising a method. In order to encode the data to be recorded on the medium,
Instructions for generating a first data array that is a first array of unencoded user data;
Instructions for imposing a first modulation constraint on each row of the first data array and generating a second data array including modulation constraint data;
Formatting the second data array by inserting a predetermined empty position in each column of the second data array interleaved with the modulation constraint data to generate a third data array And the empty position is separated by a predetermined number of bytes, and the empty data is such that each dimension of the second data array and the third data array satisfies the Diophantine equation. An instruction further comprising determining a position;
An instruction to calculate a C2 parity byte for each of the empty positions in each column of the third data array to generate a fourth data array;
Instructions for calculating P C1 parity symbols in each row to generate a fifth data array;
Instructions for implementing a second modulation constraint on each of the C1 parity symbols in each row to generate a sixth data array;
Instructions for recording a row of the sixth data array on a track of a recording medium;
A computer program that runs

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