JP5062758B2 - Storage system and semiconductor storage device used therefor - Google Patents

Description

  The present invention relates to a storage system and a semiconductor storage device used therefor, and more particularly to a technique that can withstand long-term data storage.

  With the rapid development of information communication technology in recent years, services that provide multimedia contents including large amounts of data are becoming popular. As one form of providing such multimedia content, there is a form called “digital cinema” in which shooting and screening is performed using digital information in place of the conventional film business that performs shooting and screening using film. Proposed. For such digital cinema, standardization organizations such as the Digital Cinema Initiative and LLC (Limited Liability Company) have been established.

  In this digital cinema, it is assumed that the video is digitized at the time of shooting and edited, and distributed at the time of screening to each movie theater. By using digital data in this way, it is possible to prevent image deterioration due to aging of the film or mechanical damage due to screening.

  By the way, ideally, movie contents that are also valuable as cultural assets are required to be stored permanently. In a conventional film movie, for example, the quality of movie content itself has been maintained by re-baking the film every year.

  On the other hand, digital information is stored and stored in various recording media such as a magnetic tape, a magnetic disk, an optical disk, a magneto-optical disk, and a flash memory, and such a recording medium itself has a lifetime. For example, an optical disk such as a CD (Compact Disc) or a DVD (Digital Versatile Disc) is said to have a lifetime of several tens of years because a recording layer formed of aluminum or the like corrodes due to the intrusion of air. It has been broken. In addition, in recording media that store data using magnetism, such as magnetic tape and magnetic disks (for example, hard disks and flexible disks), the magnetism itself decays naturally over time, and the influence of magnetic fields from the outside world It is practically difficult to retain data storage for a long time. In addition, even in recording media that use data such as flash memory to store data, the charge itself decays naturally over time and is easily affected by the electric field from the outside. It is virtually difficult to do.

  As described above, it is practically impossible to hold data for a long period of time with these currently used recording media, and re-duplication processing is required every predetermined period as in the case of a conventional film.

Therefore, a semiconductor storage device such as a mask ROM (Read Only Memory) can be considered as a recording medium having a longer life. Since such a semiconductor memory device is made of physically and chemically stable silicon, it is hardly affected by corrosion or the like. For example, Japanese Patent Laying-Open No. 2006-237454 (Patent Document 1) discloses the configuration and manufacturing method of such a mask ROM.
JP 2006-237454 A

  The semiconductor memory device as described above forms an electric circuit using a silicon layer and a metal layer containing a small amount of impurities, and information (digital data) is obtained based on the amount of current flowing through the electric circuit and the presence or absence of the current. Remember. That is, reading information from the semiconductor memory device means that an electrical signal corresponding to the information stored therein is output from the semiconductor memory device. Therefore, in the semiconductor memory device, a metal input / output unit called a pad unit is formed as an interface for reading information.

  However, since the normal pad portion is exposed to the atmosphere, the circuit formed in the semiconductor memory device may be corroded through the pad portion. In addition, even if corrosion can be suppressed by filling the pad part with resin or maintaining it under inert gas or vacuum environment, to the metal terminal that contacts the pad part to read information, Corrosion and wear problems can occur. That is, the problem of corrosion and wear cannot be avoided as long as information is read out by a contact method. For this reason, it is difficult to permanently store information in the semiconductor memory device.

  SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a storage system that has a longer life than a conventional semiconductor memory device and a semiconductor memory device used therefor. That is.

  According to an aspect of the present invention, a storage system including a plurality of semiconductor storage devices and a data reading device is provided. The plurality of semiconductor memory devices are arranged close to each other according to a predetermined rule. Each of the plurality of semiconductor storage devices includes a light transmissive substrate, a power generation unit that receives light transmitted through the substrate and generates power, and a nonvolatile storage unit that is disposed on the substrate and stores data in a nonvolatile manner A communication unit that is disposed on the substrate and that receives power from the power generation unit and wirelessly transmits data stored in the nonvolatile storage unit to a semiconductor storage device adjacent to the device, a power generation unit, and a nonvolatile storage And a sealing film that covers the exposed surface of the communication unit. The data reading device is provided in proximity to at least one of the light irradiating unit for irradiating light to the plurality of semiconductor storage devices and the plurality of semiconductor storage devices arranged in proximity to each other, and transmits the data wirelessly transmitted by the semiconductor storage device And a reading unit for receiving.

  Preferably, the communication unit transfers data received from the semiconductor memory device adjacent to the own device to another semiconductor memory device adjacent to the own device.

  More preferably, the communication unit transmits the data stored in the non-volatile storage unit to the transfer destination after transferring the data received from the semiconductor storage device adjacent to the communication unit.

  More preferably, the substrate has a substantially disk shape, and the communication unit is connected to a receiving unit for receiving data from a semiconductor memory device adjacent to the own device and another semiconductor memory device adjacent to the own device. A transmission unit for transmitting data, and the reception unit and the transmission unit are formed on a substantially disk-shaped substrate and separated from each other by a predetermined circumferential angle, and a plurality of semiconductor memory devices The circumferential centers are arranged on the same straight line, and one receiving unit and the other transmitting unit are arranged close to each other between adjacent semiconductor memory devices.

  Preferably, the plurality of semiconductor memory devices are arranged so that each semiconductor memory device is close to the plurality of semiconductor memory devices, and the communication unit transmits and receives data to and from the semiconductor memory device adjacent to the semiconductor memory device. A plurality of transmission / reception units capable of reception are included, and each of the transmission / reception units establishes an ad hoc network with a semiconductor memory device adjacent to the own device.

Preferably, the sealing film is a silicon dioxide film.
According to another aspect of the present invention, there is provided a semiconductor memory device used in a memory system including a plurality of semiconductor memory devices arranged in close proximity according to a predetermined rule. A semiconductor storage device includes a light-transmitting substrate, a power generation unit that generates light by receiving light transmitted through the substrate, a nonvolatile storage unit that is disposed on the substrate and stores data in a nonvolatile manner, A communication unit that receives power from the power generation unit and wirelessly transmits data stored in the non-volatile storage unit to a semiconductor storage device adjacent to the device, a power generation unit, a non-volatile storage unit, and a communication unit And a sealing film covering the exposed surface.

  According to still another aspect of the present invention, a storage system including a plurality of semiconductor storage devices and a data reading device is provided. The plurality of semiconductor memory devices are arranged in close proximity according to a predetermined rule. Each of the plurality of semiconductor memory devices receives a substrate, a non-volatile memory unit that is disposed on the substrate and stores data in a non-volatile manner, and energy that is disposed on the substrate and is supplied in a non-contact state from the outside. A power generation unit that generates internal power, a communication unit that is disposed on the substrate and that can receive and transmit data using a wireless signal between the semiconductor storage device and the semiconductor storage device adjacent to the device, and the power generation unit , A non-volatile memory part, and a sealing film covering the exposed surface of the communication part. When the communication unit receives data from the semiconductor memory device adjacent to the own device, the communication unit transfers the received data to another semiconductor memory device adjacent to the own device. The data reading device includes a reading unit that is provided in proximity to at least one of the plurality of semiconductor memory devices arranged in proximity and receives data transferred by the semiconductor memory device.

  Preferably, the communication unit transmits the data received from the semiconductor storage device adjacent to the own device, and then transmits the data stored in the nonvolatile storage unit to the transfer destination.

  Preferably, the plurality of semiconductor memory devices are arranged so that each semiconductor memory device is close to the plurality of semiconductor memory devices, and the communication unit transmits and receives data to and from the semiconductor memory device adjacent to the semiconductor memory device. A plurality of transmission / reception units capable of reception are included, and each of the transmission / reception units establishes an ad hoc network with a semiconductor memory device adjacent to the own device.

  Preferably, the substrate is a light-transmitting substrate, the power generation unit is a solar cell that generates power by receiving light transmitted through the substrate, and the data reading device irradiates light to a plurality of semiconductor memory devices. A light irradiating unit to be further included.

  Preferably, the data reading device further includes a magnetic flux supply unit that supplies an alternating magnetic flux to the plurality of semiconductor memory devices, and the power generation unit includes a coil formed at a position interlinking with the alternating magnetic flux, and the coil is an alternating magnetic flux. And a power supply circuit that generates internal power from electromotive force generated by linking.

  According to still another aspect of the present invention, there is provided a semiconductor memory device used in a memory system including a plurality of semiconductor memory devices arranged close to each other according to a predetermined rule. A semiconductor storage device is disposed on a substrate, a nonvolatile storage unit that stores data in a non-volatile manner, and is disposed on the substrate to generate internal power by receiving energy supplied in a non-contact state from the outside. A power generating unit, a communication unit arranged on the substrate and receiving internal power and capable of transmitting and receiving data using a wireless signal between the semiconductor memory device adjacent to the device, a power generating unit, and a non-volatile memory And a sealing film that covers the exposed surface of the communication unit. When the communication unit receives data from the semiconductor memory device adjacent to the own device, the communication unit transfers the received data to another semiconductor memory device adjacent to the own device.

  According to the present invention, it is possible to realize a storage system and a semiconductor storage device used therefor that have a longer life than a conventional semiconductor storage device.

  Embodiments of the present invention will be described in detail with reference to the drawings. Note that the same or corresponding parts in the drawings are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is an external view of a storage system 300 according to the first embodiment of the present invention.

  Referring to FIG. 1, storage system 300 according to the present embodiment functions as a kind of data storage device. Specifically, a plurality of insertion openings 300a are formed on the side surface of the storage system 300, and a plurality of semiconductor storage devices 100 can be received. Then, the storage system 300 reads out necessary information from these semiconductor storage devices 100 and outputs it to an external device (not shown). Note that the number of semiconductor memory devices 100 that can be received by the storage system 300 is appropriately designed according to the data speed to be read at one time, the amount of data to be stored, and the like.

  As a typical application example, each of semiconductor storage devices 100 according to the present embodiment is used as a storage medium for storing data that is also valuable as a cultural asset such as a picture or a movie. Since any semiconductor storage device 100 can be inserted into the storage system 300, only a necessary one of the multiple semiconductor storage devices 100 may be inserted into the storage system 300.

  As will be described later, data read from each of the semiconductor storage devices 100 inserted into the storage system 300 is transmitted to the storage system 300 side by radio signals.

  FIG. 2 is a schematic diagram showing a schematic cross-sectional structure of the storage system 300 shown in FIG. FIG. 2 shows a configuration in which only three insertion ports are formed for the sake of simplification, but actually, a necessary configuration is appropriately provided according to the number of insertion ports.

  With reference to FIG. 2, the storage system 300 includes a control unit 10, a plurality of light irradiation units 20, a plurality of reception units 30, and an interface unit 12. In the storage system 300, a plurality of insertion openings for inserting the semiconductor storage device 100 are formed in the side surface portion. A light irradiation unit 20 and a reception unit 30 are disposed on the lower surface side and the upper surface side of each insertion port, respectively.

  Each of the light irradiation units 20 is an energy supply unit that supplies energy to the corresponding semiconductor memory device 100 in a non-contact manner, and typically includes a light source device such as an LED (Light Emitting Diode). More specifically, each of the light irradiation units 20 receives light from a power supply unit (not shown) to generate light, and irradiates the generated light toward the semiconductor memory device 100 from the lower side of the drawing. Each of the receiving units 30 receives data transmitted by the corresponding semiconductor storage device 100 receiving light from the light irradiation unit 20, and outputs the received data to the control unit 10. The control unit 10 includes a CPU, a RAM (Random Access Memory), and the like. The control unit 10 receives data output from each receiving unit 30 and executes predetermined processing. The interface unit 12 is a part for outputting read data generated after predetermined processing is performed by the control unit 10 to an external device (not shown), and typically includes an Ethernet (registered trademark), a USB (Universal Serial). Bus), IEEE (Institute of Electrical and Electronic Engineers) 1394, SCSI (Small Computer System Interface), RS-232C, wired interface such as wireless LAN (Local Area Network) and Bluetooth (registered trademark).

FIG. 3 is a schematic diagram of semiconductor memory device 100 according to the first embodiment of the present invention.
Referring to FIG. 3, semiconductor memory device 100 has a plurality of memory cells 120 formed on substrate 102. The substrate 102 is made of a physicochemically stable insulator such as silicon or glass. In the present embodiment, a structure typically made of light-transmitting glass is exemplified. Furthermore, the exposed surfaces of the plurality of memory cells 120 are entirely covered with a sealing film. This sealing film is typically made of a physicochemically stable insulator such as a silicon dioxide film.

  Each storage cell 120 stores data in advance, and receives energy from the outside of the semiconductor storage device 100 in a non-contact state and sequentially transmits (responds) the stored data as a radio signal, as will be described later. . Note that FIG. 3 shows a schematic diagram in which each memory cell 120 is partitioned in order to more clearly show a configuration in which a plurality of memory cells 120 are formed. However, the memory cells 120 need not be clearly partitioned. There is no.

  FIG. 4 is a block diagram showing functional configurations of semiconductor memory device 100 and receiving unit 30 according to the first embodiment of the present invention.

  Referring to FIG. 4, each of memory cells 120 configuring semiconductor memory device 100 includes a solar cell 50, a control circuit 60, a mask ROM 70, a transmission circuit 80, and an antenna 90.

  The solar cell 50 is formed on the substrate 102 (FIG. 3) side, receives the light irradiated from the light irradiation unit 20 and transmitted through the substrate 102 (FIG. 3), and generates internal power. The solar cell 50 supplies the generated internal power to the control circuit 60 and the transmission circuit 80.

  When power supply from the solar cell 50 is started, the control circuit 60 reads data from the mask ROM 70 at a predetermined cycle and outputs the data to the transmission circuit 80. In particular, the control circuit 60 includes a counter circuit 60a. When the internal power is supplied from the solar cell 50, the counter circuit 60a resets the count value and starts counting up at a predetermined cycle. The control circuit 60 reads data by sequentially designating predetermined addresses (addresses) of the mask ROM 70 according to the counted up count value. When reading of all the addresses in the mask ROM 70 is completed, the control circuit 60 repeats data reading from the first address in the mask ROM 70. That is, as long as power is supplied from the solar cell 50, the control circuit 60 cyclically repeats data reading from the mask ROM 70.

  The mask ROM 70 is a nonvolatile storage unit that stores data in a nonvolatile manner by forming a circuit pattern corresponding to the data to be stored. The mask ROM 70 is typically formed by creating a circuit pattern according to data in advance and transferring the circuit pattern to a substrate using a stepper or the like.

  Instead of the mask ROM 70, a PROM (Programmable Read Only Memory) that can be programmed afterwards may be used. As such a PROM, a laser PROM, a fuse-type PROM, or the like that can store data by irradiating a laser from the outside of the semiconductor memory device 100 to form a circuit corresponding to necessary data is known. Moreover, you may use PROM as disclosed by the Japanese translations of PCT publication No. 2005-504434.

  The transmission circuit 80 receives electric power from the solar battery 50 and generates a modulation signal corresponding to data read from the mask ROM 70 by the control circuit 60. Then, the transmission circuit 80 excites the antenna 90 with this modulated signal.

  The antenna 90 is typically formed of a metal wiring formed in a loop shape on the substrate, and receives a modulation signal from the transmission circuit 80 and transmits a radio signal. Since semiconductor memory device 100 according to the present embodiment includes a plurality of memory cells 120, the carrier frequency of the radio signal transmitted from each memory cell 120 is different so that the radio signal transmitted from each memory cell 120 can be identified. An antenna 90 is formed. Specifically, each antenna 90 has a variable impedance value by adjusting a wiring length, a wiring width, a distance between adjacent wirings, and the like constituting the antenna 90. By making this impedance value variable, Each tuning frequency is formed to be different. Thereby, the frequency of the radio signal transmitted from each storage cell 120 can be identified from each other.

  On the other hand, the receiving unit 30 of the storage system 300 includes a plurality of receiving cells 310 so as to correspond to the storage cells 120 of the semiconductor storage device 100. Each of the reception cells 310 receives a radio signal transmitted from the corresponding storage cell 120 of the semiconductor memory device 100, decodes this radio signal into data, and outputs the data to the control unit 10 (FIG. 2).

  Each of the reception cells 310 includes an antenna 30a and a reception circuit 30b. The antenna 30a is configured to match the antenna 90 of the corresponding storage cell 120. Therefore, each of the antennas 30a can selectively receive a radio signal transmitted from the antenna 90 of the corresponding storage cell 120. That is, only a radio signal having a specific frequency is given to the receiving circuit 30b. The receiving circuit 30b performs a predetermined decoding process on the voltage signal induced when the connected antenna 30a receives a radio signal. The receiving circuit 30b sequentially outputs the data obtained by this decoding process. Hereinafter, data sequentially output from each receiving circuit 30b is also referred to as a data string Ch1, Ch2,.

  FIG. 5 is a schematic diagram showing a cross-sectional structure of semiconductor memory device 100 according to the first embodiment of the present invention.

  Referring to FIG. 5, semiconductor memory device 100 includes substrate 102, antireflection film 122, n-type semiconductor layer 124, p-type semiconductor layer 126, p + impurity semiconductor layer 128, electrode layer 130, and through. The holes 132, 134, 136 and 138 and the insulating films 140 and 150 are formed.

  Specifically, the n-type semiconductor layer 124 is formed in a predetermined region on the substrate 102 made of light-transmitting glass containing silicon dioxide as a main component. The n-type semiconductor layer 124 is obtained by doping silicon or germanium with an n-type impurity. An antireflection film 122 is formed on the lower layer side of the n-type semiconductor layer 124. A p-type semiconductor layer 126 is formed on the upper layer side of the n-type semiconductor layer 124. Further, a p + impurity semiconductor layer 128 is formed on the upper layer side of the p-type semiconductor layer 126. That is, the n-type semiconductor layer 124, the p-type semiconductor layer 126, and the p + impurity semiconductor layer 128 constitute a pn junction solar cell. The light irradiated from the light irradiation unit 20 (FIG. 2) located on the lower side of the semiconductor memory device 100 passes through the substrate 102 and then is irradiated to the n-type semiconductor layer 124 through the antireflection film 122. This light excites electrons in the n-type semiconductor layer 124, and an electromotive force is generated between the n-type semiconductor layer 124 and the p + impurity semiconductor layer 128 according to the amount of irradiation light. Electric power is supplied to each circuit by this electromotive force.

  On the upper layer side of the solar cell, a control circuit 60, a mask ROM 70, a transmission circuit 80, and an antenna 90 are formed. Part of the electric power generated in this solar cell passes through a through hole 138 connected to the n-type semiconductor layer 124 and a through hole 134 connected to the electrode layer 130 disposed on the upper layer side of the p + impurity semiconductor layer 128. Via the control circuit 60. In addition, a part of the electric power generated in the solar cell is supplied to the transmission circuit 80 through the through hole 136 connected to the n-type semiconductor layer 124 and the through hole 132 connected to the electrode layer 130.

  An insulating layer 140 is formed between the solar cell of the memory cell 120 and the solar cell of the adjacent memory cell, and the respective memory cells are maintained in an electrically insulated state.

  Further, the surface of the semiconductor memory device 100 is sealed with an insulating film 150. That is, the surface of the semiconductor memory device 100 is covered with the insulating film 150 over the entire surface, so that intrusion of outside air is blocked. This insulating film 150 is typically made of physicochemically stable glass or silicon dioxide.

  Regarding the correspondence relationship between the configuration shown in FIGS. 1 to 5 and the present invention, the substrate 102 corresponds to the “substrate”, the mask ROM 70 corresponds to the “nonvolatile storage portion”, and the solar cell 50 corresponds to the “power generation portion”. , The transmission circuit 80 corresponds to the “transmission unit”, the insulating film 150 corresponds to the “sealing film”, the light irradiation unit 20 corresponds to the “energy supply unit”, and the reception unit 30 corresponds to the “reception unit” ".

  FIG. 6 is a diagram for describing an example of data read from semiconductor memory device 100 according to the first embodiment of the present invention.

  Referring to FIG. 6, in each memory cell 120 of semiconductor memory device 100, when light irradiation is started from light irradiation unit 20 (FIG. 2), counter circuit 60a included in its control circuit 60 resets the counter value. Then, data reading is sequentially started from the head address of the corresponding mask ROM 70. As a result, data is sequentially read from each memory cell 120 from the head address of the corresponding mask ROM 70. That is, in any memory cell 120, the data at the next address ADD1 is read after the data at the address ADD0 of the corresponding mask ROM is read, and then the data is read in the same procedure.

  FIG. 7 is a functional block diagram showing an example of a control structure in receiving unit 30 of storage system 300 according to the first embodiment of the present invention.

  The control structure shown in FIG. 7 is a configuration for reading the stored data when the information (data string) to be stored is assigned to each storage cell 120 of the semiconductor memory device 100 in the order of addresses. The receiving unit 30 includes a parallel / serial conversion unit 31, an error correction circuit 32, and a decoding circuit 33 as its functions.

  The parallel / serial conversion unit 31 is a part for serially outputting a data string (Ch1, Ch2,...) Output in parallel (parallel) from each memory cell 120 as one-dimensional data. That is, the parallel / serial converter 31 outputs a data string in the order of the first data of Ch1, the first data of Ch2,..., The second data of Ch1, the second data of Ch2. The error correction circuit 32 performs a predetermined error correction process on the data string output from the parallel / serial converter 31. As such an error correction method, an error correction method called LDPC (Low Density Parity Check) can be used. In order to perform such error correction, it is necessary to determine data to be stored in each mask ROM 70 of the storage cell 120 in advance with an error correction code added to the data to be stored in the semiconductor memory device 100. There is. Note that by adding such an error correction code, reliable data reading can be realized even if a failure or the like occurs in a part of the configuration for transmitting and receiving wireless signals.

  FIG. 8 is a functional block diagram showing another example of the control structure in receiving unit 30 of storage system 300 according to the first embodiment of the present invention.

  The control structure shown in FIG. 8 is a configuration for randomly reading the stored data when information to be stored is allocated and stored in each storage cell 120 of the semiconductor storage device 100. The receiving unit 30 includes a plurality of buffer units 34 and 36 and a space switch 35.

  Each buffer unit 34 temporarily stores data sequentially read from the corresponding memory cell 120. The space switch 35 selectively extracts data stored in each buffer unit 34 according to an address signal from the control unit 10 or the like, and outputs the extracted data to a specific buffer unit 36. That is, the space switch 35 selectively extracts necessary data from the data read from each storage cell 120 in the order of addresses and outputs the data to a specific buffer unit 36. The buffer unit 36 temporarily stores data output from the space switch 35 and outputs a data string when a predetermined amount of data is stored. In this manner, by providing a plurality of buffer units on the input side and the output side, data stored in the memory cell 120 is randomly read out, or data stored discretely is combined and output as one data string. You can do it.

  Next, data storage and usage mode of semiconductor memory device 100 according to the present embodiment will be described.

  FIG. 9 shows an example of a processing procedure related to data distribution using semiconductor memory device 100 according to the first embodiment of the present invention.

  FIG. 10 shows another form of the processing procedure related to data distribution using semiconductor memory device 100 according to the first embodiment of the present invention.

  FIG. 9 shows a form in which data storage is performed under the control of the data owner (typically the copyright holder) when the semiconductor memory device 100 is manufactured. Specifically, in order to form the semiconductor memory device 100, a solar cell is formed on the substrate 102 (step S101), each circuit is formed on the upper layer of the solar cell (step S102), and the surface of the formed circuit is excluded. The parts are subjected to grabbing (step S103) in order. Note that “grabbing” means a process of forming a sealing film such as an insulating film. Here, the reason why the surface of the formed circuit was not grabbed is to maintain a state in which data can be written to the mask ROM.

  When the semiconductor memory device 100 is formed in this way, under the control of the data owner, pattern formation is performed on the mask ROM in accordance with the data to be stored (step S104), and further, the semiconductor memory device 100 is exposed. The surface is grabbed (step S105). At this point, the semiconductor memory device 100 is packaged over the entire surface. The semiconductor memory device 100 storing this data is distributed to the user.

  The semiconductor memory device 100 distributed to the user is placed in a state where data can be freely read using a predetermined data reading device or the like (step S106).

  On the other hand, FIG. 10 shows a mode in which the data owner arbitrarily stores data after the semiconductor memory device 100 is manufactured. Specifically, first, in order to form the semiconductor memory device 100, a solar cell is formed on the substrate 102 (step S101), each circuit is formed on the upper layer of the solar cell (step S102), and the surface of the formed circuit is formed. Grabbing (step S103) is sequentially performed on the other parts except for the above. At this time, the semiconductor memory device 100 is supplied to the data owner.

  The data owner performs pattern formation on the mask ROM according to the data to be stored (step S114). Burning a circuit pattern onto a mask ROM requires a relatively large device, so the mask ROM is composed of a laser PROM, a fuse-type PROM, etc., and the data owner uses a laser to create the necessary circuit pattern. What is necessary is just to shape | mold. Then, when the data owner completes the pattern formation on the mask ROM, the data owner performs grabbation on the entire surface of the semiconductor memory device 100 (step S115). The semiconductor memory device 100 storing this data is distributed to the user.

  The semiconductor memory device 100 distributed to the user is placed in a state where data can be freely read using a predetermined data reading device or the like (step S106).

  According to the present embodiment, a mask ROM for storing data in a nonvolatile manner and a peripheral circuit for reading data from the mask ROM are formed on the substrate, and these exposed surfaces are physicochemically treated. A structure that is covered with a stable sealing film is employed. As a result, it is possible to suppress the erosion caused by the atmosphere and to extend the life of the data retention.

  In addition, according to the present embodiment, since a read operation or the like is performed using energy supplied from the outside, the circuit configuration can be simplified. Furthermore, by employing a light-transmitting glass substrate, power can be supplied using a solar cell formed on the substrate. Silicon substrates and other materials have a certain degree of electrical conductivity, but glass substrates are good insulators, so they have high transparency because they absorb less electromagnetic waves, enabling efficient data communication with less transmission power. Can be done.

[Modification of Embodiment 1]
In the above-described embodiment, the semiconductor memory device including the solar cell that receives the light irradiated from the outside and generates internal power is illustrated, but a passive wireless system may be mounted.

  FIG. 11 is a block diagram showing functional configurations of semiconductor memory device 100A and receiver 30A according to the modification of the first embodiment of the present invention.

  Referring to FIG. 11, each of memory cells 120 </ b> A is provided with transmission / reception circuit 80 </ b> A in place of transmission circuit 80 and a control circuit after removing solar cell 50 as compared with storage cell 120 shown in FIG. 4. Instead of 60, a control circuit 60A is provided. The storage cell 120A is a passive storage medium that responds to data stored therein when receiving a radio signal from the outside of the apparatus.

  More specifically, when a radio signal for data reading is transmitted from the corresponding reception cell 310A, the radio signal is received by the transmission / reception circuit 80A via the antenna 90. The transmission / reception circuit 80A extracts power and identification information from the radio signal from the reception cell 310A and supplies the power and identification information to the control circuit 60A. Control circuit 60A is activated upon receiving power from receiving cell 310A, and reads data from a predetermined address of mask ROM 70 in accordance with the identification information from receiving cell 310A. The read data is output to transmission / reception circuit 80A. The transmission / reception circuit 80A uses a part of the radio signal received by the antenna 90, modulates the radio signal with data read from the mask ROM 70, and performs transmission again.

  In contrast, reception cell 310A includes antenna 30a and transmission / reception circuit 30c. The transmission / reception circuit 30c generates a radio signal for reading data from the memory cell 120A, transmits the radio signal from the antenna 30a, and decodes and outputs the data from the radio signal from the memory cell 120A received by the antenna 30a. .

  Thus, receiving cell 310A according to the modification of the present embodiment reads data from storage cell 120A.

  According to the present embodiment, the same effect as in the first embodiment described above can be obtained, and power is supplied to semiconductor memory device 100 by a radio signal and data is read by the radio signal. A design can be applied to the entire surface of the storage device 100.

[Embodiment 2]
FIG. 12 is an external view showing an example of a configuration using a storage system according to the second embodiment of the present invention. Referring to FIG. 12, semiconductor memory device 100 according to the present embodiment is used as a recording medium for storing an application executed on portable game device 200 as an example. More specifically, the semiconductor storage device 100 stores in a non-volatile manner a program code and various data that are executed by an arithmetic device such as a CPU (Central Processing Unit) of the portable game device 200, and the like. Device 200 includes a data reading device for reading data from semiconductor memory device 100. Then, when the semiconductor memory device 100 is inserted into the portable game device 200, such information is read out.

FIG. 13 is a schematic diagram showing a cross-sectional structure of portable game device 200 shown in FIG.
Referring to FIG. 13, portable game device 200 includes a control unit 10 </ b> A, a light irradiation unit 20, a reception unit 30, and a power supply unit (BAT) 40. The portable game apparatus 200 has a notch for inserting the semiconductor memory device 100 on the main body side. A light irradiation unit 20 and a reception unit 30 are disposed on the lower surface side and the upper surface side of the notch, respectively.

  The light irradiation unit 20 is an energy supply unit that supplies energy to the semiconductor storage device 100 in a non-contact manner. The light irradiation unit 20 generates light from the power from the power supply unit 40 and transmits the generated light from the lower side of the drawing to the semiconductor storage device 100. Irradiate toward. The receiving unit 30 receives data transmitted by the semiconductor storage device 100 in response to light from the light irradiation unit 20, and outputs the received data to the control unit 10A. The control unit 10A includes a CPU, a RAM, a display circuit, and the like. The control unit 10A receives data output from the receiving unit 30 and executes predetermined processing. The power supply unit 40 typically includes a storage battery and supplies driving power to the light irradiation unit 20 and the control unit 10A.

  Since other configurations and processes are the same as those in the first embodiment, detailed description will not be repeated.

  According to the present embodiment, the same effects as those in the first embodiment described above can be obtained, and data can be read out from the semiconductor memory device 100 in a non-contact manner. The effect of improving the resistance to occurrence and damage due to static electricity can be obtained. In addition, the effect of improving resistance to decoding (reverse engineering) and remodeling can be obtained.

  In the first and second embodiments described above, the configuration in which the circuit is formed on the substrate molded in advance in a square shape is exemplified. However, as an example of the configuration for further increasing the storage capacity, a crystal-grown disc A circuit for realizing the semiconductor memory device according to the present invention may be formed on the silicon wafer having the shape.

[Embodiment 3]
FIG. 14 is an external view of a storage system 400 according to the third embodiment of the present invention. Referring to FIG. 14, a storage system 400 according to the present embodiment includes a plurality of semiconductor storage devices 100B, a rack 410 that houses these semiconductor storage devices 100B, and light that irradiates these semiconductor storage devices 100B. It includes an irradiation unit 20B, a reading unit 30B arranged close to the semiconductor memory device 100B located at one end, a control unit 10B, and an interface unit 12. The rack 410, the light irradiation unit 20B, the reading unit 30B, the control unit 10B, and the interface unit 12 function as a “data reading device”.

  Each of the semiconductor memory devices 100B includes a non-volatile storage unit such as a mask ROM, a peripheral circuit that performs data reading and wireless transmission from the mask ROM, and a non-contact from the outside such as a solar cell on a substantially disc-shaped silicon wafer. And a power generation unit that generates internal power in response to energy supplied in the state. In the rack 410, such semiconductor memory devices 100B are stored close to each other according to a predetermined rule.

  Semiconductor memory device 100B according to the present embodiment is typically capable of autonomous communication between adjacent semiconductor memory devices 100B such as an ad-hoc network. That is, in storage system 400 according to the present embodiment, when light irradiation is started from light irradiation unit 20B toward each semiconductor storage device 100B, each semiconductor storage device 100B receives from adjacent semiconductor storage device 100B. The transmitted data is wirelessly transmitted to another adjacent semiconductor memory device 100B, and the data stored therein is wirelessly transmitted to the adjacent semiconductor memory device 100B. As a result, the data respectively stored in the semiconductor memory device 100B is sequentially transmitted in any direction along the arrangement rule of the semiconductor memory device 100B. Data transmitted from the semiconductor memory device 100B located on the most downstream side in the transmission direction is received by the reading unit 30B and output from the interface unit 12 to the outside via the control unit 10B.

  As described above, since semiconductor storage device 100B according to the present embodiment autonomously transmits data, there is no restriction on the order and number of storage in rack 410, and each semiconductor storage device 100B is not limited. As long as they are arranged adjacent to each other, the semiconductor memory device 100B can be easily added or replaced as necessary.

  The light irradiation unit 20B is the same as the above-described light irradiation unit 20 except for the irradiation area, and therefore detailed description will not be repeated. Since interface unit 12 has also been described above, detailed description thereof will not be repeated.

  The control unit 10B discriminates data sequentially transmitted from the plurality of semiconductor storage devices 100B based on their IDs, temporarily stores them in an internal memory or the like, and stores necessary data according to an external request or the like. Output from the interface unit 12.

  FIG. 15 is a block diagram showing a planar structure of semiconductor memory device 100B according to the third embodiment of the present invention. 16 is a cross-sectional view of the semiconductor memory device 100B shown in FIG. 15 taken along the line XVI-XVI.

  Referring to FIG. 15, each of semiconductor memory devices 100B includes a solar cell 50B, a control circuit 60B, a mask ROM 70B, a transmission circuit 42 including a transmission antenna, and a reception circuit 44 including a reception antenna. including. The transmission circuit 42 and the reception circuit 44 function as a “communication unit”. Each of these parts is formed on a light-transmitting substrate (wafer), and its exposed surface is entirely covered with a sealing film (typically a physicochemically stable insulator such as a silicon dioxide film). Covered.

  The solar cell 50B is formed in a horseshoe shape on a light-transmitting wafer, receives light emitted from the light irradiation unit 20B (FIG. 14), and generates internal power. The generated internal power is supplied to the control circuit 60B, the transmission circuit 42, the reception circuit 44, and the like. Semiconductor memory device 100B according to the present embodiment is arranged such that the other semiconductor memory device 100B and its plane are adjacent to each other. Even in such a state, solar cell 50B is formed on the outer peripheral side of semiconductor memory device 100B so that light from light irradiation unit 20B (FIG. 14) can be received effectively. FIG. 15 shows a configuration in which solar cell 50B is formed on one surface opposite to the surface on which other circuits are formed, but it is formed on both surfaces so that more internal power can be generated. It may be.

  When power supply from the solar battery 50B is started, the control circuit 60B cooperates with the transmission circuit 42 and the reception circuit 44 to form an ad hoc network with the other semiconductor memory device 100B. Specifically, when the receiving circuit 44 receives data transmitted from the adjacent semiconductor memory device 100B, the control circuit 60B transmits the received data from the transmitting circuit 42 to another adjacent semiconductor memory device 100B. That is, the control circuit 60B functions as a relay device that transfers data from the semiconductor memory device 100B adjacent to the own device to another adjacent semiconductor memory device 100B. In conjunction with this relay operation, the control circuit 60B reads the data from the mask ROM 70B and outputs it to the transmission circuit 42, thereby transmitting the data stored therein to the other semiconductor memory device 100B. Note that more detailed communication processing will be described later.

  Since mask ROM 70B has the same configuration as mask ROM 70 described above, detailed description will not be repeated.

  The transmission circuit 42 receives electric power from the solar battery 50B and generates a modulation signal corresponding to data read from the mask ROM 70B by the control circuit 60B. Then, the transmission circuit 42 excites an antenna (not shown) with this modulated signal, thereby transmitting a radio signal (modulated signal) to the adjacent semiconductor memory device 100B.

  When the receiving circuit 44 receives power from the solar battery 50B and receives a radio signal from another semiconductor storage device 100B via an antenna (not shown), the receiving circuit 44 decodes the radio signal into data and outputs the data to the control circuit 60B. To do.

  In each of semiconductor memory devices 100B according to the present embodiment, transmission of the radio signal and reception of the radio signal are performed independently. Therefore, transmission circuit 42 and reception circuit 44 are arranged so that the radio signals do not interfere with each other. They are formed a predetermined distance apart on the wafer surface.

  Referring to FIG. 16, semiconductor memory device 100B has the same cross-sectional structure as semiconductor memory device 100 according to the first embodiment shown in FIG. 5, and includes substrate 102, antireflection film 122, and n-type semiconductor. The layer 124 includes a p-type semiconductor layer 126, a p + impurity semiconductor layer 128, an electrode layer 130, through holes 136B and 138B, and insulating films 140 and 150.

  Specifically, solar cell 50B is formed in a predetermined region on substrate 102 made of light-transmitting glass whose main component is silicon dioxide. In this solar cell 50B, the n-type semiconductor layer 124, the p-type semiconductor layer 126, and the p + impurity semiconductor layer 128 constitute a pn junction solar cell. Then, the light irradiated from the light irradiation unit 20B (FIG. 15) passes through the substrate 102, and then is irradiated to the n-type semiconductor layer 124 through the antireflection film 122. This light excites electrons in the n-type semiconductor layer 124, and an electromotive force is generated between the n-type semiconductor layer 124 and the p + impurity semiconductor layer 128 according to the amount of irradiation light. With this electromotive force, electric power is supplied to the control circuit 60B, the reception circuit 44, the transmission circuit 42 (FIG. 15) and the like through the through holes 136B and 138B.

  As shown in FIG. 16, in the semiconductor memory device 100B, the solar cell 50B is formed in the region surrounded by the substrate 102 and the insulating film 140, and the control circuit 60B formed on the upper surface of the insulating film 140 is exposed. The surface is sealed with an insulating film 150. Therefore, the surface of the semiconductor memory device 100B is covered with an insulating film such as glass or silicon dioxide that is physicochemically stable over the entire surface, so that intrusion of outside air is blocked.

  FIG. 17 is a schematic diagram showing a state of data transmission in storage system 400 according to the third embodiment of the present invention.

  Referring to FIG. 17, in storage system 400 according to the present embodiment, a plurality of semiconductor storage devices 100B are close to each other in rack 410 (FIG. 14) such that their circumferential centers are arranged on the same straight line. Stored. As shown in FIG. 15, in each semiconductor memory device 100B, a transmission circuit 42 and a reception circuit 44 are formed on the same circumferential surface so as to be separated by a predetermined circumferential angle.

  Therefore, by rotating the semiconductor memory device 100B by the predetermined circumferential angle and arranging them adjacent to each other, the transmitter circuit 42 and the receiver circuit 44 can be arranged close to each other between the two adjacent semiconductor memory devices 100B. it can. Typically, FIG. 17 shows a case where adjacent semiconductor memory devices 100B are sequentially arranged with a relative relationship rotated by 90 °. In this semiconductor memory device 100B, the transmission circuit 42 and the reception circuit 44 are arranged with a circumferential angle of 90 ° apart.

  An ad hoc network can be formed by arranging a plurality of semiconductor memory devices 100B according to the positional relationship as shown in FIG. In other words, in the configuration shown in FIG. 17, data is transmitted in one direction from the semiconductor memory device 100B on the left side of the drawing to the semiconductor storage device 100B on the right side of the drawing.

  In each semiconductor memory device 100B, the transmission circuit 42 and the reception circuit 44 are formed a predetermined distance apart so that radio signals received or transmitted do not interfere with each other. Furthermore, the radio signal transmitted from each transmission circuit 42 is set to such an intensity that it is received only by the closest reception circuit 44. That is, the strength is set so that a radio signal transmitted from a certain transmission circuit 42 does not affect the reception circuit 44 of another semiconductor storage device 100B other than the adjacent semiconductor storage device 100B.

  Note that in FIG. 17, the transmission circuit 42 and the reception circuit 44 are representatively illustrated as being 90 ° apart from each other at a circumferential angle, but any circumferential angle can be used as long as the above-described conditions are satisfied. Also good.

  Incidentally, it is preferable that the positional relationship as described above can be easily realized for the plurality of semiconductor memory devices 100B. Therefore, in the present embodiment, a cutout portion 110 (FIG. 15) for specifying the relative positional relationship is formed in each of the semiconductor memory devices 100B so that such alignment can be performed more easily. Is done. In other words, in each slot of the rack 410 (FIG. 15) that houses the semiconductor memory device 100B, a protrusion that engages with the notch 110 is provided at an appropriate position, so that the gap between the adjacent semiconductor memory devices 100B can be reduced. A positional relationship for reliably performing wireless communication can be realized.

  By adopting such a configuration, a new semiconductor memory device 100B (that is, content) can be easily added even by a user who does not have any specialized knowledge. Further, there is no restriction on the arrangement order of the semiconductor memory devices 100B.

  The topology of the ad hoc network of the storage system 400 shown in FIG. 17 is one-dimensional. Therefore, in storage system 400 according to the present embodiment, it is assumed that data is transmitted in one direction, and each semiconductor storage device 100B receives data from the upstream side when semiconductor storage device 100B on the upstream side exists. The transmission is preferentially transferred to the downstream side, and when the transfer is completed, the data stored therein is transmitted. Hereinafter, a communication sequence related to these data transmissions will be described with reference to FIG.

  FIG. 18 is a communication sequence diagram in storage system 400 according to the third embodiment of the present invention. In FIG. 18, it is assumed that N semiconductor memory devices 100B are arranged, and each semiconductor memory device 100B is also referred to as Node1 to NodeN in order from the reading unit 30B (FIG. 15).

  Referring to FIG. 18, when light irradiation is started from light irradiation unit 20 </ b> B (FIG. 15) to N semiconductor memory devices 100 </ b> B, each semiconductor memory device 100 </ b> B is activated and starts processing. In storage system 400 according to the present embodiment, which semiconductor storage device 100B is located most upstream is determined based on whether or not a “start signal” is received from another semiconductor storage device 100B. That is, each semiconductor memory device 100B determines that it is positioned at the most upstream position when a non-reception state in which no “start signal” is received from another semiconductor memory device 100B continues for a predetermined period after the start of light irradiation. Then, the data stored therein is transmitted to the downstream semiconductor memory device 100B. When the data transmission is completed, an “end signal” is subsequently transmitted to the downstream semiconductor memory device 100B. On the other hand, when the “start signal” is received from another semiconductor memory device 100B within a predetermined period after the light irradiation is started, it is determined that the other semiconductor memory device 100B exists upstream from itself, and the other Until the “end signal” is received from the semiconductor memory device 100B, the data received from the upstream side is sequentially transferred to the semiconductor memory device 100B on the downstream side, and when the “end signal” is received thereafter, the data stored therein is transferred. When the data is transmitted to the downstream side semiconductor storage device 100B and the data transmission is completed, an “end signal” is subsequently transmitted to the downstream side semiconductor storage device 100B.

  In this way, the data is sequentially transferred from the semiconductor memory device 100B located on the most upstream side toward the semiconductor memory device 100B located on the downstream side, so that all the semiconductor memory devices 100B constituting the storage system 400 are transferred. Data to be stored can be read.

  More specifically, when the processing starts, each semiconductor memory device 100B first transmits a start signal (step S200) and waits for a predetermined period of time to receive the start signal from the upstream semiconductor memory device 100B. Note that the predetermined period may be determined randomly.

  At this time, at least semiconductor memory device 100B (NodeN) located on the most upstream side (that is, the most distant from reading unit 30B (FIG. 15)) does not receive the start signal from other semiconductor memory device 100B. The non-reception state continues for a predetermined period (step S202). Then, the NodeN reads the data N stored in its mask ROM 70B (FIG. 15) (step S204), and transmits the data N to the adjacent semiconductor memory device 100B (NodeN-1) (step S206). In other words, semiconductor memory device 100B starts its own data transmission only when it does not receive a start signal from another semiconductor memory device 100B for a predetermined time. Note that identification information indicating that there is data from the Node N may be added to the transmitted data N. Furthermore, when the node N completes its own data transmission, the Node N continues to transmit an end signal to the adjacent Node N-1.

  When Node N-1 receives data N from Node N, Node N-1 transmits (transfers) data N as it is to adjacent Node N-2 (not shown) (step S208). Hereinafter, similarly, the data N is sequentially transferred from Node N-2 to Node 1. Then, Node 1 that has received the data N (step S210) outputs (transmits) the received data N to the reading unit 30B (FIG. 15) (step S212). By such a procedure, the data N stored in NodeN is read out.

  On the other hand, when receiving an end signal transmitted subsequent to the data N, the Node N-1 reads the data N-1 stored in its own mask ROM 70B (step S214), and the data N-1 is read from the adjacent Node N- 2 (not shown) (step S216). Hereinafter, as with the data N, the data N-1 is also sequentially transferred from NodeN-2 to Node1. Node 1 that has received data N-1 (step S218) outputs (transmits) the received data N-1 to reading unit 30B (step S220). By such a procedure, data N-1 stored in NodeN-1 is read. Further, when the node N-1 completes its own data transmission, it continuously transmits an end signal to the adjacent Node N-2.

  Similarly, each of Node N-2 to Node 1 transfers data received from the upstream side to the downstream side, and then receives an end signal transmitted from the upstream side following the data, stores itself. Start transmitting data to the downstream side.

  Finally, when Node 1 receives data 2 from Node 2 (step S222), Node 1 outputs the received data 2 to reading unit 30B (step S224). When Node 1 receives the end signal transmitted from Node 2 following Data 2 (S223), Node 1 reads data 1 stored in its own mask ROM 70B (Step S226), and sends the data 1 to reading unit 30B. Output (transmit) (step S228).

  Through such a series of processing, data can be read from all the semiconductor memory devices 100B (Node 1 to Node N). The series of data is temporarily stored in the control circuit 60B (FIG. 15), and part or all of the data is output as read data from the interface unit 12 as necessary.

  According to the present embodiment, each semiconductor storage device 100B autonomously performs data communication with another adjacent semiconductor storage device 100B, and sequentially transfers data according to a predetermined communication rule. Therefore, the semiconductor memory device 100B constituting the storage system 400 can be freely set, and all data can be read if only one reading unit is provided regardless of the number of the semiconductor memory devices 100B. Further, the arrangement order of the semiconductor memory device 100B can be freely set.

  Therefore, even if the data to be stored increases, the semiconductor memory device 100B can be added or changed flexibly and freely.

  Further, according to the present embodiment, each semiconductor memory device 100B is provided with a notch, and a protrusion corresponding to the rack 410 is provided at an appropriate position, so that adjacent semiconductor memory devices 100B are predetermined. Each can be stored so as to have a relative relationship. Therefore, the positional relationship necessary for establishing an ad hoc network can be realized without making the user aware of it.

[Modification of Embodiment 3]
In the above-described embodiment, the semiconductor memory device including the solar cell that generates the internal power by receiving the light irradiated from the outside is illustrated, but the configuration that generates the internal power by receiving the electromagnetic energy irradiated from the outside. It may be adopted.

  FIG. 19 is an external view of a storage system 400A according to the modification of the third embodiment of the present invention. Referring to FIG. 19, a storage system 400A according to a modification of the present embodiment includes a plurality of semiconductor storage devices 100D, magnetic flux supply units 90A and 90B that supply magnetic fluxes to these semiconductor storage devices 100D, and one end. It includes a reading unit 30B, a control unit 10B, and an interface unit 12 that are arranged in the vicinity of the located semiconductor memory device 100D. The rack 410, the magnetic flux supply units 90A and 90B, the reading unit 30B, the control unit 10B, and the interface unit 12 function as a “data reading device”.

  The semiconductor memory device 100D according to the modification of the present embodiment is different from the semiconductor device 100B according to the third embodiment in the method of supplying energy from the outside in a non-contact state, but other configurations are substantially the same. It is the same. That is, when the supply of magnetic flux is started by the magnetic flux supply units 90A and 90B, each semiconductor storage device 100D wirelessly transmits data received from the adjacent semiconductor storage device 100D to another adjacent semiconductor storage device 100D. The data stored therein is also wirelessly transmitted to the adjacent semiconductor memory device 100D.

  The magnetic flux supply units 90A and 90B are arranged to face both sides of a plurality of semiconductor memory devices 100D arranged in series, and generate magnetic flux (alternating magnetic flux) that penetrates all the semiconductor memory devices 100D. This generated magnetic flux is converted into internal power by interlinking with a coil (described later) of each semiconductor memory device 100D.

  Since control unit 10B, interface unit 12, and reading unit 30B are the same as storage system 400 shown in FIG. 14, detailed description thereof will not be repeated.

  FIG. 20 is a block diagram showing a planar structure of semiconductor memory device 100D according to the modification of the third embodiment of the present invention.

  Referring to FIG. 20, each of semiconductor memory devices 100D includes a coil 94, a power supply circuit 96, a control circuit 60D, a mask ROM 70D, a transmission circuit 42 including a transmission antenna, and a reception antenna. And a receiving circuit 44. The transmission circuit 42 and the reception circuit 44 function as a “communication unit”. Each of these parts is formed on a physically and chemically stable substrate (wafer), and its exposed surface is entirely covered with a sealing film (typically a physicochemically stable film such as a silicon dioxide film). Covered with insulation).

  The coil 94 is formed at the center of the wafer, and receives an alternating magnetic flux supplied from the magnetic flux supply units 90A and 90B (FIG. 19) to induce an electromotive force. The electromotive force induced in the coil 94 is input to the power supply circuit 96. The power supply circuit 96 has a rectifying function and a smoothing function, and outputs an alternating electromotive force generated by the coil 94 as direct internal power. More specifically, the power supply circuit 96 includes a full-wave rectifier circuit including a diode bridge circuit and a smoothing circuit such as a capacitor connected in parallel to the line.

  When the power supply from the power supply circuit 96 is started, the control circuit 60D cooperates with the transmission circuit 42 and the reception circuit 44 to form an ad hoc network with another semiconductor memory device 100D. Specifically, the control circuit 60D functions as a relay device that transfers data from the semiconductor memory device 100D adjacent to the own device to another adjacent semiconductor memory device 100D. In conjunction with this relay operation, the control circuit 60D reads the data from the mask ROM 70D and outputs it to the transmission circuit 42, thereby transmitting the data stored therein to the other semiconductor memory device 100D as the transfer destination. Since communication processing in these ad hoc networks is the same as that in the third embodiment, detailed description will not be repeated.

  Since mask ROM 70D has the same configuration as mask ROM 70 described above, detailed description will not be repeated.

  Transmitting circuit 42 and receiving circuit 44 are the same as in the third embodiment described above except that they operate by receiving power from power supply circuit 96, and thus detailed description will not be repeated.

  According to the modification of the present embodiment, the same effect as that of the above-described third embodiment can be obtained, and the unit of internal power can be increased by increasing the strength of the supplied magnetic flux and / or the number of turns of the coil. Since the generation efficiency per area can be increased, the area in which the mask ROM is formed in each semiconductor memory device can be increased. As a result, the storage capacity of each semiconductor memory device can be increased.

[Embodiment 4]
In storage system 400 according to the above-described third embodiment, semiconductor memory device 100B is arranged one-dimensionally, and the configuration in which data stored in each semiconductor memory device 100B is transmitted in one direction is illustrated. In contrast, in the present embodiment, a configuration in which semiconductor memory devices are arranged two-dimensionally or three-dimensionally is illustrated.

  FIG. 21 is an external view of a storage system 500 according to the fourth embodiment of the present invention. Referring to FIG. 21, storage system 500 according to the present embodiment includes a plurality of semiconductor storage devices 100C, a light irradiation unit 20C that irradiates light to these semiconductor storage devices 100C, and semiconductor storage devices 100C located at the four corners. Includes four reading units 30 </ b> C, a control unit 10 </ b> C, and an interface unit 12 that are arranged close to each other. The light irradiation unit 20C, the reading unit 30C, the control unit 10C, and the interface unit 12 function as a “data reading device”.

  In storage system 500 according to the present embodiment, semiconductor memory device 100C similar to semiconductor memory device 100B according to the above-described third embodiment is two-dimensionally arranged. Except for the semiconductor memory devices 100C arranged at the four corners, each semiconductor memory device 100C is arranged adjacent to two to four semiconductor memory devices 100C. Each semiconductor memory device 100C includes a plurality of transmission / reception circuits capable of transmitting and receiving data to / from other semiconductor memory devices 100C, and independently transmits / receives data to / from adjacent semiconductor memory devices 100C. Is possible.

  Each of reading units 30C has a function of transmitting a command from control unit 10C to adjacent semiconductor memory device 100C in addition to the function of reading unit 30B according to the third embodiment.

  Since light irradiation unit 20C is similar to light irradiation unit 20B according to the third embodiment, detailed description will not be repeated.

  By adopting the network configuration as shown in FIG. 21, the degree of freedom of the path from the semiconductor memory device 100C to be read to the control unit 10C can be increased. That is, since a plurality of paths from the semiconductor memory device 100C to be read to the control unit 10C can be provided, data reading can be continued even if any one of the semiconductor memory devices 100C has a failure. Alternatively, reading speed can be increased by reading in parallel through a plurality of paths.

  In storage system 500 according to the present embodiment, each semiconductor storage device 100C can transmit and receive data independently, so that necessary data can be selectively read according to an external request or the like. is there.

  FIG. 22 is a block diagram showing a planar structure of a semiconductor memory device 100C according to the fourth embodiment of the present invention.

  Referring to FIG. 22, each of semiconductor memory devices 100C includes a solar cell 50B, a control circuit 60C, a mask ROM 70B, six transmission / reception circuits 46-1 to 46-6, and transmission / reception circuits 46-1 to 46-. 6 and antennas 48-1 to 48-6 corresponding to 6 respectively. Each of these portions is formed on the wafer, and the exposed surface is entirely covered with a sealing film (typically, a physicochemically stable insulator such as a silicon dioxide film).

  When the power supply from the solar cell 50B is started, the control circuit 60C forms an ad hoc network with at least one adjacent semiconductor memory device 100C in cooperation with the transmission / reception circuits 46-1 to 46-6. To do. Specifically, when one of the transmission / reception circuits 46-1 to 46-6 receives a data request command from the adjacent semiconductor storage device 100C, the control circuit 60C receives the data request command from the data storage command 100C. If it is a target, the requested data is read from the mask ROM 70B and transmitted to the adjacent semiconductor memory device 100C. On the other hand, if it is not the target, the received data request command is transferred to another adjacent semiconductor memory device 100C. Note that more detailed communication processing will be described later.

  The transmission / reception circuits 46-1 to 46-6 receive power from the solar cell 50B, respectively, and excite the corresponding antennas 48-1 to 48-6 in accordance with instructions from the control circuit 60C, thereby adjacent semiconductor memory devices. Radio signals (modulated signals) are transmitted to 100C, and radio signals received from other semiconductor storage devices 100C via corresponding antennas 48-1 to 48-6 are decoded into data and output to control circuit 60C.

  Since solar cell 50B and mask ROM 70B are the same as those of semiconductor memory device 100B according to the above-described third embodiment, detailed description thereof will not be repeated.

  Also, the cross-sectional structure of semiconductor memory device 100C according to the present embodiment is similar to the cross-sectional structure of semiconductor memory device 100B according to the third embodiment shown in FIG. 16, and therefore detailed description will not be repeated.

  In each of semiconductor memory devices 100C according to the present embodiment, transmission / reception processing of radio signals is performed independently, so that antennas 48-1 to 48-6 are predetermined on the wafer surface so that radio signals do not interfere with each other. Formed by a distance. More specifically, the antennas 48-1 to 48-6 are arranged on the same circumference separated by a predetermined distance from the center point of the wafer and separated by a predetermined circumferential angle.

  FIG. 23 is a schematic diagram showing an antenna arrangement in semiconductor memory device 100C according to the third embodiment of the present invention.

  Referring to FIG. 23, in each semiconductor device 100C, antennas 48-1 to 48-3 are arranged on the circumference on the left side of the drawing, and antennas 48-4 to 48-6 are arranged on the circumference on the right side of the drawing. The The antennas 48-1, 48-2, 48-3 and the antennas 48-6, 48-5, 48-4 are in a point-symmetric relationship with respect to the center point of the wafer.

  Here, the circumferential angle between the antenna 48-1 and the antenna 48-2 is approximately twice the circumferential angle between the antenna 48-2 and the antenna 48-3. Similarly, the circumferential angle between the antenna 48-6 and the antenna 48-5 is approximately twice the circumferential angle between the antenna 48-5 and the antenna 48-4. By arranging the antennas 48-1 to 48-6 in such a positional relationship, as shown below, it is possible to avoid interference between adjacent semiconductor memory devices 100 </ b> C when arranged three-dimensionally.

  More specifically, three straight lines H, M, and L are virtually considered between adjacent semiconductor memory devices 100C. By changing the relative angle of each semiconductor device 100C, the antennas 48-1 to 48-6 intersecting with these straight lines H, M, and L can be switched to at least three arrangement patterns.

  In FIG. 23A, antennas 48-2 and 48-3 disposed on the left side of the paper of the semiconductor device 100C intersect the straight line H and the straight line M, respectively, and the antenna 48- disposed on the right side of the paper of the semiconductor device 100C. The “HM-ML arrangement” in which 4 and 48-5 intersect the straight line M and the straight line L, respectively.

  In FIG. 23B, the antennas 48-2 and 48-3 disposed on the left side of the paper of the semiconductor device 100C intersect with the straight line M and the straight line L, respectively, and the antenna 48- disposed on the right side of the semiconductor device 100C of FIG. “ML-HM arrangement” in which 4 and 48-5 intersect the straight line H and the straight line M, respectively.

  In FIG. 23C, the antennas 48-1 and 48-2 arranged on the left side of the paper of the semiconductor device 100C intersect the straight line H and the straight line L, respectively, and the antenna 48- arranged on the right side of the paper of the semiconductor device 100C. “HL-HL arrangement” in which 5 and 48-6 intersect the straight line H and the straight line L, respectively.

  FIG. 24 is a schematic diagram showing the positional relationship of the semiconductor device 100C when the storage system 500 shown in FIG. 21 is configured. In FIG. 24, symbols such as “HL”, “HM”, and “ML” correspond to the arrangement patterns shown in FIG.

  In FIG. 24, data transmission / reception can be performed between adjacent semiconductor memory devices 100C via antennas arranged on the same straight line. For example, in the semiconductor memory device 100C to which the symbol “HL” is attached, the antenna is arranged at a position intersecting with the straight line H and the straight line L shown in FIG. 23, and the semiconductor memory device to which the symbol “HM” is attached. In 100C, an antenna is arranged at a position intersecting with the straight line H and the straight line M shown in FIG. Therefore, the antennas of the respective semiconductor devices 100C are positioned on the position of “H” in the vertical direction of the paper in FIG. 24, that is, on the same straight line H extending in the horizontal direction of the paper. Therefore, data is transmitted / received between the adjacent semiconductor memory devices 100C via the two antennas located on the straight line H.

  24, the antenna used for data communication with the semiconductor memory device 100C adjacent to the front and back surfaces of the semiconductor memory device 100C, that is, the right side and the left side in FIG. The positions can be different from each other. More specifically, as shown in FIG. 24, the position of the antenna used for data transmission / reception between each semiconductor storage device 100C arranged at the top of the drawing and the adjacent semiconductor storage device 100C is “H”, It changes cyclically in the order of “M”, “L”, “H”.

  The network topology of the storage system 500 shown in FIG. 21 is two-dimensional. Therefore, in storage system 500 according to the present embodiment, each semiconductor storage device 100C performs control according to a path setting protocol so that a logical communication path is dynamically formed. Hereinafter, the route setting protocol for data transmission will be described with reference to FIGS. 25 and 26. FIG.

  FIG. 25 is a diagram for describing a path setting protocol in storage system 500 according to the fourth embodiment of the present invention. FIG. 26 is a diagram for explaining processing when there is a failure in the network shown in FIG. Here, in FIG. 25 and FIG. 26, the plurality of semiconductor memory devices 100C are also referred to as Node1 to Node7 for convenience, and the reading unit 30C is disposed in the vicinity of the semiconductor memory device 100C corresponding to Node1. Note that the topology shown in FIGS. 25 and 26 shows an example of the logical connection relationship between the nodes, and does not necessarily match the actual positional relationship of the semiconductor memory device 100C.

  Referring to FIG. 25, if a read request for specific data is given from interface unit 12 (FIG. 21) to control unit 10C, a request command is transmitted to Node1. As an example, it is assumed that this request command includes a message for requesting reading of data stored in Node4. This request command is handled as a broadcast message.

  Each Node determines whether or not the requested data is included in the data stored in its own Node based on the content of the request command. When it is determined that the requested data is not included in the data stored in the own node, each node is transferred to another adjacent node (different from the transmission source of the request command). Transfer the request instruction. Note that when adjacent to a plurality of Nodes, the request command may be transferred to one or more Nodes. FIG. 25A shows a case where Node1 transfers the received request command to adjacent Node2 and Node5, respectively.

  Here, each Node adds its node information as route information to a request command to be transferred to an adjacent Node. That is, as shown in FIG. 25A, “Node 1” is added as route information to the request commands transferred from Node 1 to Node 2 and Node 5, respectively.

  Each of Node 2 and Node 5 that has received the request command from Node 1 determines whether or not the requested data is included in the data stored in its own Node based on the content of the request command. In any Node, since it is determined that the requested data is not included in the data stored in the own Node, the Node 2 and Node 5 add the information of the own Node as route information, respectively. The received request command is transferred to each adjacent Node. That is, as illustrated in FIG. 25A, “Node1 + 2” is added as route information to the request command transferred from Node 2 to Node 3, and route information is added to the request command transferred from Node 5 to Node 6 as “ Node1 + 5 "is added.

  Thereafter, the same processing is performed, and finally, the transmission request is transferred to Node 3 through two paths. The Node 3 that receives the same transmission request refers to the route information added to each node, and transfers the transmission request with the smallest number of relayed Nodes to the adjacent Node 4. Or you may make it transfer only the transmission request which arrived at each Node earliest.

  In Node 4, it is determined that the requested data is included in the data stored in its own Node. Then, Node 4 reads the requested data stored in its own mask ROM 70B, and returns the read data to the Node that is the transmission source of the request command. At this time, as shown in FIG. 25B, route information is added to the data transmitted from Node4. This route information is generated based on the route information added to the received transmission request, and in the example shown in FIG. 25B, “Node4 + 3 + 2 + 1” is added as the route information. Thereafter, according to the added route information, the requested data is transferred to each Node, and finally output (transmitted) from Node 1 to reading unit 30C (FIG. 21).

  Alternatively, the reading speed can be further increased by reading data in parallel through two paths between Node1 and Node4.

  Next, in the above-described topology, processing when data cannot be transmitted / received due to some failure in the route between Node 2 and Node 3 will be described.

  As shown in FIG. 26A, when a request command is given to Node 1, this request command is transferred to Node 2 as in FIG. 25A described above. However, the request command cannot be transferred from Node2 to Node3.

  On the other hand, the request command transferred from Node 1 to Node 5 is transferred in the order of Node 5 → Node 6 → Node 7 and reaches Node 3. Further, this request command is transferred from Node3 to Node4.

  Further, when the node 4 receives the request command transferred from the node 3, the node 4 reads the requested data stored in its mask ROM 70B, and returns the read data to the node of the transmission source of the request command. At this time, based on the route information “Node1 + 5 + 7 + 3” added to the request command, the data read out at Node4 is transferred in the order of Node4 → Node3 → Node7 → Node6 → Node5 and reaches Node1.

  Thus, when there are a plurality of routes from Node 1 to Node 4, even if there is some failure and one of the routes cannot be used, data can be read via the other route. .

  According to the present embodiment, each semiconductor storage device 100C autonomously establishes an ad hoc network with another adjacent semiconductor storage device 100C, so that the semiconductor storage device 100C constituting the storage system 500 can be freely set. can do. Further, the arrangement order of the semiconductor memory device 100C can be freely set.

  Therefore, even if the data to be stored increases, the semiconductor memory device 100C can be added or changed flexibly and freely.

  Further, according to the present embodiment, even when a failure occurs in any one of the semiconductor memory devices 100C, another path is automatically selected and the requested data is continuously read. Therefore, it is possible to realize a highly reliable storage system with higher redundancy.

[Modification of Embodiment 4]
Similarly to the modification of the third embodiment, the fourth embodiment is also configured to generate internal power in each semiconductor memory device by supplying electromagnetic energy (alternating magnetic flux) from the outside. Also good. Since the specific configuration is the same as that of the modification of the third embodiment, detailed description will not be repeated.

[Other forms]
In the above-described first to fourth embodiments and modifications thereof, the configuration using light energy (solar cell) and the configuration using electromagnetic energy are exemplified as the configuration for supplying energy to the semiconductor memory device in a non-contact manner. The configuration may be adopted.

  For example, it is possible to adopt a configuration in which heat energy is supplied from the outside. Specifically, after forming a thermoelectric conversion element that generates the Seebeck effect in each semiconductor memory device, it is possible to generate internal power by supplying thermal energy from the outside, that is, causing a temperature change in each semiconductor device. Is possible.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is an external view of a storage system 300 according to Embodiment 1 of the present invention. FIG. It is the schematic which shows the typical cross-section of the storage system 300 shown in FIG. 1 is a schematic diagram of a semiconductor memory device 100 according to a first embodiment of the present invention. FIG. 3 is a block diagram showing functional configurations of semiconductor memory device 100 and receiving unit 30 according to the first embodiment of the present invention. 1 is a schematic diagram showing a cross-sectional structure of a semiconductor memory device 100 according to a first embodiment of the present invention. FIG. 7 is a diagram for illustrating an example of data read from semiconductor memory device 100 according to the first embodiment of the present invention. It is a functional block diagram which shows an example of the control structure in the receiver 30 of the storage system 300 according to Embodiment 1 of this invention. It is a functional block diagram which shows the other example of the control structure in the receiver 30 of the storage system 300 according to Embodiment 1 of this invention. It is a figure which shows an example of the process sequence which concerns on the data distribution using the semiconductor memory device 100 according to Embodiment 1 of this invention. It is a figure which shows another form of the process sequence which concerns on the data distribution using the semiconductor memory device 100 according to Embodiment 1 of this invention. It is a block diagram showing a functional configuration of a semiconductor memory device 100A and a receiving unit 30A according to a modification of the first embodiment of the present invention. It is an external view which shows an example of the structure using the storage system according to Embodiment 2 of this invention. It is the schematic which shows the cross-section of the portable game device 200 shown in FIG. It is an external view of the storage system 400 according to Embodiment 3 of this invention. FIG. 11 is a block diagram showing a planar structure of a semiconductor memory device 100B according to the third embodiment of the present invention. FIG. 16 is a cross-sectional view of the semiconductor memory device 100B shown in FIG. 15 taken along line XVI-XVI. It is a schematic diagram which shows the state of the data transmission in the storage system 400 according to Embodiment 3 of this invention. It is a communication sequence diagram in the storage system 400 according to Embodiment 3 of this invention. It is an external view of the storage system 400A according to the modification of Embodiment 3 of this invention. It is a block diagram which shows the planar structure of semiconductor memory device 100D according to the modification of Embodiment 3 of this invention. It is an external view of the storage system 500 according to Embodiment 4 of this invention. It is a block diagram showing a planar structure of a semiconductor memory device 100C according to the fourth embodiment of the present invention. It is a schematic diagram which shows antenna arrangement | positioning in 100 C of semiconductor memory devices according to Embodiment 3 of this invention. FIG. 22 is a schematic diagram showing a positional relationship of a semiconductor device 100C when configuring the storage system 500 shown in FIG. 21. It is a figure for demonstrating the route setting protocol in the storage system 500 according to Embodiment 4 of this invention. It is a figure for demonstrating a process when there exists a failure in the network shown in FIG.

Explanation of symbols

  10, 10A, 10B, 10C control unit, 12 interface unit, 20, 20B, 20C light irradiation unit, 30, 30A reception unit, 30a, 90 antenna, 30b reception circuit, 30c transmission / reception circuit, 30B, 30C readout unit, 31 serial Conversion unit, 32 correction circuit, 33 decoding circuit, 34, 36 buffer unit, 35 space switch, 40 power supply unit, 42 transmission circuit, 44 reception circuit, 46, 46-1 to 46-6 transmission / reception circuit, 48-1 to 48 -6 antenna, 50, 50B solar cell, 60, 60A, 60B, 60C, 60D control circuit, 60a counter circuit, 70, 70B, 70D mask ROM, 80, 80A transceiver circuit, 90A, 90B magnetic flux supply unit, 96 power supply circuit , 100, 100A, 100B, 100C, 100D Semiconductor memory device, 10 2 substrate, 110 notch, 120, 120A memory cell, 122 antireflection film, 124 n-type semiconductor layer, 126 p-type semiconductor layer, 128 p + impurity semiconductor layer, 130 electrode layer, 132, 134, 136, 136B, 138B, 138 Through hole, 140, 150 insulating film, 200 portable game device, 300, 400, 400A, 500 storage system, 310, 310A receiving cell, 410 rack.

Claims (13)

A storage system comprising a plurality of semiconductor storage devices and a data reading device,
The plurality of semiconductor memory devices are arranged close to each other according to a predetermined rule,
Each of the plurality of semiconductor memory devices includes:
A light transmissive substrate;
A power generation unit that generates power by receiving light transmitted through the substrate;
A non-volatile storage unit that is disposed on the substrate and stores data in a non-volatile manner;
A communication unit that is disposed on the substrate and receives power from the power generation unit and wirelessly transmits data stored in the nonvolatile storage unit to a semiconductor storage device adjacent to the device;
A sealing film that covers an exposed surface of the power generation unit, the nonvolatile storage unit, and the communication unit;
The communication unit is
A receiving unit for receiving data from a semiconductor memory device adjacent to the device;
A transmission unit for transmitting data to another semiconductor memory device adjacent to the own device;
The receiving unit and the transmitting unit are formed apart from each other by a predetermined distance on the substrate,
The plurality of semiconductor memory devices are:
Between the adjacent semiconductor memory devices, one receiving unit and the other transmitting unit are arranged so as to be close to each other,
The data reading device comprises:
A light irradiation unit for irradiating light to the plurality of semiconductor memory devices;
A storage system comprising: a reading unit provided in proximity to at least one of the plurality of semiconductor storage devices arranged in proximity to each other and receiving data wirelessly transmitted by the semiconductor storage device.   The storage system according to claim 1, wherein the communication unit transfers data received from the semiconductor storage device adjacent to the own device to another semiconductor storage device adjacent to the own device.   The storage system according to claim 2, wherein the communication unit transmits the data stored in the nonvolatile storage unit to the transfer destination after transferring the data received from the semiconductor storage device adjacent to the communication unit. The substrate is substantially disc-shaped,
The said transmitter unit and the front Symbol receiver are spaced apart by a predetermined circumferential angle about its center in a substantially disk shape of the substrate,
The plurality of semiconductor memory devices are arranged so that their circumferential centers are on the same straight line, and one of the receiving units and the other transmitting unit are adjacent to each other between adjacent semiconductor memory devices. The storage system according to claim 2 or 3, wherein the storage system is arranged. A storage system comprising a plurality of semiconductor storage devices and a data reading device,
The plurality of semiconductor memory devices are arranged close to each other according to a predetermined rule,
Each of the plurality of semiconductor memory devices includes:
A light transmissive substrate;
A power generation unit that generates power by receiving light transmitted through the substrate;
A non-volatile storage unit that is disposed on the substrate and stores data in a non-volatile manner;
A communication unit that is disposed on the substrate and receives power from the power generation unit and wirelessly transmits data stored in the nonvolatile storage unit to a semiconductor storage device adjacent to the device;
A sealing film that covers an exposed surface of the power generation unit, the nonvolatile storage unit, and the communication unit;
The plurality of semiconductor memory devices are arranged so that each semiconductor memory device is close to the plurality of semiconductor memory devices,
The communication unit includes a plurality of transmission / reception units capable of transmitting and receiving data to and from a semiconductor storage device adjacent to the device.
The plurality of transmission / reception units are formed apart from each other by a predetermined distance on the substrate,
One semiconductor memory device of the plurality of semiconductor memory devices is
One transmitter / receiver of the plurality of transmitter / receivers is adjacent to the transmitter / receiver of the semiconductor memory device adjacent to the semiconductor memory device, and another transmitter / receiver of the plurality of transmitter / receivers is the semiconductor memory. Arranged so as to be close to the transceiver unit of another semiconductor memory device adjacent to the device,
Each of the transmission / reception units establishes an ad hoc network with a semiconductor storage device adjacent to the own device ,
The data reading device comprises:
A light irradiation unit for irradiating light to the plurality of semiconductor memory devices;
A storage system comprising: a reading unit provided in proximity to at least one of the plurality of semiconductor storage devices arranged in proximity to each other and receiving data wirelessly transmitted by the semiconductor storage device.   The storage system according to claim 1, wherein the sealing film is a silicon dioxide film. A semiconductor storage device used in a storage system comprising a plurality of semiconductor storage devices arranged close to each other according to a predetermined rule,
A light transmissive substrate;
A power generation unit that generates power by receiving light transmitted through the substrate;
A non-volatile storage unit that is disposed on the substrate and stores data in a non-volatile manner;
A communication unit that is disposed on the substrate and receives power from the power generation unit and wirelessly transmits data stored in the nonvolatile storage unit to a semiconductor storage device adjacent to the device;
Said power generating unit, the nonvolatile storage unit, seen including a sealing film covering exposed surfaces of said communication unit,
The communication unit is
A receiving unit for receiving data from a semiconductor memory device adjacent to the device;
A transmission unit for transmitting data to another semiconductor memory device adjacent to the own device;
The receiving unit and the transmitting unit are formed apart from each other by a predetermined distance on the substrate,
The semiconductor memory device
A semiconductor memory device, wherein the receiving unit of the own device is arranged so as to be close to the transmitting unit of the semiconductor memory device adjacent to the own device. A storage system comprising a plurality of semiconductor storage devices and a data reading device,
The plurality of semiconductor memory devices are arranged close to each other according to a predetermined rule,
Each of the plurality of semiconductor memory devices includes:
A substrate,
A non-volatile storage unit that is disposed on the substrate and stores data in a non-volatile manner;
A power generation unit that is disposed on the substrate and generates internal power by receiving energy supplied in a non-contact state from the outside;
A communication unit that is arranged on the substrate and receives the internal power and can transmit and receive data using a wireless signal with a semiconductor memory device adjacent to the device;
A sealing film that covers an exposed surface of the power generation unit, the nonvolatile storage unit, and the communication unit;
The communication unit is
A receiving unit for receiving data from a semiconductor memory device adjacent to the device;
A transmission unit for transmitting data to another semiconductor memory device adjacent to the own device;
The receiving unit and the transmitting unit are formed apart from each other by a predetermined distance on the substrate,
The plurality of semiconductor memory devices are:
Between the adjacent semiconductor memory devices, one receiving unit and the other transmitting unit are arranged so as to be close to each other,
When the communication unit receives data from the semiconductor memory device adjacent to the device, the communication unit transfers the received data to another semiconductor memory device adjacent to the device.
The data reading device is a storage system including a reading unit that is provided in proximity to at least one of the plurality of semiconductor memory devices arranged close to each other and receives data transferred by the semiconductor memory device.   The storage system according to claim 8, wherein the communication unit transmits the data stored in the nonvolatile storage unit to the transfer destination after transferring the data received from the semiconductor storage device adjacent to the communication unit. A storage system comprising a plurality of semiconductor storage devices and a data reading device,
The plurality of semiconductor memory devices are arranged close to each other according to a predetermined rule,
Each of the plurality of semiconductor memory devices includes:
A substrate,
A non-volatile storage unit that is disposed on the substrate and stores data in a non-volatile manner;
A power generation unit that is disposed on the substrate and generates internal power by receiving energy supplied in a non-contact state from the outside;
A communication unit that is arranged on the substrate and receives the internal power and can transmit and receive data using a wireless signal with a semiconductor memory device adjacent to the device;
A sealing film that covers an exposed surface of the power generation unit, the nonvolatile storage unit, and the communication unit;
The plurality of semiconductor memory devices are arranged so that each semiconductor memory device is close to the plurality of semiconductor memory devices,
The communication unit includes a plurality of transmission / reception units capable of transmitting and receiving data to and from a semiconductor storage device adjacent to the device.
The plurality of transmission / reception units are formed apart from each other by a predetermined distance on the substrate,
One semiconductor memory device of the plurality of semiconductor memory devices is
One transmitter / receiver of the plurality of transmitter / receivers is adjacent to the transmitter / receiver of the semiconductor memory device adjacent to the semiconductor memory device, and another transmitter / receiver of the plurality of transmitter / receivers is the semiconductor memory. Arranged so as to be close to the transceiver unit of another semiconductor memory device adjacent to the device,
Each of the transmission / reception units establishes an ad hoc network with a semiconductor storage device adjacent to the own device ,
When the communication unit receives data from the semiconductor memory device adjacent to the device, the communication unit transfers the received data to another semiconductor memory device adjacent to the device.
The data reading device is a storage system including a reading unit that is provided in proximity to at least one of the plurality of semiconductor memory devices arranged close to each other and receives data transferred by the semiconductor memory device. The substrate is a light transmissive substrate,
The power generation unit is a solar cell that generates power by receiving light transmitted through the substrate,
The storage system according to any one of claims 8 to 10, wherein the data reading device further includes a light irradiation unit that irradiates light to the plurality of semiconductor storage devices. The data reading device further includes a magnetic flux supply unit that supplies an alternating magnetic flux to the plurality of semiconductor memory devices,
The power generator is
A coil formed at a position interlinking with the alternating magnetic flux;
11. The storage system according to claim 8, further comprising: a power supply circuit that generates internal power from an electromotive force generated when the coil is interlinked with an alternating magnetic flux. A semiconductor storage device used in a storage system comprising a plurality of semiconductor storage devices arranged close to each other according to a predetermined rule,
A substrate,
A non-volatile storage unit that is disposed on the substrate and stores data in a non-volatile manner;
A power generation unit that is disposed on the substrate and generates internal power by receiving energy supplied in a non-contact state from the outside;
A communication unit that is arranged on the substrate and receives the internal power and can transmit and receive data using a wireless signal with a semiconductor memory device adjacent to the device;
A sealing film that covers an exposed surface of the power generation unit, the nonvolatile storage unit, and the communication unit;
When the communication unit receives data from the semiconductor memory device adjacent to the device, the communication unit transfers the received data to another semiconductor memory device adjacent to the device .
The communication unit is
A receiving unit for receiving data from a semiconductor memory device adjacent to the device;
A transmission unit for transmitting data to another semiconductor memory device adjacent to the own device;
The receiving unit and the transmitting unit are formed apart from each other by a predetermined distance on the substrate,
The semiconductor memory device
A semiconductor memory device, wherein the receiving unit of the own device is arranged so as to be close to the transmitting unit of the semiconductor memory device adjacent to the own device.

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