JP5059221B2 - Optical limiter circuit and optical receiver circuit - Google Patents

Optical limiter circuit and optical receiver circuit Download PDF

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JP5059221B2
JP5059221B2 JP2011199893A JP2011199893A JP5059221B2 JP 5059221 B2 JP5059221 B2 JP 5059221B2 JP 2011199893 A JP2011199893 A JP 2011199893A JP 2011199893 A JP2011199893 A JP 2011199893A JP 5059221 B2 JP5059221 B2 JP 5059221B2
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waveguide
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absorption coefficient
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JP2011248387A (en
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誠治 福島
裕之 津田
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Nippon Telegraph and Telephone Corp
Keio University
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Keio University
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an optical limiter circuit and an optical reception circuit capable of being easily integrated with other optical functional circuit and has a wide operating wavelength band. <P>SOLUTION: An optical limiter circuit comprises: an input waveguide 107, a semiconductor waveguide 108 with an enhanced absorption coefficient; and an output waveguide 109, which has an optical fuse function for protecting following optical circuits when input power exceeds several hundred mW. In the semiconductor, since the band gap wavelength shifts to longer wavelength side due to a temperature raise, in a specific wavelength, the absorption coefficient is further increased as the temperature rises. That is, the semiconductor waveguide having an absorption coefficient of certain extent has an optical limiter characteristic by itself. In this circuit, since the temperature rises up to 100&deg;C or more, the waveguide is fused by an excessive input and this circuit serves also as an optical fuse. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

本発明は、光リミッタ回路および光受信回路に関し、より詳細には、光サージによる受光素子の劣化を低減する光リミッタ回路および光受信回路に関する。   The present invention relates to an optical limiter circuit and an optical receiver circuit, and more particularly to an optical limiter circuit and an optical receiver circuit that reduce deterioration of a light receiving element due to an optical surge.

光増幅器を利用する光ネットワークにおいて、スイッチ切り替え、装置の瞬断等、光増幅器への入力光信号平均パワが非常に小さい状態が数十ミリ秒以上続いた後に、急激に光信号パワが増大すると、光サージが発生し、受信回路を破損することがある。従来、光増幅器への入力パワが零にならないようにシステム設計したり、あるいは、光信号レベルをモニタし、光増幅器内の励起レーザ光出力を調整したりして、大きな光サージが発生しないように工夫されてきた。また、上り信号の増幅時に発生する光サージを、下り信号で利得クランプすることにより抑圧する方法も提案されている(非特許文献1)。   In an optical network using an optical amplifier, the optical signal power suddenly increases after a state in which the average optical signal power to the optical amplifier is very small for several tens of milliseconds or longer, such as switch switching or instantaneous interruption of the device. An optical surge may occur and damage the receiving circuit. Conventionally, system design is made so that the input power to the optical amplifier does not become zero, or the optical signal level is monitored and the pumping laser light output in the optical amplifier is adjusted, so that a large optical surge does not occur. Has been devised. Also proposed is a method of suppressing an optical surge generated during amplification of an upstream signal by gain clamping with the downstream signal (Non-Patent Document 1).

しかしながら、これらの方法は、通信装置に大掛りな制御系、モニタシステムが必要であり、高コストである。また、励起レーザ光の調整によるフィードバックは時定数が遅く、光サージを十分に抑圧できない場合もある。   However, these methods require a large control system and monitor system in the communication apparatus, and are expensive. Further, the feedback by adjusting the excitation laser beam has a slow time constant, and there are cases where the optical surge cannot be sufficiently suppressed.

これらの代わりに、受光素子の前段に光リミッタ回路を設けることによって、光サージによる受信回路の損傷をより少なくすることが出来る。従来の光リミッタ回路としては、光非線形材料を光共振器内に挿入した非線形エタロン、あるいは、ほぼ同様の構成であるが、非対称ファブリペロー共振器に可飽和吸収体を挿入した非線形素子を利用した光リミッタ回路等がある。   Instead of these, by providing an optical limiter circuit in front of the light receiving element, damage to the receiving circuit due to optical surge can be reduced. As a conventional optical limiter circuit, a nonlinear etalon in which an optical nonlinear material is inserted in an optical resonator, or a nonlinear element in which a saturable absorber is inserted in an asymmetric Fabry-Perot resonator is used. Examples include an optical limiter circuit.

中西泰彦、中西隆、深田陽一、鈴木謙一、岩月勝美、「単一EDF構成双方向アクセス用光増幅器における光サージ抑圧」、電子情報通信学会総合大会論文集、2007年、B−8−8Yasuhiko Nakanishi, Takashi Nakanishi, Yoichi Fukada, Kenichi Suzuki, Katsumi Iwatsuki, "Optical Surge Suppression in Single EDF Bidirectional Access Optical Amplifier", IEICE General Conference Proceedings, 2007, B-8-8

しかしながら、これらの素子は面型の構成であり、導波路で構成される各種光回路への集積が困難であるという課題があった。また、共振構造であるので、波長範囲の広い波長分割多重信号に対して、使用波長毎に個別に調整が必要であるという課題があった。   However, these elements have a surface type configuration, and there is a problem that it is difficult to integrate them into various optical circuits including waveguides. In addition, since it has a resonant structure, there is a problem that it is necessary to individually adjust the wavelength division multiplexed signal having a wide wavelength range for each wavelength used.

本発明は、このような課題に鑑みてなされたもので、その目的とするところは、他の光機能回路との集積が容易に可能で、使用波長帯域が広い光リミッタ回路および光受信回路を提供することにある。   The present invention has been made in view of such problems, and an object of the present invention is to provide an optical limiter circuit and an optical receiver circuit that can be easily integrated with other optical functional circuits and have a wide wavelength band. It is to provide.

このような目的を達成するために、請求項1に記載の発明は、光リミッタ回路であって、第1のクラッド層、第1のコア層及び第2のクラッド層が順に積層された単一モードの単一導波路において、前記単一導波路のコアの一部が、周囲のコアと吸収係数が異なり、少なくとも前記単一導波路は半導体材料を用いて形成され、前記半導体材料の不純物濃度を変えることで吸収係数を調整されたことを特徴とする。 In order to achieve such an object, an invention according to claim 1 is an optical limiter circuit, wherein a first clad layer, a first core layer, and a second clad layer are sequentially laminated. in a single waveguide mode, said part of a single waveguide core, the core and the absorption coefficient of the surrounding Ri is Do different, at least said single waveguide is formed by using a semiconductor material, impurities of the semiconductor material The absorption coefficient is adjusted by changing the concentration .

請求項2に記載の発明は、光リミッタ回路であって、第1のクラッド層、コア層及び前記コア層の周囲を覆う第2のクラッド層からなる単一モードの単一導波路において、前記単一導波路のコアの一部が、周囲のコアと吸収係数が異なり、少なくとも前記単一導波路は半導体材料を用いて形成され、前記半導体材料の不純物濃度を変えることで吸収係数を調整されたことを特徴とする。 The invention according to claim 2 is an optical limiter circuit, in a single mode single waveguide comprising a first cladding layer, a core layer, and a second cladding layer covering the periphery of the core layer. part of the core of a single waveguide, the core and the absorption coefficient of the surrounding Ri is Do different, at least said single waveguide is formed by using a semiconductor material, adjust the absorption coefficient by varying the impurity concentration of the semiconductor material It is characterized by that.

請求項3に記載の発明は、光リミッタ回路であって、第1のクラッド層、第1のコア層及び第2のクラッド層が順に積層された単一モードの単一導波路において、前記単一導波路のコアの一部が、周囲のコアと吸収係数が異なり、少なくとも前記単一導波路は半導体材料を用いて形成され、前記半導体材料の結晶欠陥量を変えることで吸収係数を調整されたことを特徴とするAccording to a third aspect of the present invention, there is provided an optical limiter circuit comprising: a single mode single waveguide in which a first cladding layer, a first core layer, and a second cladding layer are sequentially stacked; Part of the core of one waveguide has an absorption coefficient different from that of the surrounding core. At least the single waveguide is formed using a semiconductor material, and the absorption coefficient is adjusted by changing the amount of crystal defects in the semiconductor material. It is characterized by that .

請求項4に記載の発明は、光リミッタ回路であって、第1のクラッド層、コア層及び前記コア層の周囲を覆う第2のクラッド層からなる単一モードの単一導波路において、前記単一導波路のコアの一部が、周囲のコアと吸収係数が異なり、少なくとも前記単一導波路は半導体材料を用いて形成され、前記半導体材料の結晶欠陥量を変えることで吸収係数を調整されたことを特徴とする。 The invention according to claim 4 is an optical limiter circuit, in a single mode single waveguide comprising a first cladding layer, a core layer, and a second cladding layer covering the periphery of the core layer. Part of the core of the single waveguide has an absorption coefficient different from that of the surrounding core. At least the single waveguide is formed using a semiconductor material, and the absorption coefficient is adjusted by changing the amount of crystal defects in the semiconductor material. It is characterized by that.

本発明によれば、他の光機能回路との集積が容易で、広い波長範囲に対して動作する光リミッタ機能が可能になる。また、光リミッタ機能と併せて光ヒューズ機能も備えることが可能になる。   According to the present invention, it is easy to integrate with other optical functional circuits, and an optical limiter function that operates over a wide wavelength range is possible. In addition, an optical fuse function can be provided in addition to the optical limiter function.

本発明の実施形態1に係る光リミッタ回路の構成を示す図である。It is a figure which shows the structure of the optical limiter circuit which concerns on Embodiment 1 of this invention. 本発明の実施形態1に係る光リミッタ回路の光入出力特性を示す図である。It is a figure which shows the optical input / output characteristic of the optical limiter circuit which concerns on Embodiment 1 of this invention. 本発明の実施形態2に係る光リミッタ回路の構成を示す図である。It is a figure which shows the structure of the optical limiter circuit which concerns on Embodiment 2 of this invention. 本発明の実施形態2に係る光リミッタ回路の光入出力特性を示す図である。It is a figure which shows the optical input / output characteristic of the optical limiter circuit which concerns on Embodiment 2 of this invention. 本発明の光リミッタ回路を備えた光受信回路の構成を示す図である。It is a figure which shows the structure of the optical receiver circuit provided with the optical limiter circuit of this invention. 本発明の一実施例に係る光リミッタ回路の光入出力特性を示す図である。It is a figure which shows the optical input / output characteristic of the optical limiter circuit based on one Example of this invention.

以下、図面を参照しながら本発明の実施形態について詳細に説明する。尚、実施形態を説明するための全図において、同一の機能を有するものは同一符号を付け、その繰り返しの説明は省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

[実施形態1]
図1に、本発明の実施形態1に係る光リミッタ回路の構成を示す。入力導波路101には分岐導波路102が接続され、出力導波路106には合波導波路105が接続され、それら分岐導波路102と合波導波路105との間を接続するように第1アーム導波路103、第2アーム導波路104が形成されている。このように、本光回路はマッハツェンダ型光干渉導波路を構成している。
[Embodiment 1]
FIG. 1 shows the configuration of an optical limiter circuit according to Embodiment 1 of the present invention. A branching waveguide 102 is connected to the input waveguide 101, a combining waveguide 105 is connected to the output waveguide 106, and the first arm guide is connected between the branching waveguide 102 and the combining waveguide 105. A waveguide 103 and a second arm waveguide 104 are formed. Thus, the present optical circuit constitutes a Mach-Zehnder type optical interference waveguide.

第1及び第2アーム導波路が同じ長さ、同じ吸収係数を有し、分岐導波路102の分岐比がY分岐導波路等のように等しく、分岐光がそれぞれ等位相である場合、合波導波路105では各分岐光が同相で結合して入力光のほぼ100%が出力導波路106から出力される。   When the first and second arm waveguides have the same length and the same absorption coefficient, the branching ratio of the branching waveguide 102 is equal to that of the Y-branching waveguide, etc., and the branched lights have the same phase, In the waveguide 105, the branched lights are coupled in phase, and almost 100% of the input light is output from the output waveguide 106.

ここで、これらの光回路を半導体導波路(例えばシリコンSi、リン化インジウムInP、ヒ素化ガリウムGaAs等)で構成し、第1アーム導波路103に不純物ドーピング、低温成長やイオン注入等による欠陥増大を行うことによって第1アーム導波路103における吸収係数を高める。即ち、第1アーム導波路103と第2アーム導波路104の吸収係数に差が生じるようにそれぞれの吸収係数を設定する。さらに、分岐導波路102の分岐比と、第1アーム導波路103及び第2アーム導波路104の長さを調整して、光入力が弱い場合に第1アーム導波路103と第2アーム導波路104が合波導波路105に結合する直前での光強度を等しく、かつ、同相にする。   Here, these optical circuits are constituted by semiconductor waveguides (for example, silicon Si, indium phosphide InP, gallium arsenide GaAs, etc.), and the first arm waveguide 103 is increased in defects by impurity doping, low temperature growth, ion implantation, or the like. To increase the absorption coefficient in the first arm waveguide 103. That is, the respective absorption coefficients are set so that there is a difference between the absorption coefficients of the first arm waveguide 103 and the second arm waveguide 104. Further, by adjusting the branching ratio of the branching waveguide 102 and the lengths of the first arm waveguide 103 and the second arm waveguide 104, the first arm waveguide 103 and the second arm waveguide when the optical input is weak. The light intensity immediately before coupling 104 to the multiplexing waveguide 105 is made equal and in phase.

このように光回路を構成し、光入力パワを増加させていくと、光吸収によって第1アーム導波路103の温度のみが局所的に上昇する。半導体は、一般に熱光学係数が大きく10-4-1程度である。即ち、第1アーム導波路103が、1mm程度の長さであれば、10℃程度の温度上昇で光の位相がπ程度シフトする。本回路は干渉系を構成しているので、合波導波路105直前で第1アーム導波路103と第2アーム導波路104からの光の位相が同相でないと出力導波路106への結合効率が低下する。そのため、本回路は、図2に示すように、入射パワが低い領域では透過出力光の出射パワは入射パワに比例して増加するが、入射パワが所定の強度を超えると出射パワが相対的に抑制されるリミッタ型の光入出力特性を有する。 When the optical circuit is configured in this way and the optical input power is increased, only the temperature of the first arm waveguide 103 locally increases due to light absorption. A semiconductor generally has a large thermo-optic coefficient and is about 10 −4 K −1 . That is, if the first arm waveguide 103 has a length of about 1 mm, the phase of light shifts by about π with a temperature increase of about 10 ° C. Since this circuit constitutes an interference system, the coupling efficiency to the output waveguide 106 decreases unless the phases of the light from the first arm waveguide 103 and the second arm waveguide 104 are in phase immediately before the multiplexing waveguide 105. To do. Therefore, as shown in FIG. 2, in this circuit, the output power of the transmitted output light increases in proportion to the incident power in the region where the incident power is low, but when the incident power exceeds a predetermined intensity, Limiter type light input / output characteristics.

ここで、実施形態1について、実施例を示しながら、その作製方法について説明する。各導波路は、MOVPE法により積層した、InP基板上の下部クラッド層、コア層、上部クラッド層の積層構造からなる。下部クラッド層はInP(層厚:500nm)、コア層はInGaAsP(組成波長は1.4μm、層厚:300nm)、上部クラッド層はInP(層厚:500nm)とする。   Here, the manufacturing method of Embodiment 1 will be described with reference to examples. Each waveguide has a laminated structure of a lower clad layer, a core layer, and an upper clad layer on an InP substrate, which are laminated by the MOVPE method. The lower cladding layer is InP (layer thickness: 500 nm), the core layer is InGaAsP (composition wavelength is 1.4 μm, layer thickness: 300 nm), and the upper cladding layer is InP (layer thickness: 500 nm).

次に、上部クラッド層上にSiO2(層厚:300nm)をプラズマCVDにより成膜する。フォトレジストプロセスとCF系RIEにより、SiO2をマッハツェンダ型光干渉導波路における第1アーム導波路103に相当する領域を含む領域を開口部とするマスクに加工する。即ち、入力導波路101、分岐導波路102、第2アーム導波路104、合波導波路105、出力導波路106に相当する領域をマスクするようにSiO2を加工する。 Next, SiO 2 (layer thickness: 300 nm) is formed on the upper cladding layer by plasma CVD. By a photoresist process and CF-based RIE, SiO 2 is processed into a mask having a region including a region corresponding to the first arm waveguide 103 in the Mach-Zehnder optical interference waveguide as an opening. That is, SiO 2 is processed so as to mask regions corresponding to the input waveguide 101, the branch waveguide 102, the second arm waveguide 104, the multiplexing waveguide 105, and the output waveguide 106.

次に、マスクの開口部からZn、Be、Cd、Mg等のp型不純物をイオン注入する。これにより、第1アーム導波路103に相当する領域を含むマスク開口部領域にのみp型不純物がイオン注入される。その後、通常のランプアニールによりp型不純物を活性化させる。   Next, p-type impurities such as Zn, Be, Cd, and Mg are ion-implanted from the opening of the mask. As a result, the p-type impurity is ion-implanted only in the mask opening region including the region corresponding to the first arm waveguide 103. Thereafter, the p-type impurity is activated by normal lamp annealing.

ここで一度SiO2マスクをフッ酸処理で除去し、その後、再度上部クラッド層表面にSiO2(層厚:300nm)をプラズマCVDにより成膜する。この新たに成膜したSiO2膜を、フォトレジストプロセスにより形成されたレジストマスクを用いてCF系RIE(Reactive Ion Etching)によりマッハツェンダ型光干渉導波路形状に加工する。 Here, the SiO 2 mask is once removed by hydrofluoric acid treatment, and then SiO 2 (layer thickness: 300 nm) is again formed on the surface of the upper cladding layer by plasma CVD. This newly formed SiO 2 film is processed into a Mach-Zehnder optical interference waveguide shape by CF-based RIE (Reactive Ion Etching) using a resist mask formed by a photoresist process.

マッハツェンダ型光干渉導波路形状に加工したSiO2をマスクとして用いて、塩素系プラズマエッチング(RIE,RIBE:Reactive Ion Beam Etching)によりInP/InGaAsP/InP層をマッハツェンダ型光干渉導波路に加工する。導波路幅は全て3μmとし、第1アーム導波路103及び第2アーム導波路104のアームの長さは1mmとする。 Using the SiO 2 processed into the Mach-Zehnder type optical interference waveguide shape as a mask, the InP / InGaAsP / InP layer is processed into a Mach-Zehnder type optical interference waveguide by chlorine-based plasma etching (RIE, RIBE: Reactive Ion Beam Etching). The waveguide widths are all 3 μm, and the arm lengths of the first arm waveguide 103 and the second arm waveguide 104 are 1 mm.

第1アーム導波路103に相当する領域には、p型不純物をイオン注入する以外に、Si、Fe等のp型以外の不純物のイオン注入、プロトン、電子線照射などにより欠陥を導入してもよい。また、選択成長により第1アーム導波路103に相当する領域にp型InP/InGaAsP/InP層を形成することで、p型不純物のイオン注入を代替してもよい。   In the region corresponding to the first arm waveguide 103, in addition to ion implantation of p-type impurities, defects may be introduced by ion implantation of impurities other than p-type such as Si and Fe, proton irradiation, electron beam irradiation, and the like. Good. Alternatively, p-type impurity ion implantation may be substituted by forming a p-type InP / InGaAsP / InP layer in a region corresponding to the first arm waveguide 103 by selective growth.

基板にはInP、導波路にはInP/InGaAsP/InPを用いたが、基板にはGaAs、Si等を用いることもでき、導波路にはInP/InGaAs/InP、AlGaAs/GaAs/AlGaAs等の化合物半導体、Si/SiGe/Si、SiO2/Si/SiO2等を用いても同様の効果が得られる。 InP was used for the substrate and InP / InGaAsP / InP was used for the waveguide, but GaAs, Si, etc. could be used for the substrate, and compounds such as InP / InGaAs / InP and AlGaAs / GaAs / AlGaAs could be used for the waveguide. The same effect can be obtained by using a semiconductor, Si / SiGe / Si, SiO 2 / Si / SiO 2 or the like.

入射光の波長を1.55μmとして計算を行ったところ、図6のような入出力特性が得られた。尚、1.55μmでなくてもInGaAsPの組成波長を調整することにより1.3μm等の他の長波長帯にも適用可能である。また、第1アーム導波路103の光非線形層に他の波長に対応する材料を用いることにより長波長帯以外の波長にも適用することができる。   When the calculation was performed with the wavelength of the incident light being 1.55 μm, the input / output characteristics as shown in FIG. 6 were obtained. Even if the wavelength is not 1.55 μm, it can be applied to other long wavelength bands such as 1.3 μm by adjusting the composition wavelength of InGaAsP. Moreover, it can apply also to wavelengths other than a long wavelength band by using the material corresponding to another wavelength for the optical nonlinear layer of the 1st arm waveguide 103. FIG.

[実施形態2]
図3に、本発明の実施形態2に係るリミッタ回路の構成を示す。また、図4に、その光入出力特性を示す。ここで、107は入力導波路、108は吸収係数を高くした半導体導波路、109は出力導波路である。
[Embodiment 2]
FIG. 3 shows a configuration of a limiter circuit according to the second embodiment of the present invention. FIG. 4 shows the light input / output characteristics. Here, 107 is an input waveguide, 108 is a semiconductor waveguide having a high absorption coefficient, and 109 is an output waveguide.

本回路は、実施形態1で想定する光パワ(数十mW)よりもさらに入力パワが大きく、数百mW以上になる場合、後段の光回路を保護するための光ヒューズ機能を有する光リミッタである。半導体は、温度上昇によってバンドギャップ波長が長波長にシフトするので、特定の波長において、温度上昇と共に吸収係数がさらに増大する。即ち、ある程度の吸収係数を持つ半導体導波路は、それ自身で光リミッタ特性を有する。この回路では、温度上昇が100℃以上になるので、過大な入力で導波路が溶融し、光ヒューズとしても機能する。即ち、図4に示されるように、ヒステリシス特性が発現する。   This circuit is an optical limiter having an optical fuse function for protecting the optical circuit in the subsequent stage when the input power is larger than the optical power (several tens of mW) assumed in the first embodiment and becomes several hundred mW or more. is there. Since the band gap wavelength of a semiconductor shifts to a long wavelength with a rise in temperature, the absorption coefficient further increases with a rise in temperature at a specific wavelength. That is, a semiconductor waveguide having a certain absorption coefficient has optical limiter characteristics by itself. In this circuit, since the temperature rise is 100 ° C. or more, the waveguide is melted by an excessive input and also functions as an optical fuse. That is, as shown in FIG. 4, hysteresis characteristics are exhibited.

このように本回路は、実施形態1と同様に、入射パワが低い領域では透過出力光の出射パワは入射パワに比例して増加するが、入射パワが所定の強度を超えると出射パワが相対的に抑制されるリミッタ型の光入出力特性を有し、さらに入射パワが増すと導波路を塞いで光を遮断する光ヒューズ機能も有している。   As described above, in this circuit, in the region where the incident power is low, the output power of the transmitted output light increases in proportion to the incident power, but when the incident power exceeds a predetermined intensity, the output power is relatively It has a limiter-type optical input / output characteristic that is suppressed, and also has an optical fuse function that blocks the light by blocking the waveguide when the incident power increases.

ここで、実施形態2について、実施例を示しながら、その作製方法について説明する。各導波路は、MOVPE法により積層した、InP基板上のクラッド層、コア層、クラッド層の積層構造からなる。下部クラッド層はInP(層厚:500nm)、コア層はInGaAsP(組成波長は1.4μm、層厚:300nm)、上部クラッド層はInP(層厚:500nm)とする。ここではコア層は、下面と上面とを下部及び上部クラッド層で挟まれているのみで、側面にはクラッド層がないが、コアの入出力面以外の側面全てがクラッドに覆われているような導波路であってもよい。   Here, a manufacturing method of the second embodiment will be described with reference to examples. Each waveguide has a laminated structure of a clad layer, a core layer, and a clad layer on an InP substrate laminated by the MOVPE method. The lower cladding layer is InP (layer thickness: 500 nm), the core layer is InGaAsP (composition wavelength is 1.4 μm, layer thickness: 300 nm), and the upper cladding layer is InP (layer thickness: 500 nm). Here, the core layer is simply sandwiched between the lower and upper clad layers by the lower and upper clad layers, and there is no clad layer on the side surfaces, but all the side surfaces other than the input / output surface of the core are covered by the clad. A simple waveguide may be used.

次に、上部クラッド層上にSiO2(層厚:300nm)をプラズマCVDにより成膜する。フォトレジストプロセスとCF系RIEにより、SiO2を半導体導波路108に相当する領域を含む領域を開口部とするマスクに加工する。即ち、入力導波路107及び出力導波路109に相当する領域をマスクするようにSiO2を加工する。 Next, SiO 2 (layer thickness: 300 nm) is formed on the upper cladding layer by plasma CVD. By a photoresist process and CF-based RIE, SiO 2 is processed into a mask having a region including a region corresponding to the semiconductor waveguide 108 as an opening. That is, the SiO 2 is processed so as to mask regions corresponding to the input waveguide 107 and the output waveguide 109.

次に、マスクの開口部からZn、Be、Cd、Mg等のp型不純物をイオン注入する。これにより、半導体導波路108に相当する領域を含むマスク開口部領域にのみp型不純物がイオン注入される。その後、通常のランプアニールによりp型不純物を活性化させる。   Next, p-type impurities such as Zn, Be, Cd, and Mg are ion-implanted from the opening of the mask. As a result, the p-type impurity is ion-implanted only into the mask opening region including the region corresponding to the semiconductor waveguide 108. Thereafter, the p-type impurity is activated by normal lamp annealing.

ここで一度SiO2マスクをフッ酸処理で除去し、その後、再度上部クラッド層表面にSiO2(層厚:300nm)をプラズマCVDにより成膜する。この新たに成膜したSiO2膜をフォトレジストプロセスにより形成されたレジストマスクを用いてCF系RIEにより単一導波路形状に加工する。 Here, the SiO 2 mask is once removed by hydrofluoric acid treatment, and then SiO 2 (layer thickness: 300 nm) is again formed on the surface of the upper cladding layer by plasma CVD. This newly formed SiO 2 film is processed into a single waveguide shape by CF RIE using a resist mask formed by a photoresist process.

単一導波路形状に加工したSiO2ストライプをマスクとして用いて、塩素系プラズマエッチングによりInP/InGaAsP/InP層を単一導波路に加工する。導波路幅は全て3μmとし、吸収係数を高くした半導体導波路108の長さは1mmとする。 The InP / InGaAsP / InP layer is processed into a single waveguide by chlorine-based plasma etching using the SiO 2 stripe processed into a single waveguide shape as a mask. The waveguide widths are all 3 μm, and the length of the semiconductor waveguide 108 having a high absorption coefficient is 1 mm.

光ヒューズとしての効果を高めるためには、p型ドーピング濃度を増加する、もしくは、導波路幅の細線化(1μm未満)が有効である。   In order to enhance the effect as an optical fuse, it is effective to increase the p-type doping concentration or to narrow the waveguide width (less than 1 μm).

このように、本発明に係る光リミッタ回路は、広い波長範囲に対して動作可能であり、PLC等の光導波路で構成できるので他の光機能回路との集積も容易である。   As described above, the optical limiter circuit according to the present invention can operate over a wide wavelength range and can be configured with an optical waveguide such as a PLC, so that it can be easily integrated with other optical functional circuits.

[実施形態3]
図5に、本発明の実施形態3に係る光受信回路の構成を示す。入力スポット変換回路110、光リミッタ回路112、出力スポット変換回路114が、単一モード導波路111、113を介して縦続接続されている。光リミッタ回路112は、本発明の実施形態1、2のいずれかの光リミッタ回路とする。また、出力スポット変換回路114の後段にはフォトダイオード115が結合されている。実施形態3は、光受信器のフロントエンドであるが、これにより光受信器の光サージに対する耐力が強化される。
[Embodiment 3]
FIG. 5 shows a configuration of an optical receiver circuit according to Embodiment 3 of the present invention. An input spot conversion circuit 110, an optical limiter circuit 112, and an output spot conversion circuit 114 are connected in cascade through single mode waveguides 111 and 113. The optical limiter circuit 112 is the optical limiter circuit according to any one of the first and second embodiments of the present invention. A photodiode 115 is coupled to the subsequent stage of the output spot conversion circuit 114. The third embodiment is a front end of an optical receiver, which enhances the resistance of the optical receiver to an optical surge.

ここで、実施形態3について、実施例を示しながら、その作製方法について説明する。   Here, a manufacturing method of the third embodiment will be described with reference to examples.

Si基板上に形成された石英導波路111、113、スポット変換回路110、114からなる平面光波回路(PLC:Planar Lightwave Circuit)に通常の実装方法により、実施形態1、2のいずれかの光リミッタ回路112、1.55μm用のフォトダイオード(アバランシェフォトダイオード:APD)115を装着する。尚、フォトダイオード115はpinフォトダイオードでもよい。   The optical limiter according to any one of Embodiments 1 and 2 is mounted on a planar lightwave circuit (PLC) formed of quartz waveguides 111 and 113 and spot conversion circuits 110 and 114 formed on a Si substrate by a normal mounting method. A circuit 112 and a 1.55 μm photodiode (avalanche photodiode: APD) 115 are mounted. The photodiode 115 may be a pin photodiode.

このように、本発明の光リミッタ回路は他の光機能回路と共にPLCチップ内に形成することができるため、光リミッタ機能を有する集積度の高い光受光回路を容易に作製することができる。   As described above, since the optical limiter circuit of the present invention can be formed in the PLC chip together with other optical functional circuits, a highly integrated light receiving circuit having an optical limiter function can be easily manufactured.

101 入力導波路
102 分岐導波路
103 第1アーム導波路
104 第2アーム導波路
105 合波導波路
106 出力導波路
107 入力半導体導波路
108 吸収係数を高くした半導体導波路
109 出力導波路
110 入力スポット変換回路
111、113 単一モード導波路
112 光リミッタ回路
114 出力スポット変換回路
115 フォトダイオード
DESCRIPTION OF SYMBOLS 101 Input waveguide 102 Branching waveguide 103 1st arm waveguide 104 2nd arm waveguide 105 Combined waveguide 106 Output waveguide 107 Input semiconductor waveguide 108 Semiconductor waveguide 109 with a high absorption coefficient Output waveguide 110 Input spot conversion Circuits 111 and 113 Single mode waveguide 112 Optical limiter circuit 114 Output spot conversion circuit 115 Photodiode

Claims (4)

第1のクラッド層、第1のコア層及び第2のクラッド層が順に積層された単一モードの単一導波路において、前記単一導波路のコアの一部が、周囲のコアと吸収係数が異なり、少なくとも前記単一導波路は半導体材料を用いて形成され、前記半導体材料の不純物濃度を変えることで吸収係数を調整されたことを特徴とする光リミッタ回路。 In a single-mode single waveguide in which a first cladding layer, a first core layer, and a second cladding layer are sequentially stacked, a part of the core of the single waveguide has an absorption coefficient that is equal to the surrounding core. but depends, at least the single waveguide is formed by using a semiconductor material, optical limiter circuit, characterized in that the adjusted absorption coefficient by varying the impurity concentration of the semiconductor material. 第1のクラッド層、コア層及び前記コア層の周囲を覆う第2のクラッド層からなる単一モードの単一導波路において、前記単一導波路のコアの一部が、周囲のコアと吸収係数が異なり、少なくとも前記単一導波路は半導体材料を用いて形成され、前記半導体材料の不純物濃度を変えることで吸収係数を調整されたことを特徴とする光リミッタ回路。 In a single-mode single waveguide comprising a first cladding layer, a core layer, and a second cladding layer covering the periphery of the core layer, a part of the core of the single waveguide is absorbed by the surrounding core coefficient Ri is Do different, at least said single waveguide is formed by using a semiconductor material, optical limiter circuit, characterized in that the adjusted absorption coefficient by varying the impurity concentration of the semiconductor material. 第1のクラッド層、第1のコア層及び第2のクラッド層が順に積層された単一モードの単一導波路において、前記単一導波路のコアの一部が、周囲のコアと吸収係数が異なり、少なくとも前記単一導波路は半導体材料を用いて形成され、前記半導体材料の結晶欠陥量を変えることで吸収係数を調整されたことを特徴とする光リミッタ回路 In a single-mode single waveguide in which a first cladding layer, a first core layer, and a second cladding layer are sequentially stacked, a part of the core of the single waveguide has an absorption coefficient that is equal to the surrounding core. The optical limiter circuit is characterized in that at least the single waveguide is formed using a semiconductor material, and an absorption coefficient is adjusted by changing a crystal defect amount of the semiconductor material . 第1のクラッド層、コア層及び前記コア層の周囲を覆う第2のクラッド層からなる単一モードの単一導波路において、前記単一導波路のコアの一部が、周囲のコアと吸収係数が異なり、少なくとも前記単一導波路は半導体材料を用いて形成され、前記半導体材料の結晶欠陥量を変えることで吸収係数を調整されたことを特徴とする光リミッタ回路 In a single-mode single waveguide comprising a first cladding layer, a core layer, and a second cladding layer covering the periphery of the core layer, a part of the core of the single waveguide is absorbed by the surrounding core An optical limiter circuit having different coefficients, wherein at least the single waveguide is formed using a semiconductor material, and an absorption coefficient is adjusted by changing a crystal defect amount of the semiconductor material.
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