JP5051411B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a magnetic semiconductor integrated circuit containing a magnetic element.

  Magnetic Random Access Memory (MRAM) using magnetic tunnel junction (MTJ) as a memory element is excellent in non-volatile recording, high-speed operation, and rewrite resistance. But expectation is high as being usable.

  FIG. 1 shows a structure of a general MTJ element used for a magnetic random access memory (MRAM). Referring to FIG. 1, the lower layer 111 of the MTJ element includes a conductor 101 and a lower magnetic layer. The lower magnetic layer includes an antiferromagnetic layer 102, a first ferromagnetic layer 103, a coupling layer 104, and a second ferromagnetic layer 105. The lower magnetic layer of the MTJ is connected to a circuit formed on the substrate via the conductor 101 and the through hole 106. As the antiferromagnetic layer 102, an IrMn layer, a PtMn layer, or the like having a thickness of about 10 to 20 nm is generally used. For example, a Ru layer having a thickness of about 1 nm is used for the coupling layer 104, and a CoFe layer, a CoFeB layer, or the like having a thickness of about 3 nm is generally used for the first ferromagnetic layer 103 and the second ferromagnetic layer 105. It is done. The coupling layer 104 couples the magnetizations of the first ferromagnetic layer 103 and the second ferromagnetic layer 105 in opposite directions by exchange interaction. The first ferromagnetic layer 103, the second ferromagnetic layer 105, and the coupling layer 104 are collectively referred to as a fixed layer (pinned layer). The magnetization direction of the fixed layer is fixed by the antiferromagnetic layer 102. In a normal operation, the magnetization direction of the fixed layer does not change with a magnetic field applied to the MTJ element.

  The MTJ element includes an upper magnetic layer 108. For the upper magnetic layer 108, for example, a NiFe layer, a CoFe layer, a CoFeB layer, or the like having a thickness of 2 to 5 nm is used. In the subsequent process, the element shown in FIG. 1 is covered with an interlayer insulating film, contacts are formed on the upper magnetic layer 108, and upper wiring is formed. In the case of the MTJ element, an external magnetic field is generated by a current flowing through the upper wiring. When there is no external magnetic field, the upper magnetic layer 108 has a magnetization direction that can be either parallel or anti-parallel to the magnetization direction of the second ferromagnetic layer 105. The shape anisotropy 108, crystal anisotropy, etc. are adjusted. The magnetization direction of the upper magnetic layer 108 can be changed according to “1” or “0” of data to be recorded. Therefore, the upper magnetic layer 108 is also called a free layer or a recording layer. As described above, information is recorded and held according to the relative magnetization direction of the upper magnetic layer 108 with the magnetization direction of the second ferromagnetic layer 105 as a reference.

  A thin tunnel barrier layer 107 is formed between the second ferromagnetic layer 105 and the upper magnetic layer 108 to form a tunnel junction. Depending on the relative magnetization direction of the upper electrode 108, the recorded information can be read based on the upper electrode 108, the tunnel barrier layer 107, the second ferromagnetic layer 105, and the change in the resistance value in the vertical direction of the element. Is possible. When the magnetizations of the second ferromagnetic layer 105 and the upper electrode 108 are antiparallel, the resistance value is large, and when the magnetizations of the second ferromagnetic layer 105 and the upper electrode 108 are parallel, the resistance value is small. Therefore, the relative magnetization direction of the upper electrode 108 on which information is recorded can be determined by examining the resistance value, and each resistance value becomes “1” or “0” in the data. It is associated. The area and width of the upper electrode 108 affect the resistance and reversal magnetic field of the MTJ element, and are important parameters that determine the read characteristics and write characteristics of the MTJ element.

    FIG. 1 shows a cross-sectional structure after the lower electrode 111 is processed using, for example, a silicon oxide hard mask. As a material of the antiferromagnetic layer 102 in the lower electrode 111, noble metals such as Ir and Pt are often used. As is well known, noble metals such as Ir and Pt have a low vapor pressure of halide, and are difficult to completely volatilize during processing.

  The tunnel barrier layer 107 of the MTJ element is very thin, about 1 nm. When the upper electrode 108 is patterned, it is necessary to accurately control the end of processing. If the upper electrode 108 is formed and deeply processed to the second ferromagnetic layer 105, the reattachment during the processing of the second ferromagnetic layer causes side surfaces of the lower electrode 111 and side surfaces of the tunnel barrier layer 107 to be formed. And the upper electrode 108 and the second ferromagnetic layer 105 are short-circuited. As a result, the function as the MTJ element is lost.

  Further, in order to prevent a short circuit between the upper electrode 108 and the second ferromagnetic layer 105 on the side surface of the tunnel barrier layer 107, if the upper electrode 108 is formed to be smaller than the lower electrode 111 in general in a planar shape, the lower electrode The side portion of the upper magnetic layer 108 is not exposed at the time of processing 111, and a short circuit in the tunnel element due to the reattachment can be prevented. However, even if the side portion of the upper magnetic layer 108 is not exposed, the reattachment 110 may cause a short circuit between the lower magnetic layer 111 and the upper wiring. As a result, the function as the MTJ element is lost.

  In the data write operation, the strength of the magnetic field generated in the upper magnetic layer 108 by the current flowing through the upper wiring depends on the distance between the upper wiring and the upper magnetic layer 108. That is, in order to reduce power consumption during data writing, it is necessary to make the interlayer insulating film thin and make the upper wiring as close to the upper magnetic layer 108 as possible. However, in a situation where the metal reattachment 110 is deposited on the side surface of the lower electrode 111, the reattachment 110 becomes a short circuit path, and it is difficult to reduce the thickness of the interlayer insulating film.

  As described above, in order to secure the manufacturing yield of a semiconductor integrated circuit using elements having magnetic layers above and below, particularly a semiconductor integrated circuit having tunnel junction elements such as MTJ, a planar shape larger than that of the upper magnetic layer 108 is used. It is necessary to design the lower magnetic layer 111 so as to have it. Further, when a memory is configured using such elements, when the memory cells are arranged in a two-dimensional array, the lower magnetic layer 111 is planarly arranged at intervals according to the resolution of the exposure apparatus used. It is necessary to arrange. FIG. 2 is a plan view showing a state when two elements are arranged using the conventional technique. As shown in FIG. 2, the element density is determined by the pattern density of the lower magnetic layer 111 on the semiconductor integrated circuit. The size of the upper magnetic layer 108 relative to the lower magnetic layer 111 is determined by the alignment accuracy of the exposure apparatus used, and the distance between the lower magnetic layers 111 is determined by the pattern resolution of the exposure apparatus.

If the pattern conversion difference at the time of processing the magnetic layer is ignored, the size of the lower magnetic layer 111 is
(Size of lower magnetic layer) = (Size of upper magnetic layer) + 2 × (Alignment accuracy) (1)
The pitch of the lower magnetic layer when the array is arranged is
(Lower magnetic layer pitch)
= (Size of lower magnetic layer) + (Exposure device resolution)
= (Size of upper magnetic layer) + 2 x (alignment accuracy) + (exposure device resolution) (2)
Determined by

  In connection with the above description, a method for manufacturing a semiconductor device is disclosed in Japanese Patent Laid-Open No. 9-270497. According to this conventional example, the dielectric film is formed on the first conductor film that becomes the lower magnetic layer of the capacitor formed on the semiconductor substrate, and the second conductor film is formed on the dielectric film. . The second conductor film is processed into the shape of the upper magnetic layer of the capacitor. The dielectric film is etched using the second conductor film processed into the shape of the upper magnetic layer as a mask. The first insulating film is formed so as to cover the side surfaces of the dielectric film and the second conductor film.

  Further, a method for manufacturing a capacitor is disclosed in Japanese Patent Laid-Open No. 2001-36024. In this conventional example, a lower magnetic layer, a dielectric layer, and an upper magnetic layer are sequentially formed on a substrate. An etching mask is formed on the upper magnetic layer. The dielectric layer is etched to a predetermined thickness by the first etching using the etching mask as a mask. An insulating layer is selectively formed on the side surface of the etched layer. The second etching is performed up to the lower magnetic layer using the etching mask and the insulating film as a mask.

A magnetic tunnel junction element is disclosed in Japanese Patent Application Laid-Open No. 2003-174215. In this conventional example, a first conductive material layer, an antiferromagnetic layer, a first ferromagnetic layer, a tunnel barrier layer, a second ferromagnetic layer, and a second conductive material layer are formed on an insulating film covering a substrate in order from the bottom. It is formed. Thereafter, selective etching is performed on the stack from the first ferromagnetic layer (or antiferromagnetic layer) to the second conductive material layer to form a separation groove, and a magnetic tunnel junction separated by the groove 38 is obtained. A magnetic tunnel is formed by subjecting a stack of the first conductive material layer and the antiferromagnetic layer (or a single layer of the first conductive material layer) to selective etching using a hard mask made of an insulating film as a selection mask to form a separation groove. A TMR element corresponding to the junction is obtained. In each TMR element, an end portion of the tunnel barrier layer is covered with an insulating material to prevent electrical short circuit or leakage.
JP-A-9-270497 JP 2001-36024 A JP 2003-174215 A

An object of the present invention is to provide a semiconductor integrated circuit in which deposition of redeposits is suppressed and a short circuit failure can be prevented.
Another object of the present invention is to provide a semiconductor integrated circuit having an element density exceeding the alignment accuracy and pattern resolution of an exposure apparatus while ensuring the element yield.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in [Best Mode for Carrying Out the Invention]. These numbers and symbols are added to clarify the correspondence between the description of [Claims] and the description of the best mode for carrying out the invention. ] Should not be used for interpretation of the technical scope of the invention described in the above.

In an aspect of the present invention, the semiconductor integrated circuit has a lower layer (306) of a two-terminal element formed directly or indirectly on the substrate (301) and a planar shape smaller than the lower layer (306). The two terminals formed between the upper layer (308) of the two-terminal element formed on the lower layer (306) and the lower layer (306) and the upper layer (308). An intermediate layer (307) of the element and an insulating layer (309, 310, 311) formed so as to cover the upper layer (308) and having an inclined portion at the upper end portion are provided. The planar shape of the insulating layers (309, 310, 311) and the planar shape of the lower layer (306) and the intermediate layer (307) are the same.
The insulating layer (309, 310, 311) includes a first insulating film (309) covering the upper layer (308) via the intermediate layer (307) and at least a part of the upper layer (308). A second insulating film (310) formed on the first insulating film (309) corresponding to the first insulating film (309), and around the second insulating film (310) on the first insulating film (309), You may comprise the 3rd insulating film (311) which has an inclination part in the said upper end part. The inclination angle of the inclined portion of the third insulating layer is preferably in the range of 20 degrees to 70 degrees with respect to the substrate normal.
The insulating layers (309, 310) correspond to a first insulating film (309) covering the upper layer (308) through the intermediate layer (307) and at least a part of the upper layer (308). And a second insulating film (310) formed on the first insulating film (309) and having an inclined portion at the upper end. The inclination angle of the inclined portion of the second insulating layer is preferably in the range of 20 degrees to 70 degrees with respect to the substrate normal.
In the above semiconductor integrated circuit, the lower layer (306) may include a metal layer containing one or more elements selected from the group consisting of Pt, Ir, Ru, Rh, Pd, and Mn. They generally have poor etching properties and are easily reattached during etching, but the present invention can reduce reattachment and prevent short circuit failure.
The lower layer (306), the intermediate layer (307), and the upper layer (308) may constitute a TMR element, and the intermediate layer (307) may be a tunnel barrier layer. The lower layer (306) may be a multilayer film using a metal layer containing one or more elements selected from the group consisting of Ni, Fe, and Co. The upper layer (308) may include a metal layer including one or more elements selected from the group of Ni, Fe, and Co. The tunnel barrier layer is an oxide layer or a nitride layer selected from Al or Mg.
In another aspect of the present invention, a method of manufacturing a semiconductor integrated circuit includes: forming a lower layer (306) of a two-terminal element directly or indirectly on a substrate (301); Forming an intermediate layer (307) of the two-terminal element, forming an upper layer (308) of the two-terminal element on the intermediate layer (307), patterning the upper layer into a desired shape, and An insulating layer (309, 310, 311) is formed so as to cover the layer (308) and have an inclined portion at the upper end, and the planar shape of the insulating layer (309, 310, 311) and the lower layer ( 306) and the intermediate layer (307) are formed by patterning the intermediate layer (307) and the lower layer (306) using the insulating layer as a mask so that the planar shapes thereof are the same.
Here, in the step of forming the insulating layer (309, 310, 311), a first insulating film (309) is formed on the intermediate layer (307) so as to cover the upper layer (308), and the upper portion is formed. A second insulating film (310) is formed on the first insulating film (309) so as to correspond to at least part of the layer (308), and the first insulating film (309) and the second insulating film ( 310), a third insulating film (311) is deposited, the third insulating film is etched back, and an insulating gradient is formed around the second insulating film (310) on the first insulating film (309). It may be achieved by forming part (311). At this time, the inclination angle of the insulating inclined portion (311) is preferably in the range of 20 degrees to 70 degrees with respect to the substrate normal.
The lower layer (306), the intermediate layer (307), and the upper layer (308) may constitute a TMR element, and the intermediate layer (307) may be a tunnel barrier layer.
At this time, the lower layer is a multilayer film, and the step of forming the lower layer (306) includes a layer containing one or more elements selected from the group of Pt, Ir, Ru, Rh, Pd, and Mn. You may have the step to form. In addition, the step of forming the lower layer (306) may include the step of forming a metal layer containing one or more elements selected from the group of Ni, Fe, and Co.
The step of forming the upper layer (308) may include the step of forming a metal layer containing one or more elements selected from the group consisting of Ni, Fe, and Co.
The tunnel barrier is preferably an oxide layer or a nitride layer selected from Al or Mg.

  According to the present invention, it is an object to reduce the thickness of an interlayer insulating film while suppressing the accumulation of redeposits during processing and ensuring the reliability of the interlayer insulating film. When the present invention is applied to an MRAM, the current magnetic field efficiency is improved by thinning the interlayer insulating film, and an MRAM with low power consumption can be provided. Further, according to the present invention, it is possible to increase the density in existing manufacturing equipment, so that it is possible to provide a lower cost semiconductor integrated circuit.

  Hereinafter, a semiconductor integrated circuit of the present invention, particularly a magnetic semiconductor integrated circuit, will be described in detail with reference to the accompanying drawings.

[First Embodiment]
FIG. 3 shows a cross-sectional structure of the magnetic semiconductor integrated circuit according to the first embodiment of the present invention. A circuit (not shown) including a transistor, a large number of wirings, and the like is formed over the semiconductor substrate 301. On such a substrate 301, first wiring layers 302 (302-1, 302-2) are formed. The wiring layer 302 is embedded with an insulating layer 303. An element 305 is disposed over the insulating layer 303. When the element 305 is, for example, a two-terminal magnetic tunnel junction (MTJ) element, the element 305 includes a lower magnetic layer 306, an upper magnetic layer 308, and a thin insulating layer 307 as an intermediate layer disposed therebetween. It has. Each of the lower magnetic layer 306 and the upper magnetic layer 308 is a multilayer film containing a magnetic element. For example, the lower magnetic layer 306 of the element 305 having the above-described configuration is connected to the first wiring layer 302 via the contact 304. Further, the first wiring layer 302 is connected to a circuit formed of a transistor, a large number of wirings, and the like formed on the substrate 301 at an appropriate position on the substrate.

  Specifically, the lower magnetic layer 306 of the MTJ element is a multilayer film including a Ta layer having a thickness of 50 nm, a PtMn layer having a thickness of 20 nm, a CoFe layer having a thickness of 3 nm, a Ru layer having a thickness of 1 nm, and a CoFe layer having a thickness of 3 nm. Is formed. As the ferromagnet, it is also possible to use a magnetic metal or magnetic alloy containing one or more elements selected from Fe, Co, Ni, etc. instead of CoFe, such as CoFeB. As the antiferromagnetic material, other antiferromagnetic materials such as IrMn and FeMn can be used instead of PtMn. The upper magnetic layer 308 in the MTJ element is specifically formed as a multilayer film such as a 5 nm thick NiFe layer, a 5 nm thick Ta layer, and a 50 nm thick TiN layer from the lower layer. Instead of NiFe, a magnetic metal or magnetic alloy containing one or more elements selected from Fe, Co, Ni, etc. may be used as the magnetic material. Further, even if the upper magnetic layer 308 is a multilayer film having a plurality of magnetic layers, an essential difference does not occur in the present invention. Further, the Ta layer is a layer for preventing the oxidation and diffusion of the magnetic metal, and can be replaced with another material if it meets the purpose. The TiN layer plays the role of a processing mask for processing and forming the upper magnetic layer 308 and an etching stopper layer for processing and forming the contact 313. If it meets the purpose, it can be replaced with another material. It is.

  In the cross-sectional view shown in FIG. 3, the element 305 further includes a thin protective insulating layer 309 covering the upper surface. The protective insulating layer 309 is for protecting the element 305 from plasma damage and chemical damage in the manufacturing process. For example, a 30 nm thick SiN layer is used. An insulating layer 310 is formed on the protective insulating layer 309 in a region inside the plane of the lower magnetic layer 306. Further, an insulating layer 311 is formed on the protective insulating layer 309 so as to surround the periphery of the insulating layer 310 on the plane. The upper end portion of the insulating layer 311 has a gently curved portion. The insulating layer 310 and the insulating layer 311 are used as a processing mask when the lower magnetic layer 306 is processed. That is, the planar shape obtained by adding the insulating layer 310 and the insulating layer 311 is a planar shape corresponding to the lower magnetic layer 306.

As shown in FIG. 3, the element 305 is further embedded with an insulating layer 312 made of, for example, SiO ₂ . A wiring 314 is formed over the insulating layer 312. A contact 313 is formed so as to penetrate the protective layer 309, the insulating layer 310, and the insulating layer 312 and connect the upper magnetic layer 308 and the wiring 314.

  In the MTJ element of the magnetic semiconductor integrated circuit according to the first embodiment of the present invention, the lower magnetic layer 306 contains Pt, which is a difficult-to-etch material, as in the conventional example. Therefore, the reattachment 315 is deposited around the lower magnetic layer 306 as in the conventional example. However, in the present invention, since a gently curved portion is formed at the upper end portion of the insulating layer 311 which is the periphery of the mask for processing the lower magnetic layer 306, the reattachment 315 grows in this portion. do not do. Therefore, even if the height of the redeposition material is lower than that of the conventional example and the thickness of the insulating layer 312 is reduced, the insulation between the lower magnetic layer 306 and the wiring 314 is sufficiently maintained, and the element yield does not decrease.

FIG. 4 shows the dependence of the etching rate of SiO ₂ on the incident angle of Ar ions with respect to the substrate normal. When physical etching is mainly used, as shown in FIG. 4, the etching rate on the inclined surface is higher than that on the flat surface or the vertical surface. This inclination angle is preferably in the range of 20 degrees to 70 degrees, and more preferably in the range of 20 degrees to 50 degrees. Since the lower magnetic layer 306 in the first embodiment of the present invention contains Pt, which is a difficult-to-etch material, physical etching is dominant during processing. Therefore, when a gentle curved portion is formed as an inclined surface in the periphery of the mask or an inclined surface having a specific inclination angle is formed, the etching rate in that portion increases, and the reattachment 315 grows. Is inhibited, and a short circuit between the lower magnetic layer 306 and the wiring 314 can be prevented. What is important here is that a curved surface portion that is not a flat surface or a vertical surface exists in the peripheral portion of the mask for processing the lower magnetic layer 306. In that respect, the effect is the same even if the upper end portion of the insulating layer 311 has an inclined surface having a specific angle. This is because the processing speed at the pattern edge is increased by providing a specific angle that is neither planar nor perpendicular to the edge of the process mask for adding the lower magnetic layer 306 and changing the relative incident angle of ions. It is based on the principle of increasing and inhibiting the growth of redeposits.

Next, the effect of the present invention will be described with reference to the plan view of FIG. In the manufacturing process of a semiconductor integrated circuit by general photolithography and dry etching techniques, the minimum processing dimension of etching is usually smaller than the resolution of photolithography. here,
2 × LSW = (lithographic resolution) − (minimum processing dimension) (3)
It is defined as When two magnetic layers of the lower magnetic layer 306 and the upper magnetic layer 308 are used in the element as in the semiconductor integrated circuit of the present invention, and the lower magnetic layer 306 is made larger than the upper magnetic layer 308 in a planar size. The size of the lower magnetic layer 306 relative to the upper magnetic layer 308 is designed using an overlap amount determined according to the alignment accuracy of the exposure apparatus used. This is the same as in the prior art. However, here, the amount of overlap is calculated using the LSW of equation (1).
(Overlap amount) = (Alignment accuracy) −LSW (4)
And decide. Therefore, the size of the lower magnetic layer is
(Design size of lower magnetic layer) = (Size of upper magnetic layer) + 2 × (overlap amount)
= (Size of upper magnetic layer) + 2 x (alignment accuracy)
-2 x LSW (5)
Is determined. On the photomask, the lower magnetic layer 306 is designed with the size of the formula (5), and the mask pattern of the lower magnetic layer 306 with the size of the formula (5) is subjected to optical restrictions. Therefore, the pitch of the lower magnetic layer 306 at the time of arranging the array of memory cells is
(Lower magnetic layer pitch) = (design size of lower magnetic layer) + (exposure device resolution)
= (Size of upper magnetic layer) + 2 x (alignment accuracy)
-2 x LSW + (exposure device resolution) (6)
Determined by It can be seen that the pitch can be reduced by 2 × LSW as compared with the lower magnetic layer pitch of the conventional example of Formula (2). The size of the LSW is nothing but the size of the insulating layer 311 in the cross-sectional view of the present invention shown in FIG.

  As described above, according to the present invention, it is possible to suppress deposition of redeposits during processing, prevent a decrease in reliability of the interlayer insulating film, and reduce the thickness of the interlayer insulating film. At the same time, the element density can be improved.

  Further, when the lower magnetic layer 306 is processed, an inclined surface having an angle that is neither parallel nor perpendicular to the substrate surface is provided at the end of the mask, and the relative ion incident angle is changed. Thus, as described above, it is important to increase the processing speed of the pattern edge and inhibit the growth of the reattachment 315. In that respect, the insulating layer 311 is not used, but a gently curved portion or an inclined surface having a specific angle is formed in the peripheral portion of the insulating layer 310, and the lower magnetic layer is formed using the insulating layer 310 as a mask. Similar effects can be achieved by processing the layer 306. Although this method can reduce the number of manufacturing steps, it is impossible to increase the density of the elements utilizing the LSW described above. Therefore, the pitch of the lower magnetic layer 306 is defined by Expression (2) as in the conventional example, and the lithography resolution and alignment accuracy are directly reflected.

  Next, a method for manufacturing a magnetic semiconductor integrated circuit using the MTJ element according to the first embodiment of the present invention will be described with reference to FIGS. 6A to 6H. 6A to 6H show a cross-sectional view and a plan view of the MTJ element. In the plan view, two memory cells are shown.

  First, as shown in FIG. 6A, a wiring layer 302 (302-1, 302-2) is formed on a substrate 301 on which a circuit including a transistor, a large number of wirings, and the like is formed. The wiring layer 302 is an insulating layer. It is embedded at 303. A contact 304 is formed on the wiring layer 302 so as to penetrate the insulating layer 303. A lower magnetic layer 306 and a tunnel barrier film 307 are sequentially formed on the insulating layer 303 so as to be in contact with the contact. The lower magnetic layer film 306 is formed from the lower layer as a multilayer film such as a 50 nm thick Ta layer, a 20 nm thick PtMn layer, a 3 nm thick CoFe layer, a 1 nm thick Ru layer, and a 3 nm thick CoFe layer. As the ferromagnetic material, instead of CoFe, a magnetic metal or magnetic alloy containing one or more elements selected from Fe, Co, Ni, etc., such as CoFeB, can be used. As the antiferromagnetic material, other antiferromagnetic materials such as IrMn and FeMn can be used instead of PtMn. The tunnel barrier film 307 has a thickness of about 0.5 nm to 3 nm, and is an oxide, nitride, oxynitride, fluoride film such as Al, Mg, SiHf, Ta, Ca, Zr, Alternatively, they are formed of a composite film thereof. Further, the upper magnetic layer 308 is formed. The upper magnetic layer 308 is formed from the lower layer as a multilayer film such as a 5 nm thick NiFe layer, a 5 nm thick Ta layer, and a 50 nm thick TiN layer. Instead of NiFe, it is also possible to use a magnetic metal or magnetic alloy containing one or more elements selected from Fe, Co, Ni, etc., instead of NiFe. Further, the Ta layer is a layer for preventing the oxidation and diffusion of the magnetic metal, and can be replaced with another material if it meets the purpose. The TiN layer serves as an etching stop layer when forming a mask and a contact 313 when processing the upper magnetic layer 308. If it meets the purpose, it can be replaced with other materials. In FIG. 6A, the upper magnetic layer film 308 has already been patterned into the shape of the upper magnetic layer of the MTJ element.

  Next, as shown in FIG. 6B, a thin protective insulating layer 309 and an insulating layer 310 are formed so as to cover the entire wafer surface. This protective insulating layer 309 is for protecting the device from plasma damage and chemical damage in the manufacturing process, and for example, a silicon nitride layer having a thickness of 30 nm is used. The insulating layer 310 is a layer used as a processing mask when processing the lower magnetic layer film 306 and the tunnel barrier film 307 into a desired element shape. For example, a silicon oxide layer having a thickness of 100 nm is used.

  As shown in FIG. 6C, the resist pattern 316 is formed by a general photolithography process in order to process the lower magnetic layer film 306 and the tunnel barrier film 307 into a desired element shape. As shown in FIG. 6C, the formed resist patterns 316 are arranged at intervals of lithography resolution, and the size is defined by Expression (5). The resist pattern 316 is aligned with respect to the upper magnetic layer film 308. FIG. 6C shows a state in which misalignment depending on the alignment accuracy of the exposure apparatus occurs.

  Next, as illustrated in FIG. 6D, the insulating layer 310 is processed into the shape of the resist pattern 316. For processing, a reactive ion etching method using an F-based gas is generally used. The thin protective insulating layer 309 is used as an etching stopper in this processing. After this processing, the resist pattern 316 is removed using, for example, oxygen plasma. At this time, the protective insulating layer 309 plays a role of protecting the element from damage of oxygen plasma.

  Next, as shown in FIG. 6E, silicon nitride is formed as an insulating layer 311 on the entire surface by, eg, CVD. The insulating layer 311 is subsequently etched back by a reactive ion etching method using, for example, an F-based gas.

  As a result, the insulating layer 311 is left only around the plane of the insulating layer 310 as shown in FIG. 6F. At this time, the size LSW of the insulating layer 311 remaining only around the insulating layer 310 is determined by Expression (3). Therefore, the process conditions such as the film thickness of the insulating layer 311 and the etch-back processing conditions are determined in advance so that the LSW determined by Expression (3) is obtained. In order to obtain the size LSW of the silicon nitride 311, it may be necessary to adjust the thickness of the insulating layer 310. In FIG. 6F, the second insulating layer 310 and the insulating layer 311 formed therearound are used as a processing mask when processing the lower magnetic layer 306 in the next step. By using the LSW determined by Equation (3) and the design size of the lower magnetic layer determined by Equation (5), an appropriate pattern is designed to align the upper magnetic layer 308 and the lower magnetic layer 306. The deviation is effectively eliminated. Further, a sidewall formed by an etch-back method like the insulating layer 311 generally has a gentle curvature at the upper end.

Next, as shown in FIG. 6G, the protective insulating layer 309 and the lower magnetic layer 306 are processed by Ar milling, for example, using the insulating layer 310 and the insulating layer 311 formed therearound as a processing mask. The element is separated by this processing, and two MTJ elements 305 are formed in FIG. 6G. Since the lower magnetic layer 306 includes a difficult-to-etch material such as Pt, Ru, or Ir, a reattachment 315 at the time of processing is formed around the element 305. However, since the insulating layer 311 has a gentle curvature at the upper end portion, the reattachment is difficult to grow. This mechanism is as described above.
Next, as shown in FIG. 6H, the element 305 is further embedded with an insulating layer 312 made of, for example, silicon oxide, and penetrates the protective layer 309, the insulating layer 310, and the insulating layer 312 on the upper magnetic layer 308. A contact 313 is formed. Thus, the wiring 314 and the upper magnetic layer 308 are connected via the contact 313.

  According to the manufacturing method of the present invention, the upper end portion of the insulating layer 311 corresponding to the periphery of the processing mask of the lower magnetic layer 306 has a gently curved portion. For this reason, the reattachment 315 does not grow in this part. Therefore, even if the height is lower than the redeposition material in the conventional example and the thickness of the insulating layer 312 is reduced, the insulating properties of the lower magnetic layer 306 and the wiring 314 are sufficiently maintained, and the element yield does not deteriorate. In addition, the size L316 of the lower magnetic layer can be designed in advance using the size LSW of the insulating layer 311, and the element pitch can be reduced by 2 × LSW compared to the conventional example. It becomes.

  When attention is paid only to the insulation between the lower magnetic layer 306 and the wiring 314, the formation of the insulating layer 311 is not necessarily essential. The mechanism for improving the insulation is as described in the first embodiment. In this case, instead of forming the insulating layer 311, a process of providing a slope or a curved surface on the upper surface of the peripheral region of the insulating layer 310 is used. Even at this time, the insulation reliability of the lower magnetic layer 306 and the wiring 314 is ensured.

FIG. 1 is a cross-sectional view showing the structure of a conventional MTJ element used in an MRAM. FIG. 2 is a plan view showing a state when two elements are arranged using a conventional technique. FIG. 3 is a sectional view showing a sectional structure of the magnetic semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 4 is a graph showing the dependence of the etching rate of SiO ₂ on the incident angle of Ar ions with respect to the substrate normal. FIG. 5 is a plan view of an MTJ element showing the effect of the present invention. FIG. 6A is a cross-sectional view and a plan view showing a method for manufacturing a magnetic semiconductor integrated circuit using MTJ elements according to the first embodiment of the present invention. FIG. 6B is a cross-sectional view and a plan view showing the method for manufacturing the magnetic semiconductor integrated circuit using the MTJ element according to the first embodiment of the present invention. FIG. 6C is a cross-sectional view and a plan view showing the method for manufacturing the magnetic semiconductor integrated circuit using the MTJ element according to the first embodiment of the present invention. FIG. 6D is a cross-sectional view and a plan view showing the method for manufacturing the magnetic semiconductor integrated circuit using the MTJ element according to the first embodiment of the present invention. FIG. 6E is a cross-sectional view and a plan view showing the method for manufacturing the magnetic semiconductor integrated circuit using the MTJ element according to the first embodiment of the present invention. FIG. 6F is a cross-sectional view and a plan view showing the method for manufacturing the magnetic semiconductor integrated circuit using the MTJ element according to the first embodiment of the present invention. FIG. 6G is a cross-sectional view and a plan view showing the method for manufacturing the magnetic semiconductor integrated circuit using the MTJ element according to the first embodiment of the present invention. FIG. 6H is a cross-sectional view and a plan view showing the method for manufacturing the magnetic semiconductor integrated circuit using the MTJ element according to the first embodiment of the present invention.

Explanation of symbols

101, 301: substrate 102: antiferromagnetic layer 103, 105: ferromagnetic layer 104: coupling layer 106: contact 107: tunnel barrier layer 108: magnetic layer 109: insulating layer 302, 314: wiring 303: insulating layers 304, 313 : Contact 305: Element (MTJ element)
306: Lower magnetic layer 307: Insulating layer 308: Upper magnetic layer 309: Protective insulating film 310, 311: Insulating film 312: Interlayer insulating film

Claims (7)

A lower layer of the MTJ element formed directly or indirectly on the substrate;
And an upper layer before Symbol MTJ element formed on top of the lower layer so as to have a smaller plane shape than the lower layer,
An intermediate layer before Symbol MTJ element formed between the upper layer and the lower layer,
An insulating layer formed so as to cover the upper layer and having an inclined portion at the upper end;
The planar shape of the insulating layer and the planar shape of the lower layer and the intermediate layer are the same,
The insulating layer is formed on the first insulating film covering the upper layer on the intermediate layer and the first insulating film corresponding to at least a part of the upper layer, and has an inclined portion at the upper end. A semiconductor integrated circuit comprising a second insulating film. The semiconductor integrated circuit according to claim 1,
It said second insulation Enmaku is
A third insulating film formed on the first insulating film corresponding to at least a part of the upper layer;
A semiconductor integrated circuit comprising: a fourth insulating film formed on the first insulating film and around the third insulating film and having an inclined portion at the upper end. The semiconductor integrated circuit according to claim 2,
The inclination angle of the inclined portion of the fourth insulation Enmaku a semiconductor integrated circuit which angle about the substrate normal is in the range of 70 degrees from 20 degrees. The semiconductor integrated circuit according to any one of claims 1 to 3,
The lower layer includes a metal layer including one or more elements selected from the group consisting of Pt, Ir, Ru, Rh, Pd, and Mn. A semiconductor integrated circuit. The semiconductor integrated circuit according to any one of claims 1 to 4 ,
Before Symbol intermediate layer is a tunnel barrier layer,
The lower layer is a multilayer film using a metal layer containing one or more elements selected from the group of Ni, Fe, and Co. Semiconductor integrated circuit. The semiconductor integrated circuit according to claim 5,
The upper layer includes a metal layer containing one or more elements selected from the group of Ni, Fe, and Co. Semiconductor integrated circuit. The semiconductor integrated circuit according to claim 5 or 6,
The tunnel barrier layer is an oxide layer or a nitride layer selected from Al or Mg. Semiconductor integrated circuit.

Images