JP5043088B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine configured with a computer circuit, and more particularly to a gaming machine that can effectively eliminate fraudulent games and can quickly and appropriately respond to abnormalities in a random number generation circuit.

  A ball and ball game machine such as a pachinko machine has a symbol start port provided on the game board, a symbol display unit for displaying a series of symbol variation modes such as stopping a plurality of display symbols after varying a predetermined time, and an opening / closing plate It is configured with a grand prize opening that opens and closes. When the detection switch provided at the symbol start port detects the passing of the game ball, the game ball is in a winning state and the symbol display unit changes the display symbol for a predetermined time. Thereafter, when the symbol stops in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a profit state advantageous to the player.

  Whether or not to enter the big hit state is determined based on, for example, a random number value at the time of winning when the game ball passes through the symbol start opening. That is, when a predetermined winning state is generated in relation to the player's gaming operation, it is determined whether or not to generate a profit state advantageous to the player by a lottery determination using a random value resulting therefrom.

  Random numbers used for winning / failing lotteries are generated by software counters that are updated every predetermined time by program processing and by hardware counters that are automatically updated without program processing There are cases. Here, it is said that a random number generation circuit using a hardware counter is effective in preventing illegal games since the update speed can be significantly increased as compared with the case of using a software counter.

  However, when generating random values using a hardware counter random number generation circuit, especially in order to maintain normal lottery processing, it is particularly safe from the failure of the counter circuit and the oscillation circuit provided in the preceding stage. Measures are required. Therefore, various proposals have been made from the viewpoint of such countermeasures (for example, Patent Document 1).

  In the invention described in Patent Document 1, a clock signal generation unit that generates a clock signal of a predetermined frequency, a numerical data update unit that updates numerical data based on the clock signal, and whether or not updating of numerical data is stopped A monitoring unit that monitors whether or not the updating of numerical data is stopped to the game control microcomputer.

JP 2004-097576 A

  However, there are various problems in the countermeasure of the above-mentioned Patent Document 1. First, there is a problem that the circuit configuration of the monitoring circuit is extremely complicated. That is, the monitoring circuit described in Patent Document 1 includes a counter unit that receives a clock signal from a clock signal generation unit, a timer circuit that outputs a time-up signal every predetermined time, and data in the counter unit every time the time-up signal is received. Therefore, it is necessary to separately provide an abnormality determination circuit that compares this with the data of the previous counter unit, and a storage unit that stores data acquired every time from the counter unit, and the circuit configuration is extremely complicated. In particular, the abnormality determination circuit cannot be realized by a simple coincidence circuit, and requires a writing function to the storage unit and a reading function from the storage unit, and the circuit configuration must be considerably complicated.

  In addition, since the monitoring circuit of Patent Document 1 monitors oscillation abnormality using a counter that is completely different from the counter for generating random numbers, there is a problem that only the oscillation stop of the clock signal generation unit can be detected at most. . In the first place, in view of the importance of the random number generation circuit, not only an abnormality in which the oscillation of the oscillation circuit has completely stopped, but also a circuit that can determine, for example, a subtle abnormality in which the specific bit of the random number generation counter does not change A configuration is highly desired.

  Furthermore, in the invention of Patent Document 1, there is a problem that when an oscillation abnormality is detected, the state is only notified to the outside, and even the minimum self-recovery function is not exhibited at all. In addition, even if it detects a modification of the random number generation circuit by a fraudulent player, it only stops informing the abnormal situation, for example, there is a possibility that the fraudulent game may be continued in a state where the surroundings of the gaming machine are blocked by a fence, It is not perfect as a countermeasure against illegal games.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a gaming machine capable of detecting an operation abnormality of a random number generation circuit with a simple circuit configuration. Another object of the present invention is to provide a gaming machine that can detect a subtle operation abnormality of the random number generation circuit, not only when the oscillation operation of the random number generation circuit is stopped. Still another object of the present invention is to provide a gaming machine that exhibits a self-recovery function when an abnormal operation of a random number generation circuit is detected, and a gaming machine that functions effectively against illegal games.

In order to achieve the above object, the present invention is advantageous in that when the detection switch detects a predetermined detection state related to the operation of the player, the main control unit executes a lottery determination based on the detection state. A gaming machine that determines whether or not to generate a state, and is provided with a random number generation circuit that automatically updates a random number value used in the lottery determination, and the random number generation circuit is supplied to a CPU of the main control unit An oscillator that oscillates a clock signal independent of the system clock, a counter that receives the clock signal and executes a counting operation, and receives the first and second latch signals whose timings are not synchronized with each other, and receives the count value of the counter It is configured to have a first and second latch circuits each for obtaining said first latch circuit, said first latch signal outputted from the detection switch corresponding to the detected state While being configured to receive said second latch circuit is configured to receive the second latch signal outputted from the CPU to the predetermined cycle, said first latch circuit receives the first latch signal and functioning conditions, an acquisition process of acquiring the output value of said first latch circuit and the second latch circuits, respectively, obtains values from the first latch circuit, and acquire values from the second latch circuit, The validity of the acquired value of the first latch circuit is determined based on whether or not it falls within a predetermined range defined based on the oscillation period of the clock signal and the output period of the second latch signal Determination processing to be performed.

  In the present invention, the predetermined detection state typically means a detection state that a game medium has passed a predetermined position. For example, a detection state that a game ball is in a winning state in the case of a ball game machine or that a game medium has been inserted in a spinning game machine is included.

  Preferably, the main control unit has a main process that is started after power-on and repeats an infinite loop process, and a timer interrupt process that is periodically started by interrupting the main process to execute a game operation. The second latch signal is output in synchronization with the start of the timer interrupt process.

  According to the above-described present invention, it is possible to realize a gaming machine that can detect an abnormal operation of the random number generation circuit with a simple circuit configuration. Further, not only the case where the oscillation operation of the random number generation circuit is stopped but also a subtle operation abnormality of the random number generation circuit can be detected. Furthermore, when an abnormal operation of the random number generation circuit is detected, a self-recovery function can be exhibited.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated in detail the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. A part of internal circuit of a power supply board is illustrated. It is a circuit diagram which shows the remaining part of the internal circuit of a power supply board, and shows the connection relation with a main control board. It is a circuit diagram which shows the internal circuit of a random number generation board, and shows the connection relation with a main control board. The internal configuration and operation contents of the one-chip microcomputer are illustrated. It is a flowchart which shows the operation | movement content of a main control part. FIG. 7 is a circuit diagram showing a modification of the circuit configuration of FIG. 6. FIG. 5 is a circuit diagram showing a modification of the circuit configuration of FIG. 4. It is a flowchart explaining the main process and NMI interruption process of a main control part. It is a circuit diagram which shows the internal circuit of the random number generation board which is a modification, and shows the connection relation with the main control board.

  Hereinafter, the embodiment of the present invention will be described in detail based on the ball game machine according to the embodiment. FIG. 1 is a front view showing a pachinko machine according to the present embodiment. The illustrated pachinko machine includes a rectangular frame-shaped wooden outer frame 1 that is detachably attached to an island structure, and a front frame 3 that is pivotally mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be freely opened and closed.

  An upper plate 8 for storing game balls for launch is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowing from or extracted from the upper plate 8 and a launch handle 10 are mounted at the bottom of the front frame 4. And are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, the game board 5 is provided with a guide rail 13 formed of a metal outer rail and an inner rail in an annular shape, and a liquid crystal color display DISP is provided at the approximate center of the game area 5a inside. Has been placed. In addition, at a suitable place in the game area 5a, a symbol starting port 15, a big winning port 16, a plurality of normal winning ports 17 (four on the right and left sides of the big winning port 16), and a gate 18 serving as two passing ports are arranged. Has been. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The liquid crystal display DISP is a device that variably displays a specific symbol related to a big hit state and displays a background image and various characters in an animated manner. This liquid crystal display DISP has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. The special symbol display portions Da to Dc execute a reach effect that expects a big hit state to be invited, and the special symbol display portions Da to Dc and the surroundings perform a notice effect that informs the result of the determination indefinitely. The

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the displayed normal symbol fluctuates for a predetermined time and is extracted at the time when the game ball passes through the gate 18. The stop symbol determined by the random number for lottery is displayed and stopped.

  For example, the symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 15a. The claw 15a is opened for a predetermined time. When a game ball wins the symbol start port 15, the display symbols of the special symbol display portions Da to Dc change for a predetermined time and are determined based on the lottery result corresponding to the winning timing of the game ball to the symbol start port 15. Stop at the stop symbol. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward. When the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit” Is started, and the opening / closing plate 16a is opened. A winning area 16 b is provided inside the big winning opening 16.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol of the special symbols, a privilege that the game after the end of the special game is in a high probability state is given. Usually, the big hit by this specific design is called “probable big hit”.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine 1 that realizes the above-described operations. Broken lines in the figure mainly indicate DC voltage lines.

  As shown in FIG. 3, the pachinko machine 1 receives AC 24V, outputs various DC voltages (5V, 12V, 32V, BU) and outputs a system reset signal SYS when the power is turned on, and a game operation The main control board 21 that centrally controls the effect, the effect control board 22 that executes the lamp effect and the sound effect based on the control command CMD received from the main control board 21, and the signal received from the effect control board 22 to each part The effect interface board 23 to be transmitted, the liquid crystal control board 24 for driving the liquid crystal display DISP based on the control command CMD ′ received from the effect interface board 23, and the payout motor based on the control command CMD ″ received from the main control board 21 The payout control board 25 for controlling the M to pay out the game ball, and the game ball in response to the player's operation It is organized around a firing control board 26 of firing.

  Here, the main control board 21, the effect control board 22, the liquid crystal control board 24, and the payout control board 25 are each mounted with a computer circuit including a one-chip microcomputer. Therefore, the functions mounted on the main control board 21, the production control board 22, the liquid crystal control board 24, and the payout control board 25 and the operations realized by the circuits are functionally named. Unit 21, effect control unit 22, liquid crystal control unit 24, and payout control unit 25. All or part of the effect control unit 22, the liquid crystal control unit 24, and the payout control unit 25 are sub-control units.

  4 and 5 are block diagrams showing the internal configuration of the power supply board 20. As shown in FIGS. 4 and 5, the power supply board 20 smoothes the output voltages of the three full-wave rectifier circuits 40 to 42 that convert AC 24 V into a pulsating voltage (DC 24 V), and the full-wave rectifier circuits 40 and 41. When the smoothing circuits 43a to 43d, the stabilized power supply circuits 44a to 44c using a three-terminal regulator, the backup power supply circuit 45 that maintains the DC voltage 5V even after the power supply is cut off, and the DC output voltage (12V, 5V) rise abnormally A forced cutoff circuit 46 that short-circuits the output of the full-wave rectifier circuit 40, a power reset circuit using a dedicated IC 47 (see the upper left column in FIG. 5), and the like are provided.

  The stabilized power supply circuits 44a to 44c are circuits that output DC voltages 5V, 12V, and 12V, respectively, and a power storage unit using a capacitor and a high-pass filter unit for noise suppression are provided on the output side. In this embodiment, the same DC voltage value DC12V is generated by two systems of circuits, one of which is supplied to the main control board 21 and the payout control board 25, and the other via the power relay board 30. This is supplied to the production interface board 23 and the liquid crystal control board 24 (see FIG. 3). This prevents high-frequency noise on the effect control board 22 side from being transmitted to the main control board 21 and the payout control board 25 through the power supply line.

  The backup power supply circuit 45 is composed of a diode and a large-capacity capacitor, and a DC5V backup power supply BU, which is the output of the backup power supply circuit 45, is supplied to the main control board 21 and the payout control board 25. The backup power BU is supplied to the RAM built in the one-chip microcomputer of each control board 21 and 25, and maintains the stored contents of the RAM even when the power is cut off (FIG. 7A). reference).

  The forced cutoff circuit 46 is configured by supplying two systems of direct current 12V and direct current 5V to an abnormal voltage detection unit composed of a current limiting resistor, a diode, and a Zener diode. When each voltage supplied to the abnormal voltage detection unit exceeds the reverse voltage of each chain diode and charges the capacitor to a predetermined level or more, the thyristor is energized and the pulsating voltage DC24V is short-circuited. . As a result, the energization of the main control board 21 and the payout control board 25 and the DC voltage 5V passing through the power relay board 30 are cut off at the same time, so that abnormal operation in each control board is avoided.

  As shown in the upper left column of FIG. 5, the power reset circuit is mainly configured by a system reset IC 47, an input prohibition circuit 48, and an output circuit 49 configured by a Schmitt trigger. The system reset IC 47 is a dedicated IC that automatically generates a system reset signal (power reset signal) SYS when the power is turned on and a power failure signal ABN when the voltage drops. For example, M5297P (RENESAS) is used. The

When the value of the pulsating voltage DC24V supplied to the AC input terminal of the system reset IC ₄₇ falls below the monitoring level for the monitoring time T _OFF2 or more, the abnormal signal ABN is operated to drop to the L level (FIG. 5 ( c)). Here, the monitoring time T _OFF2 is proportional to the product of the capacitor C2 and the resistor R2, but in this embodiment, the monitoring time T _OFF2 is designed to be about ₃₅ mS. Therefore, if the AC24V cutoff state recovers in less than 1 to 2 cycles (16 to 33 mS at 60 Hz), the power supply abnormality signal ABN is not output. By such an operation against instantaneous power failure, useless output operation of the system reset signal in a state where the DC voltage (12V, 5V) is maintained is avoided.

Further, as shown in FIG. 5C, the system reset IC ₄₇ is configured such that the system reset signal SYS falls to the L level after a predetermined time (T _D + T _OFF3 ) has elapsed since the power supply abnormality signal ABN falls. ing. Here, the drop delay time T _OFF3 is proportional to the product of the capacitor C3 and the resistor R3. In this embodiment, the predetermined delay time (T _D + T _OFF3 ) is used to control the main control unit 21 and the payout control. The highest priority interrupt processing (non maskable interrupt) in the unit 25 is finished. Therefore, in the main control unit 21 and the payout control unit 25, each CPU core is reset by the system reset signal SYS after necessary data is saved in the RAM area. The data saved in the RAM area is maintained for at least several days by the backup power supply BU.

As shown in FIG. 5B, in this system reset IC 47, when the AC input voltage AC24V is applied and the pulsating voltage DC24V is supplied to the AC input terminal of the system reset _IC47, after the first delay time _TON4 . The power supply abnormality signal ABN rises, and the system reset signal SYS rises after the second delay time _TON5 . Here, the delay time _{T ON5} and the delay time _{T ON4,} respectively, is proportional to the product of the capacitor C4, C5 and the resistor R4, R5, in the present embodiment, _T ON5 _{-T ON4} the CPU can not operate normally During this time period, the watchdog timer 53 of the main control unit 21 is automatically cleared by the logic circuits 51 and 52.

This point will be described with reference to the main control board 21 shown in the right column of FIG. As shown, the main control unit 21 includes a delay circuit 50, and 2 ^N-ary counter 51, an OR gate 52, and watchdog timer 53 is cleared processed is provided in the differential pulse of the output signal of the OR gate 52 ing. The system reset signal SYS generated by the power supply board 20 is supplied to the clear terminal CLR of the counter 51 via the delay circuit 50, while the system clock Φ is supplied to the clock terminal CLK of the counter 51. Therefore, during the period of the delay time _TON5 until the system reset signal SYS rises, the 2 ^N- ary counter 51 can count up, and the differential pulse of the count-up signal S1 becomes the clear signal WD of the watchdog timer 53. Will function as. Therefore, trouble that the watchdog timer 53 is in a free-running state and resets the CPU during a time period when the CPU of the main control unit 21 does not function is avoided.

  As described above, if the count-up signal S1 prohibits the watchdog timer 53 from entering the free-running state, the system reset signal SYS rises before long (see FIG. 5B), and thereafter the counter The counting operation of 51 is prohibited. However, thereafter, since the CPU periodically outputs the clear pulse S2, the self-running state of the watchdog timer 53 is continuously prohibited by the clear pulse S2. However, when the clear pulse S2 is interrupted due to a program runaway state or the like and the watchdog timer 53 is in a free-running state, the reset signal XURST is output and the CPU of the main control unit 21 is reset.

  On the other hand, when the power is turned on, the system reset signal SYS is delayed by the delay circuit 50 and becomes the reset signal XSRST, so that the CPU of the main control unit 21 is reset by the supply of the reset signal XSRST. Thus, in this embodiment, the CPU is reset by the XURST signal or the XSRST signal.

  Now, returning to the upper left column of FIG. 5A, the description of the power supply reset circuit of the power supply board 20 will be continued. The input prohibition circuit 48 of the power reset circuit is configured around two NOR gates and a switching transistor Q. Only when the system reset signal SYS is at the H level and the power supply abnormality signal ABN is at the L level, the two NOR gates output a signal at the H level to turn on the transistor Q.

The time zone of the power supply abnormality signal ABN = L and the system reset signal SYS = H is a time zone of T _D + T _OFF3 at the time of voltage drop, as shown in FIG. In this embodiment, in this transient state, the supply of the pulsating voltage DC24V to the AC input terminal of the system reset IC 47 is cut off by the ON operation of the transistor Q. Therefore, for example, an unstable signal or an unreasonable signal is output from the system reset IC 47 even when the AC input voltage AC24V is at a normal level, but for some reason, only when the DC voltage 5V is cut off or drops. This prevents the possibility of malfunction and prevents abnormal operation on each control board.

  Further, even when the power supply is cut off when the AC input voltage AC24V drops, abnormal operation of each control board is prevented. Therefore, even in the control boards 21 and 25 that execute data saving processing when the voltage drops, normal NMI Operation is guaranteed.

  Now that the description of the power supply board 20 has been completed, the main control board 21 will be described with reference to FIG. As described above, the main control board 21 receives the power supply abnormality signal ABN output from the power supply board 20 in addition to the DC12V, DC32V, and backup power supply BU (= DC5V) (see FIG. 4). The system reset signal SYS output upon power-on is received (see FIG. 5). In the main control board 21, the received DC 12V is stepped down to DC 5V, and used as the power supply voltage of the computer circuit in the board. As described above, the main control unit 21 does not receive the DC power supply voltage 5V directly from the power supply board 20, and therefore may receive high-frequency noise from the other control boards 25, 23, 22, 24 through the DC5V power supply line. Is avoided.

  The main control board 21 is connected to the command relay board 29 and is connected to each game component of the game board 5 via the game board relay board 27. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. Note that the switch signal from the symbol start port 15 is received directly by the main control unit 21 without going through the game board relay board 27.

  The main control unit 21 transmits a control command CMD ″ to the payout control unit 25 in one direction, while the payout control unit 25 receives a prize ball count signal indicating a game ball payout operation and a payout operation. The status signal CON related to the abnormality is received, and the status signal CON includes, for example, a replenishment out signal, a payout shortage error signal, and a lower plate full signal.

  Furthermore, the main control unit 21 supplies the power supply voltage 5 V to the random number generation board 28 and receives a random number value RND and a comparison value REF having a length of 16 bits, for example, from the random number generation board 28. This random number value RND is an extremely important numerical value used in the big hit lottery process for determining whether or not to shift the gaming state to the big hit state.

FIG. 6 is a block diagram showing the circuit configuration of the random number generation board 28 and the main part of the main control unit 21. Random number generating substrate 28 includes an oscillator 60 for oscillating a frequency of independent about 20MHz from the system clock [Phi, and 2 ^hexadecimal counter 61 for the counting operation in response to the output of the oscillator 60, disposed on the symbol start hole 15 The first latch 62 that receives the latch pulse from the winning detection switch and acquires the output value of the counter 61, and the second latch 63 that receives the latch signal LA from the main control unit 21 and acquires the output value of the counter 61 are the center. It is configured. ^{The two hexadecimal} counter 61 is circulated in the numerical range of 0 to 65535, it employs a ripple counter here.

  In this embodiment, a time-out signal TO that is output when the down-count operation of the built-in CTC of the one-chip microcomputer is completed is used as the latch signal LA output from the main control unit 21. The time-out signal TO will be described based on the internal configuration of the one-chip microcomputer (LE2080A / LL Tech) used in the embodiment.

  As shown in FIG. 7A, the one-chip microcomputer mounted on the main control unit 21 of the present embodiment includes a Z80PIO (parallel I / O) and a Z80CTC (Counter Timer Circuit). The Z80CTC adds periodic interrupts, a pulse output generation function (bit rate generator) with a constant period, and a time measurement function to the Z80 system, and is configured by integrating four 8-bit counters and timers. Yes.

In the main control unit 21 of the present embodiment, a timer interrupt for every 2 mS is realized by using the down-counting operation of Z80CTC (see FIG. 7B), but when the down-counting operation of 2 mS expires, A time-out signal TO is output from the one-chip microcomputer. Therefore, the second latch 63 in the random number generating substrate 28 in synchronization with the time-out signal TO (latch signal ^LA), has obtained a value of ^{2 hexadecimal} counter 61 (see FIG. 6).

By the way, the CPU core of the main control unit 21 executes a gaming operation in the timer interrupt process that occurs every 2 mS as shown in FIG. 7C, while the main process performs an infinite loop in the remaining time after the timer interrupt process ends. Processing is being executed. On the other hand, since the oscillator of the random number generation board 28 operates at 20 MHz, 65536 / 20M = 3.2768 mS is required for the ripple counter 61 to make a round of the numerical value range. Conversely, during 2mS timer interrupt ^{occurs, 2 hexadecimal} counter ^{61, 2 × 10 -3 × 20 ×} 10 6 = 40,000 only counting operation is that in progress.

Based on the above, timer interrupt processing in the main control unit 21 will be described. FIG. 8A is a flowchart showing a part of the processing contents of the timer interrupt. When the timer interrupt occurs, after completing the PUSH processing of the registers, the comparison value REF of the second latch 63 is acquired through the input port 7 1 (FIG. 6) (ST1). In order to prevent data and data loss, it is assumed that the same acquisition value REF is obtained by executing the IN instruction a plurality of times.

The acquired value REF in the processing of step ST1 is acquired at the time of the current timer interruption using the timeout signal TO as the latch signal LA, and should have a relationship of +40000 accurately compared to the previous acquired value. Therefore, the previous acquired value REF _OLD stored in the temporary storage area BUF is compared with the current acquired value REF (ST2). Then, taking some margin α (about 2 or 3) into consideration, a normal value is determined if REF _OLD + 40000−α <REF <REF _OLD + 40000 + α is satisfied, and an abnormal value is determined if the above condition is not satisfied. REF _OLD + 40000−α <REF <REF _OLD + 40000 + α may be caused by an abnormality that does not satisfy REF _OLD + 40000−α <REF _OLD + 40000 + α. In addition to the case where the 61 specific bit has failed in a fixed state, the counter value may be matched with the winning value by operating an illegal instrument.

  Therefore, if it is a normal value, the current acquired value REF is stored in the temporary storage area BUF (ST4), but if it is an abnormal value, an abnormality notification process is performed and the process proceeds to an infinite loop process. (ST5). The abnormality notification operation is performed using a liquid crystal display, a speaker, or an LED lamp, although not particularly limited. If the game control operation is stopped in such an abnormality notification process, the attendant will eventually cut off the AC power supply AC24V, replace the random number generation board 28, and turn on the AC power supply again. The machine will recover normally.

  FIG. 8B is a flowchart showing the operation content of the second embodiment. In this embodiment, the normal operation of the random number generation board 28 is determined only when a game ball is won at the symbol start port 15 instead of determining whether the counter 61 is normal every timer interruption.

  More specifically, after acquiring the ON / OFF states of all the switch signals including the symbol start port 15 (ST10), it is determined whether or not a winning to the symbol start port 15 is recognized (ST11). As described with reference to FIG. 6, when the game ball wins the symbol start opening 15, the random number generation board 28 should have acquired the value of the counter 61 in the first latch 62 using the switch signal as a latch pulse.

  Therefore, the main control unit 21 acquires the random value RND of the first latch 62 via the input port 70 (ST12). Further, the value of the second latch 63 is acquired as the comparison value REF via the input port 71 (ST13). In order to prevent data and data loss, the acquisition condition is that the same acquisition value is obtained by executing the IN command a plurality of times in these acquisition processes.

As shown in FIGS. 7B to 7D, the timing at which the game ball wins the symbol start opening 15 is the time from [T-2mS + τ] to [T + τ], where T is the time of the timer interruption. It is a belt. Note that τ is an elapsed time from the timer interrupt to the switch input process (ST10) (see FIG. 8B). Therefore, the random value RND acquired this time should be within the range of REF− (2 ms−τ) × (20 × 10 ⁶ ) to REF + τ × 20 × 10 ⁶ , based on the comparison value REF. Therefore, taking into account some margin β, it is determined whether it is normal or not by a determination formula of REF− (2 ms−τ) × (20 × 10 ⁶ ) −β <RND <REF + τ × 20 × 10 ⁶ + β (ST14) ). Needless to say, when the numerical value range of the counter exceeds 0 to 65535, an appropriate correction calculation is performed.

  If it is determined to be normal, a big hit lottery is performed using the random number RND acquired this time (ST15), but if it is determined to be abnormal, an abnormality notification process is performed and an infinite loop is performed as it is. The process proceeds to processing (ST16).

  The random number generation board 28 shown in FIG. 6 has been described above, but the circuit configuration is not limited to that shown in FIG. FIG. 9 illustrates another random number generation board 28, and illustrates a configuration in which the main control unit 21 controls the supply of the power supply voltage Vcc to the oscillator 60 and the ripple counter 61.

  That is, the main control unit 21 outputs the control signal CTL that is normally at the H level through the output port 72, and the output control signal CTL is supplied to the control terminal of the analog switch 64 in the pull-up state. . The input terminal of the analog switch 64 is supplied with the power supply voltage Vcc transmitted from the main controller 21, and the output terminal of the analog switch 64 is connected to the power supply lines of the oscillator 60 and the ripple counter 61.

  Since the control signal CTL is constantly at the H level, the oscillator 60 and the ripple counter 61 normally operate normally when supplied with the power supply voltage Vcc. However, when the control signal CTL becomes L level, the oscillator 60 and the ripple counter 61 stop their operations. The control signal CTL is supplied to the clear terminal CLR of the counter 61 through a delay circuit including a resistor and a capacitor and a NOT gate, and the counter 61 is cleared when the control signal CTL becomes L level. .

  FIG. 8C illustrates the operation contents when driving the random number generation board 28 of FIG. In this embodiment, instead of shifting to the infinite loop process after the abnormality notification process, a clear pulse that is at the L level for a predetermined time is output as the control signal CTL through the output port 72 (ST17). Therefore, this clear pulse causes the oscillator 60 and the ripple counter 61 to perform an operation of power-off → power-recovery, and the abnormal state may be recovered. Note that the ripple counter 61 is cleared to zero after a predetermined time from the restoration of the power supply.

  As described above, according to the control in FIG. 8C, the abnormal state of the random number generation board 28 may be automatically normalized, and the maintenance work by the staff may be eliminated. If the abnormal state does not recover, the abnormality notification process in step ST16 is repeatedly executed, so that it is possible to shift to maintenance work by a staff member.

  FIG. 10 illustrates another embodiment, and shows a part of the power supply board 20. In this embodiment, the AC input voltage AC24V of the power supply board 20 is collectively cut off and restored. 10 is used in combination with the random number generation board 28 of FIG. 6 and the main control board 21 of FIG.

  That is, in this embodiment, a one-shot multivibrator 66 that receives a control signal CTL from the output port 72 of the main control unit 21 and a relay circuit 67 that is controlled to open and close by the output of the one-shot multivibrator 66 are added to the power supply substrate 20. Has been. As the power source for the one-shot multivibrator 66 and the relay circuit 67, the backup power source BU and the like are used, so that these elements are not affected by the interruption of the AC voltage AC24V.

  As shown in FIG. 8C, in this embodiment, when the abnormality of the random number generation board 28 is detected (ST14), after the abnormality notification (ST16), the control signal CTL becomes L level. At the same time, a cut-off pulse CUT having a predetermined width is output from the one-shot multivibrator 66, and the AC input voltage AC24V is cut off for the duration of the pulse width.

When the AC input voltage AC24V is cut off, the power supply abnormality signal ABN of the dedicated IC ₄₇ falls to L level after a predetermined delay time _TOFF2 , and the main control unit 21 and the payout control unit 25 have the highest priority (NMI) interrupt processing program. Is started, and the value of the general-purpose register of the CPU is saved in the stack area (see FIG. 11B). When the saving process is completed, the backup flag BPF is set to 1. Note that the system is reset during the period (see FIG. _5C ) from when the stack area (RAM) is protected by the backup power supply BU and from when the power supply abnormality signal ABN falls to the delay time T _D + T _OFF3 . As described above, the signal SYS is configured not to fall, and the NMI processing time of FIG. 11B is sufficiently secured.

  Thereafter, when the cutoff pulse recovers to the H level, the AC input power supply AC24V is turned on, the system reset signal SYS is supplied from the power supply board 20 to each control board, and the CPU of each one-chip microcomputer is reset. In this case, the main control unit 21 and the payout control unit 25 check the value of the backup flag BPF at the first timing of the main processing. If BPF = 1, the data saved in the stack area is the general purpose of the CPU. It is restored to the register (see FIG. 11A). Then, after the backup flag BPF is cleared to zero, the gaming operation before the power stop is resumed.

  Also in this embodiment, since the abnormal operation of the oscillator 60 and the ripple counter 61 may be recovered by cutting off and restoring the power supply voltage, if the abnormality of the random number generation board 28 is recovered, FIG. Through the program processing of a), the game operation is resumed normally. On the other hand, if the random number generation board 28 remains in an abnormal state, the power reset operation is repeated. Therefore, in this embodiment, there is no adverse effect that the gaming state proceeds while the abnormal operation of the random number generation board 28 is left unattended.

  Although the embodiments of the present invention have been specifically described above, the specific description content is not intended to limit the present invention, and various modifications can be made. In particular, the circuit configurations and circuit elements specifically illustrated are naturally changed as appropriate. Of course, the process of step ST17 shown in FIG. 8C may be executed following step ST5 of FIG.

  Further, the operation check of the random number generation board 28 is not necessarily executed by the timer interrupt process, and may be executed by an infinite loop processing part provided at the end of the main process as shown in FIG. Further, the latch pulse of the second latch 63 does not necessarily need to be supplied from the main control unit 21, and as shown in FIG. 12, for example, the least significant bit (LSB) of the ripple counter 61 is provided inside the random number generation board 28. ) Data may be used as a latch pulse.

  The embodiment of FIG. 11C is preferably applied to the random number generation board 28 as shown in FIG. 12, and the comparison data REF of the second latch 63 is obtained from the input port 71 (ST21), and the immediately preceding comparison is performed. The value of the primary storage area BUF storing the data REF is compared (ST22). Then, it is determined whether or not the current acquired value is within a normal range, and if an abnormality is recognized, an abnormality notification process is performed (ST23).

  In this embodiment, after notifying the abnormality, the current acquired value is stored in the primary storage area BUF (ST26), and the progress of the game control operation is stopped by repeating the same processing (ST21 to ST23). is doing. Such a process is particularly suitable when combined with a circuit configuration as shown in FIG. 9 for resetting the power of the oscillator 60 and the counter 61 of the random number generation board 28.

  In addition, in the abnormality notification process including the case of other embodiments, it is preferable to notify abnormality in each gaming machine and transmit an alarm signal to a hall computer that collectively manages all gaming machines. If such a configuration is adopted, it is not possible to continue the illegal game by blocking the surroundings of the gaming machine with a fence, so it is not always necessary to shift to the infinite loop processing at the time of abnormality detection, even if the operation of the gaming machine proceeds good.

21 Main Control Unit RND Random Number 28 Random Number Generation Circuit 60 Oscillator 61 Counter 62 First Latch Circuit 63 Second Latch Circuit TO (LA) Second Latch Signal

Claims (3)

When the detection switch detects a predetermined detection state related to the player's action, a game machine that determines whether or not to generate a profit state advantageous to the player by executing a lottery determination due to the detection switch in the main control unit Because
A random number generation circuit for automatically updating a random number value used for the success / failure lottery is provided,
The random number generating circuit includes an oscillator for oscillating an independent clock signal from the system clock supplied to the CPU of the main control unit, a counter for performing a counting operation upon receipt of the clock signal, the no timing synchronized with each other A first latch circuit configured to receive the first latch signal and the second latch signal to obtain a count value of the counter, respectively, and a second latch circuit;
The first latch circuit is configured to receive the first latch signal output from the detection switch in response to the detection state, while the second latch circuit is output at regular intervals from the CPU. configured to receive said second latch signal that,
An obtaining process for obtaining the output values of the first latch circuit and the second latch circuit under the condition that the first latch circuit receives the first latch signal;
Obtaining values from the first latch circuit, and acquire values from the second latch circuit, and the oscillation period of the clock signal, and an output period of the second latch signal, within a predetermined range defined on the basis of based on whether contained, game machines, characterized in that a, the determination processing for determining authenticity of the acquired value of the first latch circuit. The main control unit has a main process that is started after power is turned on and repeats an infinite loop process, and a timer interrupt process that is interrupted to start the main process at regular intervals to execute a gaming operation. And
  The gaming machine according to claim 1, wherein the second latch signal is output in the timer interrupt process. The gaming machine according to claim 1 or 2, wherein when the validity is denied by the determination process, the power supply voltage of the gaming machine is temporarily stopped and then restored .

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