JP5036856B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a data bus configuration of a semiconductor memory device in which a memory array is arranged so as to surround a peripheral circuit region at the center of a chip.

  Conventionally, the storage capacity of a dynamic random access memory (DRAM) represented by a synchronous dynamic random access memory (SDRAM) has been mainly 2 n bits. In order to realize this capacity, the DRAM memory array or bank has mainly been in a 2 × 2 configuration, that is, a configuration in which it is arranged in 2 rows and 2 columns.

  However, in recent years, it has become technically difficult to improve the memory capacity in accordance with the conventional trend of developing a new DRAM having a memory capacity that is four times as large as three years. On the other hand, with the expansion of the information communication industry such as the spread of the Internet, there is a strong demand for memory capacity in the market. Under such circumstances, there has been a case where a DRAM having a capacity of 2 (2n + 1) -th power that deviates from the conventional trend has been developed. In such a DRAM, it is possible to adopt an irregular arrangement of the memory array instead of the conventional arrangement of 2 rows and 2 columns.

FIG. 14 is a diagram showing an example of an irregular arrangement of a conventional memory array.
Referring to FIG. 14, semiconductor memory device 500 includes four banks, that is, banks A to D. The banks A, B, C, and D are memory arrays AL, BL, CL, and DL that correspond to the memory arrays AU, BU, CU, DU corresponding to the upper data input / output terminals UDQ and the lower data input / output terminals LDQ, respectively. It is composed of The capacity of each memory array is 64M bits, and the capacity of each bank is 128M bits.

  That is, banks A, B, C, and D include memory arrays AU, BU, CU, and DU corresponding to the upper data input / output terminals, respectively.

  Banks A, B, C, and D further include memory arrays AL, BL, CL, and DL corresponding to lower data input / output terminals, respectively.

  Due to the shape of the unit unit of the memory cell, each memory array in which a plurality of memory cells are arranged in a matrix has a size with a short side of L and a long side of 2L. A column decoder band CPW is provided along one short side of each memory array. Column decoder band CPW includes a preamplifier and a write driver in addition to the column decoder. Each memory array is provided with a row decoder band RD along one long side.

  Semiconductor memory device 500 is divided into three rows and three columns. Memory arrays AL, DU, and DL are arranged in the regions of the first row, first column, the first row, second column, and the first row, third column, respectively. Memory arrays AU and CU are arranged in the regions of the second row and first column and the second row and third column, respectively. Memory arrays BL, BU, and CL are arranged in the regions of the third row, first column, the third row, second column, and the third row, third column, respectively.

  The region in the second row and the second column is the central region CEN. In the central area CEN, a plurality of pads PD and peripheral circuits (not shown) are arranged. The plurality of pads PD are divided and arranged in two rows parallel to the long side of the central region CEN. The first column close to the memory array DU includes pads corresponding to the lower data input / output terminals LDQ. The second column of pads PD closer to the memory array BU includes pads corresponding to the upper data input / output terminal UDQ.

  When the data input / output terminals for transmitting / receiving data receive 16-bit signals DQ0 to DQ15, the lower data input / output terminals LDQ are terminals for receiving signals DQ0 to DQ7, respectively. Terminal UDQ is a terminal for receiving signals DQ8 to DQ15.

  An example of the simplest data bus configuration corresponding to such a memory array arrangement is shown in FIG. Since the I / O line and the data bus in the memory array are connected to each other via a preamplifier and a write driver included in the column decoder band CPW arranged on the short side of the memory array, the data bus is connected to the short side of the chip. In parallel to the column decoder band CPW. These portions are connected to each other so that data can be transmitted between these portions and the data input / output terminals.

  The arrangement of the conventional memory array shown in FIG. 14 has not been sufficiently studied for the total extension of the data bus. In other words, in FIG. 14, in the arrangement of 3 rows and 3 columns, the semiconductor memory device 500 transmits data to the lower data input / output terminal LDQ and data to the lower data input / output terminal UDQ. A data bus 504 is provided.

  With this arrangement of the memory array, the total extension of the length of the data bus 502 is about 8L if the short side length of the memory array is L. In this case, the total length of the data bus is the longest. Since the load on the data bus itself is the largest, if the CAS latency at the time of data transmission / reception of the semiconductor memory device is short, there is a possibility that the frequency characteristic at the time of read operation is remarkably deteriorated. It also leads to an increase in effective data writing time, making it difficult to write data to the memory array at high speed.

  As described above, in an irregular array layout configuration in which a memory array is arranged around the central region, it may be difficult to meet the required specifications by adopting a simple memory array layout or data bus configuration. Is expensive.

  An object of the present invention is to provide a semiconductor memory device in which the operating frequency characteristics are improved by reducing the load of the data bus when the memory array is arranged so as to surround the peripheral circuit region at the center of the chip. Objective.

  A semiconductor memory device according to an aspect of the present invention is a semiconductor memory device formed in a memory region on the main surface of a semiconductor substrate, and is arranged in a central region in the memory region, and is arranged in a first region and a second region. An input / output terminal group, a plurality of first memory blocks that are arranged in a peripheral area surrounding the central area and exchange data with the first input / output terminal group, and a plurality of first memory blocks in the peripheral area with respect to the central area A plurality of second memory blocks arranged at positions symmetrical to the first memory block and surrounding the central area together with the first memory block, and for exchanging data with the second input / output terminal group A first data bus connecting the first input / output terminal group and the plurality of first memory blocks, and a second data bus connecting the second input / output terminal group and the plurality of second memory blocks. Provided with a door.

  Preferably, the surrounding area is divided into a first area and a second area, the plurality of first memory blocks are collectively arranged in the first area, and the plurality of second memory blocks are the second area Collectively placed in a region.

  Preferably, the semiconductor memory device transmits / receives a plurality of bits of data including a plurality of upper bits and a plurality of lower bits to the outside, and the first input / output terminal group transmits / receives a plurality of upper bits. The second input / output terminal group exchanges a plurality of lower-order bits.

  Preferably, the memory area is divided into 9 areas of 3 rows and 3 columns, the central area is an area of the second row and the second column of the nine areas, and the surrounding area surrounds the second row and the second column. , 9 of the 9 areas, and one of the plurality of first and second memory blocks is arranged in each of the 8 areas.

  Preferably, the first data bus includes, in the central region, a portion of the data transmission line having a wiring width wider than a wiring width in the surrounding region and a wide interval between adjacent wirings in the surrounding region.

  A semiconductor memory device according to another aspect of the present invention is a semiconductor memory device formed in a memory region on the main surface of a semiconductor substrate, and is arranged in a central region in the memory region. And a plurality of first memory blocks arranged in a peripheral region surrounding the central region, for exchanging data with the first input / output terminal group, and in the peripheral region, together with the first memory block A plurality of second memory blocks which are arranged so as to surround the area and exchange data with the second input / output terminal group, and a first input which connects the first input / output terminal group and the plurality of first memory blocks. A data bus, and a second data bus connecting the second input / output terminal group and the plurality of second memory blocks, and the second data bus is connected to one of the plurality of second memory blocks. Data exchange A first sub data bus and a second sub data bus for exchanging data with another one of the plurality of second memory blocks. The first sub data bus is disposed in the central area, and in accordance with an address signal, A selection circuit that selects any one of the second sub data buses and performs data exchange with the second input / output terminal group is provided.

  Preferably, the selection circuit includes a selector that selects one of the first and second sub data buses according to the address signal, a read data amplifier that amplifies read data transmitted through the selector, and read data An output buffer for outputting the output of the amplifier to the second input / output terminal group, an input buffer for receiving an input data signal externally applied to the second input / output terminal group, and first and second outputs according to the address signal A bus driver for selecting any one of the sub data buses and driving the selected sub data bus according to the output of the input buffer is included.

  Preferably, the selection circuit includes a main data bus that exchanges data with the second input / output terminal group, a first switch circuit that connects the main data bus and the first sub data bus according to an address signal, A second switch circuit for connecting the main data bus and the second sub data bus according to the address signal;

  Preferably, the memory area is divided into 9 areas of 3 rows and 3 columns, the central area is an area of the second row and the second column of the nine areas, and the surrounding area surrounds the second row and the second column. , 9 of the 9 areas, and one of the plurality of first and second memory blocks is arranged in each of the 8 areas.

  Preferably, the first data bus includes, in the central region, a portion of the data transmission line having a wiring width wider than a wiring width in the surrounding region and a wide interval between adjacent wirings in the surrounding region.

  The semiconductor memory device according to an aspect of the present invention can shorten the total length of the data bus and perform data transfer at high speed when the memory array is irregularly arranged so as to surround the central region.

  In addition, the total length of the data bus may be shortened when the data terminals are arranged in the upper bit and the lower bit.

  In addition, when the memory area is divided into 3 rows and 3 columns and the second row and the second column are the central region, the total length of the data bus may be shortened.

  In addition, data can be exchanged at a higher speed by reducing the parasitic capacitance of the data bus.

  According to another aspect of the present invention, a semiconductor memory device is provided by providing a plurality of sub data buses for a plurality of memory blocks when the arrangement of the memory array is an irregular arrangement surrounding the central region. The total length of the sub data bus can be shortened, and data can be exchanged at high speed.

  In addition, when the memory area is divided into 3 rows and 3 columns and the second row and the second column are the central region, the total length of the data bus may be shortened.

  In addition, by reducing the parasitic capacitance of the data bus, it may be possible to exchange data at a higher speed.

1 is a schematic block diagram showing a configuration of a semiconductor memory device 1 according to a first embodiment of the present invention. FIG. 3 is a layout diagram for explaining a semiconductor memory device 40 as a first example of the memory array layout and data bus routing according to the first embodiment; 6 is a diagram for explaining a semiconductor memory device 50 as a second example of the memory array arrangement and the data bus routing according to the first embodiment; FIG. FIG. 4 is a layout diagram showing a semiconductor memory device 60 as a third example of the memory array layout and data bus routing according to the first embodiment. FIG. 7 is a layout diagram for explaining a semiconductor memory device 70 as a fourth example of the memory array layout and data bus routing according to the first embodiment; FIG. 10 is a layout diagram for explaining a semiconductor memory device 80 which is a data bus configuration example of a second embodiment; FIG. 7 is a block diagram illustrating a configuration of a selection circuit SEL in FIG. 6. FIG. 10 is a layout diagram showing a semiconductor memory device 110 which is a modification of the data bus configuration. FIG. 10 is a layout diagram for explaining a semiconductor memory device 120 which is a configuration example of a data bus according to a third embodiment. FIG. 10 is a layout diagram illustrating a semiconductor memory device 140 that is a modification of the data bus configuration of the third embodiment. FIG. 10 is a layout diagram for explaining a data bus layout of a semiconductor memory device in a fourth embodiment; FIG. 12 is a cross-sectional view showing a cross section of a portion 162 of the data bus shown in FIG. 11. FIG. 12 is a sectional view showing a section of a data bus portion 164 in FIG. 11. It is the figure which showed an example of the irregular arrangement | positioning of the conventional memory array.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[Embodiment 1]
FIG. 1 is a schematic block diagram showing the configuration of the semiconductor memory device 1 according to the first embodiment of the present invention.

  Referring to FIG. 1, semiconductor memory device 1 includes memory array banks A to D each having a plurality of memory cells arranged in a matrix, address signals A0 to A12 and bank address signals BA0 to BA0 applied from the outside. Address buffer 2 that fetches BA1 in synchronization with clock signal CLKI and outputs an internal row address, internal column address, and internal bank address, and receives clock signal CLK and clock enable signal CKE from the outside are used inside the semiconductor memory device. Clock buffer 4 for outputting clock signals CLKI and CLKQ, and control signal input buffer for taking in control signals / CS, / RAS, / CAS, / WE and mask signal DQMU / L given from the outside in synchronization with clock signal CLKI 6 are included.

  The semiconductor memory device 1 further receives an internal address signal from the address buffer 2 and receives a control signal int. RAS, int. CAS, int. A control circuit that receives WE and outputs a control signal to each block in synchronization with a clock signal CLKI, and a mode register that holds an operation mode recognized by the control circuit. In FIG. 1, the control circuit and the mode register are shown by one block 8.

  The control circuit controls the internal bank address signal int. BA0, int. Bank address decoder for decoding BA1 and control signal int. RAS, int. CAS, int. And a command decoder for receiving and decoding the WE.

  The semiconductor memory device 1 is further provided corresponding to each of the memory array banks A to D. The row decoder decodes the row address signal X applied from the address buffer 2 and the memory array bank A according to the output signal of the row decoder. -D, and a word driver for driving the addressed row (word line) inside D to a selected state. In FIG. 1, the row decoder and the word driver are collectively shown as blocks 10 # 0 to 10 # 3.

  Semiconductor memory device 1 further includes column decoders 12 # 0-12 # 3 that decode internal column address signal Y applied from address buffer 2 to generate a column selection signal, and selected rows of memory array banks A-D. Sense amplifiers 16 # 0 to 16 # 3 for detecting and amplifying data of memory cells connected to.

  Semiconductor memory device 1 further includes an input buffer 22 that receives externally written data and generates internal write data, a write driver that amplifies internal write data from input buffer 22 and transmits the amplified internal write data to a selected memory cell. A preamplifier for amplifying data read from the selected memory cell, and an output buffer 20 for further buffering the data from the preamplifier and outputting the data to the outside.

  Preamplifiers and write drivers are provided corresponding to the memory array banks A to D, respectively. In FIG. 1, the preamplifier and the write driver are shown as blocks 18 # 0 to 18 # 3 as one block.

  The input buffer 22 and the output buffer 20 receive the clock signal CLKQ from the clock buffer 4 and send / receive data to / from the outside through the data input / output terminals DQ0 to DQ15 in synchronization with the clock signal CLKQ.

  FIG. 2 is a layout diagram for explaining a semiconductor memory device 40 as a first example of the memory array layout and data bus routing according to the first embodiment.

  Referring to FIG. 2, semiconductor memory device 40 is divided into three rows and three columns, and a memory array is formed in each region so as to surround a second row and second column region located in the center of these regions. An irregular memory array is arranged.

  The semiconductor memory device 40 includes four banks, that is, banks A to D. The banks A, B, C, and D are memory arrays AL, BL, CL, and DL that correspond to the memory arrays AU, BU, CU, DU corresponding to the upper data input / output terminals UDQ and the lower data input / output terminals LDQ, respectively. It is composed of The capacity of each memory array is 64M bits, and the capacity of each bank is 128M bits.

  That is, banks A, B, C, and D include memory arrays AU, BU, CU, and DU corresponding to the upper data input / output terminals, respectively.

  Banks A, B, C, and D further include memory arrays AL, BL, CL, and DL corresponding to lower data input / output terminals, respectively.

  Due to the shape of the unit unit of the memory cell, each memory array in which a plurality of memory cells are arranged in a matrix has a size with a short side of L and a long side of 2L. A column decoder band CPW is provided along one short side corresponding to each memory array. Column decoder band CPW includes a preamplifier and a write driver in addition to the column decoder. A row decoder band RD is provided along one long side corresponding to each memory array.

  Memory arrays AL, DL, and DU are arranged in the regions of the first row, first column, the first row, second column, and the first row, third column, respectively. Memory arrays AU and CL are arranged in the regions of the second row and first column and the second row and third column, respectively. Memory arrays BL, BU, and CU are arranged in the regions of the third row, first column, the third row, second column, and the third row, third column, respectively.

  Column decoder band CPW corresponding to memory array AL is arranged along the short side of memory array AL closer to the region of the first row and the second column. Row decoder band RD corresponding to memory array AL is arranged along the longer side of memory array AL closer to the region of the second row and first column.

  Column decoder band CPW corresponding to memory array DL is arranged along the short side of memory array DL closer to the region of the first row and the third column. Row decoder band RD corresponding to memory array DL is arranged along the long side of memory array DL closer to the region of the second row and second column.

  Column decoder band CPW corresponding to memory array DU is arranged along the short side of memory array DU closer to the region of the first row and the second column. Row decoder band RD corresponding to memory array DU is arranged along the long side of memory array DU closer to the region of the second row and the third column.

  Column decoder band CPW corresponding to memory array AU is arranged along the short side of memory array AU closer to the region of the second row and second column. Row decoder band RD corresponding to memory array AU is arranged along the long side of memory array AU closer to the region of the first row and first column.

  Column decoder band CPW corresponding to memory array CL is arranged along the short side of memory array CL closer to the region of the second row and the second column. Row decoder band RD corresponding to memory array CL is arranged along the long side of memory array CL closer to the region of the third row and third column.

  Column decoder band CPW corresponding to memory array BL is arranged along the short side of memory array BL closer to the region of the third row and second column. Row decoder band RD corresponding to memory array BL is arranged along the long side of memory array BL closer to the region of the second row and first column.

  Column decoder band CPW corresponding to memory array BU is arranged along the short side of memory array BU closer to the region of the third row and first column. Row decoder band RD corresponding to memory array BU is arranged along the longer side of memory array BU closer to the region of the second row and second column.

  Column decoder band CPW corresponding to memory array CU is arranged along the short side of memory array CU closer to the region of the third row and second column. Row decoder band RD corresponding to memory array CU is arranged along the long side of memory array CU closer to the region of the second row and third column.

  The region in the second row and the second column is the central region CEN. In the central area CEN, a plurality of pads PD and peripheral circuits (not shown) are arranged. The plurality of pads PD are divided and arranged in two rows parallel to the long side of the central region CEN. The first column near the memory array DL includes pads corresponding to the lower data input / output terminals LDQ. The second column of pads PD closer to the memory array BU includes pads corresponding to the upper data input / output terminal UDQ.

  When the data input / output terminal for transmitting / receiving data receives 16-bit signals DQ0 to DQ15, for example, the lower data input / output terminals LDQ are terminals for receiving signals DQ0 to DQ7, respectively. Input / output terminal UDQ is a terminal for receiving signals DQ8 to DQ15.

  In the arrangement shown in FIG. 2, the total extension of the data bus can be made shorter than 8L by devising the arrangement of the memory array constituting the bank.

  For example, when one of the two memory arrays arranged at point symmetry with respect to the central region CEN of the semiconductor memory device 40 is a memory array corresponding to the lower data input / output terminal LDQ, the other is the upper data The memory array is arranged so as to be a memory array corresponding to the input / output terminal UDQ.

  Specifically, in FIG. 2, the memory array AL in the first row and the first column is a memory array corresponding to the lower data input / output terminal LDQ, and is a position that is point-symmetric with the memory array AL with respect to the central region CEN. The memory array CU arranged in the third row and the third column is a memory array CU provided corresponding to the upper data input / output terminal UDQ. In addition, memory arrays DL, CL, and BL corresponding to lower data input / output terminals are arranged in the first row, second column, second row, third column, and third row, first column, respectively, and are point-symmetric with each other. The memory arrays BU, AU, and DU corresponding to the upper data input / output terminals are arranged in the regions of the third row and second column, the second row and first column, and the first row and third column, which are located at different positions. With this arrangement, the lower data bus 42 and the upper data bus 44 both have a total extension of 7L.

  In the arrangement shown in FIG. 2, since the memory arrays constituting the bank are adjacent to each other and the row decoder bands RD face each other or the column decoder bands CPW face each other, a circuit for generating a bank control signal The layout of the regions CROSS_S and CROSS_N in which are arranged is facilitated.

  Area CROSS_S is an area corresponding to banks A and B, and area CROSS_N is an area corresponding to banks C and D. In addition, signal wiring from the regions CROSS_S and CROSS_N to each memory array is facilitated.

  FIG. 3 is a diagram for explaining a semiconductor memory device 50 as a second example of the memory array arrangement and the data bus routing according to the first embodiment.

  Referring to FIG. 3, column decoder band CPW corresponding to memory array DL is arranged on the side of memory array AL in the region of the first row and first column on semiconductor memory device 50, and corresponds to memory array BU. The decoder band CPW is different from the arrangement example in the semiconductor memory device 40 shown in FIG. 2 in that the decoder band CPW is arranged on the memory array CU side in the region of the third row and the third column. The arrangement of other memory arrays, the arrangement of column decoder bands, and the arrangement of row decoder bands are the same as in the case shown in FIG. 2, and description thereof will not be repeated.

  When the arrangement of the memory array as shown in FIG. 3 is adopted, the lower data bus 52 can reduce the portion between the memory arrays DL and DU, as compared with the data bus 42 shown in FIG. Different. The upper data bus 54 is different from the data bus 44 shown in FIG. 2 in that the portion between the memory array BL and the memory array BU can be reduced. As a result, the total extension of each of the data buses 52 and 54 is about 6L, and further high-speed data transmission is possible. However, since the column decoder bands CPW of the memory arrays BL and BU included in the bank B are separated from each other as compared with the case shown in FIG. It becomes. The same can be said for bank D.

  FIG. 4 is a layout diagram showing a semiconductor memory device 60 as a third example of the memory array layout and the data bus routing according to the first embodiment.

  Referring to FIG. 4, in semiconductor memory device 60, memory arrays AU, BU, CU and DU corresponding to upper data input / output terminal UDQ are arranged in a concentrated manner. Similarly, memory arrays AL, BL, CL and DL corresponding to the lower data input / output terminals LDQ are arranged in a concentrated manner.

  Specifically, the memory arrays AL, BL, CL, and DL are respectively arranged in the first row, first column, the second row, first column, the third row, first column, and the third row, second column. The memory arrays AU, BU, CU, and DU are arranged in the third row and third column, the second row and third column, the first row and third column, and the first row and second column, respectively.

  The row decoder band RD corresponding to the memory array AL is provided along the long side on the region side of the second row and first column of the memory array AL. The column decoder band CPW corresponding to the memory array AL is provided along the short side on the region side of the first row and the second column of the memory array AL.

  The row decoder band RD corresponding to the memory array BL is provided along the long side on the region side of the first row and first column of the memory array BL. The column decoder band CPW corresponding to the memory array BL is provided along the short side on the region side of the second row and second column of the memory array BL.

  Row decoder band RD corresponding to memory array CL is provided along the long side of the memory array CL on the region side of the second row and first column. The column decoder band CPW corresponding to the memory array CL is provided along the short side on the region side of the third row and second column of the memory array CL.

  Row decoder band RD corresponding to memory array DL is provided along the long side of the memory array DL on the region side of the second row and second column. The column decoder band CPW corresponding to the memory array DL is provided along the short side on the region side of the third row and first column of the memory array DL.

  Row decoder band RD corresponding to memory array AU is provided along the long side of memory array AU on the second row and third column region side. The column decoder band CPW corresponding to the memory array AU is provided along the short side on the region side of the third row and the second column of the memory array AU.

  The row decoder band RD corresponding to the memory array BU is provided along the long side on the region side of the third row and third column of the memory array BU. The column decoder band CPW corresponding to the memory array BU is provided along the short side on the region side of the second row and second column of the memory array BU.

  The row decoder band RD corresponding to the memory array CU is provided along the long side on the region side of the second row and third column of the memory array CU. The column decoder band CPW corresponding to the memory array CU is provided along the short side on the region side of the first row and the second column of the memory array CU.

  Row decoder band RD corresponding to memory array DU is provided along the long side of memory array DU on the second row and second column region side. Column decoder band CPW corresponding to memory array DU is provided along the short side of the memory array DU on the region side of the first row and the third column.

  By adopting the arrangement of the memory array shown in FIG. 4, the lower data bus 62 and the upper data bus 64 can each have a total extension of 5L.

  FIG. 5 is a layout diagram for explaining a semiconductor memory device 70 as a fourth example of the memory array layout and data bus routing according to the first embodiment.

  Referring to FIG. 5, similar to semiconductor memory device 60 of FIG. 4, semiconductor memory device 70 has memory arrays AU, BU, CU and DU corresponding to upper data input / output terminals UDQ arranged in a concentrated manner. Memory arrays AL, BL, CL and DL corresponding to input / output terminals LDQ are arranged in a concentrated manner.

  Specifically, the memory arrays AL, BL, CL, and DL are arranged in regions of the second row and first column, the first row and first column, the first row and third column, and the first row and second column, respectively. The memory arrays AU, BU, CU, and DU are arranged in regions of a third row, first column, a third row, second column, a second row, third column, and a third row, third column, respectively.

  The row decoder band RD corresponding to the memory array AL is provided along the long side on the region side of the first row and first column of the memory array AL. The column decoder band CPW corresponding to the memory array AL is provided along the short side on the region side of the second row and second column of the memory array AL.

  The row decoder band RD corresponding to the memory array BL is provided along the long side on the region side of the second row and first column of the memory array BL. The column decoder band CPW corresponding to the memory array BL is provided along the short side of the memory array BL on the region side of the first row and the second column.

  The row decoder band RD corresponding to the memory array CL is provided along the long side on the region side of the second row and third column of the memory array CL. The column decoder band CPW corresponding to the memory array CL is provided along the short side on the region side of the first row and the second column of the memory array CL.

  Row decoder band RD corresponding to memory array DL is provided along the long side of the memory array DL on the region side of the second row and second column. Column decoder band CPW corresponding to memory array DL is provided along the short side of the first row and third column region side of memory array DL.

  The row decoder band RD corresponding to the memory array AU is provided along the long side on the region side of the first row and the second column of the memory array AU. The column decoder band CPW corresponding to the memory array AU is provided along the short side on the region side of the third row and the second column of the memory array AU.

  The row decoder band RD corresponding to the memory array BU is provided along the long side on the region side of the second row and second column of the memory array BU. The column decoder band CPW corresponding to the memory array BU is provided along the short side on the region side of the third row and first column of the memory array BU.

  The row decoder band RD corresponding to the memory array CU is provided along the long side on the region side of the third row and third column of the memory array CU. The column decoder band CPW corresponding to the memory array CU is provided along the short side on the region side of the second row and second column of the memory array CU.

  Row decoder band RD corresponding to memory array DU is provided along the long side of memory array DU on the region side of the second row and third column. Column decoder band CPW corresponding to memory array DU is provided along the short side on the region side of the third row and second column of memory array DU.

  If such a memory array arrangement is employed, the total extension of the data bus can be set to 5 L, respectively, as in the case shown in FIG.

  In addition, the region CROSS_S is arranged in the vicinity of the memory arrays belonging to the memory bank A and the memory bank B. Similarly, the region CROSS_N is arranged in the vicinity of the memory arrays belonging to the memory bank C and the memory bank D. Therefore, the control circuits of banks A and B can be concentrated in the region CROSS_S, the control circuits of banks C and D can be concentrated in the region CROSS_N, and the layout area of the bank control system including the signal wiring can be reduced. It is also possible to make it smaller than the case described in FIG.

  As described above, when one bank is composed of a plurality of memory arrays, the total length of the data bus can be further shortened by devising the arrangement of each bank memory array. Therefore, data propagation characteristics on the data bus can be improved.

[Embodiment 2]
In the first embodiment, the arrangement of the memory array is devised in order to shorten the total length of the data bus. As a result, the total length of the data bus can be improved from 8 L to the shortest 5 L, and the data propagation characteristics of the data bus are improved.

  However, the arrangement of the memory array is more complex than the case shown in FIG. 14, and bank control may be rather difficult. Further, it cannot be applied when the bank is composed of one memory array.

  Therefore, a configuration that can suppress the total extension of the data bus independently of the memory array arrangement is examined. In the second embodiment, the data bus corresponding to a certain data input / output terminal is divided into a plurality of sub data buses SDB in the chip, and the sub data bus for exchanging data is selected near the pad of the data input / output terminal. Think about what to do.

  FIG. 6 is a layout diagram for explaining a semiconductor memory device 80 which is a data bus configuration example of the second embodiment.

  Referring to FIG. 6, semiconductor memory device 80 is divided into three rows and three columns. Memory arrays AL, DU, and DL are arranged in the regions of the first row, first column, the first row, second column, and the first row, third column, respectively. Memory arrays AU and CU are arranged in the regions of the second row and first column and the second row and third column, respectively. Memory arrays BL, BU, and CL are arranged in the regions of the third row, first column, the third row, second column, and the third row, third column, respectively.

  The region in the second row and the second column is the central region CEN. In the central area CEN, a plurality of pads PD and peripheral circuits (not shown) are arranged. The plurality of pads PD are divided and arranged in two rows parallel to the long side of the central region CEN. The first column close to the memory array DU includes pads corresponding to the lower data input / output terminals LDQ. The second column of pads PD closer to the memory array BU includes pads corresponding to the upper data input / output terminal UDQ.

  In the vicinity of each data input / output terminal, a selection circuit SEL for selecting one of the two sub data buses SDB_S and SDB_N and exchanging data with the data input / output terminal is arranged. FIG. 6 typically shows one selection circuit SEL.

  The row decoder band RD corresponding to the memory array AL is provided along the long side on the region side of the second row and first column of the memory array AL. The column decoder band CPW corresponding to the memory array AL is provided along the short side on the region side of the first row and the second column of the memory array AL.

  The row decoder band RD corresponding to the memory array BL is provided along the long side on the region side of the second row and first column of the memory array BL. The column decoder band CPW corresponding to the memory array BL is provided along the short side on the region side of the third row and second column of the memory array BL.

  The row decoder band RD corresponding to the memory array CL is provided along the long side on the region side of the second row and third column of the memory array CL. The column decoder band CPW corresponding to the memory array CL is provided along the short side on the region side of the third row and second column of the memory array CL.

  The row decoder band RD corresponding to the memory array DL is provided along the long side on the region side of the second row and third column of the memory array DL. The column decoder band CPW corresponding to the memory array DL is provided along the short side on the region side of the first row and the second column of the memory array DL.

  The row decoder band RD corresponding to the memory array AU is provided along the long side on the region side of the first row and first column of the memory array AU. The column decoder band CPW corresponding to the memory array AU is provided along the short side on the region side of the second row and second column of the memory array AU.

  The row decoder band RD corresponding to the memory array BU is provided along the long side on the region side of the second row and second column of the memory array BU. The column decoder band CPW corresponding to the memory array BU is provided along the short side on the region side of the third row and first column of the memory array BU.

  The row decoder band RD corresponding to the memory array CU is provided along the long side on the region side of the third row and third column of the memory array CU. The column decoder band CPW corresponding to the memory array CU is provided along the short side on the region side of the second row and second column of the memory array CU.

  Row decoder band RD corresponding to memory array DU is provided along the long side of memory array DU on the second row and second column region side. Column decoder band CPW corresponding to memory array DU is provided along the short side of the memory array DU on the region side of the first row and the third column.

  Here, the short side of the chip close to the first row is called the S side, and the short side of the chip close to the third row is called the N side.

  In FIG. 6, a sub data bus 82 corresponding to the S side and a sub data bus 84 corresponding to the N side are provided. The sub data bus 82 is a data bus for transmitting data between the memory banks A and B and the pad. The sub data bus 84 is a data bus for transmitting data between the memory banks C and D and the pad. The sub data bus 82 is connected to the sub data bus SDB_S in the vicinity of the midpoint. Sub data bus SDB_S transmits data between the pad and sub data bus 82. The sub data bus 84 is connected to the sub data bus SDB_N in the vicinity of the midpoint. Sub data bus SDB_N transmits data between the pad and sub data bus 84.

  However, the configuration of the data bus shown in FIG. 6 representatively shows the data bus corresponding to the lower data input / output terminal side. The sub data buses SDB_S and SDB_N passing through the central area CEN pass through the area between the pad group corresponding to the terminal LDQ and the pad group corresponding to the terminal UDQ. You may pass through the area.

  In the arrangement shown in FIG. 6, since the DQ pad is on the N side from the center of the chip, the length reaching the memory array AL or memory array BL via the sub data bus SDB_S and the sub data bus 82 is the data propagation of the data bus Determine characteristics. Its length is 5L at the longest.

FIG. 7 is a block diagram showing a configuration of the selection circuit SEL in FIG.
Referring to FIG. 7, selection circuit SEL selects one of read data applied from sub data bus SDB_S and sub data bus SDB_N according to control signals RDAI_S and RDAI_N, and outputs of selector 92. A read data amplifier 94 for amplification and an output buffer 96 for outputting the output of the read data amplifier 94 to the pad 98 are included.

  The selection circuit SEL further includes an input buffer 100 that receives input data applied to the pad 98 from the outside, and a bus driver 102 that transmits the output of the input buffer 100 to the sub data bus SDB_S in response to the activation of the control signal WDT_S. The bus driver 104 outputs the output of the input buffer 100 to the sub data bus SDB_N in response to the activation of the control signal WDT_N.

  The control signal RDAI_S is activated when a read command is given from the outside and the bank A or B is designated. The control signal RDAI_N is activated when a read command is given from the outside and the bank D or C is designated.

  Control signal WDT_S is activated when a write command is applied from the outside and bank A or B is designated. Control signal WDT_N is activated when a write command is applied from the outside and bank C or D is designated. In this way, referring to the bank information accompanying the command input from the outside, one of the sub data buses SDB_S and SDB_N is selected.

  In brief, when read data is transmitted from the memory array to the selection circuit SEL, the control signal RDAI_S or RDAI_N is activated depending on whether the data is from the S side or the N side.

In response, selector 92 connects only one sub data bus to read data up.
Conversely, when write data is written to the memory array from the outside of the chip via the pad 98, the control signal WDT_S or WDT_N is activated according to the designated bank information, and the bus driver 102 corresponding to the S side or One of the bus drivers 104 corresponding to the N side is activated, and data is transmitted to an appropriate sub data bus.

FIG. 8 is a layout diagram showing a semiconductor memory device 110 which is a modification of the data bus configuration.
Referring to FIG. 8, semiconductor memory device 110 employs a memory array arrangement similar to that of semiconductor memory device 70 shown in FIG. Sub data bus 112 for transmitting data to memory array BL and memory array AL is connected to sub data bus SDB_S in the vicinity of the middle point thereof. Sub data bus SDB_S transmits data between sub data bus 112 and data input / output terminal LDQ. Sub data bus 114 for transmitting data to memory array DL and memory array CL is connected to sub data bus SDB_N. Sub data bus SDB_N transmits data between sub data bus 114 and data input / output terminal LDQ.

  In FIGS. 6 and 8, only the data bus corresponding to the lower data input / output terminal LDQ is representatively shown, but a similar sub data bus is also connected to the upper data input / output terminal UDQ. The configuration is adopted.

  That is, although not shown, in the configuration shown in FIG. 6, a first sub data bus for transmitting data to memory arrays AU and BU is provided along sub data bus 82, and data is transmitted to memory arrays DU and CU. A second sub data bus is provided along sub data bus 84. A selection circuit is provided that selects one of these two sub data buses and exchanges data with the higher-level data input / output terminal UDQ.

  Similarly, although not shown in FIG. 8, a first sub-data bus for transmitting data to memory arrays AU and BU and a second sub-data bus for transmitting data to memory arrays DU and CU are provided. It has been. When the configuration as shown in FIG. 8 is employed, the maximum length of the sub data bus can be suppressed to 4L.

  As described above, in the second embodiment, a data bus corresponding to a certain data input / output terminal is constituted by a plurality of sub data buses, and one of them is selected by a selection circuit provided near the pad, for example. Can suppress the total data bus extension. Therefore, data propagation characteristics on the data bus can be improved. More preferably, the total extension of the data bus can be further suppressed by devising the arrangement of the memory array.

[Embodiment 3]
In the second embodiment, the total extension of the data bus is suppressed by adopting the configuration of the sub data bus. It is conceivable to hierarchize the data bus as another data bus format that can achieve the same effect.

  FIG. 9 is a layout diagram for explaining the semiconductor memory device 120 which is a configuration example of the data bus according to the third embodiment.

  Referring to FIG. 9, semiconductor memory device 120 employs an arrangement similar to the arrangement of memory array, the arrangement of column decoder band CPW, and the arrangement of row decoder band RD shown in FIG.

  The semiconductor memory device 120 includes a main data bus 126 penetrating the central area CEN from the S side to the N side, a local data bus 122 for transmitting data to the memory array AL and the memory array BL, a memory array DL, A local data bus 124 for transmitting data to memory array CL is provided.

  The semiconductor memory device 120 is further provided with a switch 128 for connecting the main data bus 126 to the local data bus 122 and a switch 130 for connecting the main data bus 126 and the local data bus 124.

  The switches 128 and 130 and the main data bus operate in the same manner as the selection circuit SEL described with reference to FIG. That is, the connection control of the switches 128 and 130 is performed by referring to bank information attached to a command input from the outside as in the sub data buses SDB_S and SDB_N of the second embodiment.

  In this data bus configuration, the total extension of the data bus is 5 L because either one of the local data buses 122 and 124 is separated by the switch.

  Therefore, although there is an increase in load due to the provision of the switch, the data propagation characteristics on the data bus are greatly improved as compared with the configuration of the data bus shown in FIG. Further, since the total extension of the data bus is the same on the S side and the N side, the arrangement of the equalizing circuits is simplified. In addition, the input / output buffer circuit provided near the pad can be simplified.

  FIG. 10 is a layout diagram showing a semiconductor memory device 140 which is a modification of the data bus configuration of the third embodiment.

  Referring to FIG. 10, a memory array similar to semiconductor memory device 70 shown in FIG. 5 is arranged on semiconductor memory device 140. Each row decoder band RD and column decoder band CPW are similarly arranged as shown in FIG.

  A main data bus 146 is provided corresponding to the lower data input / output terminal LDQ. A local data bus 142 for transmitting data to the memory arrays AL and BL, and a switch 148 for connecting the local data bus 142 and the main data bus 146 are provided.

  The semiconductor memory device 140 is further provided with a local data bus 144 for transmitting data to and from the memory arrays CL and DL, and a switch 150 for connecting the local data bus 144 and the main data bus 146. .

  By adopting the memory array arrangement and the hierarchical data bus configuration as shown in FIG. 10, the total extension of the local data bus and the main data bus can be suppressed up to 4L.

  In FIGS. 9 and 10, only the data bus corresponding to the lower data input / output terminal LDQ is representatively shown, but the same hierarchical data bus is also connected to the upper data input / output terminal UDQ. The configuration is adopted.

  That is, although not shown, in the configuration shown in FIG. 9, a first local data bus for transmitting data to memory arrays AU and BU is provided along local data bus 122, and data is transmitted to memory arrays DU and CU. A second local data bus for performing the above is provided along the local data bus 124. In order to select one of these two local data buses and exchange data with the upper data input / output terminal UDQ, the upper data input / output terminal UDQ is arranged in the central area. And a main data bus connected to each other and two switches disposed at both ends thereof.

  Similarly, although not shown, in FIG. 10, a first local data bus for transmitting data to memory arrays AU and BU and a second local data bus for transmitting data to memory arrays DU and CU are provided. It has been. In order to select one of these two local data buses and exchange data with the upper data input / output terminal UDQ, the upper data input / output terminal UDQ is arranged in the central area. And a main data bus connected to each other and two switches disposed at both ends thereof.

  As described above, in the third embodiment, it is possible to suppress the total extension of the data bus by hierarchizing the data bus, and to improve the data propagation characteristics on the data bus. Further, by adding a device to the arrangement of the memory array, it is possible to further suppress the total extension of the data bus.

[Embodiment 4]
In the case where the memory array is arranged in the surrounding 8 areas of the 3 rows and 3 columns area described so far, at least the central area in which the peripheral circuit in the central portion is arranged has a margin in terms of layout. is there. Therefore, the restrictions on the design rules for the wiring width and wiring interval in the central region are loose. Therefore, by changing the wiring width and the wiring interval in a part of the data bus, it is possible to reduce the capacitive load and the resistance load parasitic on the data bus. Then, data propagation characteristics on the data bus can be improved.

  FIG. 11 is a layout diagram for explaining the data bus layout of the semiconductor memory device of the fourth embodiment.

  Referring to FIG. 11, a memory array arrangement similar to the memory array shown in FIG. The row decoder band RD and the column decoder band CPW are also arranged in the same manner as in FIG.

  FIG. 11 representatively shows a data bus corresponding to the lower data input / output terminal LDQ. The data bus connects a portion 162 for exchanging data with the memory arrays AL and BL, a portion 166 for exchanging data with the memory arrays CL and DL, a portion 162 and a portion 166, and connects the terminal group LDQ. And 164 for communicating data. A path from the memory array BL to the terminal group LDQ is indicated by a solid line. In such a data bus, the wiring width and the wiring interval (line L, space S) of the portion 164 are relaxed relative to other portions. The portion 164 is only a quarter of the total length of the data bus, but it is about a half of the maximum length 4L of the direct path from the memory array BL to the terminal LDQ. Expected to be more effective than improvement.

FIG. 12 is a cross-sectional view showing a cross section of the data bus portion 162 shown in FIG.
FIG. 13 is a sectional view showing a section of the data bus portion 164 in FIG.

  Referring to FIGS. 12 and 13, the wiring width L2 of the data bus line 190 in the portion 164 is made thicker than the wiring width L1 of the data bus line 180 in the portion 162. As a result, the wiring resistance is reduced, so that the load on the data bus is reduced. Further, when the wiring interval between the data bus line 180 and the adjacent wirings 182 and 184 is S1, the wiring interval S2 between the data bus line 190 and the adjacent wirings 192 and 194 is made larger than the wiring interval S1. Thereby, the parasitic capacitance between the wirings parasitic on the data bus line can be reduced. Therefore, the load on the data bus line can be reduced.

  In addition, when the restriction on the chip long side is not strict, the wiring width and pitch in the entire section of the data bus shown in FIG. 11 may be relaxed.

  Note that alleviating part or all of the wiring width and wiring interval of the data bus can also be applied to the configuration of the data bus exemplified in the first to third embodiments, and is synergistic with reducing the total length of the data bus. As a result, the data propagation characteristics on the data bus can be greatly improved.

  As described above, the data bus parasitic load can be reduced and the data propagation characteristics on the data bus can be improved by relaxing the wiring width and wiring interval of the data bus in a part or all of the sections.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1, 40, 50, 60, 70, 80, 110, 120, 140, 160 Semiconductor memory device, 2 address buffer, 4 clock buffer, 6 control signal input buffer, 8, 10, 18 block, 12 column decoder, 16 sense Amplifier, 20, 96 Output buffer, 22,100 Input buffer, 42, 44, 52, 54, 114 Data bus, 46 Central area, 62 Lower data bus, 64 Upper data bus, 82, 84, 112, 114 Sub Data bus, 92 selector, 94 read data amplifier, 98, PD pad, 102, 104 bus driver, 122, 124, 142, 144 Local data bus, 126, 146 Main data bus, 128, 130, 148, 150 switch, 162 , 164, 166 part, 180, 90 data bus lines, 182, 184, 192, 194 wiring, A, B, C, D memory array banks, AL, BL, CL, DL, AU, BU, CU, DU memory arrays, CEN central area, CPW column decoder Band, CROSS_N, CROSS_S area, LDQ data input / output terminal, RD row decoder band, SDB_S, SDB_N sub data bus, SEL selection circuit, UDQ data input / output terminal.

Claims (1)

A semiconductor memory device having a plurality of banks,
And the semiconductor substrate,
The semiconductor substrate is divided into 9 regions of 3 rows and 3 columns, and a plurality of higher-order input / output terminals for exchanging data with the outside are arranged in the central region of the second row and the second column of the 9 regions. a first input-output terminal group including,
A second input / output terminal group disposed in parallel with the first input / output terminal group, including a plurality of lower-order input / output terminals that exchange data with the outside arranged in a row in the central region ; ,
Wherein disposed from the first of the eight peripheral region surrounding the central region to the fourth region, and a plurality of first memory blocks to perform the first input-output terminal group and the data exchange,
Out of the eight surrounding areas, they are arranged in the fifth to eighth areas that are symmetrical to the first to fourth areas with the central area as the center, and exchange data with the second input / output terminal group. and a plurality of second memory blocks,
Each of the plurality of banks is a semiconductor memory device including the first memory block and a second memory block.

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