JP5036217B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a highly reliable CSP type semiconductor device and a manufacturing method thereof.

  In recent years, CSP (Chip Size Package) has attracted attention as a new packaging technology. The CSP refers to a small package having an outer dimension substantially the same as the outer dimension of a semiconductor chip.

  Conventionally, a BGA (Ball Grid Array) type semiconductor device is known as a kind of CSP. This BGA type semiconductor device is provided with a ball-shaped conductive terminal electrically connected to a pad electrode on the surface of a semiconductor substrate.

  When incorporating this BGA type semiconductor device into an electronic device, each conductive terminal is crimped to a wiring pattern on the printed circuit board, thereby electrically connecting the semiconductor chip and the external circuit mounted on the printed circuit board. Connected.

  Such BGA type electronic devices are provided with a larger number of conductive terminals than other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side. For example, it is widely used as an image sensor chip of a digital camera mounted on a mobile phone.

  The conventional BGA type semiconductor device will be described below with reference to the drawings (FIGS. 8 to 11). 8 to 11 are cross-sectional views shown in the order of manufacturing steps.

  First, as shown in FIG. 8, a silicon oxide film 101 and an interlayer insulating film 102 (polyimide resin film, PSG film, etc.) are formed on a semiconductor substrate 100 made of silicon (Si) or the like.

  Then, a metal layer (aluminum layer or copper layer) is formed on the interlayer insulating film 102 and etched using a mask (not shown) to form the pad electrode 103 on the interlayer insulating film 102.

  Next, as shown in FIG. 9, a plating layer 104 having a laminated structure of nickel (Ni) and gold (Au) is formed so as to cover the surface and side surfaces of the pad electrode 103 by an electrolytic plating method or an electroless plating method. Form. Here, since the adhesiveness between the plating layer 104 and the interlayer insulating film 102 (particularly, an interlayer insulating film made of an organic material such as polyimide) is low, the end portion 105 of the pad electrode 103, particularly the interlayer insulating film 102 In the vicinity of the boundary, the thickness of the plating layer 104 is extremely thin. Furthermore, the end portion 105 is not covered with the plating layer 104, and the surface (side surface) of the pad electrode 103 can be partially exposed.

  Next, as shown in FIG. 10, a passivation film 106 made of a solder resist or the like is formed on the surface of the semiconductor substrate 100 including the plating layer 104, and the passivation film 106 is exposed and developed to expose the plating layer 104. An opening 107 that exposes a predetermined surface is formed.

  Next, as shown in FIG. 11, a solder ball is fixed on a predetermined region of the plating layer 104 by electrolytic plating to form a conductive terminal 108. Note that the conductive terminals 108 (solder bumps) can be formed by screen-printing solder and reflowing the solder by heat treatment.

The following patent documents are listed as technical documents related to the present invention.
JP 2000-299406 A

  However, in the conventional BGA type semiconductor device described above, since the end portion 105 of the pad electrode 103 is not sufficiently covered with the plating layer 104, there is a problem that reliability is deteriorated. That is, since the passivation film 106 is generally an organic film, it is hydrophilic. Accordingly, there is a problem in that substances that cause corrosion, such as water, chemicals, and metal ions, enter the pad electrode 103 from the passivation film 106 through the side edge portion 105 in the manufacturing process and actual use state, leading to corrosion. there were.

  The present invention has been made in view of the above problems, and its main features are as follows. That is, a semiconductor device according to the present invention includes a first insulating film formed on a semiconductor substrate, a second insulating film formed by patterning on a surface of the first insulating film, and the second insulating film. A pad electrode covering the surface of the insulating film; a plating layer covering the surface of the pad electrode without a gap; a conductive terminal formed on the surface of the plating layer and electrically connected to the pad electrode; And a passivation film that covers the plating layer.

  The semiconductor device according to the present invention is characterized in that an end portion of the plating layer is in contact with the first insulating film.

  The semiconductor device manufacturing method according to the present invention has the following features. That is, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a first insulating film on a semiconductor substrate, a step of forming a patterned second insulating film on the first insulating film, Forming a pad electrode covering the surface of the patterned second insulating film; forming a plating layer on the surface of the pad electrode without any gaps by electrolytic plating or electroless plating; and And a step of forming a passivation film having an opening for exposing a part of the plating layer on the surface of the layer, and a step of forming a conductive terminal on the surface of the exposed plating layer.

  The method for manufacturing a semiconductor device according to the present invention is characterized in that the plating layer is formed so that an end portion of the plating layer is in contact with a part of the first insulating film.

  According to the semiconductor device and the method of manufacturing the same according to the present invention, the interlayer insulating film (second insulating film) is patterned into a predetermined pattern, and thereby, the end portion of the pad electrode, particularly the insulating film (first film). The vicinity of the boundary with the insulating film) is covered with a plating layer without a gap. Therefore, corrosion of the pad electrode can be prevented without changing the size of the wiring or the like, and a highly reliable semiconductor device can be provided. Further, when the end portion of the plating layer and the insulating film (first insulating film) are in contact with each other at a predetermined interval, that is, by increasing the width of the end portion of the plating layer, it causes further corrosion. It is possible to prevent the substance from entering the pad electrode and to secure a withstand voltage. Furthermore, when an oxide film is used as the insulating film (first insulating film), the adhesion with the plating layer is high, so that further corrosion can be prevented and a breakdown voltage can be secured.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. 1 to 6 are cross-sectional views shown in the order of manufacturing steps. 7 is a plan view of the semiconductor device according to the present invention, and FIG. 6 is a cross-sectional view taken along the line XX of FIG. An element such as a MOS transistor, a plurality of wirings, a plug for connecting the wirings, and an element isolation made of a silicon oxide film are appropriately formed on the semiconductor substrate, but the illustration thereof is omitted. Further, in FIG. 7, illustration of wiring extending from the pad electrode 4 is also omitted.

  First, as shown in FIG. 1, an insulating film 2 (for example, a silicon oxide film formed by thermal oxidation) is formed to a thickness of 2 μm, for example, on the surface of a semiconductor substrate 1 made of silicon (Si) or the like. In addition, since the plating layer 5 is formed so as to be in contact with a part of the insulating film 2 as described later, the material of the insulating film 2 is selected so as to have a higher adhesive combination depending on the material of the plating layer 5. It is preferable to select.

  Next, an interlayer insulating film 3 (an organic film such as a polyimide resin film) is formed on the surface of the insulating film 2 by a coating / coating method, for example, to a thickness of 10 μm. Then, as shown in FIG. 2, the interlayer insulating film 3 is exposed and developed to be patterned into a predetermined pattern (the same pattern as the pattern of the pad electrode, wiring layer, etc.). Thus, the interlayer insulating film 3 is not formed uniformly on the surface of the insulating film 2, but is formed only in the region where the pad electrode 4 and a wiring layer (not shown) connected thereto are formed. The interlayer insulating film 3 may be a silicon oxide film, a silicon nitride film, a PSG film, a BPSG film, or other insulating films formed by a CVD method or the like.

  Next, a metal layer such as aluminum (Al) or copper (Cu) to be the pad electrode 4 is formed on the semiconductor substrate 1 including the patterned interlayer insulating film 3 by a CVD method, a sputtering method, or other film forming methods. Thereafter, the metal layer is etched using a mask (not shown), and a pad electrode 4 is formed to a thickness of, for example, 1 μm on the surface of the interlayer insulating film 3 as shown in FIG. The pad electrode 4 is an external connection pad connected to an unillustrated input circuit or output circuit on the semiconductor substrate.

  Next, as shown in FIG. 4, a plating layer 5 having a laminated structure of nickel (Ni) and gold (Au) is formed so as to cover the surface of the pad electrode 4 by electrolytic plating or electroless plating. . Here, the plating layer 5 covers the entire surface including the end portion 7 of the pad electrode 4 without a gap. Further, the end portion 6 of the plating layer 5 is formed in contact with the insulating film 2. As described above, since the insulating film 2 (silicon oxide film) has good adhesion to the plated layer 5, the plated layer 5 is formed extremely thin near the edge 7 of the pad electrode 4, particularly in the vicinity of the boundary with the insulating film 2. It will never be done. In order to secure a withstand voltage and prevent corrosion of the pad electrode 5, it is preferable that the end portion 8 of the plated layer 5 has a sufficient width 8, that is, the area where the plated layer 5 is in contact with the insulating film 2 is secured. . Note that the end portion 6 of the plating layer 5 refers to a portion of the plating layer 5 formed outside the side surface of the pad electrode 4 as shown in FIG. In the drawing, the end 6 of the plating layer 5 is shown to have a step along the step of the end 7 of the pad electrode 4 serving as the lower layer. However, the shape of the end 6 is not particularly limited. . The same applies to the shape of the end 7 of the pad electrode 4.

  Next, as shown in FIG. 5, a passivation film 9 is formed with a thickness of, for example, 10 μm on the surface of the semiconductor substrate 1 including the plating layer 5, and the passivation film 9 is exposed and developed to thereby apply the plating layer 5. An opening 10 is formed to expose a predetermined surface (conductive terminal formation region). Specifically, the passivation film 9 is formed as follows. First, an organic material such as a polyimide resin film or a solder resist film is applied on the semiconductor substrate 1 including the plating layer 5 by a coating / coating method, and heat treatment (prebaking) is performed. Next, the applied organic material is exposed and developed to form an opening 10 that exposes a predetermined surface (conductive terminal formation region) of the plating layer 5, and then heat treatment (post-bake) is performed thereon. The passivation film 9 functions as a protective film that stabilizes the surface of the semiconductor substrate 1 and protects the semiconductor device from corrosion and the like.

  Next, as shown in FIGS. 6 and 7, a solder ball is fixed to a predetermined region of the plating layer 5 by an electrolytic plating method using the plating layer 5 as a plating electrode, thereby forming the conductive terminal 11 in the present invention. Such a semiconductor device is completed. When the conductive terminal 11 is composed of a solder ball, there is an advantage that the conductive terminal 11 can be easily formed. An example of the height of the conductive terminal 11 is 100 μm.

  Similar conductive terminals 11 (solder bumps) can be formed by screen-printing solder and reflowing the solder by heat treatment. In the case where the conductive terminal 11 is constituted by a solder bump, there is an advantage that a fine-shaped terminal can be formed with higher accuracy. The conductive terminal 11 may be made of gold, and the material is not particularly limited.

  Thus, in this embodiment, the entire surface including the end portion 7 of the pad electrode 4 is covered with the plating layer 5 with a sufficient film thickness without a gap. Therefore, according to the semiconductor device and the manufacturing method thereof in the present embodiment, the surface of the pad electrode 4 is completely covered with the plating layer 5 even if a substance such as water or a chemical solution enters from the passivation film 9. The corrosion of the pad electrode 4 can be prevented and a highly reliable semiconductor device can be provided.

  In the above embodiment, the BGA (Ball Grid Array) type semiconductor device having the ball-shaped conductive terminals 11 has been described. However, the present invention is an LGA (Land Grid Array) type having no ball-shaped conductive terminals. The present invention may also be applied to other CSP type and flip chip type semiconductor devices.

  Further, it goes without saying that the present invention is not limited to the above-described embodiment and can be changed without departing from the gist thereof.

It is sectional drawing explaining the semiconductor device of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device of this invention, and its manufacturing method. It is a top view explaining the semiconductor device of this invention, and its manufacturing method. It is sectional drawing explaining the conventional semiconductor device and its manufacturing method. It is sectional drawing explaining the conventional semiconductor device and its manufacturing method. It is sectional drawing explaining the conventional semiconductor device and its manufacturing method. It is sectional drawing explaining the conventional semiconductor device and its manufacturing method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film 3 Interlayer insulating film 4 Pad electrode 5 Plating layer 6 Edge of plating layer
7 End of Pad Electrode 8 Width of End of Plating Layer 9 Passivation Film 10 Opening 11 Conductive Terminal 100 Semiconductor Substrate 101 Silicon Oxide Film 102 Interlayer Insulating Film 103 Pad Electrode 104 Plating Layer 105 End of Pad Electrode 106 Passivation Film 107 Opening 108 Conductive terminal

Claims (8)

A first insulating film formed on the semiconductor substrate;
A second insulating film formed by patterning on the surface of the first insulating film;
A pad electrode patterned in the same pattern as the second insulating film covering and extending from the entire surface of the second insulating film, and a wiring layer continuous with the pad electrode;
A plating layer that extends from the entire surface of the pad electrode and the wiring layer that is continuous with the pad electrode, covers all the side surfaces , and has an end portion in contact with the first insulating film;
A conductive terminal formed on the surface of the plating layer on the pad electrode and electrically connected to the pad electrode;
A semiconductor device comprising: a first insulating film and a passivation film that covers the plating layer.   The semiconductor device according to claim 1, wherein the second insulating film is made of an organic material.   3. The semiconductor device according to claim 1, wherein the first insulating film is made of an oxide film.   4. The semiconductor device according to claim 1, wherein the plating layer has a laminated structure of a nickel layer and a gold layer. Forming a first insulating film on the semiconductor substrate;
Forming a patterned second insulating film on the first insulating film;
A step of forming a pad electrode patterned in the same pattern as the second insulating film covering and extending all sides from the entire surface of the patterned second insulating film, and a wiring layer continuous with the pad electrode When,
Forming a plating layer having an end portion in contact with the first insulating film without gaps on all surfaces and all side surfaces of the pad electrode and the wiring layer continuous with the pad electrode by an electroplating method or an electroless plating method; ,
Forming a passivation film having an opening exposing a part of the plating layer on the surface of the plating layer on the pad electrode;
Forming a conductive terminal on the surface of the exposed plating layer. A method for manufacturing a semiconductor device, comprising:   6. The method of manufacturing a semiconductor device according to claim 5, wherein the second insulating film is made of an organic material.   The method of manufacturing a semiconductor device according to claim 5, wherein the first insulating film is made of an oxide film. The step of forming the plating layer includes a step of forming a nickel layer by an electroplating method or an electroless plating method,
The method for manufacturing a semiconductor device according to claim 5, further comprising: forming a gold layer on the surface of the nickel layer by an electroplating method or an electroless plating method.

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