JP5035071B2 - Flip-flop circuit, frequency divider using flip-flop circuit, communication device and electronic equipment using frequency divider - Google Patents

Description

  The present invention relates to a flip-flop circuit, a frequency divider using the flip-flop circuit, a communication apparatus and an electronic apparatus using the frequency divider. More specifically, the present invention relates to a current logic type flip-flop circuit using a CML (Current Mode Logic) circuit, a frequency divider, a communication device, and an electronic device using the flip-flop circuit.

  For example, in an electronic device, a current logic type flip-flop circuit using a CML circuit may be used. The flip-flop circuit includes a master-slave flip-flop circuit in which a master unit and a slave unit are connected in cascade. As an example, a current logic type frequency divider circuit using a current logic type master-slave flip-flop circuit may be used in a front end unit (tuning circuit system) of a wireless communication device (for example, see Patent Document 1). reference).

JP 2000-22502 A

  The current logic type frequency divider is composed of a master-slave type D flip-flop. The D flip-flop includes a sample operation by a sample pair and a hold operation by a latch pair. There are two types of operation modes of the frequency divider: dynamic operation and static operation.

  Here, the dynamic operation is an operation that occurs when the output frequency of the frequency divider is close to the self-resonant frequency, and the operating frequency range is limited. On the other hand, the static operation is an operation that occurs when the output frequency of the frequency divider is lower than near the self-resonant frequency. When the gate width of the transistor of the sample pair is large, dynamic operation is dominant and high speed operation can be expected. On the other hand, when the gate width of the latch pair transistor is large, static operation is dominant, operation at low speed is guaranteed, and a wide operating frequency range can be expected.

  However, there is a trade-off relationship between a wide operating frequency range and high-speed operation, and it has been difficult for the conventional current logic type master-slave type to simultaneously realize high-speed operation and a wide operating frequency range.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a mechanism that can alleviate the trade-off relationship between high-speed operation and a wide operating frequency range.

  One form of a flip-flop circuit according to the present invention includes a master unit to which data is input, and a slave unit that receives data from the master unit and outputs data corresponding to the input data.

  The master unit includes a master sample pair including a pair of transistors that reads input data, and a master latch pair including a pair of transistors that outputs after holding the data read by the master sample pair, The operations of the master sample pair and the master latch pair are controlled by a clock.

  The slave unit reads a slave sample pair including a pair of transistors that reads data held by the master sample pair, and outputs a slave latch pair including a pair of transistors that is output after holding the data read by the slave sample pair. The operations of the slave sample pair and the slave latch pair are controlled by a clock.

  Furthermore, one form of the flip-flop circuit according to the present invention is a transistor provided for each pair for turning on and off the operating current flowing through the sample pair and the operating current flowing through the latch pair according to the clock, and according to the frequency of the clock. A current control unit including an operating current control unit that controls an operating current flowing through the latch pair.

  The current controller controls to increase the operating current flowing through the latch pair by the operating current controller as the clock frequency is lower. That is, the operating current control unit controls the operating current flowing through the latch pair to decrease when the clock frequency is high and to increase when the clock frequency is low.

  Preferably, the current control unit further includes an operating current balance control unit that controls an operating current flowing through the sample pair. In this case, the operating current balance control unit controls the operating current flowing through the sample pair in a direction that cancels out the change in the operating current flowing through the latch pair by the operating current control unit.

  Here, as a configuration of the operating current control unit and the operating current balance control unit, a variable current source can be used, or each current source that outputs a current value of a predetermined magnitude is switched using a switch ( (On / off control) can also be adopted.

  Thus, in one form of the flip-flop circuit according to the present invention, the operation current to the latch pair (preferably also the operation current to the sample pair) is controlled. By controlling the operating current in accordance with the clock frequency (that is, operating frequency), the trade-off relationship between high-speed operation and a wide operating frequency range is relaxed, and both high-speed operation and a wide operating frequency range are achieved. Specifically, the higher the clock frequency, the lower the operating current flowing through the latch pair, and the high-speed operation is guaranteed by making the sample pair operation dominant. On the other hand, by increasing the operating current flowing through the latch pair as the clock frequency is lower, the operation of the latch pair is guaranteed even at low frequencies, and a wide operating frequency range is also realized.

  At this time, preferably, the operating current balance control unit and the operating current are provided by providing an operating current balance control unit that controls the operating current to the sample pair in a direction that cancels out the operating current control to the latch pair by the operating current control unit. Performs coordinated operation of the balance controller. By controlling the operating current flowing through the sample pair in a direction that cancels out the change in operating current by the operating current control unit, the output amplitude is prevented from changing as much as possible. In this way, a wide operating frequency range and high frequency operation are realized while suppressing changes in the output amplitude (preferably maintaining the amplitude constant).

  According to one embodiment of the present invention, a current flowing through a pair of transistors can be appropriately controlled in accordance with an operating frequency, and a trade-off relationship between high-speed operation and a wide operating frequency range can be relaxed. This realizes a high operating frequency range while maintaining a wide operating frequency range.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<Basic configuration: flip-flop circuit>
FIG. 1 is a block diagram showing a basic configuration of a general master-slave type flip-flop circuit including a current logic type. The flip-flop circuit 1 includes a master unit 3 in which non-inverted data D is input to a non-inverted input terminal IN and inverted data ND is input to an inverted input terminal NIN. The flip-flop circuit 1 also receives the non-inverted data MQ output from the non-inverted output terminal OUT of the master unit 3 at the non-inverted input terminal IN and the inverted data NMQ output from the inverted output terminal NOUT of the master unit 3. A slave unit 5 is provided which is input to the inverting input terminal NIN. Non-inverted data SQ and its inverted data NSQ are output from the flip-flop circuit 1 from the slave unit 5. By such a flip-flop circuit 1, the non-inverted data D and the inverted data ND are temporarily held in the master unit 3, and the held data is transferred from the slave unit 5 as non-inverted data SQ and inverted data NSQ to the flip-flop Output from circuit 1.

<First comparative example: flip-flop circuit>
FIG. 1A is a circuit diagram showing a first comparative example of the flip-flop circuit 1 shown in FIG. The flip-flop circuit 1A of the first comparative example has a current logic type configuration in which both the master unit 3A and the slave unit 5A include a CML circuit including a sample pair transistor and a latch pair transistor. A MOS (Metal Oxide Semiconductor) type FET (Field Effect Transistor) is used as the transistor. The master unit 3A and the slave unit 5A are supplied with a high power supply voltage Vdd and a low power supply voltage Vss (triangle mark in the figure) lower than the high voltage power supply.

  The master unit 3A includes, on the low power supply voltage Vss side, a first current source I1 that provides an operating current, a transistor M1 that receives a clock CLK, and a transistor M2 that logically inverts the clock CLK but receives an inverted clock NCLK. Have. The slave unit 5A includes, on the low power supply voltage Vss side, a second current source I2 that provides an operating current, a transistor M3 and a clock CLK that receive an inverted clock NCLK that defines the holding timing of the non-inverted data D and the inverted data ND. Is input to the transistor M4. The clock CLK and the inverted clock NCLK define the holding timing of the non-inverted data D and the inverted data ND.

  The transistors M1 and M4 have a common clock CLK input to their gates, and the gates of the transistors M2 and M3 commonly receive an inverted clock NCLK. The sources of the transistors M1 and M2 are connected in common, and the sources are connected to the low power supply voltage Vss via the first current source I1, and the operating current (current value = I1a is set from the first current source I1. ) Is supplied. The sources of the transistors M3 and M4 are connected in common, and the sources are connected to the low power supply voltage Vss via the second current source I2, and the operating current (current value = I2a is set from the second current source I2. ) Is supplied.

  The master unit 3A is also connected to a pair of differentially connected transistors M5 and M6 (referred to as a master sample pair MS) for reading non-inverted data D and inverted data ND on the high power supply voltage Vdd side and their drains. And have resistance elements R1 and R2. The sources of the transistors M5 and M6 are commonly connected to the drain of the transistor M1, the non-inverted data D is input to the gate of the transistor M5 (the non-inverting input terminal IN of the master unit 3), and the gate (master unit 3) of the transistor M6. Inverting input terminal NIN) receives the inverted data ND. The drain of the transistor M5 (inverted output terminal NOUT of the master unit 3) is connected to the high power supply voltage Vdd through the resistor element R1, and the drain of the transistor M6 (non-inverted output terminal OUT of the master unit 3) is connected through the resistor element R2. Connected to the high power supply voltage Vdd.

  The master unit 3A also has a pair of gate-connected transistors M7 and M8 (referred to as master latch pair ML) that hold the drain output of the transistor M5 and the drain output of the transistor M6 on the high power supply voltage Vdd side. The sources of the transistors M7 and M8 of the master latch pair ML are commonly connected to the drain of the transistor M3, and one of the gates and the other drain are alternately connected (so as to be separated). The drain of the transistor M7 and the gate of the transistor M8 are connected to the drain of the transistor M5, and the drain of the transistor M8 and the gate of the transistor M7 are connected to the drain of the transistor M6. The drain output of the transistor M5 becomes the inverted data NMQ of the master unit 3A, and the drain output of the transistor M6 becomes the non-inverted output MQ of the master unit 3A.

  The slave unit 5A also has a pair of differentially connected transistors M9 and M10 (referred to as a slave sample pair SS) for reading the drain output of the transistor M5 and the drain output of the transistor M6 on the high power supply voltage Vdd side, and their drains. Have resistance elements R3 and R4 connected to each other. The sources of the transistors M9 and M10 are commonly connected to the drain of the transistor M2, the drain output of the transistor M5 is input to the gate of the transistor M9 (the inverting input terminal NIN of the slave unit 5), and the gate of the transistor M10 (slave unit 5). The non-inverting input terminal IN) receives the drain output of the transistor M6. The drain of the transistor M9 (non-inverted output terminal OUT of the slave unit 5) is connected to the high power supply voltage Vdd through the resistor element R3, and the drain of the transistor M10 (inverted output terminal NOUT of the slave unit 5) is connected through the resistor element R4. Connected to the high power supply voltage Vdd.

  The resistance elements R1 to R4 are load elements and are passive loads, but these are not limited to resistance elements and may be active loads using transistors.

  The slave unit 5A also includes a pair of gate-connected transistors M11 and M12 (referred to as a slave latch pair SL) that hold the drain output of the transistor M9 and the drain output of the transistor M10 on the high power supply voltage Vdd side. In the transistors M11 and M12 of the slave latch pair SL, the sources are commonly connected to the drain of the transistor M4, and one gate and the other drain are alternately connected (so as to be separated). The drain of the transistor M11 and the gate of the transistor M12 are connected to the drain of the transistor M10, and the drain of the transistor M12 and the gate of the transistor M11 are connected to the drain of the transistor M9. The master sample pair MS and the slave sample pair SS are collectively referred to as a sample pair portion S. The master latch pair ML and the slave latch pair SL are collectively referred to as a latch pair portion L.

  The drain output of the transistor M11 becomes non-inverted data SQ (same logic as the non-inverted data D) of the slave unit 5A, and the drain output of the transistor M12 becomes inverted output NSQ (same logic as the inverted data ND) of the slave unit 5A.

  The transistors M1 to M4 have the same characteristics, and the transistors M5 to M12 have the same characteristics. The transistors M1 to M4 are transistors that turn on and off the operating current flowing through each sample pair and the operating current flowing through each latch pair according to the clock CLK and the inverted clock NCLK.

  The operating current I1a of the first current source I1 and the operating current I2a of the second current source I2 are the same (I1a = I2a). Therefore, the sample pair part S (master sample pair MS and slave sample pair SS) exhibits the same operating characteristics. The latch pair portion L (master latch pair ML and slave latch pair SL) exhibits similar operating characteristics. For example, when the gate width of the transistor of the sample pair section S (master sample pair MS and slave sample pair SS) is large, dynamic operation is dominant and high speed operation can be expected. On the other hand, when the gate width of the transistors of the latch pair portion L (master latch pair ML and slave latch pair SL) is large, static operation is dominant, low-speed operation is guaranteed, and a wide operating frequency range can be expected.

  However, in one semiconductor device, the transistors of the sample pair unit S and the latch pair unit L have the same characteristics, the gate width is the same, the dynamic operation / high-speed operation of the sample pair unit S, The characteristics of the latch pair portion L such as static operation, low speed operation, and wide operating frequency range are contradictory operation characteristics. That is, the operating characteristics of the sample pair section S and the latch pair section L are in a trade-off relationship, and it is difficult to simultaneously realize a high speed operation and a wide operating frequency range.

<First embodiment: flip-flop circuit>
FIG. 1B is a circuit diagram showing a first embodiment of the flip-flop circuit 1 shown in FIG. The flip-flop circuit 1B of the first embodiment is configured to simultaneously realize high-speed operation and a wide operating frequency range by alleviating the point where the operation characteristics of the sample pair unit S and the latch pair unit L in the first comparative example conflict. To do.

  As shown in FIG. 1B, the flip-flop circuit 1B of the first embodiment is different from the flip-flop circuit 1A of the first comparative example in that a master latch pair ML on the master unit 3A side and a slave latch pair SL on the slave unit 5A side. Is characterized in that each is divided into two. That is, the master unit 3B includes transistors M7_1, M7_2, M8_1, and M8_2, and the slave unit 5B includes transistors M11_1, M11_2, M12_1, and M12_2.

  The transistors M7_1 and M8_1 constitute a first master latch pair ML_1, and the transistors M7_2 and M8_2 constitute a second master latch pair ML_2. The transistors M11_1 and M12_1 constitute a first slave latch pair SL_1, and the transistors M11_2 and M12_2 constitute a second slave latch pair SL_2. The first master latch pair ML_1 and the first slave latch pair SL_1 are collectively referred to as a first latch pair portion L1, and the second master latch pair ML_2 and the second slave latch pair SL_2 are collectively referred to as a second latch pair portion L2. Called.

  Each latch pair is divided into two. First, the drains of the transistors M7_1 and M7_2, the drains of the transistors M8_1 and M8_2, the drains of the transistors M11_1 and M11_2, and the drains of the transistors M12_1 and M12_2 are connected to each other. Yes.

  The flip-flop circuit 1B according to the first embodiment includes the operations of the transistors M7_2 and M8_2 which are the second master latch pair ML_2 on the master unit 3B side and the transistors M11_2 and M12_2 which are the second slave latch pair SL_2 on the slave unit 5B side. It is characterized in that an operating current control mechanism for controlling current is provided. In addition, when the operating current flowing through the second latch pair is controlled, in order to keep the output amplitude of the first latch pair constant, a resistance that is a load element is matched to the control for the operating current flowing through the second latch pair. It is characterized in that it has an operating current balance control mechanism that does not change the current flowing through the elements R1, R2, R3, and R4.

  Specifically, first, the first current source I1 (current value = I1b) is set on the source side of the transistors M1 and M2 that supply the operating current to the sample pair unit S (master sample pair MS and slave sample pair SS). In addition, a third current source I3 (current value = I3) is provided in parallel. A second current source I2 (current value = I2b) is provided on the source side of the transistors M3_1 and M4_1 for supplying an operating current to the first latch pair portion L1 (first master latch pair ML_1 and first slave latch pair SL_1). ), A fourth current source I4 (current value = I4) is provided in parallel.

  The second latch pair section L2 includes, on the low power supply voltage Vss side, a fifth current source I5 that supplies an operating current, a transistor M3_2 that receives an inverted clock NCLK, and a transistor M4_2 that receives a clock CLK. The gate of the transistor M3_2 is commonly connected to the gate of the transistor M3_1, and the gate of the transistor M4_2 is commonly connected to the gate of the transistor M4_1. The sources of the transistors M3_2 and M4_2 are connected in common, and the sources are connected to the fifth current source I5.

  Here, a first switch SW1 is provided on the low power supply voltage Vss side of the third current source I3, and an operating current (current value = I3) is supplied to the transistors M1 and M2 via the first switch SW1. Supplied. A second switch SW2 is provided on the low power supply voltage Vss side of the fourth current source I4, and an operating current (current value = I4) is supplied to the transistors M3_1 and M4_1 via the second switch SW2. . A third switch SW3 is provided on the low power supply voltage Vss side of the fifth current source I5, and an operating current (current value = I5) is supplied to the transistors M3_2 and M4_2 via the third switch SW3. .

  A first inverter INV1 is provided at the control input terminal of the first switch SW1, and a second inverter INV2 is provided at the control input terminal of the second switch SW2. The inputs of the first inverter INV1 and the second inverter INV2 and the control input terminal of the third switch SW3 are connected in common, and the enable signal EN is supplied. Each switch SW1, SW2, SW3 is turned on when the control input terminal is active H. Since the inverters INV1 and INV2 are interposed at the control input terminals of the first switch SW1 and the second switch SW2, the switches SW1 and SW2 are off when the third switch SW3 is on, and the third switch SW3 When is off, the switches SW1 and SW2 are on.

  The transistors M3_2 and M4_2, the fifth current source I5, and the third switch SW3 control the operating currents of the transistors M7_2 and M8_2 as the master latch pair ML_2 and the transistors M11_2 and M12_2 as the second slave latch pair SL_2. An operating current control unit CC is configured.

  In addition, the second latch pair by the operating current control unit CC is adjusted by the third current source I3, the first switch SW1, and the first inverter INV1 in accordance with the current control of the second latch pair unit L2 by the operating current control unit CC. A first operating current balance control unit BC1 is configured to control the operating current to the slave sample pair SS and the first latch pair unit L1 in a direction to cancel the current control amount to the unit L2. This control of the operating current preferably keeps the output amplitude of the first latch pair section L1 constant. By the fourth current source I4, the second switch SW2, and the second inverter INV2, the second latch pair unit L2 by the operating current control unit CC is synchronized with the current control of the second latch pair unit L2 by the operating current control unit CC. An operation current balance control unit BC2 is configured to control the operation current to the slave sample pair SS and the first latch pair unit L1 in a direction that cancels out the current control amount to. This control of the operating current preferably keeps the output amplitude of the first latch pair section L1 constant. The first operating current balance control unit BC1 and the second operating current balance control unit BC2 are collectively referred to as an operating current balance control unit BC. Then, the operating current control unit CC and the operating current balance control unit BC are combined into a current control unit 2 that controls each operating current of each sample pair and each latch pair according to the frequency of the clock CLK (and the inverted clock NCLK). Composed.

  The current control unit 2 is configured such that an increase in the operating current for the latch pair unit L (here, the second latch pair unit L2) by the operating current control unit CC is a decrease in the operating current for the sample pair unit S by the operating current balance control unit BC. Control to balance. As the clock frequency is lower, the operating current control unit CC increases the operating current for the second latch pair unit L2, while the operating current balance control unit BC increases the operating current by the operating current control unit CC. The operation current for the part S (in this example, the first latch pair part L1) is also controlled.

  That is, the current of the latch pair unit L and the sample pair unit S of the current logic type flip-flop circuit 1 can be switched, and the operation current control of the operation current control unit CC and the operation current balance control unit BC can be performed simultaneously. Make the output amplitude of data as constant as possible.

  Here, the current relationship is as follows. When the enable signal EN is active H, the third switch SW3 is turned on, and the operating current is supplied from the fifth current source I5 to the second master latch pair ML_2 and the second slave latch pair SL_2. . At this time, the first switch SW1 and the second switch SW2 are off, and the third current source I3 and the fourth current source I4 do not have a current supply capability.

  In this state, the second master latch pair ML_2 operates in parallel with the first master latch pair ML_1, and the second slave latch pair SL_2 operates in parallel with the first slave latch pair SL_1. The operation state is substantially the same as in the first comparative example. Therefore, the operating current I1b of the first current source I1 is equal to the operating current I1a of the first current source I1 of the first comparative example, and the operating currents I2b of the second current source I2 and the operations of the fifth current source I5. The sum (I2b + I5) of the current I5 is made equal to the operating current I2a of the second current source I2 of the first comparative example. That is, I1b = I1a and I2b + I5 = I2a.

  When the enable signal EN is inactive L, the first switch SW1 and the second switch SW2 are on, and the third current source I3 is connected to the transistors M1 and M2, and the fourth current source I4 is Each of the transistors M3_1 and M4_1 has a current supply capability. At this time, the third switch SW3 is off, and the operating current I5 from the fifth current source I5 is not supplied to the second master latch pair ML_2 and the second slave latch pair SL_2.

  At this time, the first operating current balance control unit BC1 and the second operating current balance control unit BC2 are deficient in the operating current I5 generated by the operating current control unit CC that is generated because the third switch SW3 is turned off (operation Function to cancel out the current variation). Therefore, the sum (I3 + I4) of the operating current I3 (the amount of change in operating current) of the third current source I3 and the operating current I4 (the amount of change in operating current) of the fourth current source I4 is turned on. To be equal to the operating current I5 of the fifth current source I5 at the time. That is, I3 + I4 = I5.

  When the third switch SW3 is turned off, the amount of current flowing through the second latch pair unit L2 (second master latch pair ML_2 and second slave latch pair SL_2) when the third switch SW3 is on is sampled when the third switch SW3 is off. S (master sample pair MS and slave sample pair SS) and first latch pair unit L1 (first master latch pair ML_1 and first slave latch pair SL_1) are distributed. By doing so, the current flowing through the resistance elements R1, R2, R3, and R4 is the same (not changed) when the third switch SW3 is on and when SW3 is off.

  As described above, the flip-flop circuit 1B according to the first embodiment prevents the current from changing between the sampling operation and the latching operation. The flip-flop alternately performs the sample operation and the latch operation, but in order to keep the amplitude constant, the current during each operation is made constant. Under these conditions, in order to change the strength of the latch operation so that the trade-off relationship between the high-speed operation and the wide operating frequency range can be relaxed, the latch pair is divided into a plurality of parts, and current control for each of the latch pairs is performed. A mechanism to change the gate width equivalently is adopted.

<Operation of flip-flop>
Here, operations of the flip-flop circuits 1A and 1B of the first comparative example and the first embodiment will be described. Since both basic operations are the same, the flip-flop circuit 1A of the first comparative example will be described for easy understanding.

  First, it is assumed that the non-inverted data SQ is stable at L and the inverted data NSQ is currently at H. At this time, it is assumed that H is input to the clock CLK and L is input to the inverted clock NCLK. In this state, the transistors M2 and M3 are off, so that the transistors M7 to M10 are off regardless of their gate potentials. On the other hand, the transistors M1 and M4 are on. At this time, the gate of the transistor M12 is in the ON state because it is at the potential H of the inverted data NSQ, and the gate of the transistor M11 is in the OFF state because it is at the potential L of the non-inverted data SQ.

  Here, when the clock CLK is H and the inverted clock NCLK is L, the non-inverted data D supplied to the gate of the transistor M5 is L, and when the inverted data ND supplied to the gate of the transistor M6 is H, the transistor M5 is Since the transistor M6 is turned on, the gate of the transistor M8 is turned on and turned on, and the gate of the transistor M7 is turned off and turned off. Thereafter, when the clock CLK becomes L and the inverted clock NCLK becomes H, the operating current to the transistors M1 and M2 is stopped, and the operating current is supplied to the transistors M7 and M8. Since the gates and drains of the transistors M7 and M8 are connected to each other, this state is maintained. At this time, the operating current is supplied to the transistors M9 and M10, and the operating current to the transistors M11 and M12 is stopped. Since the gate of the transistor M9 is turned on at H, the non-inverted data SQ is maintained at L, and the gate of the transistor M10 is turned off at L, so that H of the inverted data NSQ is maintained. This state is the initial state.

  On the other hand, when the clock CLK is H and the inverted clock NCLK is L, the non-inverted data D supplied to the gate of the transistor M5 is H, and the inverted data ND supplied to the gate of the transistor M6 is L, the transistor M5 is turned on. Since the transistor M6 side is turned off, the gate of the transistor M8 transitions to the L side, and the gate of the transistor M7 transitions to the H side.

  Thereafter, when the clock CLK becomes L and the inverted clock NCLK becomes H, the operating current to the transistors M1 and M2 is stopped, and the operating current is supplied to the transistors M7 and M8. Since the gates and drains of the transistors M7 and M8 are connected to each other, the above transition operation is rapidly transmitted, the transistor M7 is rapidly turned on and the inverted data NMQ is changed to L, and the transistor M8 is rapidly turned off. Then, the non-inverted output MQ is changed to H. At this time, an operating current is supplied to the transistors M9 and M10. Since the gate of the transistor M9 is turned off at L, the non-inverted data SQ is changed to H, and the gate of the transistor M10 is turned on at H, so that L of the inverted data NSQ is changed.

  Next, when the clock CLK is H and the inverted clock NCLK is L, the non-inverted data D supplied to the gate of the transistor M5 is switched to L, and the inverted data ND supplied to the gate of the transistor M6 is switched to H. Since M5 is turned off and the transistor M6 side is turned on, the gate of the transistor M8 transitions to the H side, and the gate of the transistor M7 transitions to the L side.

  Thereafter, when the clock CLK becomes L and the inverted clock NCLK becomes H, the operating current to the transistors M1 and M2 is stopped, and the operating current is supplied to the transistors M7 and M8. Since the gates and drains of the transistors M7 and M8 are connected to each other, the above transition operation is rapidly transmitted, the transistor M7 is rapidly turned off and the inverted data NMQ is changed to H, and the transistor M8 is rapidly turned on. Then, the non-inverted output MQ is changed to L. At this time, an operating current is supplied to the transistors M9 and M10. Since the gate of the transistor M9 is turned on at H, the non-inverted data SQ is changed to L, and the gate of the transistor M10 is turned off at L, so that H of the inverted data NSQ is changed.

  As can be seen from these, when the clock CLK is H, the potential state supplied to the gate of the transistor M5 of the master sample pair MS is maintained as the non-inverted data SQ, and the potential state supplied to the gate of the transistor M6. Is maintained by the inverted data NSQ.

<< Divisor >>
<Basic configuration>
2 to 2B are diagrams illustrating a frequency divider using a current logic type master-slave flip-flop circuit. Here, FIG. 2 is a block diagram showing a basic configuration of the frequency divider 7. FIG. 2A shows a circuit configuration of a frequency divider 7A of the second comparative example using the flip-flop circuit 1A of the first comparative example, and FIG. 2B shows a first configuration using the flip-flop circuit 1B of the first embodiment. The circuit structure of the frequency divider 7B of embodiment is shown.

  The flip-flop circuits 1 to 1B shown in FIGS. 1 to 1B have various uses. As an example, there is a frequency dividing circuit (frequency divider). The frequency divider 7 sets the inverted data NSQ of the flip-flop circuit 1 as non-inverted data D and the non-inverted data SQ as inverted data ND. As a result, the frequency divider 7 (flip-flop circuit 1) generates a divided signal and an inverted divided signal obtained by dividing the clock CLK and the inverted clock NCLK.

<Operation of Frequency Divider: First Comparative Example>
Here, the operation of the frequency divider 7A of the first comparative example using the flip-flop circuit 1A of the first comparative example will be described. This operation is the same as the basic operation of the frequency divider 7B of the first embodiment using the flip-flop circuit 1B of the first embodiment.

  The description will be continued from the initial state of the flip-flop circuit 1. Information in which the non-inverted data SQ is L in the initial state is input to the gate of the transistor M6, and information in which the inverted data NSQ is H is input to the gate of the transistor M5. Here, when the clock CLK is switched to H and the inverted clock NCLK is switched to L, the transistor M5 is turned on and the transistor M6 side is turned off, so that the gate of the transistor M8 is shifted to the L side and the gate of the transistor M7 is moved to the H side. Transition. Therefore, after that, when the clock CLK becomes L and the inverted clock NCLK becomes H, the non-inverted data SQ changes to H and the inverted data NSQ changes to L as understood from the operation description of the flip-flop circuit 1. .

  In the state after the change, information with non-inverted data SQ being H is input to the gate of the transistor M6, and information with inversion data NSQ being L is input to the gate of the transistor M5. Here, when the clock CLK is switched to H and the inverted clock NCLK is switched to L, the transistor M5 is turned off and the transistor M6 side is turned on, so that the gate of the transistor M8 is shifted to the H side and the gate of the transistor M7 is moved to the L side. Transition. Therefore, after that, when the clock CLK becomes L and the inverted clock NCLK becomes H, the non-inverted data SQ changes to L and the inverted data NSQ changes to H as understood from the operation description of the flip-flop circuit 1. .

  As described above, the states of the non-inverted data SQ and the inverted data NSQ are switched every two cycles of the clock CLK, and the 1/2 frequency divided signal of the clock CLK is output from the non-inverted data SQ and the inverted data NSQ. Become.

  Here, the current logic type frequency divider 7A is configured by the master-slave type D-type flip-flop circuit 1A as described above. The flip-flop circuit 1A has, as its operation state, a sample operation by the sample pair unit S (master sample pair MS and slave sample pair SS) and a hold operation by the latch pair unit L (master latch pair ML and slave latch pair SL). Have. There are two types of operation modes of the frequency divider 7, which are dynamic operation and static operation. The dynamic operation is an operation that occurs when the output frequency of the frequency divider 7 is near the self-resonant frequency, and the operating frequency range is limited. On the other hand, the static operation is an operation that occurs when the output frequency of the frequency divider 7 is lower than the vicinity of the self-resonant frequency.

  As described in the flip-flop circuit 1A, when the gate widths of the transistors M5, M6, M9, and M10 constituting the sample pair unit S (master sample pair MS and slave sample pair SS) are large, the dynamic operation is dominant. High-speed operation can be expected. On the other hand, when the gate widths of the transistors M7, M8, M11, and M12 constituting the latch pair portion L (the master latch pair ML and the slave latch pair SL) are large, the static operation is dominant and the operation at a low speed is guaranteed. A wide operating frequency range can be expected. However, as described above, the dynamic operation / high-speed operation of the sample pair unit S and the static operation / low-speed operation / wide operating frequency range of the latch pair unit L are in a trade-off relationship. It is difficult to realize.

<Operation of Frequency Divider: First Embodiment>
On the other hand, the frequency divider 7B according to the first embodiment shown in FIG. 2B basically includes the flip-flop circuit 1B according to the first embodiment shown in FIG. 1B. The advantage of having the balance control unit BC is obtained. Hereinafter, this point will be described in detail.

  First, when the third switch SW3 is off, the second latch pair unit L2 (the second master latch pair ML_2 and the second slave latch pair SL_2) is also turned off, so that the master sample pair MS and the slave sample pair SS A large amount of current flows and dynamic operation becomes dominant, and high-speed operation can be expected. In this state, when the operation speed decreases, the frequency divider does not operate.

  In such a frequency band, the third switch SW3 is turned on to turn on the second latch pair unit L2 (second master latch pair ML_2 and second slave latch pair SL_2), and the second master latch pair ML_2 is turned on. The static operation can be made dominant by increasing the current flowing through the second slave latch pair SL_2.

  Thus, in the mechanism of the first embodiment, the operating current control unit CC turns off the third switch SW3 at a high frequency to reduce the operating current for the second latch pair unit L2, and the third switch at a low frequency. By turning on SW3 and increasing the operating current for the second latch pair portion L2, a high operating frequency range can be realized while maintaining a wide operating frequency range.

  At this time, the operating current balance control unit BC performs on / off control of the first switch SW1 so as to cancel the change in the operating current to the second latch pair unit L2 by the operating current control unit CC. While controlling the operating current for the part S, the operating current for the first latch pair part L1 is controlled by ON / OFF control of the second switch SW2. By doing so, the output amplitude can be kept constant, and a wide operating frequency range can be maintained while maintaining a wide operating frequency range.

<Example of operating characteristics>
FIG. 2C is a diagram illustrating an example of operation characteristics of the frequency divider 7B according to the first embodiment. The horizontal axis indicates the input frequency (clock CLK frequency), and the vertical axis indicates Vin (Vpp-per-phase). It is assumed that the frequency cover range of each mode that is not inconvenient as the operation of the frequency divider 7 is ½ or more with respect to the required operating frequency range.

  At a high frequency, the third switch SW3 is turned off to make the dynamic operation dominant (used in the dynamic mode). In this case, a high operating frequency range is naturally realized. On the other hand, at a low frequency, the third switch SW3 is turned on to make the static operation dominant (used in the static mode). At this time, since the third switch SW3 is turned on, the current flowing through the second master latch pair ML_2 and the second slave latch pair SL_2 increases, so that it operates as a frequency divider even at a low operating speed. Therefore, as a whole of the frequency divider 7B, a high operating frequency range is realized while maintaining a wide operating frequency range.

  As can be seen from the illustrated example, when the frequency cover range of each mode is ½ or more with respect to the required operating frequency range, the second latch pair unit L2 is supplied to the mode (that is, the operating frequency). By turning on / off the current supply, a wide operating frequency range and high frequency operation are realized.

<Wireless communication device>
FIG. 3 is a block diagram illustrating a configuration example of the wireless communication device 9 that uses the frequency divider 7 as an example of the electronic device 8. Here, the receiving unit 90 of the front end unit (tuning circuit system) of the wireless communication device 9 (for example, a TV tuner wireless communication device) is shown. The reception unit 90 of the wireless communication device 9 includes an input filter unit 91, a local oscillation unit 92 that outputs a local oscillation signal Lo, and quadrature signals P_0 (0 ° component) and P_90 (90 ° component) that are 90 degrees out of phase. ), Frequency mixing units 94 and 95 (mixers), and output filter circuit units 96 and 97. In addition, although it has shown about the receiving part 90 here, the structure similar to the orthogonal phase signal generation part 93 and the frequency mixing parts 94 and 95 is provided also in the case of a transmission part.

  The receiving unit 90 receives a high frequency signal RF to the filter circuit 91 via an antenna unit (not shown) that receives broadcast waves and the like. The high-frequency signal RF that has been band-limited through the input filter unit 91 is input to the frequency mixing units 94 and 95. In the frequency mixing unit 94, modulation is performed between the quadrature signal P_0 (0 ° component) generated by the quadrature signal generator 93 and the high frequency signal RF based on the local oscillation signal Lo, and an I signal component is generated. . The frequency mixing unit 95 performs modulation between the quadrature signal P_90 (90 ° component) generated by the quadrature signal generator 93 based on the local oscillation signal Lo and the high frequency signal RF to generate a Q signal component. .

  The I signal component generated by the frequency mixing unit 94 is band-limited by the output filter unit 96 and output as an intermediate frequency IF (I component). The Q signal component generated by the frequency mixing unit 95 is band-limited by the output filter unit 97 and output as an intermediate frequency IF (Q component).

  Here, the frequency divider 7 is used in the quadrature signal generator 93. The frequency divider 7 is useful as a quadrature signal generator for TV tuner radio communication equipment. Next, a more appropriate frequency divider 7 for the quadrature signal generator 93 will be described.

<Divisor: Second Embodiment>
FIGS. 3A and 3B are diagrams illustrating another example of the frequency divider 7 using a current logic type master-slave flip-flop circuit. Here, FIG. 3A shows a circuit configuration of the frequency divider 7C of the second comparative example, and FIG. 3B shows a circuit configuration of the frequency divider 7D of the second embodiment.

  The frequency divider 7 is used for the quadrature signal generator 93 in the front end of the wireless communication device 9. The quadrature signal generator 93 is a circuit that outputs a quadrature signal with respect to the differential input.

  Here, in the quadrature signal generator 93 (quadrature signal generator) used in the radio communication device 9 such as a TV tuner, a wide operating frequency range and a low phase error are important. For example, in the case of the frequency divider 7A of the first comparative example shown in FIG. 2A, one cause of the phase error is that the duty ratio of the input differential signal is not 50%. When the duty ratio of the input differential signal is greatly deviated from 50%, the phase error of the output signal is not improved even if the phase error characteristic of the frequency divider 7A itself of the first comparative example is improved.

  As a technique for improving such a phase error and realizing a low phase error, for example, a circuit system such as the frequency divider 7C of the second comparative example shown in FIG. It is conceivable to reduce. That is, the frequency divider 7C according to the second comparative example is based on the frequency divider 7A according to the first comparative example shown in FIG. 2A, and has a resistance element R5 between the source of the transistor M1 and the first current source I1. The resistor element R6 is provided for gain adjustment between the source of the transistor M2 and the first current source I1, respectively. Similarly, a resistor element R7 is provided between the source of the transistor M3 and the second current source I2, and a resistor element R8 is provided between the source of the transistor M4 and the second current source I2 for gain adjustment. The idea is that the sensitivity to the phase error is reduced by reducing the gain of the transistors M1, M2, M3, and M4, which are input transistors, due to the presence of the resistance elements R5 to R8.

  However, if the resistance elements R5 to R8 for gain adjustment are provided on the source side of the transistors M1, M2, M3, and M4 as input transistors in this way, a voltage drop due to the resistance elements R5 to R8 also occurs, so that high speed operation is possible. Cannot be expected.

  As a countermeasure, a circuit system such as the frequency divider 7D of the second embodiment shown in FIG. 3B functions effectively. That is, the frequency divider 7D of the second embodiment is based on the frequency divider 7B of the first embodiment shown in FIG. 2B, and is similar to the frequency divider 7C of the first comparative example. A resistance element R5 is provided for gain adjustment between the source and the first current source I1 and the third current source I3. Similarly, a resistance element R6 is provided for gain adjustment between the source of the transistor M2 and the first current source I1 and the third current source I3.

  Similarly, a resistance element R7_1 is provided between the source of the transistor M3_1 and the second current source I2 and the fourth current source I4, and between the source of the transistor M4_1 and the second current source I2 and the fourth current source I4. A resistance element R8_1 is provided for gain adjustment. Similarly, a resistor R7_2 is provided between the source of the transistor M3_2 and the fifth current source I5, and a resistor R8_2 is provided between the source of the transistor M4_2 and the fifth current source I5 for gain adjustment.

  Similar to the second comparative example, the resistance elements R5 to R8 for gain adjustment are provided on the source side of the transistors M1, M2, M3, and M4 that are input transistors to reduce the sensitivity to the phase error. On the other hand, regarding the high-speed operation (of course, a wide operating frequency range), the function of the frequency divider 7B of the first embodiment can be enjoyed. Therefore, according to the frequency divider 7D of the second embodiment, high-speed operation (and a wide operating frequency range) can be expected while reducing the phase error.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, in the above-described embodiment, the latch pair unit L (the master latch pair ML and the slave latch pair SL) is divided into two and the operating current control unit CC is provided. However, the number of divisions is not limited to two. When the frequency cover range of each mode is greater than or equal to 1 / (N + 1) and less than 1 / N with respect to the required operating frequency range, the division of the latch pair portion L is set to (N + 1), and the current in accordance with the frequency Switching may be made in (N + 1) ways.

  Moreover, although the structural example using a switch was shown as a current switching mechanism of the operating current control unit CC and the operating current balance control unit BC, each of the switches SW1 to SW3 is removed, and the third to fifth current sources I3 to I3 are removed. I5 can also be a variable current source. In this case, for example, the enable signal EN is changed to a current control signal. The current control unit 2 performs control so that the operating current for the second latch pair unit L2 by the operating current control unit CC is increased as the frequency of the clock CLK is lower. That is, the operating current control unit CC controls the operating current for the second latch pair unit L2 to be decreased when the frequency of the clock CLK is high and to be increased when the frequency of the clock CLK is low. The operating current balance control unit BC controls the operating current for the sample pair unit S and the first latch pair unit L1 so as to cancel the increase and decrease of the operating current by the operating current control unit CC.

  The change direction of the current values of the fifth current source I5, the third current source I3, and the fourth current source I4 with respect to the current control signal is reversed. When the variable current source is used, the third current source I3 is combined with the first current source I1, and the fourth current source I4 is combined with the second current source I2. Is also possible.

  Further, the flip-flop circuit 1B and the frequency dividers 7B and 7D are not limited to being applied to the wireless communication device 9, but can be applied to general electronic devices.

It is a block diagram showing a basic configuration of a general master-slave type flip-flop circuit including a current logic type. FIG. 3 is a circuit diagram showing a first comparative example of the flip-flop circuit shown in FIG. 1. FIG. 2 is a circuit diagram showing a first embodiment of a flip-flop circuit shown in FIG. 1. It is a block diagram which shows the basic composition of a frequency divider. It is a figure which shows the circuit structure of the frequency divider of the 2nd comparative example using the flip-flop circuit of a 1st comparative example. It is a figure which shows the circuit structure of the frequency divider of 2nd Embodiment using the flip-flop circuit of 1st Embodiment. It is a figure which shows the example of an operating characteristic of the frequency divider of 1st Embodiment. It is a block diagram which shows the structural example of the radio | wireless communication apparatus using a frequency divider. It is a figure which shows the circuit structure of the frequency divider of a 2nd comparative example. It is a figure which shows the circuit structure of the frequency divider of 2nd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Flip-flop circuit, 2 ... Current control part 2, 3 ... Master part 3, 5 ... Slave part 5, 7 ... Frequency divider, 8 ... Electronic device, 9 ... Wireless communication apparatus, 90 ... Reception part, 91 ... Input filter unit, 92 ... Local oscillation unit, 93 ... Quadrature phase signal generation unit, 94 ... Frequency mixing unit, 95 ... Frequency mixing unit, 96 ... Output filter unit, 97 ... Output filter unit, BC ... Operating current balance control unit, BC1 ... first operating current balance control unit, BC2 ... second operating current balance control unit, L ... latch pair unit, L1 ... first latch pair unit, L2 ... second latch pair unit, ML ... master latch pair, ML_1 ... first 1 master latch pair, ML_2 ... second master latch pair, MS ... master sample pair, S ... sample pair part, SL ... slave latch pair, SL_1 ... first slave latch pair, SL_2 ... second Slave latch pair, SW1 ... first switch SW1, SW2 ... second switch SW2, SW3 ... third switch SW3, I1 ... first current source, I2 ... second current source, I3 ... third current Source, I4 ... fourth current source, I5 ... fifth current source, INV1 ... first inverter, INV2 ... second inverter

Claims (9)

A master part to which data is input;
The data from the master unit is input, and a slave unit that outputs data corresponding to the input data,
The master unit reads a master sample pair including a pair of transistors that reads the input data, and outputs a master latch pair including a pair of transistors that is output after holding the data read by the master sample pair. And the operation of the master sample pair and the master latch pair is controlled by a clock,
The slave unit is configured to read data held by the master sample pair, read a slave sample pair including a pair of transistors, and output a slave sample pair read after holding the data read by the slave sample pair. Having a latch pair, the operation of the slave sample pair and the slave latch pair is controlled by the clock,
A transistor provided for each pair that turns on and off the operating current flowing through the sample pair and the operating current flowing through the latch pair according to the clock;
An operating current control unit for controlling an operating current flowing in the latch pair according to the frequency of the clock;
Further comprising
The flip-flop circuit that controls the operating current control unit to increase the operating current flowing through the latch pair as the frequency of the clock is lower. An operating current balance control unit for controlling an operating current flowing through the sample pair;
2. The flip-flop circuit according to claim 1, wherein the operating current balance control unit controls the operating current flowing through the sample pair in a direction that cancels a change in the operating current flowing through the latch pair by the operating current control unit. The operating current balance control unit flows to the sample pair so that the amplitude of data output from the slave unit is maintained constant even when the operating current to the latch pair is changed by the operating current control unit. The flip-flop circuit according to claim 2, which controls an operating current. Each of the latch pairs is divided into a plurality,
The operating current control unit is configured to increase the operating current as the frequency of the clock is lower for each one of the separated latch pairs,
The operating current balance control unit is configured to control a working current flowing through the sample pair in a direction that cancels a change in operating current flowing through the one latch pair by the operating current control unit; The second operating current balance control unit that controls the operating current in a direction that cancels out the change of the operating current flowing through the one latch pair by the operating current control unit with respect to each of the other separated latch pairs. 4. The flip-flop circuit according to any one of 3. The amount of change in the operating current flowing through the one latch pair by the operating current control unit is the amount of change in the operating current flowing through the sample pair by the operating current balance control unit and the other latch pair by the operating current balance control unit. The flip-flop circuit according to claim 4, wherein the flip-flop circuit is equal to a sum of a change amount of an operating current flowing through the FF. A master part to which data is input;
The data from the master unit is input, and a slave unit that outputs data corresponding to the input data,
Non-inverted data output from the slave unit is supplied to the inverting input terminal of the master unit, or inverted data output from the slave unit is supplied to the non-inverted input terminal of the master unit,
The master unit reads a master sample pair including a pair of transistors that reads the input data, and outputs a master latch pair including a pair of transistors that is output after holding the data read by the master sample pair. And the operation of the master sample pair and the master latch pair is controlled by a clock,
The slave unit is configured to read data held by the master sample pair, read a slave sample pair including a pair of transistors, and output a slave sample pair read after holding the data read by the slave sample pair. Having a latch pair, the operation of the slave sample pair and the slave latch pair is controlled by the clock,
A transistor provided for each pair that turns on and off the operating current flowing through the sample pair and the operating current flowing through the latch pair according to the clock;
A current control unit comprising an operating current control unit for controlling an operating current flowing through the latch pair in accordance with the frequency of the clock;
Further comprising
The operating current control unit performs control to increase the operating current flowing through the latch pair as the frequency of the clock is lower. The frequency divider according to claim 6, wherein a resistor for adjusting a gain is provided at a current supply side terminal of each pair of transistors. A communication unit that receives or transmits a high-frequency signal,
The communication unit is
A master part to which data is input;
The data from the master unit is input, and a slave unit that outputs data corresponding to the input data,
Non-inverted data output from the slave unit is supplied to the inverting input terminal of the master unit, or inverted data output from the slave unit is supplied to the non-inverted input terminal of the master unit,
The master unit reads a master sample pair including a pair of transistors that reads the input data, and outputs a master latch pair including a pair of transistors that is output after holding the data read by the master sample pair. And the operation of the master sample pair and the master latch pair is controlled by a clock,
The slave unit is configured to read data held by the master sample pair, read a slave sample pair including a pair of transistors, and output a slave sample pair read after holding the data read by the slave sample pair. Having a latch pair, the operation of the slave sample pair and the slave latch pair is controlled by the clock,
A transistor provided for each pair that turns on and off the operating current flowing through the sample pair and the operating current flowing through the latch pair according to the clock;
An operating current control unit for controlling an operating current flowing in the latch pair according to the frequency of the clock;
Further comprising
The communication device that controls the operation current control unit to increase an operation current flowing in the latch pair as the frequency of the clock is lower. A master part to which data is input;
The data from the master unit is input, and a slave unit that outputs data corresponding to the input data,
Non-inverted data output from the slave unit is supplied to the inverting input terminal of the master unit, or inverted data output from the slave unit is supplied to the non-inverted input terminal of the master unit,
The master unit reads a master sample pair including a pair of transistors that reads the input data, and outputs a master latch pair including a pair of transistors that is output after holding the data read by the master sample pair. And the operation of the master sample pair and the master latch pair is controlled by a clock,
The slave unit is configured to read data held by the master sample pair, read a slave sample pair including a pair of transistors, and output a slave sample pair read after holding the data read by the slave sample pair. Having a latch pair, the operation of the slave sample pair and the slave latch pair is controlled by the clock,
A transistor provided for each pair that turns on and off the operating current flowing through the sample pair and the operating current flowing through the latch pair according to the clock;
An operating current control unit for controlling an operating current flowing in the latch pair according to the frequency of the clock;
Further comprising
The electronic device that controls the operating current control unit to increase the operating current flowing through the latch pair as the frequency of the clock is lower.

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