JP5034844B2 - Electronics - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit having an error detection function and a power down function.

  In order to realize a fail-safe function in an electronic device, an error detection circuit is often provided in a semiconductor integrated circuit incorporated in the electronic device. This error detection circuit is a circuit that outputs an error detection signal to the outside of the semiconductor integrated circuit when, for example, the semiconductor integrated circuit generates heat and becomes high temperature or an overcurrent flows through the semiconductor integrated circuit or its load. When such an error detection signal is output from the semiconductor integrated circuit, the host processor provided in the electronic device takes measures such as cutting off the power supply to the semiconductor integrated circuit. This prevents the occurrence of fatal damage such as destruction of the semiconductor integrated circuit and its load. As an example of a semiconductor integrated circuit having this type of fail-safe function, there is a semiconductor integrated circuit disclosed in Patent Document 1.

  Some semiconductor integrated circuits include a power-down control circuit. This is because, when a power down command is given from the outside, the operation clock of the semiconductor integrated circuit is stopped, the circuit with large power consumption is stopped, or the output transistor of the semiconductor integrated circuit is turned off. This is a circuit for shifting a semiconductor integrated circuit to a power-down state with low power consumption.

Of course, the main purpose of providing such a power-down control circuit in a semiconductor integrated circuit is to prevent the semiconductor integrated circuit from consuming unnecessary power. However, depending on the configuration of the semiconductor integrated circuit, the transition to the power-down state may be a measure to prevent the expansion of damage that prevents the damage to the semiconductor integrated circuit and the load from expanding when an error such as generation of heat or overcurrent occurs. Often becomes. For this reason, in order to realize a fail-safe function in an electronic device, a configuration in which an error detection circuit and a power-down control circuit are linked may be employed. That is, a signal transmission path connecting the error detection signal output terminal and the power down command signal input terminal in the semiconductor integrated circuit is provided outside the semiconductor integrated circuit. According to such a configuration, when an error such as generation of heat or overcurrent occurs in the semiconductor integrated circuit and the error detection circuit outputs an error detection signal, this is given to the power-down control circuit as a power-down command signal. . Therefore, it is possible to prevent the spread of damage due to the occurrence of an error without going through the host processor.
Special table 2003-506951 gazette

  There are cases where a plurality of semiconductor integrated circuits including an error detection circuit and a power-down control circuit are mounted on an electronic device. In such an electronic device, when the error detection circuit of at least one of the plurality of semiconductor integrated circuits outputs an error detection signal, it is desired to shift all the semiconductor integrated circuits to the power-down state. There is a case. As a configuration of a semiconductor integrated circuit and an electronic apparatus using the semiconductor integrated circuit for satisfying such a requirement, for example, a configuration as shown in FIG. 3 can be considered.

  In the example shown in FIG. 3, the semiconductor devices 10A, 10B, 10C, and 10D are mounted on the electronic device. The semiconductor integrated circuit 10A includes an error detection circuit 11, an N-channel field effect transistor 12 as a switching element, an inverter 13, and a power-down control circuit 14. Here, the source of the N-channel field effect transistor 12 is grounded, and the drain is connected to the output terminal of the semiconductor integrated circuit 10A that outputs the error detection signal ERN, thereby forming an open drain type output circuit. . The error detection circuit 11 turns on the N-channel field effect transistor 12 when an error is detected in the semiconductor integrated circuit 10A, and activates the error detection signal ERN output from the N-channel field effect transistor 12 to the outside of the semiconductor integrated circuit 10A. Level (L level).

  The inverter 13 serves as an input circuit that receives the power-down command signal PDN from the outside of the semiconductor integrated circuit 10 </ b> A and delivers it to the power-down control circuit 14. The inverter 13 has an input / output transmission characteristic having a hysteresis characteristic. That is, in the process in which the power down command signal PDN falls from the power supply voltage VDD toward the ground level, the output signal of the inverter 13 rises from the L level to the H level when the power down command signal PDN falls below the threshold value VLa, for example. In the process in which the power down command signal PDN rises from the ground level toward the power supply voltage VDD, the output signal of the inverter 13 falls from the H level to the L level when the power down command signal PDN exceeds the threshold value VHa higher than the threshold value VLa. .

  The power-down control circuit 14 sets the power-down control signal to be sent to each part to be subjected to power-down control in the semiconductor integrated circuit 10A when the output signal of the inverter 13 becomes active level (H level). When the output signal becomes the inactive level (L level), the power down control signal is set to the inactive level. The target of this power-down control includes the error detection circuit 11. The error detection circuit 11 forcibly turns off the N-channel field effect transistor 12 when the power-down control signal is at an active level, and responds to whether or not an error is detected when the power-down control signal is at an inactive level. The N-channel field effect transistor 12 is turned on / off.

  The configuration of the semiconductor integrated circuit 10A has been described above as an example, but the error detection circuit 11 similar to that of the semiconductor integrated circuit 10A, the N-channel field effect transistor 12, and the other semiconductor integrated circuits 10B, 10C, and 10D An inverter 13 and a power-down control circuit 14 are provided (not shown).

  In the electronic device illustrated in FIG. 3, the output terminals of the error detection signals ERN of the semiconductor integrated circuits 10A, 10B, 10C, and 10D are commonly connected, and a pull-up is performed between the common connection point and the power supply of the power supply voltage VDD. A resistor 21 is inserted to form a wired OR circuit. A capacitor 22 is interposed between the common connection point of the output terminals of the error detection signal ERN and the ground line. The common connection point of the output terminals of the wired OR circuit, that is, the output terminals of the error detection signals ERN of the semiconductor integrated circuits 10A, 10B, 10C, and 10D is the power down command signal of the semiconductor integrated circuits 10A, 10B, 10C, and 10D. It is connected to each input terminal of the PDN.

  According to such a configuration, when the error detection circuit 11 of any of the semiconductor integrated circuits 10A, 10B, 10C, and 10D turns on the N-channel field effect transistor 12, the error detection signal ERN changes to the active level. The error detection signal ERN is applied to the semiconductor integrated circuits 10A, 10B, 10C, and 10D as the power down command signal PDN. Accordingly, if the threshold values of the inverters 13 of the semiconductor integrated circuits 10A, 10B, 10C, and 10D (corresponding to the threshold value VLa of the semiconductor integrated circuit 10A) match, all the semiconductor integrated circuits 10A, 10B, 10C, and 10D are used. Move to the power-down state simultaneously. However, since the semiconductor integrated circuits 10A, 10B, 10C, and 10D have manufacturing variations, it is difficult to match the threshold values of the inverters 13 of the semiconductor integrated circuits 10A, 10B, 10C, and 10D. For this reason, the configuration shown in FIG. 3 causes a problem that the operation of the power-down control accompanying the generation of the error detection signal ERN becomes unstable.

  FIG. 4 is a waveform diagram showing an operation example of this unstable power-down control. In this example, the error detection circuit 11 of the semiconductor integrated circuit 10A detects an error, the N-channel field effect transistor 12 is turned on, and the error detection signal ERN is lowered. In the illustrated example, when the error detection signal ERN falls below the threshold value VLa of the inverter 13 of the semiconductor integrated circuit 10A, the power down control circuit 14 of the semiconductor integrated circuit 10A sends power down control to each part in the semiconductor integrated circuit 10A. The signal is set to the active level, and the semiconductor integrated circuit 10A is shifted to the power down state. Then, when the power-down control signal becomes an active level, the error detection circuit 11 turns off the N-channel field effect transistor 12. For this reason, charging of the capacitor 22 via the pull-up resistor 21 starts, and the error detection signal ERN increases at a speed corresponding to a time constant obtained by multiplying the resistance value of the pull-up resistor 21 and the capacitance value of the capacitor 22. . When the error detection signal ERN exceeds the threshold value VHa of the inverter 13 of the semiconductor integrated circuit 10A, the power-down control circuit 14 of the semiconductor integrated circuit 10A sets the power-down control signal to the inactive level, and makes the semiconductor integrated circuit 10A normal. Return to the operating state. As described above, the semiconductor integrated circuit 10A is in a power-down state for a period until the error detection signal ERN rises to the threshold value VHa after the error detection signal ERN falls below the threshold value VLa.

  However, in the example shown in FIG. 4, the threshold value VLb of the inverter 13 of the semiconductor integrated circuit 10B is lower than the threshold value VLa of the inverter 13 of the semiconductor integrated circuit 10A. Then, after the error detection signal ERN falls below the threshold value VLa, the error detection signal ERN rises toward the power supply voltage VDD without reaching the threshold value VLb. For this reason, in the semiconductor integrated circuit 10B, the output signal of the inverter 13 remains unchanged at the inactive level (L level), and the transition to the power down state is not performed. The semiconductor integrated circuit 10B has been described above as an example. However, when the threshold value of the inverter 13 (corresponding to the threshold value VLa) of the semiconductor integrated circuits 10C and 10D is lower than the threshold value VLa, the semiconductor integrated circuits 10C and 10D also have power. There is no transition to the down state.

  The present invention has been made in view of the circumstances described above, and when a wired OR of error detection signals output from a plurality of semiconductor integrated circuits is taken and supplied to each semiconductor integrated circuit as a power-down command signal. Another object of the present invention is to provide a technical means that enables each semiconductor integrated circuit to be stably shifted to a power-down state.

  The present invention reduces power consumption when an input circuit for binarizing a power-down command signal supplied from the outside and a power-down command signal binarized by the input circuit are at an active level. One end is connected to the power-down control circuit that sets the power-down control signal to be shifted to the power-down state to an active level, and the output terminal that outputs an error detection signal to the outside of the semiconductor integrated circuit, and is turned on. A switching element that makes an error detection signal an active level, a delay circuit that delays the power-down control signal for a predetermined time, a power-down control signal delayed by the delay circuit is at an inactive level, and the semiconductor integrated circuit When an error occurring in the circuit is detected, the switching element is And an error detection circuit for setting an error detection signal output from the output terminal to an active level and setting the switching element to an OFF state when the power-down control signal delayed by the delay circuit is at an active level. A semiconductor integrated circuit is provided.

  According to this invention, when a wired OR of error detection signals output from a plurality of semiconductor integrated circuits is taken and supplied to each semiconductor integrated circuit as a power-down command signal, error detection of any of the semiconductor integrated circuits is performed. When the circuit turns on the switching element, the error detection signal changes from the inactive level toward the active level, and the power-down command signal applied to each semiconductor integrated circuit also changes from the inactive level toward the active level. . Here, in the semiconductor integrated circuit in which the switching element is turned on and the error detection signal is changed from the inactive level to the active level, the power down command signal binarized by the input circuit has become the active level. And the power-down control circuit sets the power-down control signal to an active level and makes a transition to the power-down state. However, the power down control signal output from the power down control circuit reaches the error detection circuit after being delayed by the delay circuit. Accordingly, a delay corresponding to the delay time of the delay circuit occurs between the time when the power-down command signal crosses the threshold value of the input circuit and the time when the error detection circuit turns the switching element to the OFF state. The error detection signal) continues to change in the direction from the inactive level to the active level. If the delay time of the delay circuit is sufficiently long, even if the threshold value of the input circuit for binarizing the power-down command signal (error detection signal) varies among a plurality of semiconductor integrated circuits, the power-down command signal (Error detection signal) crosses the threshold values of the input circuits of all the semiconductor integrated circuits. Therefore, the transition to the power down state is performed in all the semiconductor integrated circuits.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a circuit diagram showing a configuration example of an electronic apparatus using a plurality of semiconductor integrated circuits according to an embodiment of the present invention. In FIG. 1, all of the semiconductor integrated circuits 10A ′, 10B ′, 10C ′, and 10D ′ are semiconductor integrated circuits according to the present embodiment. Similar to the configuration of FIG. 3, the electronic apparatus shown in FIG. 1 takes the wired OR of the error detection signal ERN output from each of the semiconductor integrated circuits 10A ′, 10B ′, 10C ′, and 10D ′, and the power down command signal PDN. Is given to each of the semiconductor integrated circuits 10A ′, 10B ′, 10C ′, and 10D ′.

  The difference between the semiconductor integrated circuits 10A ′, 10B ′, 10C ′, and 10D ′ according to the present embodiment and the semiconductor integrated circuits 10A, 10B, 10C, and 10D shown in FIG. 3 is that the former is different from the latter. The delay circuit 15 is not provided. The delay circuit 15 delays a power-down control signal output from the power-down control circuit 14 and addressed to the error detection circuit 11 by a predetermined delay time td, and supplies the delayed signal to the error detection circuit 11.

  FIG. 2 is a waveform diagram showing an operation example of this embodiment. In this operation example, as in FIG. 3, the error detection circuit 11 of the semiconductor integrated circuit 10A ′ detects an error, turns on the N-channel field effect transistor 12, and lowers the error detection signal ERN. When the error detection signal ERN falls below the threshold value VLa of the inverter 13 of the semiconductor integrated circuit 10A, the output signal of the inverter 13 becomes H level, and the power down control circuit 14 of the semiconductor integrated circuit 10A ′ The power down control signal sent to each of the components is set to the active level, and the semiconductor integrated circuit 10A ′ is shifted to the power down state.

  However, the power-down control signal addressed to the error detection circuit 11 is delayed by the delay time td by the delay circuit 15 and reaches the error detection circuit 11. The error detection circuit 11 turns off the N-channel field effect transistor 12 when the power-down control signal delayed by the delay circuit 15 becomes an active level. For this reason, the power down control signal PDN (error detection signal ERN) is lower than the threshold value VLa of the inverter 13 of the semiconductor integrated circuit 10A ′ and the output signal of the inverter 13 becomes the active level (H level). A delay corresponding to the delay time td of the delay circuit 15 occurs between the detection of the circuit 14 and the error detection circuit 11 until the N-channel field effect transistor 12 is turned off. During this time, the power-down command signal PDN ( The error detection signal ERN) continues to change from the inactive level (H level) to the active level (L level).

  Therefore, if the delay time td is sufficiently long, the threshold value of the inverter 13 that binarizes the power-down command signal PDN (error detection signal ERN) and passes it to the power-down control circuit 14 is between the semiconductor integrated circuits 10A ′ to 10D ′. Even if it varies, the power-down command signal PDN (error detection signal ERN) crosses the threshold value of the inverter 13 of all the semiconductor integrated circuits 10A ′ to 10D ′. Therefore, the transition to the power down state is performed in all the semiconductor integrated circuits 10A ′, 10B ′, 10C ′, and 10D ′.

  In the example shown in FIG. 2, the threshold value VLb of the inverter 13 of the semiconductor integrated circuit 10B 'is lower than the threshold value VLa of the semiconductor integrated circuit 10A'. Then, after the power-down command signal PDN (error detection signal ERN) falls below the threshold value VLa of the inverter 13 of the semiconductor integrated circuit 10A ′, the power-down command signal PDN (error detection signal ERN) is semiconductor during the delay time td. A state in which the threshold value VLb of the inverter 13 of the integrated circuit 10B ′ is lower is shown. In the semiconductor integrated circuit 10B ′, when the power-down command signal PDN (error detection signal ERN) decreases and falls below the threshold VLb of the inverter 13, the power-down command signal PDN (error detection signal ERN) increases and the inverter 13 The power-down state is established until the time point exceeds the threshold value VHb (> VLb). Although not shown, the same applies to the case where the threshold value of the inverter 13 of the other semiconductor integrated circuits 10C 'and 10D' (corresponding to the threshold value VLa) is lower than the threshold value VLa of the semiconductor integrated circuit 10A '.

  In this embodiment, even if any of the semiconductor integrated circuits 10A ′, 10B ′, 10C ′, and 10D ′ changes the error detection signal ERN from the inactive level to the active level, all the semiconductor integrated circuits 10A ′, It is necessary to shift 10B ′, 10C ′, and 10D ′ to the power down state. For this purpose, the range of variation of the threshold values (corresponding to the threshold value VLa) of the inverters 13 of all the semiconductor integrated circuits 10A ′, 10B ′, 10C ′, and 10D ′ when there is a manufacturing variation is obtained, and the power down command The delay time td of the delay circuit 15 may be made longer than the time from when the signal PDN (error detection signal ERN) reaches the lower limit after reaching the upper limit of the threshold variation range of the inverter 13. The range of the threshold variation of the inverter 13 and the time from when the power-down command signal PDN (error detection signal ERN) reaches the lower limit after reaching the upper limit of the threshold variation range of the inverter 13 are obtained by, for example, simulation. Is possible.

  As described above, according to the present embodiment, the wired OR of the error detection signal ERN output from the plurality of semiconductor integrated circuits 10A ′, 10B ′, 10C ′, and 10D ′ is obtained, and each semiconductor integrated circuit 10A ′, When the power down command signal PDN is supplied to 10B ′, 10C ′, and 10D ′, each of the semiconductor integrated circuits 10A ′, 10B ′, 10C ′, and 10D ′ can be stably shifted to the power down state. it can.

  Although one embodiment of the present invention has been described above, various other embodiments are conceivable for the present invention. For example:

(1) In the above embodiment, the power down command signal PDN received by each semiconductor integrated circuit 10A ′, 10B ′, 10C ′, 10D ′ is used as a low-active input signal, and each semiconductor integrated circuit 10A ′, 10B ′, 10C ′. The error detection signal ERN output by 10D ′ is also a low active output signal. However, the power-down command signal PDN received by each semiconductor integrated circuit 10A ′, 10B ′, 10C ′, 10D ′ is used as a high-active input signal, and each semiconductor integrated circuit 10A ′, 10B ′, 10C ′, 10D ′ outputs. The error detection signal ERN may also be a high active output signal. In this case, the switching element on which the error detection circuit 11 switches ON / OFF is a P-channel field effect transistor, and each source of each P-channel field effect transistor of each semiconductor integrated circuit 10A ′, 10B ′, 10C ′, 10D ′ is used. The power supply voltage VDD is fixed, the drains are connected in common outside the semiconductor integrated circuit, and a pull-down resistor is inserted between the common connection point and the ground line to form a wired OR circuit. What is necessary is just to give an output signal to each semiconductor integrated circuit 10A ', 10B', 10C ', 10D' as a power down command signal.

(2) In the above embodiment, each of the semiconductor integrated circuits 10A ′, 10B ′, 10C ′, and 10D ′ is configured by a field effect transistor, but each of the semiconductor integrated circuits 10A ′, 10B ′, 10C ′, and 10D ′ is a bipolar transistor. You may comprise by.

(3) In the above embodiment, in each of the semiconductor integrated circuits 10A ′, 10B ′, 10C ′, and 10D ′, the inverter 13 having hysteresis characteristics having two threshold values as an input circuit for binarizing the power-down command signal PDN. When the power-down command signal PDN decreases and falls below the low threshold, the power-down state is entered, and when the power-down command signal rises and rises above the high threshold, Return to the state. However, a signal other than the power-down command signal PDN may be given to each semiconductor integrated circuit 10A ', 10B', 10C ', 10D' as a trigger for returning from the power-down state to the normal state. In this case, in each of the semiconductor integrated circuits 10A ', 10B', 10C ', 10D', the input circuit for binarizing the power down command signal PDN may be a normal inverter having no hysteresis characteristic.

It is a circuit diagram which shows the structural example of the electronic device using multiple semiconductor integrated circuits which are one Embodiment of this invention. It is a wave form chart showing a waveform of each part in an example of operation of the electronic device. It has multiple semiconductor integrated circuits with error detection circuits and power-down control circuits, takes wired OR of error detection signals output from the error detection circuits of each semiconductor integrated circuit, and powers down each semiconductor integrated circuit as a pull-down command signal It is a circuit diagram which shows the structural example of the electronic device made to give to a control circuit. FIG. 4 is a waveform diagram illustrating an operation example in which the transition to the power-down state becomes unstable in the electronic device illustrated in FIG. 3.

Explanation of symbols

10A ', 10B', 10C ', 10D' ... Semiconductor integrated circuit, 11 ... Error detection circuit, 12 ... N-channel field effect transistor, 13 ... Inverter, 14 ... Power-down control circuit, 15 ... Delay Circuit, 21 ... pull-up resistor, 22 ... capacitor.

Claims (1)

An input circuit for binarizing a power-down command signal given from the outside;
A power-down control circuit having an active level as a power-down control signal for shifting the semiconductor integrated circuit to a power-down state with low power consumption when the power-down command signal binarized by the input circuit is at an active level;
One end is connected to an output terminal that outputs an error detection signal to the outside of the semiconductor integrated circuit, and the switching element that makes the error detection signal active level by being turned on,
A delay circuit for delaying the power-down control signal by a predetermined time;
When the power down control signal delayed by the delay circuit is at an inactive level and an error occurring in the semiconductor integrated circuit is detected, an error detection signal is output from the output terminal with the switching element turned on. A plurality of semiconductor integrated circuits each having an active level and an error detection circuit that turns off the switching element when the power down control signal delayed by the delay circuit is at an active level ;
The wired OR of each error detection signal output from the plurality of semiconductor integrated circuits is applied to the input circuit of the plurality of semiconductor integrated circuits as the power down command signal,
In a process in which any one of the switching elements of the plurality of semiconductor integrated circuits is turned on and the error detection signal becomes an active level, the error detection signal has a threshold variation range of each input circuit of the plurality of semiconductor integrated circuits. An electronic apparatus, wherein a delay time of each delay circuit of the plurality of semiconductor integrated circuits is made longer than a required time for passing between an upper limit and a lower limit.

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